1/*
2 * auich BeOS Driver for Intel Southbridge audio
3 *
4 * Copyright (c) 2003, Jerome Duval (jerome.duval@free.fr)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
16 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef _DEV_PCI_AUICH_H_
29#define _DEV_PCI_AUICH_H_
30
31#include <Drivers.h>
32#include <SupportDefs.h>
33#include <OS.h>
34#include <PCI.h>
35#include "auichreg.h"
36#include "config.h"
37#include "queue.h"
38#include "hmulti_audio.h"
39#include "multi.h"
40
41#define INTEL_VENDOR_ID		0x8086	/* Intel */
42#define INTEL_82443MX_AC97_DEVICE_ID	0x7195
43#define INTEL_82801AA_AC97_DEVICE_ID	0x2415
44#define INTEL_82801AB_AC97_DEVICE_ID	0x2425
45#define INTEL_82801BA_AC97_DEVICE_ID	0x2445
46#define INTEL_82801CA_AC97_DEVICE_ID	0x2485
47#define INTEL_82801DB_AC97_DEVICE_ID	0x24c5
48#define INTEL_82801EB_AC97_DEVICE_ID	0x24d5
49#define INTEL_82801FB_AC97_DEVICE_ID	0x266e
50#define INTEL_631xESB_AC97_DEVICE_ID	0x2698
51#define INTEL_82801GB_AC97_DEVICE_ID	0x27de
52#define INTEL_6300ESB_AC97_DEVICE_ID	0x25a6
53#define SIS_VENDOR_ID		0x1039	/* Sis */
54#define SIS_SI7012_AC97_DEVICE_ID		0x7012
55#define NVIDIA_VENDOR_ID	0x10de	/* Nvidia */
56#define NVIDIA_nForce_AC97_DEVICE_ID	0x01b1
57#define NVIDIA_nForce2_AC97_DEVICE_ID	0x006a
58#define NVIDIA_nForce2_400_AC97_DEVICE_ID	0x008a
59#define NVIDIA_nForce3_AC97_DEVICE_ID	0x00da
60#define NVIDIA_nForce3_250_AC97_DEVICE_ID	0x00ea
61#define NVIDIA_CK804_AC97_DEVICE_ID		0x0059
62#define NVIDIA_MCP51_AC97_DEVICE_ID		0x026b
63#define NVIDIA_MCP04_AC97_DEVICE_ID		0x003a
64#define AMD_VENDOR_ID		0x1022	/* Amd */
65#define AMD_AMD8111_AC97_DEVICE_ID		0x764d
66#define AMD_AMD768_AC97_DEVICE_ID		0x7445
67
68#define VERSION "Version alpha 1, Copyright (c) 2003 J��r��me Duval, compiled on " __DATE__ " " __TIME__
69#define DRIVER_NAME "auich"
70#define FRIENDLY_NAME "Auich"
71#define AUTHOR "J��r��me Duval"
72
73#define FRIENDLY_NAME_ICH "Auich ICH"
74#define FRIENDLY_NAME_SIS "Auich SiS"
75#define FRIENDLY_NAME_NVIDIA "Auich nVidia"
76#define FRIENDLY_NAME_AMD "Auich AMD"
77
78#define	AUICH_DMALIST_MAX	32
79typedef struct _auich_dmalist {
80	uint32	base;
81	uint32	len;
82#define	AUICH_DMAF_IOC		0x80000000	/* 1-int on complete */
83#define	AUICH_DMAF_BUP		0x40000000	/* 0-retrans last, 1-transmit 0 */
84} auich_dmalist;
85
86#define	AUICH_USE_PLAY		(1 << 0)
87#define	AUICH_USE_RECORD	(1 << 1)
88#define AUICH_STATE_STARTED	(1 << 0)
89
90/*
91 * auich memory managment
92 */
93
94typedef struct _auich_mem {
95	LIST_ENTRY(_auich_mem) next;
96	void	*log_base;
97	phys_addr_t	phy_base;
98	area_id area;
99	size_t	size;
100} auich_mem;
101
102/*
103 * Streams
104 */
105
106typedef struct _auich_stream {
107	struct _auich_dev 	*card;
108	uint8        		use;
109	uint8        		state;
110	uint8        		b16;
111	uint32       		sample_rate;
112	uint8				channels;
113	uint32 				bufframes;
114	uint8 				bufcount;
115
116	uint32				base;
117
118	LIST_ENTRY(_auich_stream)	next;
119
120	void            	(*inth) (void *);
121	void           		*inthparam;
122
123	void		*dmaops_log_base;
124	phys_addr_t	dmaops_phy_base;
125	area_id dmaops_area;
126
127	auich_mem *buffer;
128	uint16       blksize;	/* in samples */
129	uint16       trigblk;	/* blk on which to trigger inth */
130	uint16       blkmod;	/* Modulo value to wrap trigblk */
131
132	uint16 		 		sta; /* GLOB_STA int bit */
133
134	/* multi_audio */
135	volatile int64	frames_count;	// for play or record
136	volatile bigtime_t real_time;	// for play or record
137	volatile int32	buffer_cycle;	// for play or record
138	int32 first_channel;
139	bool update_needed;
140} auich_stream;
141
142/*
143 * Devices
144 */
145
146typedef struct _auich_dev {
147	char		name[DEVNAME];	/* used for resources */
148	pci_info	info;
149	device_config config;
150
151	void	*ptb_log_base;
152	void	*ptb_phy_base;
153	area_id ptb_area;
154
155	sem_id buffer_ready_sem;
156
157	uint32			interrupt_mask;
158
159	LIST_HEAD(, _auich_stream) streams;
160
161	LIST_HEAD(, _auich_mem) mems;
162
163	auich_stream	*pstream;
164	auich_stream	*rstream;
165
166	/* multi_audio */
167	multi_dev	multi;
168} auich_dev;
169
170
171#define AUICH_SETTINGS "auich.settings"
172
173typedef struct {
174	uint32	sample_rate;
175	uint32	buffer_frames;
176	int32	buffer_count;
177	bool	use_thread;
178} auich_settings;
179
180extern auich_settings current_settings;
181
182extern int32 num_cards;
183extern auich_dev cards[NUM_CARDS];
184
185status_t auich_stream_set_audioparms(auich_stream *stream, uint8 channels,
186			     uint8 b16, uint32 sample_rate);
187status_t auich_stream_commit_parms(auich_stream *stream);
188status_t auich_stream_get_nth_buffer(auich_stream *stream, uint8 chan, uint8 buf,
189					char** buffer, size_t *stride);
190void auich_stream_start(auich_stream *stream, void (*inth) (void *), void *inthparam);
191void auich_stream_halt(auich_stream *stream);
192auich_stream *auich_stream_new(auich_dev *card, uint8 use, uint32 bufframes, uint8 bufcount);
193void auich_stream_delete(auich_stream *stream);
194
195#endif /* _DEV_PCI_AUICH_H_ */
196