1/* 2 * Copyright 2011-2012, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jian Chiang <j.jian.chiang@gmail.com> 7 * J��r��me Duval <jerome.duval@gmail.com> 8 * Akshay Jaggi <akshay1994.leo@gmail.com> 9 */ 10#ifndef XHCI_HARDWARE_H 11#define XHCI_HARDWARE_H 12 13// PCI IDs 14#define PCI_VENDOR_INTEL 0x8086 15#define PCI_DEVICE_INTEL_PANTHER_POINT_XHCI 0x1e31 16#define PCI_DEVICE_INTEL_LYNX_POINT_XHCI 0x8c31 17#define PCI_DEVICE_INTEL_LYNX_POINT_LP_XHCI 0x9c31 18#define PCI_DEVICE_INTEL_BAYTRAIL_XHCI 0x0f35 19#define PCI_DEVICE_INTEL_WILDCAT_POINT_XHCI 0x8cb1 20#define PCI_DEVICE_INTEL_WILDCAT_POINT_LP_XHCI 0x9cb1 21 22// Intel quirks registers in PCI config 23#define XHCI_INTEL_USB3PRM 0xdc // USB 3.0 Port Routing Mask 24#define XHCI_INTEL_USB3_PSSEN 0xd8 // USB 3.0 Port SuperSpeed Enable 25#define XHCI_INTEL_USB2PRM 0xd4 // USB 2.0 Port Routing Mask 26#define XHCI_INTEL_XUSB2PR 0xd0 // USB 2.0 Port Routing 27 28// Host Controller Capability Registers 29#define XHCI_HCI_CAPLENGTH 0x00 // HCI Capability Register Length 30#define HCI_CAPLENGTH(p) (((p) >> 0) & 0xff) 31#define XHCI_HCI_VERSION 0x00 // HCI Interface Version Number 32#define HCI_VERSION(p) (((p) >> 16) & 0xffff) 33#define XHCI_HCSPARAMS1 0x04 // Structural Parameters 1 34// HCSPARAMS1 35#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 36#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) 37#define XHCI_HCSPARAMS2 0x08 // Structural Parameters 2 38#define HCS_IST(p) (((p) >> 0) & 0xf) 39#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 40#define HCS_SPR(p) (((p) >> 26) & 0x1) 41#define HCS_MAX_SC_BUFFERS(p) (((((p) >> 21) & 0x1f)<<5)|(((p) >> 27) & 0x1f)) 42#define XHCI_HCSPARAMS3 0x0C // Structural Parameters 3 43#define HCS_U1_DEVICE_LATENCY(p) (((p) >> 0) & 0xff) 44#define HCS_U2_DEVICE_LATENCY(p) (((p) >> 16) & 0xffff) 45#define XHCI_HCCPARAMS 0x10 // Capability Parameters 46#define HCC_AC64(p) (((p) >> 0) & 0x1) 47#define HCC_BNC(p) (((p) >> 1) & 0x1) 48#define HCC_CSZ(p) (((p) >> 2) & 0x1) 49#define HCC_PPC(p) (((p) >> 3) & 0x1) 50#define HCC_PIND(p) (((p) >> 4) & 0x1) 51#define HCC_LHRC(p) (((p) >> 5) & 0x1) 52#define HCC_LTC(p) (((p) >> 6) & 0x1) 53#define HCC_NSS(p) (((p) >> 7) & 0x1) 54#define HCC_PAE(p) (((p) >> 8) & 0x1) 55#define HCC_SPC(p) (((p) >> 9) & 0x1) 56#define HCC_SEC(p) (((p) >> 10) & 0x1) 57#define HCC_CFC(p) (((p) >> 11) & 0x1) 58#define HCC_MAXPSASIZE(p) (((p) >> 12) & 0xf) 59#define HCC_XECP(p) (((p) >> 16) & 0xfff) 60#define XHCI_DBOFF 0x14 // Doorbell Register offset 61#define XHCI_RTSOFF 0x18 // Runtime Register Space offset 62 63 64// Host Controller Operational Registers 65#define XHCI_CMD 0x00 // USB Command 66// USB Command Register 67#define CMD_RUN (1 << 0) 68#define CMD_HCRST (1 << 1) // Host Controller Reset 69#define CMD_INTE (1 << 2) // IRQ Enable 70#define CMD_HSEE (1 << 3) // Host System Error En 71#define CMD_LHCRST (1 << 7) // Light Host Controller Reset 72#define CMD_CSS (1 << 8) // Controller Save State 73#define CMD_CRS (1 << 9) // Controller Restore State 74#define CMD_EWE (1 << 10) // Enable Wrap Event 75 76#define XHCI_STS 0x04 // USB Status 77// USB Status Register 78#define STS_HCH (1 << 0) // Host Controller Halt 79#define STS_HSE (1 << 2) // Host System Error 80#define STS_EINT (1 << 3) // Event Interrupt 81#define STS_PCD (1 << 4) // Port Change Detect 82#define STS_SSS (1 << 8) // Save State Status 83#define STS_RSS (1 << 9) // Restore State Status 84#define STS_SRE (1 << 10) // Save Restore Error 85#define STS_CNR (1 << 11) // Controller Not Ready 86#define STS_HCE (1 << 12) // Host Controller Error 87 88#define XHCI_PAGESIZE 0x08 // PAGE SIZE 89#define XHCI_DNCTRL 0x14 90// Section 5.4.5 91#define XHCI_CRCR_LO 0x18 92#define XHCI_CRCR_HI 0x1C 93#define CRCR_RCS (1<<0) 94#define CRCR_CS (1<<1) 95#define CRCR_CA (1<<2) 96#define CRCR_CRR (1<<3) 97// Section 5.4.6 98#define XHCI_DCBAAP_LO 0x30 99#define XHCI_DCBAAP_HI 0x34 100// Section 5.4.7 101#define XHCI_CONFIG 0x38 102 103 104// Host Controller Runtime Registers 105#define XHCI_MFINDEX 0x0000 106// Section 5.5.2.1 107#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) 108// IMAN 109#define IMAN_INTR_ENA 0x00000002 110// Section 5.5.2.2 111#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 112// Section 5.5.2.3.1 113#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 114// ERSTSZ 115#define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 116// Section 5.5.2.3.2 117#define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) 118#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 119// Section 5.5.2.3.3 120#define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) 121#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) 122// Event Handler Busy (EHB) 123#define ERDP_BUSY (1 << 3) 124 125 126// Host Controller Doorbell Registers 127#define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 128#define XHCI_DOORBELL_TARGET(x) ((x) & 0xff) 129#define XHCI_DOORBELL_TARGET_GET(x) ((x) & 0xff) 130#define XHCI_DOORBELL_STREAMID(x) (((x) & 0xffff) << 16) 131#define XHCI_DOORBELL_STREAMID_GET(x) (((x) >> 16) & 0xffff) 132 133 134// Extended Capabilities 135#define XECP_ID(x) ((x) & 0xff) 136#define HCS0_XECP(x) (((x) >> 16) & 0xffff) 137#define XECP_NEXT(x) (((x) >> 8) & 0xff) 138#define XHCI_LEGSUP_CAPID 0x01 139#define XHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore 140#define XHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore 141 142#define XHCI_LEGCTLSTS 0x04 143#define XHCI_LEGCTLSTS_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17)) 144#define XHCI_LEGCTLSTS_EVENTS_SMI (0x7 << 29) 145 146#define XHCI_SUPPORTED_PROTOCOLS_CAPID 0x02 147#define XHCI_SUPPORTED_PROTOCOLS_0_MINOR(x) (((x) >> 16) & 0xff) 148#define XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(x) (((x) >> 24) & 0xff) 149 150#define XHCI_SUPPORTED_PROTOCOLS_1_COUNT(x) (((x) >> 8) & 0xff) 151#define XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(x) (((x) >> 0) & 0xff) 152 153 154// Port status Registers 155// Section 5.4.8 156#define XHCI_PORTSC(n) (0x400 + (0x10 * (n))) 157#define PS_CCS (1 << 0) 158#define PS_PED (1 << 1) 159#define PS_OCA (1 << 3) 160#define PS_PR (1 << 4) 161#define PS_PP (1 << 9) 162#define PS_SPEED_GET(x) (((x) >> 10) & 0xF) 163#define PS_LWS (1 << 16) 164#define PS_CSC (1 << 17) 165#define PS_PEC (1 << 18) 166#define PS_WRC (1 << 19) 167#define PS_OCC (1 << 20) 168#define PS_PRC (1 << 21) 169#define PS_PLC (1 << 22) 170#define PS_CEC (1 << 23) 171#define PS_CAS (1 << 24) 172#define PS_WCE (1 << 25) 173#define PS_WDE (1 << 26) 174#define PS_WPR (1 << 30) 175 176#define PS_CLEAR 0x80FF00F7U 177 178#define PS_PLS_MASK (0xf << 5) 179#define PS_XDEV_U0 (0x0 << 5) 180#define PS_XDEV_U1 (0x1 << 5) 181#define PS_XDEV_U2 (0x2 << 5) 182#define PS_XDEV_U3 (0x3 << 5) 183#define PS_XDEV_DISABLED (0x4 << 5) 184#define PS_XDEV_RXDETECT (0x5 << 5) 185#define PS_XDEV_INACTIVE (0x6 << 5) 186#define PS_XDEV_POLLING (0x7 << 5) 187#define PS_XDEV_RECOVERY (0x8 << 5) 188#define PS_XDEV_HOT_RESET (0x9 << 5) 189#define PS_XDEV_COMP_MODE (0xa << 5) 190#define PS_XDEV_TEST_MODE (0xb << 5) 191#define PS_XDEV_RESUME (0xf << 5) 192 193 194// Completion Code 195#define TRB_2_COMP_CODE_GET(x) (((x) >> 24) & 0xff) 196#define COMP_INVALID 0 197#define COMP_SUCCESS 1 198#define COMP_DATA_BUFFER 2 199#define COMP_BABBLE 3 200#define COMP_USB_TRANSACTION 4 201#define COMP_TRB 5 202#define COMP_STALL 6 203#define COMP_RESOURCE 7 204#define COMP_BANDWIDTH 8 205#define COMP_NO_SLOTS 9 206#define COMP_INVALID_STREAM 10 207#define COMP_SLOT_NOT_ENABLED 11 208#define COMP_ENDPOINT_NOT_ENABLED 12 209#define COMP_SHORT_PACKET 13 210#define COMP_RING_UNDERRUN 14 211#define COMP_RING_OVERRUN 15 212#define COMP_VF_RING_FULL 16 213#define COMP_PARAMETER 17 214#define COMP_BANDWIDTH_OVERRUN 18 215#define COMP_CONTEXT_STATE 19 216#define COMP_NO_PING_RESPONSE 20 217#define COMP_EVENT_RING_FULL 21 218#define COMP_INCOMPATIBLE_DEVICE 22 219#define COMP_MISSED_SERVICE 23 220#define COMP_COMMAND_RING_STOPPED 24 221#define COMP_COMMAND_ABORTED 25 222#define COMP_STOPPED 26 223#define COMP_STOPPED_LENGTH_INVALID 27 224#define COMP_MAX_EXIT_LATENCY 29 225#define COMP_ISOC_OVERRUN 31 226#define COMP_EVENT_LOST 32 227#define COMP_UNDEFINED 33 228#define COMP_INVALID_STREAM_ID 34 229#define COMP_SECONDARY_BANDWIDTH 35 230#define COMP_SPLIT_TRANSACTION 36 231 232#define TRB_2_TD_SIZE(x) (((x) & 0x1F) << 17) 233#define TRB_2_TD_SIZE_GET(x) (((x) >> 17) & 0x1F) 234#define TRB_2_REM(x) ((x) & 0xFFFFFF) 235#define TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 236#define TRB_2_BYTES(x) ((x) & 0x1FFFF) 237#define TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 238#define TRB_2_IRQ(x) (((x) & 0x3FF) << 22) 239#define TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 240#define TRB_2_STREAM(x) (((x) & 0xFF) << 16) 241#define TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFF) 242 243#define TRB_3_TYPE(x) (((x) & 0x3F) << 10) 244#define TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 245// TRB Type (table 131) 246#define TRB_TYPE_NORMAL 1 247#define TRB_TYPE_SETUP_STAGE 2 248#define TRB_TYPE_DATA_STAGE 3 249#define TRB_TYPE_STATUS_STAGE 4 250#define TRB_TYPE_ISOCH 5 251#define TRB_TYPE_LINK 6 252#define TRB_TYPE_EVENT_DATA 7 253#define TRB_TYPE_TR_NOOP 8 254// commands 255#define TRB_TYPE_ENABLE_SLOT 9 256#define TRB_TYPE_DISABLE_SLOT 10 257#define TRB_TYPE_ADDRESS_DEVICE 11 258#define TRB_TYPE_CONFIGURE_ENDPOINT 12 259#define TRB_TYPE_EVALUATE_CONTEXT 13 260#define TRB_TYPE_RESET_ENDPOINT 14 261#define TRB_TYPE_STOP_ENDPOINT 15 262#define TRB_TYPE_SET_TR_DEQUEUE 16 263#define TRB_TYPE_RESET_DEVICE 17 264#define TRB_TYPE_FORCE_EVENT 18 265#define TRB_TYPE_NEGOCIATE_BW 19 266#define TRB_TYPE_SET_LATENCY_TOLERANCE 20 267#define TRB_TYPE_GET_PORT_BW 21 268#define TRB_TYPE_FORCE_HEADER 22 269#define TRB_TYPE_CMD_NOOP 23 270// events 271#define TRB_TYPE_TRANSFER 32 272#define TRB_TYPE_COMMAND_COMPLETION 33 273#define TRB_TYPE_PORT_STATUS_CHANGE 34 274#define TRB_TYPE_BANDWIDTH_REQUEST 35 275#define TRB_TYPE_DOORBELL 36 276#define TRB_TYPE_HOST_CONTROLLER 37 277#define TRB_TYPE_DEVICE_NOTIFICATION 38 278#define TRB_TYPE_MFINDEX_WRAP 39 279// vendor 280#define TRB_TYPE_NEC_COMMAND_COMPLETION 48 281#define TRB_TYPE_NEC_GET_FIRMWARE_REV 49 282 283#define TRB_3_CYCLE_BIT (1U << 0) 284#define TRB_3_TC_BIT (1U << 1) 285#define TRB_3_ENT_BIT (1U << 1) 286#define TRB_3_ISP_BIT (1U << 2) 287#define TRB_3_EVENT_DATA_BIT (1U << 2) 288#define TRB_3_NSNOOP_BIT (1U << 3) 289#define TRB_3_CHAIN_BIT (1U << 4) 290#define TRB_3_IOC_BIT (1U << 5) 291#define TRB_3_IDT_BIT (1U << 6) 292#define TRB_3_BEI_BIT (1U << 9) 293#define TRB_3_DCEP_BIT (1U << 9) 294#define TRB_3_PRSV_BIT (1U << 9) 295#define TRB_3_BSR_BIT (1U << 9) 296#define TRB_3_TRT_MASK (3U << 16) 297#define TRB_3_DIR_IN (1U << 16) 298#define TRB_3_TRT_OUT (2U << 16) 299#define TRB_3_TRT_IN (3U << 16) 300#define TRB_3_SUSPEND_ENDPOINT_BIT (1U << 23) 301#define TRB_3_ISO_SIA_BIT (1U << 31) 302 303#define TRB_3_TBC(x) (((x) & 0x3) << 7) 304#define TRB_3_TBC_GET(x) (((x) >> 7) & 0x3) 305#define TRB_3_TLBPC(x) (((x) & 0xf) << 16) 306#define TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xf) 307#define TRB_3_ENDPOINT(x) (((x) & 0x1f) << 16) 308#define TRB_3_ENDPOINT_GET(x) (((x) >> 16) & 0x1f) 309#define TRB_3_FRID(x) (((x) & 0x7ff) << 20) 310#define TRB_3_FRID_GET(x) (((x) >> 20) & 0x7ff) 311#define TRB_3_SLOT(x) (((x) & 0xff) << 24) 312#define TRB_3_SLOT_GET(x) (((x) >> 24) & 0xff) 313 314 315#define XHCI_MAX_EVENTS (16 * 13) 316#define XHCI_MAX_COMMANDS (16 * 1) 317#define XHCI_MAX_SLOTS 255 318#define XHCI_MAX_PORTS 127 319#define XHCI_MAX_ENDPOINTS 32 320// the spec says 1023, however this would cross the page boundary 321#define XHCI_MAX_SCRATCHPADS 256 322#define XHCI_MAX_DEVICES 128 323#define XHCI_MAX_TRANSFERS 8 324 325 326struct xhci_trb { 327 uint64 address; 328 uint32 status; 329 uint32 flags; 330} __attribute__((__aligned__(4))); 331 332 333// Section 6.5 334struct xhci_erst_element { 335 uint64 rs_addr; 336 uint32 rs_size; 337 uint32 rsvdz; 338} __attribute__((__aligned__(64))); 339 340 341struct xhci_device_context_array { 342 uint64 baseAddress[XHCI_MAX_SLOTS]; 343 struct { 344 uint64 padding; 345 } __attribute__((__aligned__(64))); 346 uint64 scratchpad[XHCI_MAX_SCRATCHPADS]; 347}; 348 349 350struct xhci_slot_ctx { 351 uint32 dwslot0; 352 uint32 dwslot1; 353 uint32 dwslot2; 354 uint32 dwslot3; 355 uint32 reserved[4]; 356}; 357 358#define SLOT_0_ROUTE(x) ((x) & 0xFFFFF) 359#define SLOT_0_ROUTE_GET(x) ((x) & 0xFFFFF) 360#define SLOT_0_SPEED(x) (((x) & 0xF) << 20) 361#define SLOT_0_SPEED_GET(x) (((x) >> 20) & 0xF) 362#define SLOT_0_MTT_BIT (1U << 25) 363#define SLOT_0_HUB_BIT (1U << 26) 364#define SLOT_0_NUM_ENTRIES(x) (((x) & 0x1F) << 27) 365#define SLOT_0_NUM_ENTRIES_GET(x) (((x) >> 27) & 0x1F) 366 367#define SLOT_1_MAX_EXIT_LATENCY(x) ((x) & 0xFFFF) 368#define SLOT_1_MAX_EXIT_LATENCY_GET(x) ((x) & 0xFFFF) 369#define SLOT_1_RH_PORT(x) (((x) & 0xFF) << 16) 370#define SLOT_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 371#define SLOT_1_NUM_PORTS(x) (((x) & 0xFF) << 24) 372#define SLOT_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 373 374#define SLOT_2_TT_HUB_SLOT(x) ((x) & 0xFF) 375#define SLOT_2_TT_HUB_SLOT_GET(x) ((x) & 0xFF) 376#define SLOT_2_PORT_NUM(x) (((x) & 0xFF) << 8) 377#define SLOT_2_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 378#define SLOT_2_TT_TIME(x) (((x) & 0x3) << 16) 379#define SLOT_2_TT_TIME_GET(x) (((x) >> 16) & 0x3) 380#define SLOT_2_IRQ_TARGET(x) (((x) & 0x7F) << 22) 381#define SLOT_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x7F) 382 383#define SLOT_3_DEVICE_ADDRESS(x) ((x) & 0xFF) 384#define SLOT_3_DEVICE_ADDRESS_GET(x) ((x) & 0xFF) 385#define SLOT_3_SLOT_STATE(x) (((x) & 0x1F) << 27) 386#define SLOT_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 387 388#define HUB_TTT_GET(x) (((x) >> 5) & 0x3) 389 390struct xhci_endpoint_ctx { 391 uint32 dwendpoint0; 392 uint32 dwendpoint1; 393 uint64 qwendpoint2; 394 uint32 dwendpoint4; 395 uint32 reserved[3]; 396}; 397 398 399#define ENDPOINT_0_STATE(x) ((x) & 0x7) 400#define ENDPOINT_0_STATE_GET(x) ((x) & 0x7) 401#define ENDPOINT_0_MULT(x) (((x) & 0x3) << 8) 402#define ENDPOINT_0_MULT_GET(x) (((x) >> 8) & 0x3) 403#define ENDPOINT_0_MAXPSTREAMS(x) (((x) & 0x1F) << 10) 404#define ENDPOINT_0_MAXPSTREAMS_GET(x) (((x) >> 10) & 0x1F) 405#define ENDPOINT_0_LSA_BIT (1U << 15) 406#define ENDPOINT_0_INTERVAL(x) (((x) & 0xFF) << 16) 407#define ENDPOINT_0_INTERVAL_GET(x) (((x) >> 16) & 0xFF) 408 409#define ENDPOINT_1_CERR(x) (((x) & 0x3) << 1) 410#define ENDPOINT_1_CERR_GET(x) (((x) >> 1) & 0x3) 411#define ENDPOINT_1_EPTYPE(x) (((x) & 0x7) << 3) 412#define ENDPOINT_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 413#define ENDPOINT_1_HID_BIT (1U << 7) 414#define ENDPOINT_1_MAXBURST(x) (((x) & 0xFF) << 8) 415#define ENDPOINT_1_MAXBURST_GET(x) (((x) >> 8) & 0xFF) 416#define ENDPOINT_1_MAXPACKETSIZE(x) (((x) & 0xFFFF) << 16) 417#define ENDPOINT_1_MAXPACKETSIZE_GET(x) (((x) >> 16) & 0xFFFF) 418 419#define ENDPOINT_2_DCS_BIT (1U << 0) 420 421#define ENDPOINT_4_AVGTRBLENGTH(x) ((x) & 0xFFFF) 422#define ENDPOINT_4_AVGTRBLENGTH_GET(x) ((x) & 0xFFFF) 423#define ENDPOINT_4_MAXESITPAYLOAD(x) (((x) & 0xFFFF) << 16) 424#define ENDPOINT_4_MAXESITPAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 425 426#define ENDPOINT_STATE_DISABLED 0 427#define ENDPOINT_STATE_RUNNING 1 428#define ENDPOINT_STATE_HALTED 2 429#define ENDPOINT_STATE_STOPPED 3 430#define ENDPOINT_STATE_ERROR 4 431#define ENDPOINT_STATE_RESERVED_5 5 432#define ENDPOINT_STATE_RESERVED_6 6 433#define ENDPOINT_STATE_RESERVED_7 7 434 435struct xhci_stream_ctx { 436 uint64 qwstream0; 437 uint32 reserved[2]; 438}; 439 440 441struct xhci_input_ctx { 442 uint32 dropFlags; 443 uint32 addFlags; 444 uint32 reserved[6]; 445}; 446 447 448struct xhci_input_device_ctx { 449 struct xhci_input_ctx input; 450 struct xhci_slot_ctx slot; 451 struct xhci_endpoint_ctx endpoints[XHCI_MAX_ENDPOINTS - 1]; 452}; 453 454 455struct xhci_device_ctx { 456 struct xhci_slot_ctx slot; 457 struct xhci_endpoint_ctx endpoints[XHCI_MAX_ENDPOINTS - 1]; 458}; 459 460 461#endif // !XHCI_HARDWARE_H 462