1262395Sbapt/*
2262395Sbapt	Copyright (c) 2002-2004, Thomas Kurschel
3262395Sbapt
4262395Sbapt
5262395Sbapt	Part of Radeon accelerant
6262395Sbapt
7262395Sbapt	Palette handling. Though it's very often referred to as
8262395Sbapt	being part of the DAC, this is not really true as palette
9262395Sbapt	lookup is part of the CRTC unit (else it wouldn't work for
10262395Sbapt	digital output like DVI)
11262395Sbapt*/
12262395Sbapt
13262395Sbapt
14262395Sbapt#include "GlobalData.h"
15262395Sbapt#include "dac_regs.h"
16262395Sbapt#include "mmio.h"
17262395Sbapt#include "CP.h"
18262395Sbapt#include "generic.h"
19262395Sbapt
20262395Sbapt// set standard colour palette (needed for non-palette modes)
21void Radeon_InitPalette(
22	accelerator_info *ai, int crtc_idx )
23{
24	int i;
25
26	if ( ai->si->acc_dma ) {
27		START_IB();
28
29		WRITE_IB_REG( RADEON_DAC_CNTL2,
30			(crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
31			(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
32
33		WRITE_IB_REG( RADEON_PALETTE_INDEX, 0 );
34
35		for( i = 0; i < 256; ++i )
36			WRITE_IB_REG( RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
37
38		SUBMIT_IB();
39	} else {
40		Radeon_WaitForFifo ( ai , 1 );
41		OUTREG( ai->regs, RADEON_DAC_CNTL2,
42			(crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
43			(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
44
45		OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 );
46		for( i = 0; i < 256; ++i ) {
47			Radeon_WaitForFifo ( ai , 1 );  // TODO FIXME good god this is gonna be slow...
48			OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
49		}
50	}
51}
52
53static void setPalette(
54	accelerator_info *ai, int crtc_idx,
55	uint count, uint8 first, uint8 *color_data );
56
57// public function: set colour palette
58void SET_INDEXED_COLORS(
59	uint count, uint8 first, uint8 *color_data, uint32 flags )
60{
61	virtual_card *vc = ai->vc;
62
63	(void)flags;
64
65	SHOW_FLOW( 3, "first=%d, count=%d", first, count );
66
67	if( vc->mode.space != B_CMAP8 ) {
68		SHOW_ERROR0( 2, "Tried to set palette in non-palette mode" );
69		return;
70	}
71
72	if( vc->used_crtc[0] )
73		setPalette( ai, 0, count, first, color_data );
74	if( vc->used_crtc[1] )
75		setPalette( ai, 1, count, first, color_data );
76}
77
78
79// set palette of one DAC
80static void setPalette(
81	accelerator_info *ai, int crtc_idx,
82	uint count, uint8 first, uint8 *color_data )
83{
84	uint i;
85
86	if ( ai->si->acc_dma ) {
87		START_IB();
88
89		WRITE_IB_REG( RADEON_DAC_CNTL2,
90			(crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
91			(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
92
93		WRITE_IB_REG( RADEON_PALETTE_INDEX, first );
94
95		for( i = 0; i < count; ++i, color_data += 3 )
96			WRITE_IB_REG( RADEON_PALETTE_DATA,
97				((uint32)color_data[0] << 16) |
98				((uint32)color_data[1] << 8) |
99				 color_data[2] );
100
101		SUBMIT_IB();
102	} else {
103		Radeon_WaitForFifo ( ai , 1 );
104		OUTREG( ai->regs, RADEON_DAC_CNTL2,
105			(crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
106			(ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
107
108		OUTREG( ai->regs, RADEON_PALETTE_INDEX, first );
109		for( i = 0; i < count; ++i, color_data += 3 ) {
110			Radeon_WaitForFifo ( ai , 1 );  // TODO FIXME good god this is gonna be slow...
111			OUTREG( ai->regs, RADEON_PALETTE_DATA,
112				((uint32)color_data[0] << 16) |
113				((uint32)color_data[1] << 8) |
114				 color_data[2] );
115		}
116	}
117}
118