1/*
2 * Copyright 2011-2015, Haiku, Inc. All Rights Reserved.
3 * Distributed under the terms of the MIT License.
4 *
5 * Authors:
6 *		Michael Lotz, mmlr@mlotz.ch
7 *		Alexander von Gluck IV, kallisti5@unixzen.com
8 */
9#ifndef INTEL_FDI_H
10#define INTEL_FDI_H
11
12
13#include "intel_extreme.h"
14
15
16class FDITransmitter {
17public:
18									FDITransmitter(pipe_index pipeIndex);
19									~FDITransmitter();
20
21		void						Enable();
22		void						Disable();
23
24		bool						IsPLLEnabled();
25		void						EnablePLL(uint32 lanes);
26		void						DisablePLL();
27
28		pipe_index					PipeIndex()
29										 { return fPipeIndex; };
30
31protected:
32		pipe_index					fPipeIndex;
33};
34
35
36class FDIReceiver {
37public:
38									FDIReceiver(pipe_index pipeIndex);
39									~FDIReceiver();
40
41		void						Enable();
42		void						Disable();
43
44		bool						IsPLLEnabled();
45		void						EnablePLL(uint32 lanes);
46		void						DisablePLL();
47
48		void						SwitchClock(bool toPCDClock);
49
50		pipe_index					PipeIndex()
51										 { return fPipeIndex; };
52
53protected:
54		pipe_index					fPipeIndex;
55};
56
57
58class FDILink {
59public:
60									FDILink(pipe_index pipeIndex);
61									~FDILink();
62
63		FDITransmitter&				Transmitter()
64										{ return fTransmitter; };
65		FDIReceiver&				Receiver()
66										{ return fReceiver; };
67
68		status_t					PreTrain(
69										display_timing* target,
70										uint32* linkBandwidth,
71										uint32* lanes,
72										uint32* bitsPerPixel);
73		status_t					Train(display_timing* target, uint32 lanes);
74
75private:
76		status_t					_NormalTrain(uint32 lanes);
77		status_t					_IlkTrain(uint32 lanes);
78		status_t					_SnbTrain(uint32 lanes);
79		status_t					_ManualTrain(uint32 lanes);
80		status_t					_AutoTrain(uint32 lanes);
81
82		FDITransmitter				fTransmitter;
83		FDIReceiver					fReceiver;
84
85		pipe_index					fPipeIndex;
86};
87
88
89#endif // INTEL_FDI_H
90