1/* 2 Copyright (c) 2002, Thomas Kurschel 3 4 5 Part of Radeon driver 6 7 Overlay unit and Subpicture registers 8*/ 9 10#ifndef _OVERLAY_REGS_H 11#define _OVERLAY_REGS_H 12 13 14#define RADEON_OV0_Y_X_START 0x0400 15#define RADEON_OV0_Y_X_END 0x0404 16#define RADEON_OV0_PIPELINE_CNTL 0x0408 17#define RADEON_OV0_REG_LOAD_CNTL 0x0410 18# define RADEON_REG_LD_CTL_LOCK 0x00000001L 19# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 20# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 21# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L 22#define RADEON_OV0_SCALE_CNTL 0x0420 23# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L 24# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L 25# define RADEON_SCALER_SIGNED_UV 0x00000010L 26# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L 27# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L 28# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L 29# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L 30# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L 31# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 32# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L 33# define RADEON_SCALER_SOURCE_15BPP 0x00000300L 34# define RADEON_SCALER_SOURCE_16BPP 0x00000400L 35# define RADEON_SCALER_SOURCE_32BPP 0x00000600L 36# define RADEON_SCALER_SOURCE_YUV9 0x00000900L 37# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L 38# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L 39# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L 40# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 41# define R200_SCALER_TEMPORAL_DEINT 0x00002000L 42# define RADEON_SCALER_CRTC_SEL 0x00004000L 43# define RADEON_SCALER_SMART_SWITCH 0x00008000L 44# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L 45# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L 46# define RADEON_SCALER_DIS_LIMIT 0x08000000L 47# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L 48# define RADEON_SCALER_INT_EMU 0x20000000L 49# define RADEON_SCALER_ENABLE 0x40000000L 50# define RADEON_SCALER_SOFT_RESET 0x80000000L 51#define RADEON_OV0_V_INC 0x0424 52#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 53# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 54# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 55#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C 56# define RADEON_OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L 57# define RADEON_OV0_P23_V_ACCUM_INIT_MASK 0x00ff8000L 58#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 59# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 60# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L 61#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 62# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 63# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L 64#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 65# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L 66# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L 67# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 68# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 69#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 70# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L 71# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L 72# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 73# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 74#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 75# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L 76# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L 77# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 78# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 79#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C 80#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 81#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 82#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 83#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 84#define RADEON_OV0_AUTO_FLIP_CNTRL 0x0470 85# define RADEON_OV0_SOFT_BUF_NUM_MASK 0x00000007 86# define RADEON_OV0_SOFT_REPEAT_FIELD_MASK 0x00000008 87# define RADEON_OV0_SOFT_REPEAT_FIELD 0x00000008 88# define RADEON_OV0_SOFT_BUF_ODD_MASK 0x00000010 89# define RADEON_OV0_SOFT_BUF_ODD 0x00000010 90# define RADEON_OV0_IGNORE_REPEAT_FIELD_MASK 0x00000020 91# define RADEON_OV0_IGNORE_REPEAT_FIELD 0x00000020 92# define RADEON_OV0_SOFT_EOF_TOGGLE_MASK (1 << 6) 93# define RADEON_OV0_SOFT_EOF_TOGGLE (1 << 6) 94# define RADEON_OV0_VID_PORT_SELECT_MASK (3 << 8) 95# define RADEON_OV0_VID_PORT_SELECT_PORT0 (0 << 8) 96# define RADEON_OV0_VID_PORT_SELECT_SOFTWARE (2 << 8) 97# define RADEON_OV0_P1_FIRST_LINE_EVEN_MASK 0x00010000 98# define RADEON_OV0_P1_FIRST_LINE_EVEN 0x00010000 99# define RADEON_OV0_SHIFT_EVEN_DOWN_MASK 0x00040000 100# define RADEON_OV0_SHIFT_EVEN_DOWN 0x00040000 101# define RADEON_OV0_SHIFT_ODD_DOWN_MASK 0x00080000 102# define RADEON_OV0_SHIFT_ODD_DOWN 0x00080000 103# define RADEON_OV0_FIELD_POL_SOURCE_MASK 0x00800000 104# define RADEON_OV0_FIELD_POL_SOURCE 0x00800000 105 106#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 107# define RADEON_OV0_DEINT_PAT_SHIFT 0 108# define RADEON_OV0_DEINT_PAT_MASK (0xfffff << 0) 109# define RADEON_OV0_DEINT_PAT_PNTR_SHIFT 24 110# define RADEON_OV0_DEINT_PAT_PNTR_MASK (0xf << 24) 111# define RADEON_OV0_DEINT_PAT_LEN_M1_SHIFT 28 112# define RADEON_OV0_DEINT_PAT_LEN_M1_MASK (0xf << 28) 113#define RADEON_OV0_H_INC 0x0480 114#define RADEON_OV0_STEP_BY 0x0484 115#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 116# define RADEON_OV0_P1_H_ACCUM_INIT_MASK 0x000f8000L 117# define RADEON_OV0_P1_PRESHIFT_MASK 0xf0000000L 118#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C 119# define RADEON_OV0_P23_H_ACCUM_INIT_MASK 0x000f8000L 120# define RADEON_OV0_P23_PRESHIFT_MASK 0x70000000L 121#define RADEON_OV0_P1_X_START_END 0x0494 122#define RADEON_OV0_P2_X_START_END 0x0498 123#define RADEON_OV0_P3_X_START_END 0x049C 124#define RADEON_OV0_FILTER_CNTL 0x04A0 125# define RADEON_OV0_HC_COEF_ON_HORZ_Y 0x0001 126# define RADEON_OV0_HC_COEF_ON_HORZ_UV 0x0002 127# define RADEON_OV0_HC_COEF_ON_VERT_Y 0x0004 128# define RADEON_OV0_HC_COEF_ON_VERT_UV 0x0008 129#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 130#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 131#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 132#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC 133#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 134#define RADEON_OV0_COLOUR_CNTL 0x04E0 135 136#define RADEON_OV0_VIDEO_KEY_CLR 0x04E4 137#define RADEON_OV0_VIDEO_KEY_MSK 0x04E8 138#define RADEON_OV0_GRAPHICS_KEY_CLR 0x04EC 139#define RADEON_OV0_GRAPHICS_KEY_MSK 0x04F0 140 141#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 142#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 143#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC 144#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 145 146#define RADEON_OV0_KEY_CNTL 0x04F4 147# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L 148# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L 149# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L 150# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L 151# define RADEON_VIDEO_KEY_FN_NE 0x00000003L 152# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L 153# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L 154# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L 155# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L 156# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L 157# define RADEON_CMP_MIX_MASK 0x00000100L 158# define RADEON_CMP_MIX_OR 0x00000000L 159# define RADEON_CMP_MIX_AND 0x00000100L 160#define RADEON_OV0_TEST 0x04F8 161 162#define RADEON_OV1_Y_X_START 0x0600 163#define RADEON_OV1_Y_X_END 0x0604 164#define RADEON_OV1_PIPELINE_CNTL 0x0608 165 166#define RADEON_OV0_GAMMA_0_F 0x0d40 167#define RADEON_OV0_GAMMA_10_1F 0x0d44 168#define RADEON_OV0_GAMMA_20_3F 0x0d48 169#define RADEON_OV0_GAMMA_40_7F 0x0d4c 170/* the registers that control gamma in the 80-37f range do not 171 exist on pre-R200 radeons */ 172#define RADEON_OV0_GAMMA_80_BF 0x0e00 173#define RADEON_OV0_GAMMA_C0_FF 0x0e04 174#define RADEON_OV0_GAMMA_100_13F 0x0e08 175#define RADEON_OV0_GAMMA_140_17F 0x0e0c 176#define RADEON_OV0_GAMMA_180_1BF 0x0e10 177#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 178#define RADEON_OV0_GAMMA_200_23F 0x0e18 179#define RADEON_OV0_GAMMA_240_27F 0x0e1c 180#define RADEON_OV0_GAMMA_280_2BF 0x0e20 181#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 182#define RADEON_OV0_GAMMA_300_33F 0x0e28 183#define RADEON_OV0_GAMMA_340_37F 0x0e2c 184#define RADEON_OV0_GAMMA_380_3BF 0x0d50 185#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 186#define RADEON_OV0_LIN_TRANS_A 0x0d20 187#define RADEON_OV0_LIN_TRANS_B 0x0d24 188#define RADEON_OV0_LIN_TRANS_C 0x0d28 189#define RADEON_OV0_LIN_TRANS_D 0x0d2c 190#define RADEON_OV0_LIN_TRANS_E 0x0d30 191#define RADEON_OV0_LIN_TRANS_F 0x0d34 192 193#define RADEON_SUBPIC_CNTL 0x0540 194 195#endif 196