1/*
2	Copyright 2007-2011 Haiku, Inc.  All rights reserved.
3	Distributed under the terms of the MIT license.
4
5	Authors:
6	Gerald Zajac
7*/
8
9#ifndef DRIVERINTERFACE_H
10#define DRIVERINTERFACE_H
11
12
13#include <Accelerant.h>
14#include <GraphicsDefs.h>
15#include <Drivers.h>
16#include <edid.h>
17#include <video_overlay.h>
18
19
20// This file contains info that is shared between the kernel driver and the
21// accelerant, and info that is shared among the source files of the accelerant.
22
23
24#define ENABLE_DEBUG_TRACE		// if defined, turns on debug output to syslog
25
26
27struct Benaphore {
28	sem_id	sem;
29	int32	count;
30
31	status_t Init(const char* name)
32	{
33		count = 0;
34		sem = create_sem(0, name);
35		return sem < 0 ? sem : B_OK;
36	}
37
38	status_t Acquire()
39	{
40		if (atomic_add(&count, 1) > 0)
41			return acquire_sem(sem);
42		return B_OK;
43	}
44
45	status_t Release()
46	{
47		if (atomic_add(&count, -1) > 1)
48			return release_sem(sem);
49		return B_OK;
50	}
51
52	void Delete()	{ delete_sem(sem); }
53};
54
55
56enum {
57	ATI_GET_SHARED_DATA = B_DEVICE_OP_CODES_END + 123,
58	ATI_DEVICE_NAME,
59	ATI_GET_EDID,
60	ATI_RUN_INTERRUPTS,
61	ATI_SET_VESA_DISPLAY_MODE
62};
63
64
65// Chip type numbers.  These are used to group the chips into related
66// groups.	See table chipTable in driver.c
67// Note that the order of the Mach64 chip types must not be changed because
68// < or > comparisons of the chip types are made.  They should be in the order
69// of the evolution of the chips.
70
71enum ChipType {
72	ATI_NONE = 0,
73
74	MACH64_264VT,
75	MACH64_264GT,
76	MACH64_264VTB,
77	MACH64_264GTB,
78	MACH64_264VT3,
79	MACH64_264GTDVD,
80	MACH64_264LT,
81	MACH64_264VT4,
82	MACH64_264GT2C,
83	MACH64_264GTPRO,
84	MACH64_264LTPRO,
85	MACH64_264XL,
86	MACH64_MOBILITY,
87		Mach64_ChipsEnd,		// marks end of Mach64's
88	RAGE128_GL,
89	RAGE128_MOBILITY,
90	RAGE128_PRO_GL,
91	RAGE128_PRO_VR,
92	RAGE128_PRO_ULTRA,
93	RAGE128_VR,
94};
95
96
97#define MACH64_FAMILY(chipType)		(chipType < Mach64_ChipsEnd)
98#define RAGE128_FAMILY(chipType)	(chipType > Mach64_ChipsEnd)
99
100
101
102enum MonitorType {
103	MT_VGA,			// monitor with analog VGA interface
104	MT_DVI,			// monitor with DVI interface
105	MT_LAPTOP		// laptop video display
106};
107
108
109// Mach64 parameters for computing register vaules and other parameters.
110
111struct M64_Params {
112	// Clock parameters
113	uint8	clockNumberToProgram;	// obtained from video BIOS
114	uint32	maxPixelClock;			// obtained from video BIOS
115	int		refFreq;				// obtained from video BIOS
116	int		refDivider;				// obtained from video BIOS
117	uint8	xClkPostDivider;
118	uint8	xClkRefDivider;
119	uint16	xClkPageFaultDelay;
120	uint16	xClkMaxRASDelay;
121	uint16	displayFIFODepth;
122	uint16	displayLoopLatency;
123	uint8	vClkPostDivider;
124	uint8	vClkFeedbackDivider;
125};
126
127
128struct R128_PLLParams {
129	uint16	reference_freq;
130	uint16	reference_div;
131	uint32	min_pll_freq;
132	uint32	max_pll_freq;
133	uint16	xclk;
134};
135
136
137struct R128_RAMSpec {		// All values in XCLKS
138	int  memReadLatency;	// Memory Read Latency
139	int  memBurstLen;		// Memory Burst Length
140	int  rasToCasDelay;		// RAS to CAS delay
141	int  rasPercentage;		// RAS percentage
142	int  writeRecovery;		// Write Recovery
143	int  casLatency;		// CAS Latency
144	int  readToWriteDelay;	// Read to Write Delay
145	int  loopLatency;		// Loop Latency
146	int  loopFudgeFactor;	// Add to memReadLatency to get loopLatency
147	const char *name;
148};
149
150
151struct VesaMode {
152	uint16			mode;		// VESA mode number
153	uint16			width;
154	uint16			height;
155	uint8			bitsPerPixel;
156};
157
158
159struct DisplayModeEx : display_mode {
160	uint8	bitsPerPixel;
161	uint16	bytesPerRow;		// number of bytes in one line/row
162};
163
164
165struct OverlayBuffer : overlay_buffer {
166	OverlayBuffer*	nextBuffer;	// pointer to next buffer in chain, NULL = none
167	uint32			size;		// size of overlay buffer
168};
169
170
171struct SharedInfo {
172	// Device ID info.
173	uint16	vendorID;			// PCI vendor ID, from pci_info
174	uint16	deviceID;			// PCI device ID, from pci_info
175	uint8	revision;			// PCI device revsion, from pci_info
176	ChipType chipType;			// indicates group in which chip belongs (a group has similar functionality)
177	char	chipName[32];		// user recognizable name of chip
178
179	bool	bAccelerantInUse;	// true = accelerant has been initialized
180	bool	bInterruptAssigned;	// card has a useable interrupt assigned to it
181
182	sem_id	vertBlankSem;		// vertical blank semaphore; if < 0, there is no semaphore
183
184	// Memory mappings.
185	area_id regsArea;			// area_id for the memory mapped registers. It will
186								// be cloned into accelerant's address space.
187	area_id videoMemArea;		// video memory area_id.  The addresses are shared with all teams.
188	addr_t	videoMemAddr;		// video memory addr as viewed from virtual memory
189	phys_addr_t	videoMemPCI;	// video memory addr as viewed from the PCI bus (for DMA)
190	uint32	videoMemSize; 		// video memory size in bytes.
191
192	uint32	cursorOffset;		// offset of cursor in video memory
193	uint32	frameBufferOffset;	// offset of frame buffer in video memory
194	uint32	maxFrameBufferSize;	// max available video memory for frame buffer
195
196	// Color spaces supported by current video chip/driver.
197	color_space	colorSpaces[6];
198	uint32	colorSpaceCount;	// number of color spaces in array colorSpaces
199
200	// List of screen modes.
201	area_id modeArea;			// area containing list of display modes the driver supports
202	uint32	modeCount;			// number of display modes in the list
203
204	DisplayModeEx displayMode;	// current display mode configuration
205
206	// List of VESA modes supported by current chip.
207	uint32		vesaModeTableOffset;	// offset of table in shared info
208	uint32		vesaModeCount;
209
210	uint16		cursorHotX;		// Cursor hot spot. Top left corner of the cursor
211	uint16		cursorHotY;		// is 0,0
212
213	edid1_info	edidInfo;
214	bool		bHaveEDID;		// true = EDID info from device is in edidInfo
215
216	Benaphore	engineLock;		// for serializing access to the acceleration engine
217	Benaphore	overlayLock;	// for overlay operations
218
219	int32		overlayAllocated;	// non-zero if overlay is allocated
220	uint32		overlayToken;
221	OverlayBuffer* overlayBuffer;	// pointer to linked list of buffers; NULL = none
222
223	MonitorType	displayType;
224
225	uint16		panelX;			// laptop LCD width
226	uint16		panelY;			// laptop LCD height
227	uint16		panelPowerDelay;
228
229	// Data members for Mach64 chips.
230	//-------------------------------
231
232	M64_Params	m64Params;			// parameters for Mach64 chips
233
234	// Data members for Rage128 chips.
235	//--------------------------------
236
237	R128_RAMSpec	r128MemSpec;	// Rage128 memory timing spec's
238	R128_PLLParams	r128PLLParams;	// Rage128 PLL parameters from video BIOS ROM
239
240	uint32		r128_dpGuiMasterCntl;	// flags for accelerated drawing
241};
242
243
244#endif	// DRIVERINTERFACE_H
245