1/* 2 * Copyright 2006-2012, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Some code borrowed from the Haiku EHCI driver 6 * 7 * Authors: 8 * Michael Lotz <mmlr@mlotz.ch> 9 * Jian Chiang <j.jian.chiang@gmail.com> 10 * J��r��me Duval <jerome.duval@gmail.com> 11 */ 12 13 14#include <module.h> 15#include <PCI.h> 16#include <USB3.h> 17#include <KernelExport.h> 18 19#include <util/AutoLock.h> 20 21#define TRACE_USB 22#include "xhci.h" 23 24#define USB_MODULE_NAME "xhci" 25 26pci_module_info *XHCI::sPCIModule = NULL; 27 28 29static int32 30xhci_std_ops(int32 op, ...) 31{ 32 switch (op) { 33 case B_MODULE_INIT: 34 TRACE_MODULE("xhci init module\n"); 35 return B_OK; 36 case B_MODULE_UNINIT: 37 TRACE_MODULE("xhci uninit module\n"); 38 return B_OK; 39 } 40 41 return EINVAL; 42} 43 44 45static const char* 46xhci_error_string(uint32 error) 47{ 48 switch (error) { 49 case COMP_INVALID: return "Invalid"; 50 case COMP_SUCCESS: return "Success"; 51 case COMP_DATA_BUFFER: return "Data buffer"; 52 case COMP_BABBLE: return "Babble detected"; 53 case COMP_USB_TRANSACTION: return "USB transaction"; 54 case COMP_TRB: return "TRB"; 55 case COMP_STALL: return "Stall"; 56 case COMP_RESOURCE: return "Resource"; 57 case COMP_BANDWIDTH: return "Bandwidth"; 58 case COMP_NO_SLOTS: return "No slots"; 59 case COMP_INVALID_STREAM: return "Invalid stream"; 60 case COMP_SLOT_NOT_ENABLED: return "Slot not enabled"; 61 case COMP_ENDPOINT_NOT_ENABLED: return "Endpoint not enabled"; 62 case COMP_SHORT_PACKET: return "Short packet"; 63 case COMP_RING_UNDERRUN: return "Ring underrun"; 64 case COMP_RING_OVERRUN: return "Ring overrun"; 65 case COMP_VF_RING_FULL: return "VF Event Ring Full"; 66 case COMP_PARAMETER: return "Parameter"; 67 case COMP_BANDWIDTH_OVERRUN: return "Bandwidth overrun"; 68 case COMP_CONTEXT_STATE: return "Context state"; 69 case COMP_NO_PING_RESPONSE: return "No ping response"; 70 case COMP_EVENT_RING_FULL: return "Event ring full"; 71 case COMP_INCOMPATIBLE_DEVICE: return "Incompatible device"; 72 case COMP_MISSED_SERVICE: return "Missed service"; 73 case COMP_COMMAND_RING_STOPPED: return "Command ring stopped"; 74 case COMP_COMMAND_ABORTED: return "Command aborted"; 75 case COMP_STOPPED: return "Stopped"; 76 case COMP_LENGTH_INVALID: return "Length invalid"; 77 case COMP_MAX_EXIT_LATENCY: return "Max exit latency too large"; 78 case COMP_ISOC_OVERRUN: return "Isoch buffer overrun"; 79 case COMP_EVENT_LOST: return "Event lost"; 80 case COMP_UNDEFINED: return "Undefined"; 81 case COMP_INVALID_STREAM_ID: return "Invalid stream ID"; 82 case COMP_SECONDARY_BANDWIDTH: return "Secondary bandwidth"; 83 case COMP_SPLIT_TRANSACTION: return "Split transaction"; 84 85 default: return "Undefined"; 86 } 87} 88 89 90usb_host_controller_info xhci_module = { 91 { 92 "busses/usb/xhci", 93 0, 94 xhci_std_ops 95 }, 96 NULL, 97 XHCI::AddTo 98}; 99 100 101module_info *modules[] = { 102 (module_info *)&xhci_module, 103 NULL 104}; 105 106 107XHCI::XHCI(pci_info *info, Stack *stack) 108 : BusManager(stack), 109 fCapabilityRegisters(NULL), 110 fOperationalRegisters(NULL), 111 fRegisterArea(-1), 112 fPCIInfo(info), 113 fStack(stack), 114 fErstArea(-1), 115 fDcbaArea(-1), 116 fSpinlock(B_SPINLOCK_INITIALIZER), 117 fCmdCompSem(-1), 118 fFinishTransfersSem(-1), 119 fFinishThread(-1), 120 fStopThreads(false), 121 fFinishedHead(NULL), 122 fRootHub(NULL), 123 fRootHubAddress(0), 124 fPortCount(0), 125 fSlotCount(0), 126 fScratchpadCount(0), 127 fEventSem(-1), 128 fEventThread(-1), 129 fEventIdx(0), 130 fCmdIdx(0), 131 fEventCcs(1), 132 fCmdCcs(1) 133{ 134 if (BusManager::InitCheck() < B_OK) { 135 TRACE_ERROR("bus manager failed to init\n"); 136 return; 137 } 138 139 TRACE("constructing new XHCI host controller driver\n"); 140 fInitOK = false; 141 142 // enable busmaster and memory mapped access 143 uint16 command = sPCIModule->read_pci_config(fPCIInfo->bus, 144 fPCIInfo->device, fPCIInfo->function, PCI_command, 2); 145 command &= ~(PCI_command_io | PCI_command_int_disable); 146 command |= PCI_command_master | PCI_command_memory; 147 148 sPCIModule->write_pci_config(fPCIInfo->bus, fPCIInfo->device, 149 fPCIInfo->function, PCI_command, 2, command); 150 151 // map the registers 152 uint32 offset = fPCIInfo->u.h0.base_registers[0] & (B_PAGE_SIZE - 1); 153 phys_addr_t physicalAddress = fPCIInfo->u.h0.base_registers[0] - offset; 154 size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset 155 + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); 156 157 TRACE("map physical memory 0x%08lx (base: 0x%08" B_PRIxPHYSADDR "; offset:" 158 " %lx); size: %ld\n", fPCIInfo->u.h0.base_registers[0], 159 physicalAddress, offset, fPCIInfo->u.h0.base_register_sizes[0]); 160 161 fRegisterArea = map_physical_memory("XHCI memory mapped registers", 162 physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS, 163 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_READ_AREA | B_WRITE_AREA, 164 (void **)&fCapabilityRegisters); 165 if (fRegisterArea < B_OK) { 166 TRACE("failed to map register memory\n"); 167 return; 168 } 169 170 uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH); 171 fCapabilityRegisters += offset; 172 TRACE("mapped capability length: 0x%lx\n", fCapabilityLength); 173 fOperationalRegisters = fCapabilityRegisters + HCI_CAPLENGTH(hciCapLength); 174 fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF); 175 fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF); 176 TRACE("mapped capability registers: 0x%08lx\n", (uint32)fCapabilityRegisters); 177 TRACE("mapped operational registers: 0x%08lx\n", (uint32)fOperationalRegisters); 178 TRACE("mapped runtime registers: 0x%08lx\n", (uint32)fRuntimeRegisters); 179 TRACE("mapped doorbell registers: 0x%08lx\n", (uint32)fDoorbellRegisters); 180 181 TRACE("structural parameters1: 0x%08lx\n", ReadCapReg32(XHCI_HCSPARAMS1)); 182 TRACE("structural parameters2: 0x%08lx\n", ReadCapReg32(XHCI_HCSPARAMS2)); 183 TRACE("structural parameters3: 0x%08lx\n", ReadCapReg32(XHCI_HCSPARAMS3)); 184 TRACE("capability parameters: 0x%08lx\n", ReadCapReg32(XHCI_HCCPARAMS)); 185 186 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 187 uint32 eec = 0xffffffff; 188 uint32 eecp = HCS0_XECP(cparams) << 2; 189 for (; eecp != 0 && XECP_NEXT(eec); eecp += XECP_NEXT(eec) << 2) { 190 eec = ReadCapReg32(eecp); 191 if (XECP_ID(eec) != XHCI_LEGSUP_CAPID) 192 continue; 193 } 194 TRACE("eecp register: 0x%04lx\n", eecp); 195 if (eec & XHCI_LEGSUP_BIOSOWNED) { 196 TRACE_ALWAYS("the host controller is bios owned, claiming" 197 " ownership\n"); 198 WriteCapReg32(eecp, eec | XHCI_LEGSUP_OSOWNED); 199 200 for (int32 i = 0; i < 20; i++) { 201 eec = ReadCapReg32(eecp); 202 203 if ((eec & XHCI_LEGSUP_BIOSOWNED) == 0) 204 break; 205 206 TRACE_ALWAYS("controller is still bios owned, waiting\n"); 207 snooze(50000); 208 } 209 210 if (eec & XHCI_LEGSUP_BIOSOWNED) { 211 TRACE_ERROR("bios won't give up control over the host " 212 "controller (ignoring)\n"); 213 } else if (eec & XHCI_LEGSUP_OSOWNED) { 214 TRACE_ALWAYS("successfully took ownership of the host " 215 "controller\n"); 216 } 217 218 // Force off the BIOS owned flag, and clear all SMIs. Some BIOSes 219 // do indicate a successful handover but do not remove their SMIs 220 // and then freeze the system when interrupts are generated. 221 WriteCapReg32(eecp, eec & ~XHCI_LEGSUP_BIOSOWNED); 222 } 223 WriteCapReg32(eecp + XHCI_LEGCTLSTS, XHCI_LEGCTLSTS_DISABLE_SMI); 224 225 // halt the host controller 226 if (ControllerHalt() < B_OK) { 227 return; 228 } 229 230 // reset the host controller 231 if (ControllerReset() < B_OK) { 232 TRACE_ERROR("host controller failed to reset\n"); 233 return; 234 } 235 236 fCmdCompSem = create_sem(0, "XHCI Command Complete"); 237 fFinishTransfersSem = create_sem(0, "XHCI Finish Transfers"); 238 fEventSem = create_sem(0, "XHCI Event"); 239 if (fFinishTransfersSem < B_OK || fCmdCompSem < B_OK || fEventSem < B_OK) { 240 TRACE_ERROR("failed to create semaphores\n"); 241 return; 242 } 243 244 // create finisher service thread 245 fFinishThread = spawn_kernel_thread(FinishThread, "xhci finish thread", 246 B_NORMAL_PRIORITY, (void *)this); 247 resume_thread(fFinishThread); 248 249 // create finisher service thread 250 fEventThread = spawn_kernel_thread(EventThread, "xhci event thread", 251 B_NORMAL_PRIORITY, (void *)this); 252 resume_thread(fEventThread); 253 254 // Install the interrupt handler 255 TRACE("installing interrupt handler\n"); 256 install_io_interrupt_handler(fPCIInfo->u.h0.interrupt_line, 257 InterruptHandler, (void *)this, 0); 258 259 memset(fPortSpeeds, 0, sizeof(fPortSpeeds)); 260 memset(fPortSlots, 0, sizeof(fPortSlots)); 261 memset(fDevices, 0, sizeof(fDevices)); 262 263 fInitOK = true; 264 TRACE("XHCI host controller driver constructed\n"); 265} 266 267 268XHCI::~XHCI() 269{ 270 TRACE("tear down XHCI host controller driver\n"); 271 272 WriteOpReg(XHCI_CMD, 0); 273 274 int32 result = 0; 275 fStopThreads = true; 276 delete_sem(fCmdCompSem); 277 delete_sem(fFinishTransfersSem); 278 delete_sem(fEventSem); 279 delete_area(fRegisterArea); 280 delete_area(fErstArea); 281 for (uint32 i = 0; i < fScratchpadCount; i++) 282 delete_area(fScratchpadArea[i]); 283 delete_area(fDcbaArea); 284 wait_for_thread(fFinishThread, &result); 285 wait_for_thread(fEventThread, &result); 286 put_module(B_PCI_MODULE_NAME); 287} 288 289 290status_t 291XHCI::Start() 292{ 293 TRACE("starting XHCI host controller\n"); 294 TRACE("usbcmd: 0x%08lx; usbsts: 0x%08lx\n", ReadOpReg(XHCI_CMD), 295 ReadOpReg(XHCI_STS)); 296 297 if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) { 298 TRACE_ERROR("Controller does not support 4K page size.\n"); 299 return B_ERROR; 300 } 301 302 // read port count from capability register 303 uint32 capabilities = ReadCapReg32(XHCI_HCSPARAMS1); 304 305 fPortCount = HCS_MAX_PORTS(capabilities); 306 if (fPortCount == 0) { 307 TRACE_ERROR("Invalid number of ports: %u\n", fPortCount); 308 fPortCount = 0; 309 return B_ERROR; 310 } 311 fSlotCount = HCS_MAX_SLOTS(capabilities); 312 WriteOpReg(XHCI_CONFIG, fSlotCount); 313 314 // find out which protocol is used for each port 315 uint8 portFound = 0; 316 uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS); 317 uint32 eec = 0xffffffff; 318 uint32 eecp = HCS0_XECP(cparams) << 2; 319 for (; eecp != 0 && XECP_NEXT(eec) && portFound < fPortCount; 320 eecp += XECP_NEXT(eec) << 2) { 321 eec = ReadCapReg32(eecp); 322 if (XECP_ID(eec) != XHCI_SUPPORTED_PROTOCOLS_CAPID) 323 continue; 324 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) > 3) 325 continue; 326 uint32 temp = ReadCapReg32(eecp + 8); 327 uint32 offset = XHCI_SUPPORTED_PROTOCOLS_1_OFFSET(temp); 328 uint32 count = XHCI_SUPPORTED_PROTOCOLS_1_COUNT(temp); 329 if (offset == 0 || count == 0) 330 continue; 331 offset--; 332 for (uint32 i = offset; i < offset + count; i++) { 333 if (XHCI_SUPPORTED_PROTOCOLS_0_MAJOR(eec) == 0x3) 334 fPortSpeeds[i] = USB_SPEED_SUPER; 335 else 336 fPortSpeeds[i] = USB_SPEED_HIGHSPEED; 337 TRACE("speed for port %ld is %s\n", i, 338 fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high"); 339 } 340 portFound += count; 341 } 342 343 uint32 params2 = ReadCapReg32(XHCI_HCSPARAMS2); 344 fScratchpadCount = HCS_MAX_SC_BUFFERS(params2); 345 if (fScratchpadCount > XHCI_MAX_SCRATCHPADS) { 346 TRACE_ERROR("Invalid number of scratchpads: %u\n", fScratchpadCount); 347 return B_ERROR; 348 } 349 350 uint32 params3 = ReadCapReg32(XHCI_HCSPARAMS3); 351 fExitLatMax = HCS_U1_DEVICE_LATENCY(params3) 352 + HCS_U2_DEVICE_LATENCY(params3); 353 354 WriteOpReg(XHCI_DNCTRL, 0); 355 356 // allocate Device Context Base Address array 357 addr_t dmaAddress; 358 fDcbaArea = fStack->AllocateArea((void **)&fDcba, (void**)&dmaAddress, 359 sizeof(*fDcba), "DCBA Area"); 360 if (fDcbaArea < B_OK) { 361 TRACE_ERROR("unable to create the DCBA area\n"); 362 return B_ERROR; 363 } 364 memset(fDcba, 0, sizeof(*fDcba)); 365 memset(fScratchpadArea, 0, sizeof(fScratchpadArea)); 366 memset(fScratchpad, 0, sizeof(fScratchpad)); 367 368 // setting the first address to the scratchpad array address 369 fDcba->baseAddress[0] = dmaAddress 370 + offsetof(struct xhci_device_context_array, scratchpad); 371 372 // fill up the scratchpad array with scratchpad pages 373 for (uint32 i = 0; i < fScratchpadCount; i++) { 374 addr_t scratchDmaAddress; 375 fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i], 376 (void**)&scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area"); 377 if (fScratchpadArea[i] < B_OK) { 378 TRACE_ERROR("unable to create the scratchpad area\n"); 379 return B_ERROR; 380 } 381 fDcba->scratchpad[i] = scratchDmaAddress; 382 } 383 384 TRACE("setting DCBAAP %lx\n", dmaAddress); 385 WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress); 386 WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0); 387 388 // allocate Event Ring Segment Table 389 uint8 *addr; 390 fErstArea = fStack->AllocateArea((void **)&addr, (void**)&dmaAddress, 391 (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 392 + sizeof(xhci_erst_element), 393 "USB XHCI ERST CMD_RING and EVENT_RING Area"); 394 395 if (fErstArea < B_OK) { 396 TRACE_ERROR("unable to create the ERST AND RING area\n"); 397 delete_area(fDcbaArea); 398 return B_ERROR; 399 } 400 fErst = (xhci_erst_element *)addr; 401 memset(fErst, 0, (XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb) 402 + sizeof(xhci_erst_element)); 403 404 // fill with Event Ring Segment Base Address and Event Ring Segment Size 405 fErst->rs_addr = (uint64)(dmaAddress + sizeof(xhci_erst_element)); 406 fErst->rs_size = XHCI_MAX_EVENTS; 407 fErst->rsvdz = 0; 408 409 addr += sizeof(xhci_erst_element); 410 fEventRing = (xhci_trb *)addr; 411 addr += XHCI_MAX_EVENTS * sizeof(xhci_trb); 412 fCmdRing = (xhci_trb *)addr; 413 414 TRACE("setting ERST size\n"); 415 WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 416 417 TRACE("setting ERDP addr = 0x%llx\n", fErst->rs_addr); 418 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr); 419 WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0); 420 421 TRACE("setting ERST base addr = 0x%lx\n", dmaAddress); 422 WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress); 423 WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0); 424 425 dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS 426 * sizeof(xhci_trb); 427 TRACE("setting CRCR addr = 0x%lx\n", dmaAddress); 428 WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS); 429 WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0); 430 //link trb 431 fCmdRing[XHCI_MAX_COMMANDS - 1].qwtrb0 = dmaAddress; 432 433 TRACE("setting interrupt rate\n"); 434 WriteRunReg32(XHCI_IMOD(0), 160); // 25000 irq/s 435 436 TRACE("enabling interrupt\n"); 437 WriteRunReg32(XHCI_IMAN(0), ReadRunReg32(XHCI_IMAN(0)) | IMAN_INTR_ENA); 438 439 WriteOpReg(XHCI_CMD, CMD_RUN | CMD_EIE | CMD_HSEIE); 440 441 // wait for start up state 442 int32 tries = 100; 443 while ((ReadOpReg(XHCI_STS) & STS_HCH) != 0) { 444 snooze(1000); 445 if (tries-- < 0) { 446 TRACE_ERROR("start up timeout\n"); 447 break; 448 } 449 } 450 451 fRootHubAddress = AllocateAddress(); 452 fRootHub = new(std::nothrow) XHCIRootHub(RootObject(), fRootHubAddress); 453 if (!fRootHub) { 454 TRACE_ERROR("no memory to allocate root hub\n"); 455 return B_NO_MEMORY; 456 } 457 458 if (fRootHub->InitCheck() < B_OK) { 459 TRACE_ERROR("root hub failed init check\n"); 460 return fRootHub->InitCheck(); 461 } 462 463 SetRootHub(fRootHub); 464 465 TRACE_ALWAYS("successfully started the controller\n"); 466#ifdef TRACE_USB 467 TRACE("No-Op test\n"); 468 Noop(); 469#endif 470 return BusManager::Start(); 471} 472 473 474status_t 475XHCI::SubmitTransfer(Transfer *transfer) 476{ 477 // short circuit the root hub 478 if (transfer->TransferPipe()->DeviceAddress() == fRootHubAddress) 479 return fRootHub->ProcessTransfer(this, transfer); 480 481 TRACE("SubmitTransfer()\n"); 482 Pipe *pipe = transfer->TransferPipe(); 483 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 484 return B_UNSUPPORTED; 485 if ((pipe->Type() & USB_OBJECT_CONTROL_PIPE) != 0) 486 return SubmitControlRequest(transfer); 487 return SubmitNormalRequest(transfer); 488} 489 490 491status_t 492XHCI::SubmitControlRequest(Transfer *transfer) 493{ 494 Pipe *pipe = transfer->TransferPipe(); 495 usb_request_data *requestData = transfer->RequestData(); 496 bool directionIn = (requestData->RequestType & USB_REQTYPE_DEVICE_IN) != 0; 497 498 TRACE("SubmitControlRequest() length %d\n", requestData->Length); 499 500 xhci_td *setupDescriptor = CreateDescriptor(requestData->Length); 501 502 // set SetupStage 503 uint8 index = 0; 504 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) | TRB_2_BYTES(8); 505 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_SETUP_STAGE) 506 | TRB_3_IDT_BIT | TRB_3_CYCLE_BIT; 507 if (requestData->Length > 0) { 508 setupDescriptor->trbs[index].dwtrb3 |= directionIn ? TRB_3_TRT_IN 509 : TRB_3_TRT_OUT; 510 } 511 memcpy(&setupDescriptor->trbs[index].qwtrb0, requestData, 512 sizeof(usb_request_data)); 513 514 index++; 515 516 if (requestData->Length > 0) { 517 // set DataStage if any 518 setupDescriptor->trbs[index].qwtrb0 = setupDescriptor->buffer_phy[0]; 519 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 520 | TRB_2_BYTES(requestData->Length) 521 | TRB_2_TD_SIZE(transfer->VectorCount()); 522 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_DATA_STAGE) 523 | (directionIn ? TRB_3_DIR_IN : 0) | TRB_3_CYCLE_BIT; 524 525 // TODO copy data for out transfers 526 index++; 527 } 528 529 // set StatusStage 530 setupDescriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0); 531 setupDescriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_STATUS_STAGE) 532 | ((directionIn && requestData->Length > 0) ? 0 : TRB_3_DIR_IN) 533 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 534 535 setupDescriptor->trb_count = index + 1; 536 537 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 538 uint8 id = XHCI_ENDPOINT_ID(pipe); 539 if (id >= XHCI_MAX_ENDPOINTS) 540 return B_BAD_VALUE; 541 setupDescriptor->transfer = transfer; 542 _LinkDescriptorForPipe(setupDescriptor, endpoint); 543 544 TRACE("SubmitControlRequest() request linked\n"); 545 546 Ring(endpoint->device->slot, id); 547 548 return B_OK; 549} 550 551 552status_t 553XHCI::SubmitNormalRequest(Transfer *transfer) 554{ 555 TRACE("SubmitNormalRequest() length %ld\n", transfer->DataLength()); 556 Pipe *pipe = transfer->TransferPipe(); 557 uint8 id = XHCI_ENDPOINT_ID(pipe); 558 if (id >= XHCI_MAX_ENDPOINTS) 559 return B_BAD_VALUE; 560 bool directionIn = (pipe->Direction() == Pipe::In); 561 562 xhci_td *descriptor = CreateDescriptorChain(transfer->DataLength()); 563 descriptor->trb_count = descriptor->buffer_count; 564 565 // set NormalStage 566 uint8 index; 567 for (index = 0; index < descriptor->buffer_count; index++) { 568 descriptor->trbs[index].qwtrb0 = descriptor->buffer_phy[index]; 569 descriptor->trbs[index].dwtrb2 = TRB_2_IRQ(0) 570 | TRB_2_BYTES(descriptor->buffer_size[index]) 571 | TRB_2_TD_SIZE(descriptor->trb_count); 572 descriptor->trbs[index].dwtrb3 = TRB_3_TYPE(TRB_TYPE_NORMAL) 573 | TRB_3_CYCLE_BIT; 574 } 575 if (descriptor->trb_count > 0) 576 descriptor->trbs[index - 1].dwtrb3 |= TRB_3_IOC_BIT; 577 578 if (!directionIn) { 579 TRACE("copying out iov count %ld\n", transfer->VectorCount()); 580 WriteDescriptorChain(descriptor, transfer->Vector(), 581 transfer->VectorCount()); 582 } 583 /* memcpy(descriptor->buffer_log[index], 584 (uint8 *)transfer->Vector()[index].iov_base, transfer->VectorLength()); 585 }*/ 586 587 xhci_endpoint *endpoint = (xhci_endpoint *)pipe->ControllerCookie(); 588 descriptor->transfer = transfer; 589 _LinkDescriptorForPipe(descriptor, endpoint); 590 591 TRACE("SubmitNormalRequest() request linked\n"); 592 593 Ring(endpoint->device->slot, id); 594 595 return B_OK; 596} 597 598 599status_t 600XHCI::CancelQueuedTransfers(Pipe *pipe, bool force) 601{ 602 return B_OK; 603} 604 605 606status_t 607XHCI::NotifyPipeChange(Pipe *pipe, usb_change change) 608{ 609 TRACE("pipe change %d for pipe %p (%d)\n", change, pipe, 610 pipe->EndpointAddress()); 611 switch (change) { 612 case USB_CHANGE_CREATED: 613 _InsertEndpointForPipe(pipe); 614 break; 615 case USB_CHANGE_DESTROYED: 616 _RemoveEndpointForPipe(pipe); 617 break; 618 619 case USB_CHANGE_PIPE_POLICY_CHANGED: { 620 // ToDo: for isochronous pipes we might need to adapt to new 621 // pipe policy settings here 622 break; 623 } 624 } 625 626 return B_OK; 627} 628 629 630status_t 631XHCI::AddTo(Stack *stack) 632{ 633#ifdef TRACE_USB 634 set_dprintf_enabled(true); 635#endif 636 637 if (!sPCIModule) { 638 status_t status = get_module(B_PCI_MODULE_NAME, 639 (module_info **)&sPCIModule); 640 if (status < B_OK) { 641 TRACE_MODULE_ERROR("getting pci module failed! 0x%08lx\n", status); 642 return status; 643 } 644 } 645 646 TRACE_MODULE("searching devices\n"); 647 bool found = false; 648 pci_info *item = new(std::nothrow) pci_info; 649 if (!item) { 650 sPCIModule = NULL; 651 put_module(B_PCI_MODULE_NAME); 652 return B_NO_MEMORY; 653 } 654 655 for (int32 i = 0; sPCIModule->get_nth_pci_info(i, item) >= B_OK; i++) { 656 if (item->class_base == PCI_serial_bus && item->class_sub == PCI_usb 657 && item->class_api == PCI_usb_xhci) { 658 if (item->u.h0.interrupt_line == 0 659 || item->u.h0.interrupt_line == 0xFF) { 660 TRACE_MODULE_ERROR("found device with invalid IRQ - check IRQ " 661 "assignment\n"); 662 continue; 663 } 664 665 TRACE_MODULE("found device at IRQ %u\n", 666 item->u.h0.interrupt_line); 667 XHCI *bus = new(std::nothrow) XHCI(item, stack); 668 if (!bus) { 669 delete item; 670 sPCIModule = NULL; 671 put_module(B_PCI_MODULE_NAME); 672 return B_NO_MEMORY; 673 } 674 675 if (bus->InitCheck() < B_OK) { 676 TRACE_MODULE_ERROR("bus failed init check\n"); 677 delete bus; 678 continue; 679 } 680 681 // the bus took it away 682 item = new(std::nothrow) pci_info; 683 684 bus->Start(); 685 stack->AddBusManager(bus); 686 found = true; 687 } 688 } 689 690 if (!found) { 691 TRACE_MODULE_ERROR("no devices found\n"); 692 delete item; 693 sPCIModule = NULL; 694 put_module(B_PCI_MODULE_NAME); 695 return ENODEV; 696 } 697 698 delete item; 699 return B_OK; 700} 701 702 703xhci_td * 704XHCI::CreateDescriptorChain(size_t bufferSize) 705{ 706 size_t packetSize = B_PAGE_SIZE * 16; 707 int32 trbCount = (bufferSize + packetSize - 1) / packetSize; 708 // keep one trb for linking 709 int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) / (XHCI_MAX_TRBS_PER_TD - 1); 710 711 xhci_td *first = NULL; 712 xhci_td *last = NULL; 713 for (int32 i = 0; i < tdCount; i++) { 714 xhci_td *descriptor = CreateDescriptor(0); 715 if (!descriptor) { 716 //FreeDescriptorChain(firstDescriptor); 717 return NULL; 718 } else if (first == NULL) 719 first = descriptor; 720 721 uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD); 722 TRACE("CreateDescriptorChain trbs %d for td %ld\n", trbs, i); 723 for (int j = 0; j < trbs; j++) { 724 if (fStack->AllocateChunk(&descriptor->buffer_log[j], 725 (void **)&descriptor->buffer_phy[j], 726 min_c(packetSize, bufferSize)) < B_OK) { 727 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 728 bufferSize); 729 return NULL; 730 } 731 732 descriptor->buffer_size[j] = min_c(packetSize, bufferSize); 733 bufferSize -= descriptor->buffer_size[j]; 734 TRACE("CreateDescriptorChain allocated %ld for trb %d\n", 735 descriptor->buffer_size[j], j); 736 } 737 738 descriptor->buffer_count = trbs; 739 trbCount -= trbs; 740 if (last != NULL) 741 last->next = descriptor; 742 last = descriptor; 743 } 744 745 return first; 746} 747 748 749xhci_td * 750XHCI::CreateDescriptor(size_t bufferSize) 751{ 752 xhci_td *result; 753 addr_t physicalAddress; 754 755 if (fStack->AllocateChunk((void **)&result, (void**)&physicalAddress, 756 sizeof(xhci_td)) < B_OK) { 757 TRACE_ERROR("failed to allocate a transfer descriptor\n"); 758 return NULL; 759 } 760 761 result->this_phy = (addr_t)physicalAddress; 762 result->buffer_size[0] = bufferSize; 763 result->trb_count = 0; 764 result->buffer_count = 1; 765 if (bufferSize <= 0) { 766 result->buffer_log[0] = NULL; 767 result->buffer_phy[0] = 0; 768 return result; 769 } 770 771 if (fStack->AllocateChunk(&result->buffer_log[0], 772 (void **)&result->buffer_phy[0], bufferSize) < B_OK) { 773 TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n", 774 bufferSize); 775 fStack->FreeChunk(result, (void *)result->this_phy, sizeof(xhci_td)); 776 return NULL; 777 } 778 779 return result; 780} 781 782 783void 784XHCI::FreeDescriptor(xhci_td *descriptor) 785{ 786 if (!descriptor) 787 return; 788 789 for (int i = 0; i < descriptor->buffer_count; i++) { 790 if (descriptor->buffer_size[i] == 0) 791 continue; 792 TRACE("FreeDescriptor buffer %d buffer_size %ld\n", i, 793 descriptor->buffer_size[i]); 794 fStack->FreeChunk(descriptor->buffer_log[i], 795 (void *)descriptor->buffer_phy[i], descriptor->buffer_size[i]); 796 } 797 798 fStack->FreeChunk(descriptor, (void *)descriptor->this_phy, 799 sizeof(xhci_td)); 800} 801 802 803size_t 804XHCI::WriteDescriptorChain(xhci_td *descriptor, iovec *vector, 805 size_t vectorCount) 806{ 807 xhci_td *current = descriptor; 808 uint8 trbIndex = 0; 809 size_t actualLength = 0; 810 uint8 vectorIndex = 0; 811 size_t vectorOffset = 0; 812 size_t bufferOffset = 0; 813 814 while (current != NULL) { 815 if (current->buffer_log == NULL) 816 break; 817 818 while (true) { 819 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 820 vector[vectorIndex].iov_len - vectorOffset); 821 822 TRACE("copying %ld bytes to bufferOffset %ld from" 823 " vectorOffset %ld at index %d of %ld\n", length, bufferOffset, 824 vectorOffset, vectorIndex, vectorCount); 825 memcpy((uint8 *)current->buffer_log[trbIndex] + bufferOffset, 826 (uint8 *)vector[vectorIndex].iov_base + vectorOffset, length); 827 828 actualLength += length; 829 vectorOffset += length; 830 bufferOffset += length; 831 832 if (vectorOffset >= vector[vectorIndex].iov_len) { 833 if (++vectorIndex >= vectorCount) { 834 TRACE("wrote descriptor chain (%ld bytes, no more vectors)\n", 835 actualLength); 836 return actualLength; 837 } 838 839 vectorOffset = 0; 840 } 841 842 if (bufferOffset >= current->buffer_size[trbIndex]) { 843 if (++trbIndex >= current->buffer_count) 844 break; 845 bufferOffset = 0; 846 } 847 } 848 849 current = current->next; 850 trbIndex = 0; 851 } 852 853 TRACE("wrote descriptor chain (%ld bytes)\n", actualLength); 854 return actualLength; 855} 856 857 858size_t 859XHCI::ReadDescriptorChain(xhci_td *descriptor, iovec *vector, 860 size_t vectorCount) 861{ 862 xhci_td *current = descriptor; 863 uint8 trbIndex = 0; 864 size_t actualLength = 0; 865 uint8 vectorIndex = 0; 866 size_t vectorOffset = 0; 867 size_t bufferOffset = 0; 868 869 while (current != NULL) { 870 if (current->buffer_log == NULL) 871 break; 872 873 while (true) { 874 size_t length = min_c(current->buffer_size[trbIndex] - bufferOffset, 875 vector[vectorIndex].iov_len - vectorOffset); 876 877 TRACE("copying %ld bytes to vectorOffset %ld from" 878 " bufferOffset %ld at index %d of %ld\n", length, vectorOffset, 879 bufferOffset, vectorIndex, vectorCount); 880 memcpy((uint8 *)vector[vectorIndex].iov_base + vectorOffset, 881 (uint8 *)current->buffer_log[trbIndex] + bufferOffset, length); 882 883 actualLength += length; 884 vectorOffset += length; 885 bufferOffset += length; 886 887 if (vectorOffset >= vector[vectorIndex].iov_len) { 888 if (++vectorIndex >= vectorCount) { 889 TRACE("read descriptor chain (%ld bytes, no more vectors)\n", 890 actualLength); 891 return actualLength; 892 } 893 894 vectorOffset = 0; 895 } 896 897 if (bufferOffset >= current->buffer_size[trbIndex]) { 898 if (++trbIndex >= current->buffer_count) 899 break; 900 bufferOffset = 0; 901 } 902 } 903 904 current = current->next; 905 trbIndex = 0; 906 } 907 908 TRACE("read descriptor chain (%ld bytes)\n", actualLength); 909 return actualLength; 910} 911 912 913Device * 914XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort, 915 usb_speed speed) 916{ 917 TRACE("AllocateDevice hubAddress %d hubPort %d speed %d\n", hubAddress, 918 hubPort, speed); 919 GetPortSpeed(hubPort - 1, &speed); 920 TRACE("speed %d\n", speed); 921 922 uint8 slot = XHCI_MAX_SLOTS; 923 if (EnableSlot(&slot) != B_OK) { 924 TRACE_ERROR("AllocateDevice() failed enable slot\n"); 925 return NULL; 926 } 927 928 if (slot == 0 || slot > fSlotCount) { 929 TRACE_ERROR("AllocateDevice() bad slot\n"); 930 return NULL; 931 } 932 933 if (fDevices[slot].state != XHCI_STATE_DISABLED) { 934 TRACE_ERROR("AllocateDevice() slot already used\n"); 935 return NULL; 936 } 937 938 struct xhci_device *device = &fDevices[slot]; 939 memset(device, 0, sizeof(struct xhci_device)); 940 device->state = XHCI_STATE_ENABLED; 941 device->slot = slot; 942 943 device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx, 944 (void**)&device->input_ctx_addr, sizeof(*device->input_ctx), 945 "XHCI input context"); 946 if (device->input_ctx_area < B_OK) { 947 TRACE_ERROR("unable to create a input context area\n"); 948 return NULL; 949 } 950 951 memset(device->input_ctx, 0, sizeof(*device->input_ctx)); 952 device->input_ctx->input.dropFlags = 0; 953 device->input_ctx->input.addFlags = 3; 954 955 uint32 route = 0; 956 uint8 routePort = hubPort; 957 uint8 rhPort = 0; 958 for (Device *hubDevice = parent; hubDevice != RootObject(); 959 hubDevice = (Device *)hubDevice->Parent()) { 960 route *= 16; 961 if (hubPort > 15) 962 route += 15; 963 else 964 route += routePort; 965 rhPort = routePort; 966 routePort = hubDevice->HubPort(); 967 } 968 969 device->input_ctx->slot.dwslot0 = SLOT_0_NUM_ENTRIES(1) | SLOT_0_ROUTE(route); 970 //device->input_ctx->slot.dwslot0 = 971 // SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1) | SLOT_0_ROUTE(route); 972 973 // add the speed 974 switch (speed) { 975 case USB_SPEED_LOWSPEED: 976 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(2); 977 break; 978 case USB_SPEED_HIGHSPEED: 979 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(3); 980 break; 981 case USB_SPEED_FULLSPEED: 982 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(1); 983 break; 984 case USB_SPEED_SUPER: 985 device->input_ctx->slot.dwslot0 |= SLOT_0_SPEED(4); 986 break; 987 default: 988 TRACE_ERROR("unknown usb speed\n"); 989 break; 990 } 991 992 device->input_ctx->slot.dwslot1 = SLOT_1_RH_PORT(rhPort); // TODO enable power save 993 device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0); 994 if (0) 995 device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort); 996 device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) | SLOT_3_DEVICE_ADDRESS(0); 997 998 TRACE("slot 0x%lx 0x%lx 0x%lx 0x%lx\n", device->input_ctx->slot.dwslot0, 999 device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2, 1000 device->input_ctx->slot.dwslot3); 1001 1002 device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx, 1003 (void**)&device->device_ctx_addr, sizeof(*device->device_ctx), "XHCI device context"); 1004 if (device->device_ctx_area < B_OK) { 1005 TRACE_ERROR("unable to create a device context area\n"); 1006 delete_area(device->input_ctx_area); 1007 return NULL; 1008 } 1009 memset(device->device_ctx, 0, sizeof(*device->device_ctx)); 1010 1011 device->trb_area = fStack->AllocateArea((void **)&device->trbs, 1012 (void**)&device->trb_addr, sizeof(*device->trbs), "XHCI endpoint trbs"); 1013 if (device->trb_area < B_OK) { 1014 TRACE_ERROR("unable to create a device trbs area\n"); 1015 delete_area(device->input_ctx_area); 1016 delete_area(device->device_ctx_area); 1017 return NULL; 1018 } 1019 1020 for (uint32 i = 0; i < XHCI_MAX_ENDPOINTS; i++) { 1021 struct xhci_trb *linkTrb = device->trbs + (i + 1) * XHCI_MAX_TRANSFERS - 1; 1022 linkTrb->qwtrb0 = device->trb_addr 1023 + i * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1024 linkTrb->dwtrb2 = TRB_2_IRQ(0); 1025 linkTrb->dwtrb3 = TRB_3_CYCLE_BIT | TRB_3_TYPE(TRB_TYPE_LINK); 1026 } 1027 1028 // set up slot pointer to device context 1029 fDcba->baseAddress[slot] = device->device_ctx_addr; 1030 1031 size_t maxPacketSize; 1032 switch (speed) { 1033 case USB_SPEED_LOWSPEED: 1034 case USB_SPEED_FULLSPEED: 1035 maxPacketSize = 8; 1036 break; 1037 case USB_SPEED_HIGHSPEED: 1038 maxPacketSize = 64; 1039 break; 1040 default: 1041 maxPacketSize = 512; 1042 break; 1043 } 1044 1045 // configure the Control endpoint 0 (type 4) 1046 if (ConfigureEndpoint(slot, 0, 4, device->trb_addr, 0, 1, 1, 0, 1047 maxPacketSize, maxPacketSize, speed) != B_OK) { 1048 TRACE_ERROR("unable to configure default control endpoint\n"); 1049 return NULL; 1050 } 1051 1052 device->endpoints[0].device = device; 1053 device->endpoints[0].td_head = NULL; 1054 device->endpoints[0].trbs = device->trbs; 1055 device->endpoints[0].used = 0; 1056 device->endpoints[0].current = 0; 1057 device->endpoints[0].trb_addr = device->trb_addr; 1058 mutex_init(&device->endpoints[0].lock, "xhci endpoint lock"); 1059 1060 // device should get to addressed state (bsr = 0) 1061 if (SetAddress(device->input_ctx_addr, false, slot) != B_OK) { 1062 TRACE_ERROR("unable to set address\n"); 1063 return NULL; 1064 } 1065 1066 device->state = XHCI_STATE_ADDRESSED; 1067 device->address = SLOT_3_DEVICE_ADDRESS_GET(device->device_ctx->slot.dwslot3); 1068 1069 TRACE("device: address 0x%x state 0x%lx\n", device->address, 1070 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1071 TRACE("endpoint0 state 0x%lx\n", 1072 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1073 1074 // Create a temporary pipe with the new address 1075 ControlPipe pipe(parent); 1076 pipe.SetControllerCookie(&device->endpoints[0]); 1077 pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0, hubAddress, 1078 hubPort); 1079 1080 // Get the device descriptor 1081 // Just retrieve the first 8 bytes of the descriptor -> minimum supported 1082 // size of any device. It is enough because it includes the device type. 1083 1084 size_t actualLength = 0; 1085 usb_device_descriptor deviceDescriptor; 1086 1087 TRACE("getting the device descriptor\n"); 1088 pipe.SendRequest( 1089 USB_REQTYPE_DEVICE_IN | USB_REQTYPE_STANDARD, // type 1090 USB_REQUEST_GET_DESCRIPTOR, // request 1091 USB_DESCRIPTOR_DEVICE << 8, // value 1092 0, // index 1093 8, // length 1094 (void *)&deviceDescriptor, // buffer 1095 8, // buffer length 1096 &actualLength); // actual length 1097 1098 if (actualLength != 8) { 1099 TRACE_ERROR("error while getting the device descriptor\n"); 1100 return NULL; 1101 } 1102 1103 TRACE("device_class: %d device_subclass %d device_protocol %d\n", 1104 deviceDescriptor.device_class, deviceDescriptor.device_subclass, 1105 deviceDescriptor.device_protocol); 1106 1107 TRACE("creating new device\n"); 1108 Device *deviceObject = new(std::nothrow) Device(parent, hubAddress, hubPort, 1109 deviceDescriptor, device->address + 1, speed, false, device); 1110 if (!deviceObject) { 1111 TRACE_ERROR("no memory to allocate device\n"); 1112 return NULL; 1113 } 1114 fPortSlots[hubPort] = slot; 1115 TRACE("AllocateDevice() port %d slot %d\n", hubPort, slot); 1116 return deviceObject; 1117} 1118 1119 1120void 1121XHCI::FreeDevice(Device *device) 1122{ 1123 uint8 slot = fPortSlots[device->HubPort()]; 1124 TRACE("FreeDevice() port %d slot %d\n", device->HubPort(), slot); 1125 DisableSlot(slot); 1126 fDcba->baseAddress[slot] = 0; 1127 fPortSlots[device->HubPort()] = 0; 1128 delete_area(fDevices[slot].trb_area); 1129 delete_area(fDevices[slot].input_ctx_area); 1130 delete_area(fDevices[slot].device_ctx_area); 1131 fDevices[slot].state = XHCI_STATE_DISABLED; 1132 delete device; 1133} 1134 1135 1136status_t 1137XHCI::_InsertEndpointForPipe(Pipe *pipe) 1138{ 1139 if (pipe->ControllerCookie() != NULL 1140 || pipe->Parent()->Type() != USB_OBJECT_DEVICE) { 1141 // default pipe is already referenced 1142 return B_OK; 1143 } 1144 1145 Device* usbDevice = (Device *)pipe->Parent(); 1146 struct xhci_device *device = (struct xhci_device *) 1147 usbDevice->ControllerCookie(); 1148 if (usbDevice->Parent() == RootObject()) 1149 return B_OK; 1150 if (device == NULL) { 1151 panic("_InsertEndpointForPipe device is NULL\n"); 1152 return B_OK; 1153 } 1154 1155 uint8 id = XHCI_ENDPOINT_ID(pipe) - 1; 1156 if (id >= XHCI_MAX_ENDPOINTS) 1157 return B_BAD_VALUE; 1158 1159 if (id > 0) { 1160 if (SLOT_0_NUM_ENTRIES_GET(device->device_ctx->slot.dwslot0) == 1) { 1161 device->input_ctx->slot.dwslot0 &= ~(SLOT_0_NUM_ENTRIES(0x1f)); 1162 device->input_ctx->slot.dwslot0 |= 1163 SLOT_0_NUM_ENTRIES(XHCI_MAX_ENDPOINTS - 1); 1164 EvaluateContext(device->input_ctx_addr, device->slot); 1165 } 1166 1167 device->endpoints[id].device = device; 1168 device->endpoints[id].trbs = device->trbs 1169 + id * XHCI_MAX_TRANSFERS; 1170 device->endpoints[id].td_head = NULL; 1171 device->endpoints[id].used = 0; 1172 device->endpoints[id].trb_addr = device->trb_addr 1173 + id * XHCI_MAX_TRANSFERS * sizeof(xhci_trb); 1174 mutex_init(&device->endpoints[id].lock, "xhci endpoint lock"); 1175 1176 TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n", 1177 device->trbs, device->endpoints[id].trbs); 1178 TRACE("_InsertEndpointForPipe trb_addr device 0x%lx endpoint 0x%lx\n", 1179 device->trb_addr, device->endpoints[id].trb_addr); 1180 1181 uint8 endpoint = id + 1; 1182 1183 StopEndpoint(false, endpoint, device->slot); 1184 1185 ResetEndpoint(false, endpoint, device->slot); 1186 1187 SetTRDequeue(device->endpoints[id].trb_addr, 0, endpoint, 1188 device->slot); 1189 1190 device->input_ctx->input.dropFlags = 0; 1191 device->input_ctx->input.addFlags = (1 << endpoint) | (1 << 0); 1192 1193 // configure the Control endpoint 0 (type 4) 1194 uint32 type = 4; 1195 if ((pipe->Type() & USB_OBJECT_INTERRUPT_PIPE) != 0) 1196 type = 3; 1197 if ((pipe->Type() & USB_OBJECT_BULK_PIPE) != 0) 1198 type = 2; 1199 if ((pipe->Type() & USB_OBJECT_ISO_PIPE) != 0) 1200 type = 1; 1201 type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0; 1202 1203 TRACE("trb_addr 0x%lx\n", device->endpoints[id].trb_addr); 1204 1205 if (ConfigureEndpoint(device->slot, id, type, 1206 device->endpoints[id].trb_addr, pipe->Interval(), 1207 1, 1, 0, pipe->MaxPacketSize(), pipe->MaxPacketSize(), 1208 usbDevice->Speed()) != B_OK) { 1209 TRACE_ERROR("unable to configure endpoint\n"); 1210 return B_ERROR; 1211 } 1212 1213 EvaluateContext(device->input_ctx_addr, device->slot); 1214 1215 ConfigureEndpoint(device->input_ctx_addr, false, device->slot); 1216 TRACE("device: address 0x%x state 0x%lx\n", device->address, 1217 SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3)); 1218 TRACE("endpoint[0] state 0x%lx\n", 1219 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0)); 1220 TRACE("endpoint[%d] state 0x%lx\n", id, 1221 ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0)); 1222 device->state = XHCI_STATE_CONFIGURED; 1223 } 1224 pipe->SetControllerCookie(&device->endpoints[id]); 1225 1226 TRACE("_InsertEndpointForPipe for pipe %p at id %d\n", pipe, id); 1227 1228 return B_OK; 1229} 1230 1231 1232status_t 1233XHCI::_RemoveEndpointForPipe(Pipe *pipe) 1234{ 1235 if (pipe->Parent()->Type() != USB_OBJECT_DEVICE) 1236 return B_OK; 1237 //Device* device = (Device *)pipe->Parent(); 1238 1239 return B_OK; 1240} 1241 1242 1243status_t 1244XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1245{ 1246 TRACE("_LinkDescriptorForPipe\n"); 1247 MutexLocker endpointLocker(endpoint->lock); 1248 if (endpoint->used >= XHCI_MAX_TRANSFERS) 1249 return B_BAD_VALUE; 1250 1251 endpoint->used++; 1252 if (endpoint->td_head == NULL) 1253 descriptor->next = NULL; 1254 else 1255 descriptor->next = endpoint->td_head; 1256 endpoint->td_head = descriptor; 1257 1258 uint8 current = endpoint->current; 1259 uint8 next = (current + 1) % (XHCI_MAX_TRANSFERS - 1); 1260 1261 TRACE("_LinkDescriptorForPipe current %d, next %d\n", current, next); 1262 1263 // compute next link 1264 addr_t addr = endpoint->trb_addr + next * sizeof(struct xhci_trb); 1265 descriptor->trbs[descriptor->trb_count].qwtrb0 = addr; 1266 descriptor->trbs[descriptor->trb_count].dwtrb2 = TRB_2_IRQ(0); 1267 descriptor->trbs[descriptor->trb_count].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1268 | TRB_3_IOC_BIT | TRB_3_CYCLE_BIT; 1269 1270 endpoint->trbs[next].qwtrb0 = 0; 1271 endpoint->trbs[next].dwtrb2 = 0; 1272 endpoint->trbs[next].dwtrb3 = 0; 1273 1274 endpoint->trbs[current].qwtrb0 = descriptor->this_phy; 1275 endpoint->trbs[current].dwtrb2 = TRB_2_IRQ(0); 1276 endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK) 1277 | TRB_3_CYCLE_BIT; 1278 1279 TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%lx 0x%llx 0x%lx\n", 1280 &endpoint->trbs[current], 1281 endpoint->trb_addr + current * sizeof(struct xhci_trb), 1282 endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3); 1283 endpoint->current = next; 1284 1285 return B_OK; 1286} 1287 1288 1289status_t 1290XHCI::_UnlinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint) 1291{ 1292 TRACE("_UnlinkDescriptorForPipe\n"); 1293 MutexLocker endpointLocker(endpoint->lock); 1294 endpoint->used--; 1295 if (descriptor == endpoint->td_head) { 1296 endpoint->td_head = descriptor->next; 1297 descriptor->next = NULL; 1298 return B_OK; 1299 } else { 1300 for (xhci_td *td = endpoint->td_head; td->next != NULL; td = td->next) { 1301 if (td->next == descriptor) { 1302 td->next = descriptor->next; 1303 descriptor->next = NULL; 1304 return B_OK; 1305 } 1306 } 1307 } 1308 1309 endpoint->used++; 1310 return B_ERROR; 1311} 1312 1313 1314status_t 1315XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, uint16 interval, 1316 uint8 maxPacketCount, uint8 mult, uint8 fpsShift, uint16 maxPacketSize, 1317 uint16 maxFrameSize, usb_speed speed) 1318{ 1319 struct xhci_device *device = &fDevices[slot]; 1320 struct xhci_endpoint_ctx *endpoint = &device->input_ctx->endpoints[number]; 1321 1322 if (mult == 0 || maxPacketCount == 0) 1323 return B_BAD_VALUE; 1324 1325 maxPacketCount--; 1326 1327 endpoint->dwendpoint0 = ENDPOINT_0_STATE(0) | ENDPOINT_0_MAXPSTREAMS(0); 1328 // add mult for isochronous and interrupt types 1329 switch (speed) { 1330 case USB_SPEED_LOWSPEED: 1331 case USB_SPEED_FULLSPEED: 1332 fpsShift += 3; 1333 break; 1334 default: 1335 break; 1336 } 1337 switch (type) { 1338 case 1: 1339 case 5: 1340 if (fpsShift > 3) 1341 fpsShift--; 1342 case 3: 1343 case 7: 1344 endpoint->dwendpoint0 |= ENDPOINT_0_INTERVAL(fpsShift); 1345 break; 1346 default: 1347 break; 1348 } 1349 // add interval 1350 endpoint->dwendpoint1 = ENDPOINT_1_EPTYPE(type) 1351 | ENDPOINT_1_MAXBURST(maxPacketCount) 1352 | ENDPOINT_1_MAXPACKETSIZE(maxPacketSize) 1353 | ENDPOINT_1_CERR(3); 1354 endpoint->qwendpoint2 = ENDPOINT_2_DCS_BIT | ringAddr; 1355 // 8 for Control endpoint 1356 switch (type) { 1357 case 4: 1358 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(8); 1359 break; 1360 case 1: 1361 case 3: 1362 case 5: 1363 case 7: 1364 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(min_c(maxFrameSize, 1365 B_PAGE_SIZE)) | ENDPOINT_4_MAXESITPAYLOAD(maxFrameSize); 1366 break; 1367 default: 1368 endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE); 1369 } 1370 1371 TRACE("endpoint 0x%lx 0x%lx 0x%llx 0x%lx\n", endpoint->dwendpoint0, 1372 endpoint->dwendpoint1, endpoint->qwendpoint2, endpoint->dwendpoint4); 1373 1374 return B_OK; 1375} 1376 1377 1378status_t 1379XHCI::GetPortSpeed(uint8 index, usb_speed *speed) 1380{ 1381 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1382 *speed = USB_SPEED_SUPER; 1383 else { 1384 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1385 1386 switch (PS_SPEED_GET(portStatus)) { 1387 case 3: 1388 *speed = USB_SPEED_HIGHSPEED; 1389 break; 1390 case 2: 1391 *speed = USB_SPEED_LOWSPEED; 1392 break; 1393 case 1: 1394 *speed = USB_SPEED_FULLSPEED; 1395 break; 1396 default: 1397 *speed = USB_SPEED_SUPER; 1398 } 1399 } 1400 return B_OK; 1401} 1402 1403 1404status_t 1405XHCI::GetPortStatus(uint8 index, usb_port_status *status) 1406{ 1407 if (index >= fPortCount) 1408 return B_BAD_INDEX; 1409 1410 status->status = status->change = 0; 1411 uint32 portStatus = ReadOpReg(XHCI_PORTSC(index)); 1412 //TRACE("port status=0x%08lx\n", portStatus); 1413 1414 // build the status 1415 switch (PS_SPEED_GET(portStatus)) { 1416 case 3: 1417 status->status |= PORT_STATUS_HIGH_SPEED; 1418 break; 1419 case 2: 1420 status->status |= PORT_STATUS_LOW_SPEED; 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 if (portStatus & PS_CCS) 1427 status->status |= PORT_STATUS_CONNECTION; 1428 if (portStatus & PS_PED) 1429 status->status |= PORT_STATUS_ENABLE; 1430 if (portStatus & PS_OCA) 1431 status->status |= PORT_STATUS_OVER_CURRENT; 1432 if (portStatus & PS_PR) 1433 status->status |= PORT_STATUS_RESET; 1434 if (portStatus & PS_PP) { 1435 if (fPortSpeeds[index] == USB_SPEED_SUPER) 1436 status->status |= PORT_STATUS_SS_POWER; 1437 else 1438 status->status |= PORT_STATUS_POWER; 1439 } 1440 1441 // build the change 1442 if (portStatus & PS_CSC) 1443 status->change |= PORT_STATUS_CONNECTION; 1444 if (portStatus & PS_PEC) 1445 status->change |= PORT_STATUS_ENABLE; 1446 if (portStatus & PS_OCC) 1447 status->change |= PORT_STATUS_OVER_CURRENT; 1448 if (portStatus & PS_PRC) 1449 status->change |= PORT_STATUS_RESET; 1450 1451 if (fPortSpeeds[index] == USB_SPEED_SUPER) { 1452 if (portStatus & PS_PLC) 1453 status->change |= PORT_LINK_STATE; 1454 if (portStatus & PS_WRC) 1455 status->change |= PORT_BH_PORT_RESET; 1456 } 1457 1458 return B_OK; 1459} 1460 1461 1462status_t 1463XHCI::SetPortFeature(uint8 index, uint16 feature) 1464{ 1465 TRACE("set port feature index %u feature %u\n", index, feature); 1466 if (index >= fPortCount) 1467 return B_BAD_INDEX; 1468 1469 uint32 portRegister = XHCI_PORTSC(index); 1470 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1471 1472 switch (feature) { 1473 case PORT_SUSPEND: 1474 if ((portStatus & PS_PED) == 0 || (portStatus & PS_PR) 1475 || (portStatus & PS_PLS_MASK) >= PS_XDEV_U3) { 1476 TRACE_ERROR("USB core suspending device not in U0/U1/U2.\n"); 1477 return B_BAD_VALUE; 1478 } 1479 portStatus &= ~PS_PLS_MASK; 1480 WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3); 1481 break; 1482 1483 case PORT_RESET: 1484 WriteOpReg(portRegister, portStatus | PS_PR); 1485 break; 1486 1487 case PORT_POWER: 1488 WriteOpReg(portRegister, portStatus | PS_PP); 1489 break; 1490 default: 1491 return B_BAD_VALUE; 1492 } 1493 ReadOpReg(portRegister); 1494 return B_OK; 1495} 1496 1497 1498status_t 1499XHCI::ClearPortFeature(uint8 index, uint16 feature) 1500{ 1501 TRACE("clear port feature index %u feature %u\n", index, feature); 1502 if (index >= fPortCount) 1503 return B_BAD_INDEX; 1504 1505 uint32 portRegister = XHCI_PORTSC(index); 1506 uint32 portStatus = ReadOpReg(portRegister) & ~PS_CLEAR; 1507 1508 switch (feature) { 1509 case PORT_SUSPEND: 1510 portStatus = ReadOpReg(portRegister); 1511 if (portStatus & PS_PR) 1512 return B_BAD_VALUE; 1513 if (portStatus & PS_XDEV_U3) { 1514 if ((portStatus & PS_PED) == 0) 1515 return B_BAD_VALUE; 1516 portStatus &= ~PS_PLS_MASK; 1517 WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS); 1518 } 1519 break; 1520 case PORT_ENABLE: 1521 WriteOpReg(portRegister, portStatus | PS_PED); 1522 break; 1523 case PORT_POWER: 1524 WriteOpReg(portRegister, portStatus & ~PS_PP); 1525 break; 1526 case C_PORT_CONNECTION: 1527 WriteOpReg(portRegister, portStatus | PS_CSC); 1528 break; 1529 case C_PORT_ENABLE: 1530 WriteOpReg(portRegister, portStatus | PS_PEC); 1531 break; 1532 case C_PORT_OVER_CURRENT: 1533 WriteOpReg(portRegister, portStatus | PS_OCC); 1534 break; 1535 case C_PORT_RESET: 1536 WriteOpReg(portRegister, portStatus | PS_PRC); 1537 break; 1538 default: 1539 return B_BAD_VALUE; 1540 } 1541 1542 ReadOpReg(portRegister); 1543 return B_OK; 1544} 1545 1546 1547status_t 1548XHCI::ControllerHalt() 1549{ 1550 WriteOpReg(XHCI_CMD, 0); 1551 1552 int32 tries = 100; 1553 while ((ReadOpReg(XHCI_STS) & STS_HCH) == 0) { 1554 snooze(1000); 1555 if (tries-- < 0) 1556 return B_ERROR; 1557 } 1558 1559 return B_OK; 1560} 1561 1562 1563status_t 1564XHCI::ControllerReset() 1565{ 1566 TRACE("ControllerReset() cmd: 0x%lx sts: 0x%lx\n", ReadOpReg(XHCI_CMD), 1567 ReadOpReg(XHCI_STS)); 1568 WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST); 1569 1570 int32 tries = 250; 1571 while (ReadOpReg(XHCI_CMD) & CMD_HCRST) { 1572 snooze(1000); 1573 if (tries-- < 0) { 1574 TRACE("ControllerReset() failed CMD_HCRST\n"); 1575 return B_ERROR; 1576 } 1577 } 1578 1579 tries = 250; 1580 while (ReadOpReg(XHCI_STS) & STS_CNR) { 1581 snooze(1000); 1582 if (tries-- < 0) { 1583 TRACE("ControllerReset() failed STS_CNR\n"); 1584 return B_ERROR; 1585 } 1586 } 1587 1588 return B_OK; 1589} 1590 1591 1592int32 1593XHCI::InterruptHandler(void *data) 1594{ 1595 return ((XHCI *)data)->Interrupt(); 1596} 1597 1598 1599int32 1600XHCI::Interrupt() 1601{ 1602 SpinLocker _(&fSpinlock); 1603 1604 uint32 status = ReadOpReg(XHCI_STS); 1605 uint32 temp = ReadRunReg32(XHCI_IMAN(0)); 1606 WriteOpReg(XHCI_STS, status); 1607 WriteRunReg32(XHCI_IMAN(0), temp); 1608 1609 int32 result = B_HANDLED_INTERRUPT; 1610 1611 if ((status & STS_HCH) != 0) { 1612 TRACE_ERROR("Host Controller halted\n"); 1613 return result; 1614 } 1615 if ((status & STS_HSE) != 0) { 1616 TRACE_ERROR("Host System Error\n"); 1617 return result; 1618 } 1619 if ((status & STS_HCE) != 0) { 1620 TRACE_ERROR("Host Controller Error\n"); 1621 return result; 1622 } 1623 1624 if ((status & STS_EINT) == 0) { 1625 TRACE("STS: %lx IRQ_PENDING: %lx\n", status, temp); 1626 return B_UNHANDLED_INTERRUPT; 1627 } 1628 1629 TRACE("Event Interrupt\n"); 1630 release_sem_etc(fEventSem, 1, B_DO_NOT_RESCHEDULE); 1631 return B_INVOKE_SCHEDULER; 1632} 1633 1634 1635void 1636XHCI::Ring(uint8 slot, uint8 endpoint) 1637{ 1638 TRACE("Ding Dong! slot:%d endpoint %d\n", slot, endpoint) 1639 if ((slot == 0 && endpoint > 0) || (slot > 0 && endpoint == 0)) 1640 panic("Ring() invalid slot/endpoint combination\n"); 1641 if (slot > fSlotCount || endpoint > XHCI_MAX_ENDPOINTS) 1642 panic("Ring() invalid slot or endpoint\n"); 1643 WriteDoorReg32(XHCI_DOORBELL(slot), XHCI_DOORBELL_TARGET(endpoint) 1644 | XHCI_DOORBELL_STREAMID(0)); 1645 /* Flush PCI posted writes */ 1646 ReadDoorReg32(XHCI_DOORBELL(slot)); 1647} 1648 1649 1650void 1651XHCI::QueueCommand(xhci_trb *trb) 1652{ 1653 uint8 i, j; 1654 uint32 temp; 1655 1656 i = fCmdIdx; 1657 j = fCmdCcs; 1658 1659 TRACE("command[%u] = %lx (0x%016llx, 0x%08lx, 0x%08lx)\n", 1660 i, TRB_3_TYPE_GET(trb->dwtrb3), 1661 trb->qwtrb0, trb->dwtrb2, trb->dwtrb3); 1662 1663 fCmdRing[i].qwtrb0 = trb->qwtrb0; 1664 fCmdRing[i].dwtrb2 = trb->dwtrb2; 1665 temp = trb->dwtrb3; 1666 1667 if (j) 1668 temp |= TRB_3_CYCLE_BIT; 1669 else 1670 temp &= ~TRB_3_CYCLE_BIT; 1671 temp &= ~TRB_3_TC_BIT; 1672 fCmdRing[i].dwtrb3 = temp; 1673 1674 fCmdAddr = fErst->rs_addr + (XHCI_MAX_EVENTS + i) * sizeof(xhci_trb); 1675 1676 i++; 1677 1678 if (i == (XHCI_MAX_COMMANDS - 1)) { 1679 temp = TRB_3_TYPE(TRB_TYPE_LINK) | TRB_3_TC_BIT; 1680 if (j) 1681 temp |= TRB_3_CYCLE_BIT; 1682 fCmdRing[i].dwtrb3 = temp; 1683 1684 i = 0; 1685 j ^= 1; 1686 } 1687 1688 fCmdIdx = i; 1689 fCmdCcs = j; 1690} 1691 1692 1693void 1694XHCI::HandleCmdComplete(xhci_trb *trb) 1695{ 1696 if (fCmdAddr == trb->qwtrb0) { 1697 TRACE("Received command event\n"); 1698 fCmdResult[0] = trb->dwtrb2; 1699 fCmdResult[1] = trb->dwtrb3; 1700 release_sem_etc(fCmdCompSem, 1, B_DO_NOT_RESCHEDULE); 1701 } 1702 1703} 1704 1705 1706void 1707XHCI::HandleTransferComplete(xhci_trb *trb) 1708{ 1709 TRACE("HandleTransferComplete trb %p\n", trb); 1710 addr_t source = trb->qwtrb0; 1711 //uint8 completionCode = TRB_2_COMP_CODE_GET(trb->dwtrb2); 1712 //uint32 remainder = TRB_2_REM_GET(trb->dwtrb2); 1713 uint8 endpointNumber = TRB_3_ENDPOINT_GET(trb->dwtrb3); 1714 uint8 slot = TRB_3_SLOT_GET(trb->dwtrb3); 1715 1716 if (slot > fSlotCount) 1717 TRACE_ERROR("invalid slot\n"); 1718 if (endpointNumber == 0 || endpointNumber > XHCI_MAX_ENDPOINTS) 1719 TRACE_ERROR("invalid endpoint\n"); 1720 1721 xhci_device *device = &fDevices[slot]; 1722 xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1]; 1723 for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) { 1724 int64 offset = source - td->this_phy; 1725 TRACE("HandleTransferComplete td %p offset %lld\n", td, offset); 1726 _UnlinkDescriptorForPipe(td, endpoint); 1727 1728 // add descriptor to finished list (to be processed and freed) 1729 Lock(); 1730 td->next = fFinishedHead; 1731 fFinishedHead = td; 1732 Unlock(); 1733 release_sem(fFinishTransfersSem); 1734 break; 1735 } 1736} 1737 1738 1739status_t 1740XHCI::DoCommand(xhci_trb *trb) 1741{ 1742 if (!Lock()) 1743 return B_ERROR; 1744 1745 QueueCommand(trb); 1746 Ring(0, 0); 1747 1748 if (acquire_sem(fCmdCompSem) < B_OK) { 1749 Unlock(); 1750 return B_ERROR; 1751 } 1752 // eat up sems that have been released by multiple interrupts 1753 int32 semCount = 0; 1754 get_sem_count(fCmdCompSem, &semCount); 1755 if (semCount > 0) 1756 acquire_sem_etc(fCmdCompSem, semCount, B_RELATIVE_TIMEOUT, 0); 1757 1758 status_t status = B_OK; 1759 TRACE("Command Complete\n"); 1760 if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) { 1761 uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]); 1762 TRACE_ERROR("unsuccessful command %s (%ld)\n", 1763 xhci_error_string(errorCode), errorCode); 1764 status = B_IO_ERROR; 1765 } 1766 1767 trb->dwtrb2 = fCmdResult[0]; 1768 trb->dwtrb3 = fCmdResult[1]; 1769 TRACE("Storing trb 0x%08lx 0x%08lx\n", trb->dwtrb2, trb->dwtrb3); 1770 1771 Unlock(); 1772 return status; 1773} 1774 1775 1776status_t 1777XHCI::Noop() 1778{ 1779 xhci_trb trb; 1780 trb.qwtrb0 = 0; 1781 trb.dwtrb2 = 0; 1782 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CMD_NOOP); 1783 1784 return DoCommand(&trb); 1785} 1786 1787 1788status_t 1789XHCI::EnableSlot(uint8 *slot) 1790{ 1791 xhci_trb trb; 1792 trb.qwtrb0 = 0; 1793 trb.dwtrb2 = 0; 1794 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ENABLE_SLOT); 1795 1796 status_t status = DoCommand(&trb); 1797 if (status != B_OK) 1798 return status; 1799 1800 *slot = TRB_3_SLOT_GET(trb.dwtrb3); 1801 return *slot != 0 ? B_OK : B_BAD_VALUE; 1802} 1803 1804 1805status_t 1806XHCI::DisableSlot(uint8 slot) 1807{ 1808 xhci_trb trb; 1809 trb.qwtrb0 = 0; 1810 trb.dwtrb2 = 0; 1811 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_DISABLE_SLOT) | TRB_3_SLOT(slot); 1812 1813 return DoCommand(&trb); 1814} 1815 1816 1817status_t 1818XHCI::SetAddress(uint64 inputContext, bool bsr, uint8 slot) 1819{ 1820 xhci_trb trb; 1821 trb.qwtrb0 = inputContext; 1822 trb.dwtrb2 = 0; 1823 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_ADDRESS_DEVICE) | TRB_3_SLOT(slot); 1824 1825 if (bsr) 1826 trb.dwtrb3 |= TRB_3_BSR_BIT; 1827 1828 return DoCommand(&trb); 1829} 1830 1831 1832status_t 1833XHCI::ConfigureEndpoint(uint64 inputContext, bool deconfigure, uint8 slot) 1834{ 1835 xhci_trb trb; 1836 trb.qwtrb0 = inputContext; 1837 trb.dwtrb2 = 0; 1838 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_CONFIGURE_ENDPOINT) | TRB_3_SLOT(slot); 1839 1840 if (deconfigure) 1841 trb.dwtrb3 |= TRB_3_DCEP_BIT; 1842 1843 return DoCommand(&trb); 1844} 1845 1846 1847status_t 1848XHCI::EvaluateContext(uint64 inputContext, uint8 slot) 1849{ 1850 xhci_trb trb; 1851 trb.qwtrb0 = inputContext; 1852 trb.dwtrb2 = 0; 1853 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_EVALUATE_CONTEXT) | TRB_3_SLOT(slot); 1854 1855 return DoCommand(&trb); 1856} 1857 1858 1859status_t 1860XHCI::ResetEndpoint(bool preserve, uint8 endpoint, uint8 slot) 1861{ 1862 xhci_trb trb; 1863 trb.qwtrb0 = 0; 1864 trb.dwtrb2 = 0; 1865 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_ENDPOINT) | TRB_3_SLOT(slot) 1866 | TRB_3_ENDPOINT(endpoint); 1867 if (preserve) 1868 trb.dwtrb3 |= TRB_3_PRSV_BIT; 1869 1870 return DoCommand(&trb); 1871} 1872 1873 1874status_t 1875XHCI::StopEndpoint(bool suspend, uint8 endpoint, uint8 slot) 1876{ 1877 xhci_trb trb; 1878 trb.qwtrb0 = 0; 1879 trb.dwtrb2 = 0; 1880 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_STOP_ENDPOINT) | TRB_3_SLOT(slot) 1881 | TRB_3_ENDPOINT(endpoint); 1882 if (suspend) 1883 trb.dwtrb3 |= TRB_3_SUSPEND_ENDPOINT_BIT; 1884 1885 return DoCommand(&trb); 1886} 1887 1888 1889status_t 1890XHCI::SetTRDequeue(uint64 dequeue, uint16 stream, uint8 endpoint, uint8 slot) 1891{ 1892 xhci_trb trb; 1893 trb.qwtrb0 = dequeue; 1894 trb.dwtrb2 = TRB_2_STREAM(stream); 1895 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_SET_TR_DEQUEUE) | TRB_3_SLOT(slot) 1896 | TRB_3_ENDPOINT(endpoint); 1897 1898 return DoCommand(&trb); 1899} 1900 1901 1902status_t 1903XHCI::ResetDevice(uint8 slot) 1904{ 1905 xhci_trb trb; 1906 trb.qwtrb0 = 0; 1907 trb.dwtrb2 = 0; 1908 trb.dwtrb3 = TRB_3_TYPE(TRB_TYPE_RESET_DEVICE) | TRB_3_SLOT(slot); 1909 1910 return DoCommand(&trb); 1911} 1912 1913 1914int32 1915XHCI::EventThread(void* data) 1916{ 1917 ((XHCI *)data)->CompleteEvents(); 1918 return B_OK; 1919} 1920 1921 1922void 1923XHCI::CompleteEvents() 1924{ 1925 while (!fStopThreads) { 1926 if (acquire_sem(fEventSem) < B_OK) 1927 continue; 1928 1929 // eat up sems that have been released by multiple interrupts 1930 int32 semCount = 0; 1931 get_sem_count(fEventSem, &semCount); 1932 if (semCount > 0) 1933 acquire_sem_etc(fEventSem, semCount, B_RELATIVE_TIMEOUT, 0); 1934 1935 uint16 i = fEventIdx; 1936 uint8 j = fEventCcs; 1937 uint8 t = 2; 1938 1939 while (1) { 1940 uint32 temp = fEventRing[i].dwtrb3; 1941 uint8 k = (temp & TRB_3_CYCLE_BIT) ? 1 : 0; 1942 if (j != k) 1943 break; 1944 1945 uint8 event = TRB_3_TYPE_GET(temp); 1946 1947 TRACE("event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", i, event, 1948 fEventRing[i].qwtrb0, fEventRing[i].dwtrb2, fEventRing[i].dwtrb3); 1949 switch (event) { 1950 case TRB_TYPE_COMMAND_COMPLETION: 1951 HandleCmdComplete(&fEventRing[i]); 1952 break; 1953 case TRB_TYPE_TRANSFER: 1954 HandleTransferComplete(&fEventRing[i]); 1955 break; 1956 case TRB_TYPE_PORT_STATUS_CHANGE: 1957 TRACE("port change detected\n"); 1958 break; 1959 default: 1960 TRACE_ERROR("Unhandled event = %u\n", event); 1961 break; 1962 } 1963 1964 i++; 1965 if (i == XHCI_MAX_EVENTS) { 1966 i = 0; 1967 j ^= 1; 1968 if (!--t) 1969 break; 1970 } 1971 } 1972 1973 fEventIdx = i; 1974 fEventCcs = j; 1975 1976 uint64 addr = fErst->rs_addr + i * sizeof(xhci_trb); 1977 addr |= ERST_EHB; 1978 WriteRunReg32(XHCI_ERDP_LO(0), (uint32)addr); 1979 WriteRunReg32(XHCI_ERDP_HI(0), (uint32)(addr >> 32)); 1980 } 1981} 1982 1983 1984int32 1985XHCI::FinishThread(void* data) 1986{ 1987 ((XHCI *)data)->FinishTransfers(); 1988 return B_OK; 1989} 1990 1991 1992void 1993XHCI::FinishTransfers() 1994{ 1995 while (!fStopThreads) { 1996 if (acquire_sem(fFinishTransfersSem) < B_OK) 1997 continue; 1998 1999 // eat up sems that have been released by multiple interrupts 2000 int32 semCount = 0; 2001 get_sem_count(fFinishTransfersSem, &semCount); 2002 if (semCount > 0) 2003 acquire_sem_etc(fFinishTransfersSem, semCount, B_RELATIVE_TIMEOUT, 0); 2004 2005 Lock(); 2006 TRACE("finishing transfers\n"); 2007 while (fFinishedHead != NULL) { 2008 xhci_td* td = fFinishedHead; 2009 fFinishedHead = td->next; 2010 td->next = NULL; 2011 Unlock(); 2012 2013 Transfer* transfer = td->transfer; 2014 bool directionIn = (transfer->TransferPipe()->Direction() != Pipe::Out); 2015 usb_request_data *requestData = transfer->RequestData(); 2016 2017 // TODO check event 2018 status_t callbackStatus = B_OK; 2019 size_t actualLength = requestData ? requestData->Length 2020 : transfer->DataLength(); 2021 TRACE("finishing transfer td %p\n", td); 2022 if (directionIn && actualLength > 0) { 2023 if (requestData) { 2024 TRACE("copying in data %d bytes\n", requestData->Length); 2025 memcpy((uint8 *)transfer->Vector()[0].iov_base, 2026 td->buffer_log[0], requestData->Length); 2027 } else { 2028 TRACE("copying in iov count %ld\n", transfer->VectorCount()); 2029 ReadDescriptorChain(td, transfer->Vector(), 2030 transfer->VectorCount()); 2031 } 2032 } 2033 transfer->Finished(callbackStatus, actualLength); 2034 2035 FreeDescriptor(td); 2036 Lock(); 2037 } 2038 Unlock(); 2039 2040 } 2041} 2042 2043inline void 2044XHCI::WriteOpReg(uint32 reg, uint32 value) 2045{ 2046 *(volatile uint32 *)(fOperationalRegisters + reg) = value; 2047} 2048 2049 2050inline uint32 2051XHCI::ReadOpReg(uint32 reg) 2052{ 2053 return *(volatile uint32 *)(fOperationalRegisters + reg); 2054} 2055 2056 2057inline uint32 2058XHCI::ReadCapReg32(uint32 reg) 2059{ 2060 return *(volatile uint32 *)(fCapabilityRegisters + reg); 2061} 2062 2063 2064inline void 2065XHCI::WriteCapReg32(uint32 reg, uint32 value) 2066{ 2067 *(volatile uint32 *)(fCapabilityRegisters + reg) = value; 2068} 2069 2070 2071inline uint32 2072XHCI::ReadRunReg32(uint32 reg) 2073{ 2074 return *(volatile uint32 *)(fRuntimeRegisters + reg); 2075} 2076 2077 2078inline void 2079XHCI::WriteRunReg32(uint32 reg, uint32 value) 2080{ 2081 *(volatile uint32 *)(fRuntimeRegisters + reg) = value; 2082} 2083 2084 2085inline uint32 2086XHCI::ReadDoorReg32(uint32 reg) 2087{ 2088 return *(volatile uint32 *)(fDoorbellRegisters + reg); 2089} 2090 2091 2092inline void 2093XHCI::WriteDoorReg32(uint32 reg, uint32 value) 2094{ 2095 *(volatile uint32 *)(fDoorbellRegisters + reg) = value; 2096} 2097