1/*
2** Copyright 2001, Travis Geiselbrecht. All rights reserved.
3** Distributed under the terms of the NewOS License.
4*/
5#ifndef _SH4_H
6#define _SH4_H
7
8#define P4_AREA 0xe0000000
9#define P4_AREA_LEN 0x20000000
10#define P3_AREA 0xc0000000
11#define P3_AREA_LEN (P4_AREA - P3_AREA)
12#define P2_AREA 0xa0000000
13#define P2_AREA_LEN (P3_AREA - P2_AREA)
14#define P1_AREA 0x80000000
15#define P1_AREA_LEN (P2_AREA - P1_AREA)
16#define P0_AREA 0
17#define P0_AREA_LEN (P1_AREA - P0_AREA)
18#define U0_AREA P0_AREA
19#define U0_AREA_LEN P0_AREA_LEN
20
21#define PHYS_MEM_START    0x0c000000
22#define PHYS_MEM_LEN      0x01000000
23#define PHYS_MEM_END      (PHYS_MEM_START + PHYS_MEM_LEN)
24#define P1_PHYS_MEM_START (P1_AREA + PHYS_MEM_START)
25#define P1_PHYS_MEM_LEN   PHYS_MEM_LEN
26#define P1_PHYS_MEM_END   (P1_PHYS_MEM_START + P1_PHYS_MEM_LEN)
27
28#define PHYS_ADDR_TO_P1(x) (((unsigned int)(x)) + P1_AREA)
29#define PHYS_ADDR_TO_P2(x) (((unsigned int)(x)) + P2_AREA)
30#define P1_TO_PHYS_ADDR(x) (((unsigned int)(x)) - P1_AREA)
31
32#define PHYS_ADDR_SIZE     (0x1fffffff+1)
33
34//#define PAGE_SIZE	4096
35#define PAGE_SIZE_1K	0
36#define PAGE_SIZE_4K	1
37#define PAGE_SIZE_64K	2
38#define PAGE_SIZE_1M	3
39
40#define PTEH 	0xff000000
41#define PTEL 	0xff000004
42#define PTEA	0xff000034
43#define TTB  	0xff000008
44#define TEA  	0xff00000c
45#define MMUCR 	0xff000010
46
47#define UTLB    0xf6000000
48#define UTLB1   0xf7000000
49#define UTLB2   0xf3800000
50#define UTLB_ADDR_SHIFT 0x8
51#define UTLB_COUNT 64
52
53struct utlb_addr_array {
54	unsigned int asid: 8;
55	unsigned int valid: 1;
56	unsigned int dirty: 1;
57	unsigned int vpn: 22;
58};
59
60struct utlb_data_array_1 {
61	unsigned int wt: 1;
62	unsigned int sh: 1;
63	unsigned int dirty: 1;
64	unsigned int cacheability: 1;
65	unsigned int psize0: 1;
66	unsigned int prot_key: 2;
67	unsigned int psize1: 1;
68	unsigned int valid: 1;
69	unsigned int unused: 1;
70	unsigned int ppn: 19;
71	unsigned int unused2: 3;
72};
73
74struct utlb_data_array_2 {
75	unsigned int sa: 2;
76	unsigned int tc: 1;
77	unsigned int unused: 29;
78};
79
80struct utlb_data {
81	struct utlb_addr_array a;
82	struct utlb_data_array_1 da1;
83	struct utlb_data_array_2 da2;
84};
85
86#define	ITLB	0xf2000000
87#define	ITLB1	0xf3000000
88#define ITLB2	0xf3800000
89#define ITLB_ADDR_SHIFT 0x8
90#define ITLB_COUNT 4
91
92struct itlb_addr_array {
93	unsigned int asid: 8;
94	unsigned int valid: 1;
95	unsigned int unused: 1;
96	unsigned int vpn: 22;
97};
98
99struct itlb_data_array_1 {
100	unsigned int unused1: 1;
101	unsigned int sh: 1;
102	unsigned int unused2: 1;
103	unsigned int cacheability: 1;
104	unsigned int psize0: 1;
105	unsigned int unused3: 1;
106	unsigned int prot_key: 1;
107	unsigned int psize1: 1;
108	unsigned int valid: 1;
109	unsigned int unused4: 1;
110	unsigned int ppn: 19;
111	unsigned int unused5: 3;
112};
113
114struct itlb_data_array_2 {
115	unsigned int sa: 2;
116	unsigned int tc: 1;
117	unsigned int unused: 29;
118};
119
120struct itlb_data {
121	struct itlb_addr_array a;
122	struct itlb_data_array_1 da1;
123	struct itlb_data_array_2 da2;
124};
125
126// timer stuff
127#define	TOCR	0xffd80000
128#define TSTR	0xffd80004
129#define	TCOR0	0xffd80008
130#define TCNT0	0xffd8000c
131#define TCR0	0xffd80010
132#define TCOR1	0xffd80014
133#define TCNT1	0xffd80018
134#define TCR1	0xffd8001c
135#define TCOR2	0xffd80020
136#define TCNT2	0xffd80024
137#define TCR2	0xffd80028
138#define TCPR2	0xffd8002c
139
140// interrupt controller stuff
141#define ICR		0xffd00000
142#define IPRA	0xffd00004
143#define IPRB	0xffd00008
144#define IPRC	0xffd0000c
145
146// cache stuff
147#define CCR		0xff00001c
148#define QACR0	0xff000038
149#define QACR1	0xff00003c
150
151#endif
152
153