1/* Subroutines used for MIPS code generation. 2 Copyright (C) 1989-2015 Free Software Foundation, Inc. 3 Contributed by A. Lichnewsky, lich@inria.inria.fr. 4 Changes by Michael Meissner, meissner@osf.org. 5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 6 Brendan Eich, brendan@microunity.com. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 3, or (at your option) 13any later version. 14 15GCC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING3. If not see 22<http://www.gnu.org/licenses/>. */ 23 24#include "config.h" 25#include "system.h" 26#include "coretypes.h" 27#include "tm.h" 28#include "rtl.h" 29#include "regs.h" 30#include "hard-reg-set.h" 31#include "insn-config.h" 32#include "conditions.h" 33#include "insn-attr.h" 34#include "recog.h" 35#include "output.h" 36#include "hash-set.h" 37#include "machmode.h" 38#include "vec.h" 39#include "double-int.h" 40#include "input.h" 41#include "alias.h" 42#include "symtab.h" 43#include "wide-int.h" 44#include "inchash.h" 45#include "tree.h" 46#include "fold-const.h" 47#include "varasm.h" 48#include "stringpool.h" 49#include "stor-layout.h" 50#include "calls.h" 51#include "function.h" 52#include "hashtab.h" 53#include "flags.h" 54#include "statistics.h" 55#include "real.h" 56#include "fixed-value.h" 57#include "expmed.h" 58#include "dojump.h" 59#include "explow.h" 60#include "emit-rtl.h" 61#include "stmt.h" 62#include "expr.h" 63#include "insn-codes.h" 64#include "optabs.h" 65#include "libfuncs.h" 66#include "reload.h" 67#include "tm_p.h" 68#include "ggc.h" 69#include "gstab.h" 70#include "hash-table.h" 71#include "debug.h" 72#include "target.h" 73#include "target-def.h" 74#include "common/common-target.h" 75#include "langhooks.h" 76#include "dominance.h" 77#include "cfg.h" 78#include "cfgrtl.h" 79#include "cfganal.h" 80#include "lcm.h" 81#include "cfgbuild.h" 82#include "cfgcleanup.h" 83#include "predict.h" 84#include "basic-block.h" 85#include "sched-int.h" 86#include "tree-ssa-alias.h" 87#include "internal-fn.h" 88#include "gimple-fold.h" 89#include "tree-eh.h" 90#include "gimple-expr.h" 91#include "is-a.h" 92#include "gimple.h" 93#include "gimplify.h" 94#include "bitmap.h" 95#include "diagnostic.h" 96#include "target-globals.h" 97#include "opts.h" 98#include "tree-pass.h" 99#include "context.h" 100#include "hash-map.h" 101#include "plugin-api.h" 102#include "ipa-ref.h" 103#include "cgraph.h" 104#include "builtins.h" 105#include "rtl-iter.h" 106 107/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ 108#define UNSPEC_ADDRESS_P(X) \ 109 (GET_CODE (X) == UNSPEC \ 110 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ 111 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) 112 113/* Extract the symbol or label from UNSPEC wrapper X. */ 114#define UNSPEC_ADDRESS(X) \ 115 XVECEXP (X, 0, 0) 116 117/* Extract the symbol type from UNSPEC wrapper X. */ 118#define UNSPEC_ADDRESS_TYPE(X) \ 119 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) 120 121/* The maximum distance between the top of the stack frame and the 122 value $sp has when we save and restore registers. 123 124 The value for normal-mode code must be a SMALL_OPERAND and must 125 preserve the maximum stack alignment. We therefore use a value 126 of 0x7ff0 in this case. 127 128 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff), 129 so we use a maximum of 0x7f0 for TARGET_MICROMIPS. 130 131 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by 132 up to 0x7f8 bytes and can usually save or restore all the registers 133 that we need to save or restore. (Note that we can only use these 134 instructions for o32, for which the stack alignment is 8 bytes.) 135 136 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and 137 RESTORE are not available. We can then use unextended instructions 138 to save and restore registers, and to allocate and deallocate the top 139 part of the frame. */ 140#define MIPS_MAX_FIRST_STACK_STEP \ 141 (!TARGET_COMPRESSION ? 0x7ff0 \ 142 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \ 143 : TARGET_64BIT ? 0x100 : 0x400) 144 145/* True if INSN is a mips.md pattern or asm statement. */ 146/* ??? This test exists through the compiler, perhaps it should be 147 moved to rtl.h. */ 148#define USEFUL_INSN_P(INSN) \ 149 (NONDEBUG_INSN_P (INSN) \ 150 && GET_CODE (PATTERN (INSN)) != USE \ 151 && GET_CODE (PATTERN (INSN)) != CLOBBER) 152 153/* If INSN is a delayed branch sequence, return the first instruction 154 in the sequence, otherwise return INSN itself. */ 155#define SEQ_BEGIN(INSN) \ 156 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ 157 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \ 158 : (INSN)) 159 160/* Likewise for the last instruction in a delayed branch sequence. */ 161#define SEQ_END(INSN) \ 162 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ 163 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \ 164 0, \ 165 XVECLEN (PATTERN (INSN), 0) - 1)) \ 166 : (INSN)) 167 168/* Execute the following loop body with SUBINSN set to each instruction 169 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */ 170#define FOR_EACH_SUBINSN(SUBINSN, INSN) \ 171 for ((SUBINSN) = SEQ_BEGIN (INSN); \ 172 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \ 173 (SUBINSN) = NEXT_INSN (SUBINSN)) 174 175/* True if bit BIT is set in VALUE. */ 176#define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) 177 178/* Return the opcode for a ptr_mode load of the form: 179 180 l[wd] DEST, OFFSET(BASE). */ 181#define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \ 182 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \ 183 | ((BASE) << 21) \ 184 | ((DEST) << 16) \ 185 | (OFFSET)) 186 187/* Return the opcode to move register SRC into register DEST. */ 188#define MIPS_MOVE(DEST, SRC) \ 189 ((TARGET_64BIT ? 0x2d : 0x21) \ 190 | ((DEST) << 11) \ 191 | ((SRC) << 21)) 192 193/* Return the opcode for: 194 195 lui DEST, VALUE. */ 196#define MIPS_LUI(DEST, VALUE) \ 197 ((0xf << 26) | ((DEST) << 16) | (VALUE)) 198 199/* Return the opcode to jump to register DEST. When the JR opcode is not 200 available use JALR $0, DEST. */ 201#define MIPS_JR(DEST) \ 202 (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9)) 203 204/* Return the opcode for: 205 206 bal . + (1 + OFFSET) * 4. */ 207#define MIPS_BAL(OFFSET) \ 208 ((0x1 << 26) | (0x11 << 16) | (OFFSET)) 209 210/* Return the usual opcode for a nop. */ 211#define MIPS_NOP 0 212 213/* Classifies an address. 214 215 ADDRESS_REG 216 A natural register + offset address. The register satisfies 217 mips_valid_base_register_p and the offset is a const_arith_operand. 218 219 ADDRESS_LO_SUM 220 A LO_SUM rtx. The first operand is a valid base register and 221 the second operand is a symbolic address. 222 223 ADDRESS_CONST_INT 224 A signed 16-bit constant address. 225 226 ADDRESS_SYMBOLIC: 227 A constant symbolic address. */ 228enum mips_address_type { 229 ADDRESS_REG, 230 ADDRESS_LO_SUM, 231 ADDRESS_CONST_INT, 232 ADDRESS_SYMBOLIC 233}; 234 235/* Macros to create an enumeration identifier for a function prototype. */ 236#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B 237#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C 238#define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D 239#define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E 240 241/* Classifies the prototype of a built-in function. */ 242enum mips_function_type { 243#define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST, 244#include "config/mips/mips-ftypes.def" 245#undef DEF_MIPS_FTYPE 246 MIPS_MAX_FTYPE_MAX 247}; 248 249/* Specifies how a built-in function should be converted into rtl. */ 250enum mips_builtin_type { 251 /* The function corresponds directly to an .md pattern. The return 252 value is mapped to operand 0 and the arguments are mapped to 253 operands 1 and above. */ 254 MIPS_BUILTIN_DIRECT, 255 256 /* The function corresponds directly to an .md pattern. There is no return 257 value and the arguments are mapped to operands 0 and above. */ 258 MIPS_BUILTIN_DIRECT_NO_TARGET, 259 260 /* The function corresponds to a comparison instruction followed by 261 a mips_cond_move_tf_ps pattern. The first two arguments are the 262 values to compare and the second two arguments are the vector 263 operands for the movt.ps or movf.ps instruction (in assembly order). */ 264 MIPS_BUILTIN_MOVF, 265 MIPS_BUILTIN_MOVT, 266 267 /* The function corresponds to a V2SF comparison instruction. Operand 0 268 of this instruction is the result of the comparison, which has mode 269 CCV2 or CCV4. The function arguments are mapped to operands 1 and 270 above. The function's return value is an SImode boolean that is 271 true under the following conditions: 272 273 MIPS_BUILTIN_CMP_ANY: one of the registers is true 274 MIPS_BUILTIN_CMP_ALL: all of the registers are true 275 MIPS_BUILTIN_CMP_LOWER: the first register is true 276 MIPS_BUILTIN_CMP_UPPER: the second register is true. */ 277 MIPS_BUILTIN_CMP_ANY, 278 MIPS_BUILTIN_CMP_ALL, 279 MIPS_BUILTIN_CMP_UPPER, 280 MIPS_BUILTIN_CMP_LOWER, 281 282 /* As above, but the instruction only sets a single $fcc register. */ 283 MIPS_BUILTIN_CMP_SINGLE, 284 285 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ 286 MIPS_BUILTIN_BPOSGE32 287}; 288 289/* Invoke MACRO (COND) for each C.cond.fmt condition. */ 290#define MIPS_FP_CONDITIONS(MACRO) \ 291 MACRO (f), \ 292 MACRO (un), \ 293 MACRO (eq), \ 294 MACRO (ueq), \ 295 MACRO (olt), \ 296 MACRO (ult), \ 297 MACRO (ole), \ 298 MACRO (ule), \ 299 MACRO (sf), \ 300 MACRO (ngle), \ 301 MACRO (seq), \ 302 MACRO (ngl), \ 303 MACRO (lt), \ 304 MACRO (nge), \ 305 MACRO (le), \ 306 MACRO (ngt) 307 308/* Enumerates the codes above as MIPS_FP_COND_<X>. */ 309#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X 310enum mips_fp_condition { 311 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND) 312}; 313#undef DECLARE_MIPS_COND 314 315/* Index X provides the string representation of MIPS_FP_COND_<X>. */ 316#define STRINGIFY(X) #X 317static const char *const mips_fp_conditions[] = { 318 MIPS_FP_CONDITIONS (STRINGIFY) 319}; 320#undef STRINGIFY 321 322/* A class used to control a comdat-style stub that we output in each 323 translation unit that needs it. */ 324class mips_one_only_stub { 325public: 326 virtual ~mips_one_only_stub () {} 327 328 /* Return the name of the stub. */ 329 virtual const char *get_name () = 0; 330 331 /* Output the body of the function to asm_out_file. */ 332 virtual void output_body () = 0; 333}; 334 335/* Tuning information that is automatically derived from other sources 336 (such as the scheduler). */ 337static struct { 338 /* The architecture and tuning settings that this structure describes. */ 339 enum processor arch; 340 enum processor tune; 341 342 /* True if this structure describes MIPS16 settings. */ 343 bool mips16_p; 344 345 /* True if the structure has been initialized. */ 346 bool initialized_p; 347 348 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0" 349 when optimizing for speed. */ 350 bool fast_mult_zero_zero_p; 351} mips_tuning_info; 352 353/* Information about a function's frame layout. */ 354struct GTY(()) mips_frame_info { 355 /* The size of the frame in bytes. */ 356 HOST_WIDE_INT total_size; 357 358 /* The number of bytes allocated to variables. */ 359 HOST_WIDE_INT var_size; 360 361 /* The number of bytes allocated to outgoing function arguments. */ 362 HOST_WIDE_INT args_size; 363 364 /* The number of bytes allocated to the .cprestore slot, or 0 if there 365 is no such slot. */ 366 HOST_WIDE_INT cprestore_size; 367 368 /* Bit X is set if the function saves or restores GPR X. */ 369 unsigned int mask; 370 371 /* Likewise FPR X. */ 372 unsigned int fmask; 373 374 /* Likewise doubleword accumulator X ($acX). */ 375 unsigned int acc_mask; 376 377 /* The number of GPRs, FPRs, doubleword accumulators and COP0 378 registers saved. */ 379 unsigned int num_gp; 380 unsigned int num_fp; 381 unsigned int num_acc; 382 unsigned int num_cop0_regs; 383 384 /* The offset of the topmost GPR, FPR, accumulator and COP0-register 385 save slots from the top of the frame, or zero if no such slots are 386 needed. */ 387 HOST_WIDE_INT gp_save_offset; 388 HOST_WIDE_INT fp_save_offset; 389 HOST_WIDE_INT acc_save_offset; 390 HOST_WIDE_INT cop0_save_offset; 391 392 /* Likewise, but giving offsets from the bottom of the frame. */ 393 HOST_WIDE_INT gp_sp_offset; 394 HOST_WIDE_INT fp_sp_offset; 395 HOST_WIDE_INT acc_sp_offset; 396 HOST_WIDE_INT cop0_sp_offset; 397 398 /* Similar, but the value passed to _mcount. */ 399 HOST_WIDE_INT ra_fp_offset; 400 401 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 402 HOST_WIDE_INT arg_pointer_offset; 403 404 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ 405 HOST_WIDE_INT hard_frame_pointer_offset; 406}; 407 408struct GTY(()) machine_function { 409 /* The next floating-point condition-code register to allocate 410 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */ 411 unsigned int next_fcc; 412 413 /* The register returned by mips16_gp_pseudo_reg; see there for details. */ 414 rtx mips16_gp_pseudo_rtx; 415 416 /* The number of extra stack bytes taken up by register varargs. 417 This area is allocated by the callee at the very top of the frame. */ 418 int varargs_size; 419 420 /* The current frame information, calculated by mips_compute_frame_info. */ 421 struct mips_frame_info frame; 422 423 /* The register to use as the function's global pointer, or INVALID_REGNUM 424 if the function doesn't need one. */ 425 unsigned int global_pointer; 426 427 /* How many instructions it takes to load a label into $AT, or 0 if 428 this property hasn't yet been calculated. */ 429 unsigned int load_label_num_insns; 430 431 /* True if mips_adjust_insn_length should ignore an instruction's 432 hazard attribute. */ 433 bool ignore_hazard_length_p; 434 435 /* True if the whole function is suitable for .set noreorder and 436 .set nomacro. */ 437 bool all_noreorder_p; 438 439 /* True if the function has "inflexible" and "flexible" references 440 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p 441 and mips_cfun_has_flexible_gp_ref_p for details. */ 442 bool has_inflexible_gp_insn_p; 443 bool has_flexible_gp_insn_p; 444 445 /* True if the function's prologue must load the global pointer 446 value into pic_offset_table_rtx and store the same value in 447 the function's cprestore slot (if any). Even if this value 448 is currently false, we may decide to set it to true later; 449 see mips_must_initialize_gp_p () for details. */ 450 bool must_initialize_gp_p; 451 452 /* True if the current function must restore $gp after any potential 453 clobber. This value is only meaningful during the first post-epilogue 454 split_insns pass; see mips_must_initialize_gp_p () for details. */ 455 bool must_restore_gp_when_clobbered_p; 456 457 /* True if this is an interrupt handler. */ 458 bool interrupt_handler_p; 459 460 /* True if this is an interrupt handler that uses shadow registers. */ 461 bool use_shadow_register_set_p; 462 463 /* True if this is an interrupt handler that should keep interrupts 464 masked. */ 465 bool keep_interrupts_masked_p; 466 467 /* True if this is an interrupt handler that should use DERET 468 instead of ERET. */ 469 bool use_debug_exception_return_p; 470}; 471 472/* Information about a single argument. */ 473struct mips_arg_info { 474 /* True if the argument is passed in a floating-point register, or 475 would have been if we hadn't run out of registers. */ 476 bool fpr_p; 477 478 /* The number of words passed in registers, rounded up. */ 479 unsigned int reg_words; 480 481 /* For EABI, the offset of the first register from GP_ARG_FIRST or 482 FP_ARG_FIRST. For other ABIs, the offset of the first register from 483 the start of the ABI's argument structure (see the CUMULATIVE_ARGS 484 comment for details). 485 486 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely 487 on the stack. */ 488 unsigned int reg_offset; 489 490 /* The number of words that must be passed on the stack, rounded up. */ 491 unsigned int stack_words; 492 493 /* The offset from the start of the stack overflow area of the argument's 494 first stack word. Only meaningful when STACK_WORDS is nonzero. */ 495 unsigned int stack_offset; 496}; 497 498/* Information about an address described by mips_address_type. 499 500 ADDRESS_CONST_INT 501 No fields are used. 502 503 ADDRESS_REG 504 REG is the base register and OFFSET is the constant offset. 505 506 ADDRESS_LO_SUM 507 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE 508 is the type of symbol it references. 509 510 ADDRESS_SYMBOLIC 511 SYMBOL_TYPE is the type of symbol that the address references. */ 512struct mips_address_info { 513 enum mips_address_type type; 514 rtx reg; 515 rtx offset; 516 enum mips_symbol_type symbol_type; 517}; 518 519/* One stage in a constant building sequence. These sequences have 520 the form: 521 522 A = VALUE[0] 523 A = A CODE[1] VALUE[1] 524 A = A CODE[2] VALUE[2] 525 ... 526 527 where A is an accumulator, each CODE[i] is a binary rtl operation 528 and each VALUE[i] is a constant integer. CODE[0] is undefined. */ 529struct mips_integer_op { 530 enum rtx_code code; 531 unsigned HOST_WIDE_INT value; 532}; 533 534/* The largest number of operations needed to load an integer constant. 535 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. 536 When the lowest bit is clear, we can try, but reject a sequence with 537 an extra SLL at the end. */ 538#define MIPS_MAX_INTEGER_OPS 7 539 540/* Information about a MIPS16e SAVE or RESTORE instruction. */ 541struct mips16e_save_restore_info { 542 /* The number of argument registers saved by a SAVE instruction. 543 0 for RESTORE instructions. */ 544 unsigned int nargs; 545 546 /* Bit X is set if the instruction saves or restores GPR X. */ 547 unsigned int mask; 548 549 /* The total number of bytes to allocate. */ 550 HOST_WIDE_INT size; 551}; 552 553/* Costs of various operations on the different architectures. */ 554 555struct mips_rtx_cost_data 556{ 557 unsigned short fp_add; 558 unsigned short fp_mult_sf; 559 unsigned short fp_mult_df; 560 unsigned short fp_div_sf; 561 unsigned short fp_div_df; 562 unsigned short int_mult_si; 563 unsigned short int_mult_di; 564 unsigned short int_div_si; 565 unsigned short int_div_di; 566 unsigned short branch_cost; 567 unsigned short memory_latency; 568}; 569 570/* Global variables for machine-dependent things. */ 571 572/* The -G setting, or the configuration's default small-data limit if 573 no -G option is given. */ 574static unsigned int mips_small_data_threshold; 575 576/* The number of file directives written by mips_output_filename. */ 577int num_source_filenames; 578 579/* The name that appeared in the last .file directive written by 580 mips_output_filename, or "" if mips_output_filename hasn't 581 written anything yet. */ 582const char *current_function_file = ""; 583 584/* Arrays that map GCC register numbers to debugger register numbers. */ 585int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; 586int mips_dwarf_regno[FIRST_PSEUDO_REGISTER]; 587 588/* Information about the current function's epilogue, used only while 589 expanding it. */ 590static struct { 591 /* A list of queued REG_CFA_RESTORE notes. */ 592 rtx cfa_restores; 593 594 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */ 595 rtx cfa_reg; 596 HOST_WIDE_INT cfa_offset; 597 598 /* The offset of the CFA from the stack pointer while restoring 599 registers. */ 600 HOST_WIDE_INT cfa_restore_sp_offset; 601} mips_epilogue; 602 603/* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */ 604struct mips_asm_switch mips_noreorder = { "reorder", 0 }; 605struct mips_asm_switch mips_nomacro = { "macro", 0 }; 606struct mips_asm_switch mips_noat = { "at", 0 }; 607 608/* True if we're writing out a branch-likely instruction rather than a 609 normal branch. */ 610static bool mips_branch_likely; 611 612/* The current instruction-set architecture. */ 613enum processor mips_arch; 614const struct mips_cpu_info *mips_arch_info; 615 616/* The processor that we should tune the code for. */ 617enum processor mips_tune; 618const struct mips_cpu_info *mips_tune_info; 619 620/* The ISA level associated with mips_arch. */ 621int mips_isa; 622 623/* The ISA revision level. This is 0 for MIPS I to V and N for 624 MIPS{32,64}rN. */ 625int mips_isa_rev; 626 627/* The architecture selected by -mipsN, or null if -mipsN wasn't used. */ 628static const struct mips_cpu_info *mips_isa_option_info; 629 630/* Which cost information to use. */ 631static const struct mips_rtx_cost_data *mips_cost; 632 633/* The ambient target flags, excluding MASK_MIPS16. */ 634static int mips_base_target_flags; 635 636/* The default compression mode. */ 637unsigned int mips_base_compression_flags; 638 639/* The ambient values of other global variables. */ 640static int mips_base_schedule_insns; /* flag_schedule_insns */ 641static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */ 642static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */ 643static int mips_base_align_loops; /* align_loops */ 644static int mips_base_align_jumps; /* align_jumps */ 645static int mips_base_align_functions; /* align_functions */ 646 647/* Index [M][R] is true if register R is allowed to hold a value of mode M. */ 648bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; 649 650/* Index C is true if character C is a valid PRINT_OPERAND punctation 651 character. */ 652static bool mips_print_operand_punct[256]; 653 654static GTY (()) int mips_output_filename_first_time = 1; 655 656/* mips_split_p[X] is true if symbols of type X can be split by 657 mips_split_symbol. */ 658bool mips_split_p[NUM_SYMBOL_TYPES]; 659 660/* mips_split_hi_p[X] is true if the high parts of symbols of type X 661 can be split by mips_split_symbol. */ 662bool mips_split_hi_p[NUM_SYMBOL_TYPES]; 663 664/* mips_use_pcrel_pool_p[X] is true if symbols of type X should be 665 forced into a PC-relative constant pool. */ 666bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES]; 667 668/* mips_lo_relocs[X] is the relocation to use when a symbol of type X 669 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or 670 if they are matched by a special .md file pattern. */ 671const char *mips_lo_relocs[NUM_SYMBOL_TYPES]; 672 673/* Likewise for HIGHs. */ 674const char *mips_hi_relocs[NUM_SYMBOL_TYPES]; 675 676/* Target state for MIPS16. */ 677struct target_globals *mips16_globals; 678 679/* Cached value of can_issue_more. This is cached in mips_variable_issue hook 680 and returned from mips_sched_reorder2. */ 681static int cached_can_issue_more; 682 683/* The stubs for various MIPS16 support functions, if used. */ 684static mips_one_only_stub *mips16_rdhwr_stub; 685static mips_one_only_stub *mips16_get_fcsr_stub; 686static mips_one_only_stub *mips16_set_fcsr_stub; 687 688/* Index R is the smallest register class that contains register R. */ 689const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { 690 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG, 691 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, 692 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 693 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 694 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS, 695 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 696 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, 697 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS, 698 699 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 700 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 701 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 702 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 703 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 704 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 705 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 706 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 707 MD0_REG, MD1_REG, NO_REGS, ST_REGS, 708 ST_REGS, ST_REGS, ST_REGS, ST_REGS, 709 ST_REGS, ST_REGS, ST_REGS, NO_REGS, 710 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS, 711 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 712 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 713 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 714 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 715 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 716 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 717 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 718 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 719 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 720 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 721 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 722 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 723 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 724 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 725 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 726 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 727 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 728 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 729 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 730 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 731 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 732 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 733 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 734 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 735 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, 736 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS, 737 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS 738}; 739 740/* The value of TARGET_ATTRIBUTE_TABLE. */ 741static const struct attribute_spec mips_attribute_table[] = { 742 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, 743 om_diagnostic } */ 744 { "long_call", 0, 0, false, true, true, NULL, false }, 745 { "far", 0, 0, false, true, true, NULL, false }, 746 { "near", 0, 0, false, true, true, NULL, false }, 747 /* We would really like to treat "mips16" and "nomips16" as type 748 attributes, but GCC doesn't provide the hooks we need to support 749 the right conversion rules. As declaration attributes, they affect 750 code generation but don't carry other semantics. */ 751 { "mips16", 0, 0, true, false, false, NULL, false }, 752 { "nomips16", 0, 0, true, false, false, NULL, false }, 753 { "micromips", 0, 0, true, false, false, NULL, false }, 754 { "nomicromips", 0, 0, true, false, false, NULL, false }, 755 { "nocompression", 0, 0, true, false, false, NULL, false }, 756 /* Allow functions to be specified as interrupt handlers */ 757 { "interrupt", 0, 0, false, true, true, NULL, false }, 758 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false }, 759 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false }, 760 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false }, 761 { NULL, 0, 0, false, false, false, NULL, false } 762}; 763 764/* A table describing all the processors GCC knows about; see 765 mips-cpus.def for details. */ 766static const struct mips_cpu_info mips_cpu_info_table[] = { 767#define MIPS_CPU(NAME, CPU, ISA, FLAGS) \ 768 { NAME, CPU, ISA, FLAGS }, 769#include "mips-cpus.def" 770#undef MIPS_CPU 771}; 772 773/* Default costs. If these are used for a processor we should look 774 up the actual costs. */ 775#define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ 776 COSTS_N_INSNS (7), /* fp_mult_sf */ \ 777 COSTS_N_INSNS (8), /* fp_mult_df */ \ 778 COSTS_N_INSNS (23), /* fp_div_sf */ \ 779 COSTS_N_INSNS (36), /* fp_div_df */ \ 780 COSTS_N_INSNS (10), /* int_mult_si */ \ 781 COSTS_N_INSNS (10), /* int_mult_di */ \ 782 COSTS_N_INSNS (69), /* int_div_si */ \ 783 COSTS_N_INSNS (69), /* int_div_di */ \ 784 2, /* branch_cost */ \ 785 4 /* memory_latency */ 786 787/* Floating-point costs for processors without an FPU. Just assume that 788 all floating-point libcalls are very expensive. */ 789#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ 790 COSTS_N_INSNS (256), /* fp_mult_sf */ \ 791 COSTS_N_INSNS (256), /* fp_mult_df */ \ 792 COSTS_N_INSNS (256), /* fp_div_sf */ \ 793 COSTS_N_INSNS (256) /* fp_div_df */ 794 795/* Costs to use when optimizing for size. */ 796static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { 797 COSTS_N_INSNS (1), /* fp_add */ 798 COSTS_N_INSNS (1), /* fp_mult_sf */ 799 COSTS_N_INSNS (1), /* fp_mult_df */ 800 COSTS_N_INSNS (1), /* fp_div_sf */ 801 COSTS_N_INSNS (1), /* fp_div_df */ 802 COSTS_N_INSNS (1), /* int_mult_si */ 803 COSTS_N_INSNS (1), /* int_mult_di */ 804 COSTS_N_INSNS (1), /* int_div_si */ 805 COSTS_N_INSNS (1), /* int_div_di */ 806 2, /* branch_cost */ 807 4 /* memory_latency */ 808}; 809 810/* Costs to use when optimizing for speed, indexed by processor. */ 811static const struct mips_rtx_cost_data 812 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = { 813 { /* R3000 */ 814 COSTS_N_INSNS (2), /* fp_add */ 815 COSTS_N_INSNS (4), /* fp_mult_sf */ 816 COSTS_N_INSNS (5), /* fp_mult_df */ 817 COSTS_N_INSNS (12), /* fp_div_sf */ 818 COSTS_N_INSNS (19), /* fp_div_df */ 819 COSTS_N_INSNS (12), /* int_mult_si */ 820 COSTS_N_INSNS (12), /* int_mult_di */ 821 COSTS_N_INSNS (35), /* int_div_si */ 822 COSTS_N_INSNS (35), /* int_div_di */ 823 1, /* branch_cost */ 824 4 /* memory_latency */ 825 }, 826 { /* 4KC */ 827 SOFT_FP_COSTS, 828 COSTS_N_INSNS (6), /* int_mult_si */ 829 COSTS_N_INSNS (6), /* int_mult_di */ 830 COSTS_N_INSNS (36), /* int_div_si */ 831 COSTS_N_INSNS (36), /* int_div_di */ 832 1, /* branch_cost */ 833 4 /* memory_latency */ 834 }, 835 { /* 4KP */ 836 SOFT_FP_COSTS, 837 COSTS_N_INSNS (36), /* int_mult_si */ 838 COSTS_N_INSNS (36), /* int_mult_di */ 839 COSTS_N_INSNS (37), /* int_div_si */ 840 COSTS_N_INSNS (37), /* int_div_di */ 841 1, /* branch_cost */ 842 4 /* memory_latency */ 843 }, 844 { /* 5KC */ 845 SOFT_FP_COSTS, 846 COSTS_N_INSNS (4), /* int_mult_si */ 847 COSTS_N_INSNS (11), /* int_mult_di */ 848 COSTS_N_INSNS (36), /* int_div_si */ 849 COSTS_N_INSNS (68), /* int_div_di */ 850 1, /* branch_cost */ 851 4 /* memory_latency */ 852 }, 853 { /* 5KF */ 854 COSTS_N_INSNS (4), /* fp_add */ 855 COSTS_N_INSNS (4), /* fp_mult_sf */ 856 COSTS_N_INSNS (5), /* fp_mult_df */ 857 COSTS_N_INSNS (17), /* fp_div_sf */ 858 COSTS_N_INSNS (32), /* fp_div_df */ 859 COSTS_N_INSNS (4), /* int_mult_si */ 860 COSTS_N_INSNS (11), /* int_mult_di */ 861 COSTS_N_INSNS (36), /* int_div_si */ 862 COSTS_N_INSNS (68), /* int_div_di */ 863 1, /* branch_cost */ 864 4 /* memory_latency */ 865 }, 866 { /* 20KC */ 867 COSTS_N_INSNS (4), /* fp_add */ 868 COSTS_N_INSNS (4), /* fp_mult_sf */ 869 COSTS_N_INSNS (5), /* fp_mult_df */ 870 COSTS_N_INSNS (17), /* fp_div_sf */ 871 COSTS_N_INSNS (32), /* fp_div_df */ 872 COSTS_N_INSNS (4), /* int_mult_si */ 873 COSTS_N_INSNS (7), /* int_mult_di */ 874 COSTS_N_INSNS (42), /* int_div_si */ 875 COSTS_N_INSNS (72), /* int_div_di */ 876 1, /* branch_cost */ 877 4 /* memory_latency */ 878 }, 879 { /* 24KC */ 880 SOFT_FP_COSTS, 881 COSTS_N_INSNS (5), /* int_mult_si */ 882 COSTS_N_INSNS (5), /* int_mult_di */ 883 COSTS_N_INSNS (41), /* int_div_si */ 884 COSTS_N_INSNS (41), /* int_div_di */ 885 1, /* branch_cost */ 886 4 /* memory_latency */ 887 }, 888 { /* 24KF2_1 */ 889 COSTS_N_INSNS (8), /* fp_add */ 890 COSTS_N_INSNS (8), /* fp_mult_sf */ 891 COSTS_N_INSNS (10), /* fp_mult_df */ 892 COSTS_N_INSNS (34), /* fp_div_sf */ 893 COSTS_N_INSNS (64), /* fp_div_df */ 894 COSTS_N_INSNS (5), /* int_mult_si */ 895 COSTS_N_INSNS (5), /* int_mult_di */ 896 COSTS_N_INSNS (41), /* int_div_si */ 897 COSTS_N_INSNS (41), /* int_div_di */ 898 1, /* branch_cost */ 899 4 /* memory_latency */ 900 }, 901 { /* 24KF1_1 */ 902 COSTS_N_INSNS (4), /* fp_add */ 903 COSTS_N_INSNS (4), /* fp_mult_sf */ 904 COSTS_N_INSNS (5), /* fp_mult_df */ 905 COSTS_N_INSNS (17), /* fp_div_sf */ 906 COSTS_N_INSNS (32), /* fp_div_df */ 907 COSTS_N_INSNS (5), /* int_mult_si */ 908 COSTS_N_INSNS (5), /* int_mult_di */ 909 COSTS_N_INSNS (41), /* int_div_si */ 910 COSTS_N_INSNS (41), /* int_div_di */ 911 1, /* branch_cost */ 912 4 /* memory_latency */ 913 }, 914 { /* 74KC */ 915 SOFT_FP_COSTS, 916 COSTS_N_INSNS (5), /* int_mult_si */ 917 COSTS_N_INSNS (5), /* int_mult_di */ 918 COSTS_N_INSNS (41), /* int_div_si */ 919 COSTS_N_INSNS (41), /* int_div_di */ 920 1, /* branch_cost */ 921 4 /* memory_latency */ 922 }, 923 { /* 74KF2_1 */ 924 COSTS_N_INSNS (8), /* fp_add */ 925 COSTS_N_INSNS (8), /* fp_mult_sf */ 926 COSTS_N_INSNS (10), /* fp_mult_df */ 927 COSTS_N_INSNS (34), /* fp_div_sf */ 928 COSTS_N_INSNS (64), /* fp_div_df */ 929 COSTS_N_INSNS (5), /* int_mult_si */ 930 COSTS_N_INSNS (5), /* int_mult_di */ 931 COSTS_N_INSNS (41), /* int_div_si */ 932 COSTS_N_INSNS (41), /* int_div_di */ 933 1, /* branch_cost */ 934 4 /* memory_latency */ 935 }, 936 { /* 74KF1_1 */ 937 COSTS_N_INSNS (4), /* fp_add */ 938 COSTS_N_INSNS (4), /* fp_mult_sf */ 939 COSTS_N_INSNS (5), /* fp_mult_df */ 940 COSTS_N_INSNS (17), /* fp_div_sf */ 941 COSTS_N_INSNS (32), /* fp_div_df */ 942 COSTS_N_INSNS (5), /* int_mult_si */ 943 COSTS_N_INSNS (5), /* int_mult_di */ 944 COSTS_N_INSNS (41), /* int_div_si */ 945 COSTS_N_INSNS (41), /* int_div_di */ 946 1, /* branch_cost */ 947 4 /* memory_latency */ 948 }, 949 { /* 74KF3_2 */ 950 COSTS_N_INSNS (6), /* fp_add */ 951 COSTS_N_INSNS (6), /* fp_mult_sf */ 952 COSTS_N_INSNS (7), /* fp_mult_df */ 953 COSTS_N_INSNS (25), /* fp_div_sf */ 954 COSTS_N_INSNS (48), /* fp_div_df */ 955 COSTS_N_INSNS (5), /* int_mult_si */ 956 COSTS_N_INSNS (5), /* int_mult_di */ 957 COSTS_N_INSNS (41), /* int_div_si */ 958 COSTS_N_INSNS (41), /* int_div_di */ 959 1, /* branch_cost */ 960 4 /* memory_latency */ 961 }, 962 { /* Loongson-2E */ 963 DEFAULT_COSTS 964 }, 965 { /* Loongson-2F */ 966 DEFAULT_COSTS 967 }, 968 { /* Loongson-3A */ 969 DEFAULT_COSTS 970 }, 971 { /* M4k */ 972 DEFAULT_COSTS 973 }, 974 /* Octeon */ 975 { 976 SOFT_FP_COSTS, 977 COSTS_N_INSNS (5), /* int_mult_si */ 978 COSTS_N_INSNS (5), /* int_mult_di */ 979 COSTS_N_INSNS (72), /* int_div_si */ 980 COSTS_N_INSNS (72), /* int_div_di */ 981 1, /* branch_cost */ 982 4 /* memory_latency */ 983 }, 984 /* Octeon II */ 985 { 986 SOFT_FP_COSTS, 987 COSTS_N_INSNS (6), /* int_mult_si */ 988 COSTS_N_INSNS (6), /* int_mult_di */ 989 COSTS_N_INSNS (18), /* int_div_si */ 990 COSTS_N_INSNS (35), /* int_div_di */ 991 4, /* branch_cost */ 992 4 /* memory_latency */ 993 }, 994 /* Octeon III */ 995 { 996 COSTS_N_INSNS (6), /* fp_add */ 997 COSTS_N_INSNS (6), /* fp_mult_sf */ 998 COSTS_N_INSNS (7), /* fp_mult_df */ 999 COSTS_N_INSNS (25), /* fp_div_sf */ 1000 COSTS_N_INSNS (48), /* fp_div_df */ 1001 COSTS_N_INSNS (6), /* int_mult_si */ 1002 COSTS_N_INSNS (6), /* int_mult_di */ 1003 COSTS_N_INSNS (18), /* int_div_si */ 1004 COSTS_N_INSNS (35), /* int_div_di */ 1005 4, /* branch_cost */ 1006 4 /* memory_latency */ 1007 }, 1008 { /* R3900 */ 1009 COSTS_N_INSNS (2), /* fp_add */ 1010 COSTS_N_INSNS (4), /* fp_mult_sf */ 1011 COSTS_N_INSNS (5), /* fp_mult_df */ 1012 COSTS_N_INSNS (12), /* fp_div_sf */ 1013 COSTS_N_INSNS (19), /* fp_div_df */ 1014 COSTS_N_INSNS (2), /* int_mult_si */ 1015 COSTS_N_INSNS (2), /* int_mult_di */ 1016 COSTS_N_INSNS (35), /* int_div_si */ 1017 COSTS_N_INSNS (35), /* int_div_di */ 1018 1, /* branch_cost */ 1019 4 /* memory_latency */ 1020 }, 1021 { /* R6000 */ 1022 COSTS_N_INSNS (3), /* fp_add */ 1023 COSTS_N_INSNS (5), /* fp_mult_sf */ 1024 COSTS_N_INSNS (6), /* fp_mult_df */ 1025 COSTS_N_INSNS (15), /* fp_div_sf */ 1026 COSTS_N_INSNS (16), /* fp_div_df */ 1027 COSTS_N_INSNS (17), /* int_mult_si */ 1028 COSTS_N_INSNS (17), /* int_mult_di */ 1029 COSTS_N_INSNS (38), /* int_div_si */ 1030 COSTS_N_INSNS (38), /* int_div_di */ 1031 2, /* branch_cost */ 1032 6 /* memory_latency */ 1033 }, 1034 { /* R4000 */ 1035 COSTS_N_INSNS (6), /* fp_add */ 1036 COSTS_N_INSNS (7), /* fp_mult_sf */ 1037 COSTS_N_INSNS (8), /* fp_mult_df */ 1038 COSTS_N_INSNS (23), /* fp_div_sf */ 1039 COSTS_N_INSNS (36), /* fp_div_df */ 1040 COSTS_N_INSNS (10), /* int_mult_si */ 1041 COSTS_N_INSNS (10), /* int_mult_di */ 1042 COSTS_N_INSNS (69), /* int_div_si */ 1043 COSTS_N_INSNS (69), /* int_div_di */ 1044 2, /* branch_cost */ 1045 6 /* memory_latency */ 1046 }, 1047 { /* R4100 */ 1048 DEFAULT_COSTS 1049 }, 1050 { /* R4111 */ 1051 DEFAULT_COSTS 1052 }, 1053 { /* R4120 */ 1054 DEFAULT_COSTS 1055 }, 1056 { /* R4130 */ 1057 /* The only costs that appear to be updated here are 1058 integer multiplication. */ 1059 SOFT_FP_COSTS, 1060 COSTS_N_INSNS (4), /* int_mult_si */ 1061 COSTS_N_INSNS (6), /* int_mult_di */ 1062 COSTS_N_INSNS (69), /* int_div_si */ 1063 COSTS_N_INSNS (69), /* int_div_di */ 1064 1, /* branch_cost */ 1065 4 /* memory_latency */ 1066 }, 1067 { /* R4300 */ 1068 DEFAULT_COSTS 1069 }, 1070 { /* R4600 */ 1071 DEFAULT_COSTS 1072 }, 1073 { /* R4650 */ 1074 DEFAULT_COSTS 1075 }, 1076 { /* R4700 */ 1077 DEFAULT_COSTS 1078 }, 1079 { /* R5000 */ 1080 COSTS_N_INSNS (6), /* fp_add */ 1081 COSTS_N_INSNS (4), /* fp_mult_sf */ 1082 COSTS_N_INSNS (5), /* fp_mult_df */ 1083 COSTS_N_INSNS (23), /* fp_div_sf */ 1084 COSTS_N_INSNS (36), /* fp_div_df */ 1085 COSTS_N_INSNS (5), /* int_mult_si */ 1086 COSTS_N_INSNS (5), /* int_mult_di */ 1087 COSTS_N_INSNS (36), /* int_div_si */ 1088 COSTS_N_INSNS (36), /* int_div_di */ 1089 1, /* branch_cost */ 1090 4 /* memory_latency */ 1091 }, 1092 { /* R5400 */ 1093 COSTS_N_INSNS (6), /* fp_add */ 1094 COSTS_N_INSNS (5), /* fp_mult_sf */ 1095 COSTS_N_INSNS (6), /* fp_mult_df */ 1096 COSTS_N_INSNS (30), /* fp_div_sf */ 1097 COSTS_N_INSNS (59), /* fp_div_df */ 1098 COSTS_N_INSNS (3), /* int_mult_si */ 1099 COSTS_N_INSNS (4), /* int_mult_di */ 1100 COSTS_N_INSNS (42), /* int_div_si */ 1101 COSTS_N_INSNS (74), /* int_div_di */ 1102 1, /* branch_cost */ 1103 4 /* memory_latency */ 1104 }, 1105 { /* R5500 */ 1106 COSTS_N_INSNS (6), /* fp_add */ 1107 COSTS_N_INSNS (5), /* fp_mult_sf */ 1108 COSTS_N_INSNS (6), /* fp_mult_df */ 1109 COSTS_N_INSNS (30), /* fp_div_sf */ 1110 COSTS_N_INSNS (59), /* fp_div_df */ 1111 COSTS_N_INSNS (5), /* int_mult_si */ 1112 COSTS_N_INSNS (9), /* int_mult_di */ 1113 COSTS_N_INSNS (42), /* int_div_si */ 1114 COSTS_N_INSNS (74), /* int_div_di */ 1115 1, /* branch_cost */ 1116 4 /* memory_latency */ 1117 }, 1118 { /* R5900 */ 1119 COSTS_N_INSNS (4), /* fp_add */ 1120 COSTS_N_INSNS (4), /* fp_mult_sf */ 1121 COSTS_N_INSNS (256), /* fp_mult_df */ 1122 COSTS_N_INSNS (8), /* fp_div_sf */ 1123 COSTS_N_INSNS (256), /* fp_div_df */ 1124 COSTS_N_INSNS (4), /* int_mult_si */ 1125 COSTS_N_INSNS (256), /* int_mult_di */ 1126 COSTS_N_INSNS (37), /* int_div_si */ 1127 COSTS_N_INSNS (256), /* int_div_di */ 1128 1, /* branch_cost */ 1129 4 /* memory_latency */ 1130 }, 1131 { /* R7000 */ 1132 /* The only costs that are changed here are 1133 integer multiplication. */ 1134 COSTS_N_INSNS (6), /* fp_add */ 1135 COSTS_N_INSNS (7), /* fp_mult_sf */ 1136 COSTS_N_INSNS (8), /* fp_mult_df */ 1137 COSTS_N_INSNS (23), /* fp_div_sf */ 1138 COSTS_N_INSNS (36), /* fp_div_df */ 1139 COSTS_N_INSNS (5), /* int_mult_si */ 1140 COSTS_N_INSNS (9), /* int_mult_di */ 1141 COSTS_N_INSNS (69), /* int_div_si */ 1142 COSTS_N_INSNS (69), /* int_div_di */ 1143 1, /* branch_cost */ 1144 4 /* memory_latency */ 1145 }, 1146 { /* R8000 */ 1147 DEFAULT_COSTS 1148 }, 1149 { /* R9000 */ 1150 /* The only costs that are changed here are 1151 integer multiplication. */ 1152 COSTS_N_INSNS (6), /* fp_add */ 1153 COSTS_N_INSNS (7), /* fp_mult_sf */ 1154 COSTS_N_INSNS (8), /* fp_mult_df */ 1155 COSTS_N_INSNS (23), /* fp_div_sf */ 1156 COSTS_N_INSNS (36), /* fp_div_df */ 1157 COSTS_N_INSNS (3), /* int_mult_si */ 1158 COSTS_N_INSNS (8), /* int_mult_di */ 1159 COSTS_N_INSNS (69), /* int_div_si */ 1160 COSTS_N_INSNS (69), /* int_div_di */ 1161 1, /* branch_cost */ 1162 4 /* memory_latency */ 1163 }, 1164 { /* R1x000 */ 1165 COSTS_N_INSNS (2), /* fp_add */ 1166 COSTS_N_INSNS (2), /* fp_mult_sf */ 1167 COSTS_N_INSNS (2), /* fp_mult_df */ 1168 COSTS_N_INSNS (12), /* fp_div_sf */ 1169 COSTS_N_INSNS (19), /* fp_div_df */ 1170 COSTS_N_INSNS (5), /* int_mult_si */ 1171 COSTS_N_INSNS (9), /* int_mult_di */ 1172 COSTS_N_INSNS (34), /* int_div_si */ 1173 COSTS_N_INSNS (66), /* int_div_di */ 1174 1, /* branch_cost */ 1175 4 /* memory_latency */ 1176 }, 1177 { /* SB1 */ 1178 /* These costs are the same as the SB-1A below. */ 1179 COSTS_N_INSNS (4), /* fp_add */ 1180 COSTS_N_INSNS (4), /* fp_mult_sf */ 1181 COSTS_N_INSNS (4), /* fp_mult_df */ 1182 COSTS_N_INSNS (24), /* fp_div_sf */ 1183 COSTS_N_INSNS (32), /* fp_div_df */ 1184 COSTS_N_INSNS (3), /* int_mult_si */ 1185 COSTS_N_INSNS (4), /* int_mult_di */ 1186 COSTS_N_INSNS (36), /* int_div_si */ 1187 COSTS_N_INSNS (68), /* int_div_di */ 1188 1, /* branch_cost */ 1189 4 /* memory_latency */ 1190 }, 1191 { /* SB1-A */ 1192 /* These costs are the same as the SB-1 above. */ 1193 COSTS_N_INSNS (4), /* fp_add */ 1194 COSTS_N_INSNS (4), /* fp_mult_sf */ 1195 COSTS_N_INSNS (4), /* fp_mult_df */ 1196 COSTS_N_INSNS (24), /* fp_div_sf */ 1197 COSTS_N_INSNS (32), /* fp_div_df */ 1198 COSTS_N_INSNS (3), /* int_mult_si */ 1199 COSTS_N_INSNS (4), /* int_mult_di */ 1200 COSTS_N_INSNS (36), /* int_div_si */ 1201 COSTS_N_INSNS (68), /* int_div_di */ 1202 1, /* branch_cost */ 1203 4 /* memory_latency */ 1204 }, 1205 { /* SR71000 */ 1206 DEFAULT_COSTS 1207 }, 1208 { /* XLR */ 1209 SOFT_FP_COSTS, 1210 COSTS_N_INSNS (8), /* int_mult_si */ 1211 COSTS_N_INSNS (8), /* int_mult_di */ 1212 COSTS_N_INSNS (72), /* int_div_si */ 1213 COSTS_N_INSNS (72), /* int_div_di */ 1214 1, /* branch_cost */ 1215 4 /* memory_latency */ 1216 }, 1217 { /* XLP */ 1218 /* These costs are the same as 5KF above. */ 1219 COSTS_N_INSNS (4), /* fp_add */ 1220 COSTS_N_INSNS (4), /* fp_mult_sf */ 1221 COSTS_N_INSNS (5), /* fp_mult_df */ 1222 COSTS_N_INSNS (17), /* fp_div_sf */ 1223 COSTS_N_INSNS (32), /* fp_div_df */ 1224 COSTS_N_INSNS (4), /* int_mult_si */ 1225 COSTS_N_INSNS (11), /* int_mult_di */ 1226 COSTS_N_INSNS (36), /* int_div_si */ 1227 COSTS_N_INSNS (68), /* int_div_di */ 1228 1, /* branch_cost */ 1229 4 /* memory_latency */ 1230 }, 1231 { /* P5600 */ 1232 COSTS_N_INSNS (4), /* fp_add */ 1233 COSTS_N_INSNS (5), /* fp_mult_sf */ 1234 COSTS_N_INSNS (5), /* fp_mult_df */ 1235 COSTS_N_INSNS (17), /* fp_div_sf */ 1236 COSTS_N_INSNS (17), /* fp_div_df */ 1237 COSTS_N_INSNS (5), /* int_mult_si */ 1238 COSTS_N_INSNS (5), /* int_mult_di */ 1239 COSTS_N_INSNS (8), /* int_div_si */ 1240 COSTS_N_INSNS (8), /* int_div_di */ 1241 2, /* branch_cost */ 1242 4 /* memory_latency */ 1243 }, 1244 { /* W32 */ 1245 COSTS_N_INSNS (4), /* fp_add */ 1246 COSTS_N_INSNS (4), /* fp_mult_sf */ 1247 COSTS_N_INSNS (5), /* fp_mult_df */ 1248 COSTS_N_INSNS (17), /* fp_div_sf */ 1249 COSTS_N_INSNS (32), /* fp_div_df */ 1250 COSTS_N_INSNS (5), /* int_mult_si */ 1251 COSTS_N_INSNS (5), /* int_mult_di */ 1252 COSTS_N_INSNS (41), /* int_div_si */ 1253 COSTS_N_INSNS (41), /* int_div_di */ 1254 1, /* branch_cost */ 1255 4 /* memory_latency */ 1256 }, 1257 { /* W64 */ 1258 COSTS_N_INSNS (4), /* fp_add */ 1259 COSTS_N_INSNS (4), /* fp_mult_sf */ 1260 COSTS_N_INSNS (5), /* fp_mult_df */ 1261 COSTS_N_INSNS (17), /* fp_div_sf */ 1262 COSTS_N_INSNS (32), /* fp_div_df */ 1263 COSTS_N_INSNS (5), /* int_mult_si */ 1264 COSTS_N_INSNS (5), /* int_mult_di */ 1265 COSTS_N_INSNS (41), /* int_div_si */ 1266 COSTS_N_INSNS (41), /* int_div_di */ 1267 1, /* branch_cost */ 1268 4 /* memory_latency */ 1269 } 1270}; 1271 1272static rtx mips_find_pic_call_symbol (rtx_insn *, rtx, bool); 1273static int mips_register_move_cost (machine_mode, reg_class_t, 1274 reg_class_t); 1275static unsigned int mips_function_arg_boundary (machine_mode, const_tree); 1276static machine_mode mips_get_reg_raw_mode (int regno); 1277 1278struct mips16_flip_traits : default_hashmap_traits 1279{ 1280 static hashval_t hash (const char *s) { return htab_hash_string (s); } 1281 static bool 1282 equal_keys (const char *a, const char *b) 1283 { 1284 return !strcmp (a, b); 1285 } 1286}; 1287 1288/* This hash table keeps track of implicit "mips16" and "nomips16" attributes 1289 for -mflip_mips16. It maps decl names onto a boolean mode setting. */ 1290static GTY (()) hash_map<const char *, bool, mips16_flip_traits> * 1291 mflip_mips16_htab; 1292 1293/* True if -mflip-mips16 should next add an attribute for the default MIPS16 1294 mode, false if it should next add an attribute for the opposite mode. */ 1295static GTY(()) bool mips16_flipper; 1296 1297/* DECL is a function that needs a default "mips16" or "nomips16" attribute 1298 for -mflip-mips16. Return true if it should use "mips16" and false if 1299 it should use "nomips16". */ 1300 1301static bool 1302mflip_mips16_use_mips16_p (tree decl) 1303{ 1304 const char *name; 1305 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0; 1306 1307 /* Use the opposite of the command-line setting for anonymous decls. */ 1308 if (!DECL_NAME (decl)) 1309 return !base_is_mips16; 1310 1311 if (!mflip_mips16_htab) 1312 mflip_mips16_htab 1313 = hash_map<const char *, bool, mips16_flip_traits>::create_ggc (37); 1314 1315 name = IDENTIFIER_POINTER (DECL_NAME (decl)); 1316 1317 bool existed; 1318 bool *slot = &mflip_mips16_htab->get_or_insert (name, &existed); 1319 if (!existed) 1320 { 1321 mips16_flipper = !mips16_flipper; 1322 *slot = mips16_flipper ? !base_is_mips16 : base_is_mips16; 1323 } 1324 return *slot; 1325} 1326 1327/* Predicates to test for presence of "near" and "far"/"long_call" 1328 attributes on the given TYPE. */ 1329 1330static bool 1331mips_near_type_p (const_tree type) 1332{ 1333 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; 1334} 1335 1336static bool 1337mips_far_type_p (const_tree type) 1338{ 1339 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL 1340 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); 1341} 1342 1343 1344/* Check if the interrupt attribute is set for a function. */ 1345 1346static bool 1347mips_interrupt_type_p (tree type) 1348{ 1349 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; 1350} 1351 1352/* Check if the attribute to use shadow register set is set for a function. */ 1353 1354static bool 1355mips_use_shadow_register_set_p (tree type) 1356{ 1357 return lookup_attribute ("use_shadow_register_set", 1358 TYPE_ATTRIBUTES (type)) != NULL; 1359} 1360 1361/* Check if the attribute to keep interrupts masked is set for a function. */ 1362 1363static bool 1364mips_keep_interrupts_masked_p (tree type) 1365{ 1366 return lookup_attribute ("keep_interrupts_masked", 1367 TYPE_ATTRIBUTES (type)) != NULL; 1368} 1369 1370/* Check if the attribute to use debug exception return is set for 1371 a function. */ 1372 1373static bool 1374mips_use_debug_exception_return_p (tree type) 1375{ 1376 return lookup_attribute ("use_debug_exception_return", 1377 TYPE_ATTRIBUTES (type)) != NULL; 1378} 1379 1380/* Return the set of compression modes that are explicitly required 1381 by the attributes in ATTRIBUTES. */ 1382 1383static unsigned int 1384mips_get_compress_on_flags (tree attributes) 1385{ 1386 unsigned int flags = 0; 1387 1388 if (lookup_attribute ("mips16", attributes) != NULL) 1389 flags |= MASK_MIPS16; 1390 1391 if (lookup_attribute ("micromips", attributes) != NULL) 1392 flags |= MASK_MICROMIPS; 1393 1394 return flags; 1395} 1396 1397/* Return the set of compression modes that are explicitly forbidden 1398 by the attributes in ATTRIBUTES. */ 1399 1400static unsigned int 1401mips_get_compress_off_flags (tree attributes) 1402{ 1403 unsigned int flags = 0; 1404 1405 if (lookup_attribute ("nocompression", attributes) != NULL) 1406 flags |= MASK_MIPS16 | MASK_MICROMIPS; 1407 1408 if (lookup_attribute ("nomips16", attributes) != NULL) 1409 flags |= MASK_MIPS16; 1410 1411 if (lookup_attribute ("nomicromips", attributes) != NULL) 1412 flags |= MASK_MICROMIPS; 1413 1414 return flags; 1415} 1416 1417/* Return the compression mode that should be used for function DECL. 1418 Return the ambient setting if DECL is null. */ 1419 1420static unsigned int 1421mips_get_compress_mode (tree decl) 1422{ 1423 unsigned int flags, force_on; 1424 1425 flags = mips_base_compression_flags; 1426 if (decl) 1427 { 1428 /* Nested functions must use the same frame pointer as their 1429 parent and must therefore use the same ISA mode. */ 1430 tree parent = decl_function_context (decl); 1431 if (parent) 1432 decl = parent; 1433 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)); 1434 if (force_on) 1435 return force_on; 1436 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)); 1437 } 1438 return flags; 1439} 1440 1441/* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS 1442 flags FLAGS. */ 1443 1444static const char * 1445mips_get_compress_on_name (unsigned int flags) 1446{ 1447 if (flags == MASK_MIPS16) 1448 return "mips16"; 1449 return "micromips"; 1450} 1451 1452/* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS 1453 flags FLAGS. */ 1454 1455static const char * 1456mips_get_compress_off_name (unsigned int flags) 1457{ 1458 if (flags == MASK_MIPS16) 1459 return "nomips16"; 1460 if (flags == MASK_MICROMIPS) 1461 return "nomicromips"; 1462 return "nocompression"; 1463} 1464 1465/* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ 1466 1467static int 1468mips_comp_type_attributes (const_tree type1, const_tree type2) 1469{ 1470 /* Disallow mixed near/far attributes. */ 1471 if (mips_far_type_p (type1) && mips_near_type_p (type2)) 1472 return 0; 1473 if (mips_near_type_p (type1) && mips_far_type_p (type2)) 1474 return 0; 1475 return 1; 1476} 1477 1478/* Implement TARGET_INSERT_ATTRIBUTES. */ 1479 1480static void 1481mips_insert_attributes (tree decl, tree *attributes) 1482{ 1483 const char *name; 1484 unsigned int compression_flags, nocompression_flags; 1485 1486 /* Check for "mips16" and "nomips16" attributes. */ 1487 compression_flags = mips_get_compress_on_flags (*attributes); 1488 nocompression_flags = mips_get_compress_off_flags (*attributes); 1489 1490 if (TREE_CODE (decl) != FUNCTION_DECL) 1491 { 1492 if (nocompression_flags) 1493 error ("%qs attribute only applies to functions", 1494 mips_get_compress_off_name (nocompression_flags)); 1495 1496 if (compression_flags) 1497 error ("%qs attribute only applies to functions", 1498 mips_get_compress_on_name (nocompression_flags)); 1499 } 1500 else 1501 { 1502 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)); 1503 nocompression_flags |= 1504 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)); 1505 1506 if (compression_flags && nocompression_flags) 1507 error ("%qE cannot have both %qs and %qs attributes", 1508 DECL_NAME (decl), mips_get_compress_on_name (compression_flags), 1509 mips_get_compress_off_name (nocompression_flags)); 1510 1511 if (compression_flags & MASK_MIPS16 1512 && compression_flags & MASK_MICROMIPS) 1513 error ("%qE cannot have both %qs and %qs attributes", 1514 DECL_NAME (decl), "mips16", "micromips"); 1515 1516 if (TARGET_FLIP_MIPS16 1517 && !DECL_ARTIFICIAL (decl) 1518 && compression_flags == 0 1519 && nocompression_flags == 0) 1520 { 1521 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a 1522 "mips16" attribute, arbitrarily pick one. We must pick the same 1523 setting for duplicate declarations of a function. */ 1524 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16"; 1525 *attributes = tree_cons (get_identifier (name), NULL, *attributes); 1526 name = "nomicromips"; 1527 *attributes = tree_cons (get_identifier (name), NULL, *attributes); 1528 } 1529 } 1530} 1531 1532/* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ 1533 1534static tree 1535mips_merge_decl_attributes (tree olddecl, tree newdecl) 1536{ 1537 unsigned int diff; 1538 1539 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl)) 1540 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl))); 1541 if (diff) 1542 error ("%qE redeclared with conflicting %qs attributes", 1543 DECL_NAME (newdecl), mips_get_compress_on_name (diff)); 1544 1545 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl)) 1546 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl))); 1547 if (diff) 1548 error ("%qE redeclared with conflicting %qs attributes", 1549 DECL_NAME (newdecl), mips_get_compress_off_name (diff)); 1550 1551 return merge_attributes (DECL_ATTRIBUTES (olddecl), 1552 DECL_ATTRIBUTES (newdecl)); 1553} 1554 1555/* Implement TARGET_CAN_INLINE_P. */ 1556 1557static bool 1558mips_can_inline_p (tree caller, tree callee) 1559{ 1560 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller)) 1561 return false; 1562 return default_target_can_inline_p (caller, callee); 1563} 1564 1565/* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR 1566 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */ 1567 1568static void 1569mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr) 1570{ 1571 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) 1572 { 1573 *base_ptr = XEXP (x, 0); 1574 *offset_ptr = INTVAL (XEXP (x, 1)); 1575 } 1576 else 1577 { 1578 *base_ptr = x; 1579 *offset_ptr = 0; 1580 } 1581} 1582 1583static unsigned int mips_build_integer (struct mips_integer_op *, 1584 unsigned HOST_WIDE_INT); 1585 1586/* A subroutine of mips_build_integer, with the same interface. 1587 Assume that the final action in the sequence should be a left shift. */ 1588 1589static unsigned int 1590mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value) 1591{ 1592 unsigned int i, shift; 1593 1594 /* Shift VALUE right until its lowest bit is set. Shift arithmetically 1595 since signed numbers are easier to load than unsigned ones. */ 1596 shift = 0; 1597 while ((value & 1) == 0) 1598 value /= 2, shift++; 1599 1600 i = mips_build_integer (codes, value); 1601 codes[i].code = ASHIFT; 1602 codes[i].value = shift; 1603 return i + 1; 1604} 1605 1606/* As for mips_build_shift, but assume that the final action will be 1607 an IOR or PLUS operation. */ 1608 1609static unsigned int 1610mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) 1611{ 1612 unsigned HOST_WIDE_INT high; 1613 unsigned int i; 1614 1615 high = value & ~(unsigned HOST_WIDE_INT) 0xffff; 1616 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000) 1617 { 1618 /* The constant is too complex to load with a simple LUI/ORI pair, 1619 so we want to give the recursive call as many trailing zeros as 1620 possible. In this case, we know bit 16 is set and that the 1621 low 16 bits form a negative number. If we subtract that number 1622 from VALUE, we will clear at least the lowest 17 bits, maybe more. */ 1623 i = mips_build_integer (codes, CONST_HIGH_PART (value)); 1624 codes[i].code = PLUS; 1625 codes[i].value = CONST_LOW_PART (value); 1626 } 1627 else 1628 { 1629 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16 1630 bits gives a value with at least 17 trailing zeros. */ 1631 i = mips_build_integer (codes, high); 1632 codes[i].code = IOR; 1633 codes[i].value = value & 0xffff; 1634 } 1635 return i + 1; 1636} 1637 1638/* Fill CODES with a sequence of rtl operations to load VALUE. 1639 Return the number of operations needed. */ 1640 1641static unsigned int 1642mips_build_integer (struct mips_integer_op *codes, 1643 unsigned HOST_WIDE_INT value) 1644{ 1645 if (SMALL_OPERAND (value) 1646 || SMALL_OPERAND_UNSIGNED (value) 1647 || LUI_OPERAND (value)) 1648 { 1649 /* The value can be loaded with a single instruction. */ 1650 codes[0].code = UNKNOWN; 1651 codes[0].value = value; 1652 return 1; 1653 } 1654 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value))) 1655 { 1656 /* Either the constant is a simple LUI/ORI combination or its 1657 lowest bit is set. We don't want to shift in this case. */ 1658 return mips_build_lower (codes, value); 1659 } 1660 else if ((value & 0xffff) == 0) 1661 { 1662 /* The constant will need at least three actions. The lowest 1663 16 bits are clear, so the final action will be a shift. */ 1664 return mips_build_shift (codes, value); 1665 } 1666 else 1667 { 1668 /* The final action could be a shift, add or inclusive OR. 1669 Rather than use a complex condition to select the best 1670 approach, try both mips_build_shift and mips_build_lower 1671 and pick the one that gives the shortest sequence. 1672 Note that this case is only used once per constant. */ 1673 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS]; 1674 unsigned int cost, alt_cost; 1675 1676 cost = mips_build_shift (codes, value); 1677 alt_cost = mips_build_lower (alt_codes, value); 1678 if (alt_cost < cost) 1679 { 1680 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0])); 1681 cost = alt_cost; 1682 } 1683 return cost; 1684 } 1685} 1686 1687/* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 1688 1689static bool 1690mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1691{ 1692 return mips_const_insns (x) > 0; 1693} 1694 1695/* Return a SYMBOL_REF for a MIPS16 function called NAME. */ 1696 1697static rtx 1698mips16_stub_function (const char *name) 1699{ 1700 rtx x; 1701 1702 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); 1703 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION); 1704 return x; 1705} 1706 1707/* Return a legitimate call address for STUB, given that STUB is a MIPS16 1708 support function. */ 1709 1710static rtx 1711mips16_stub_call_address (mips_one_only_stub *stub) 1712{ 1713 rtx fn = mips16_stub_function (stub->get_name ()); 1714 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL; 1715 if (!call_insn_operand (fn, VOIDmode)) 1716 fn = force_reg (Pmode, fn); 1717 return fn; 1718} 1719 1720/* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */ 1721 1722class mips16_rdhwr_one_only_stub : public mips_one_only_stub 1723{ 1724 virtual const char *get_name (); 1725 virtual void output_body (); 1726}; 1727 1728const char * 1729mips16_rdhwr_one_only_stub::get_name () 1730{ 1731 return "__mips16_rdhwr"; 1732} 1733 1734void 1735mips16_rdhwr_one_only_stub::output_body () 1736{ 1737 fprintf (asm_out_file, 1738 "\t.set\tpush\n" 1739 "\t.set\tmips32r2\n" 1740 "\t.set\tnoreorder\n" 1741 "\trdhwr\t$3,$29\n" 1742 "\t.set\tpop\n" 1743 "\tj\t$31\n"); 1744} 1745 1746/* A stub for moving the FCSR into GET_FCSR_REGNUM. */ 1747class mips16_get_fcsr_one_only_stub : public mips_one_only_stub 1748{ 1749 virtual const char *get_name (); 1750 virtual void output_body (); 1751}; 1752 1753const char * 1754mips16_get_fcsr_one_only_stub::get_name () 1755{ 1756 return "__mips16_get_fcsr"; 1757} 1758 1759void 1760mips16_get_fcsr_one_only_stub::output_body () 1761{ 1762 fprintf (asm_out_file, 1763 "\tcfc1\t%s,$31\n" 1764 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]); 1765} 1766 1767/* A stub for moving SET_FCSR_REGNUM into the FCSR. */ 1768class mips16_set_fcsr_one_only_stub : public mips_one_only_stub 1769{ 1770 virtual const char *get_name (); 1771 virtual void output_body (); 1772}; 1773 1774const char * 1775mips16_set_fcsr_one_only_stub::get_name () 1776{ 1777 return "__mips16_set_fcsr"; 1778} 1779 1780void 1781mips16_set_fcsr_one_only_stub::output_body () 1782{ 1783 fprintf (asm_out_file, 1784 "\tctc1\t%s,$31\n" 1785 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]); 1786} 1787 1788/* Return true if symbols of type TYPE require a GOT access. */ 1789 1790static bool 1791mips_got_symbol_type_p (enum mips_symbol_type type) 1792{ 1793 switch (type) 1794 { 1795 case SYMBOL_GOT_PAGE_OFST: 1796 case SYMBOL_GOT_DISP: 1797 return true; 1798 1799 default: 1800 return false; 1801 } 1802} 1803 1804/* Return true if X is a thread-local symbol. */ 1805 1806static bool 1807mips_tls_symbol_p (rtx x) 1808{ 1809 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; 1810} 1811 1812/* Return true if SYMBOL_REF X is associated with a global symbol 1813 (in the STB_GLOBAL sense). */ 1814 1815static bool 1816mips_global_symbol_p (const_rtx x) 1817{ 1818 const_tree decl = SYMBOL_REF_DECL (x); 1819 1820 if (!decl) 1821 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x); 1822 1823 /* Weakref symbols are not TREE_PUBLIC, but their targets are global 1824 or weak symbols. Relocations in the object file will be against 1825 the target symbol, so it's that symbol's binding that matters here. */ 1826 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl)); 1827} 1828 1829/* Return true if function X is a libgcc MIPS16 stub function. */ 1830 1831static bool 1832mips16_stub_function_p (const_rtx x) 1833{ 1834 return (GET_CODE (x) == SYMBOL_REF 1835 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0); 1836} 1837 1838/* Return true if function X is a locally-defined and locally-binding 1839 MIPS16 function. */ 1840 1841static bool 1842mips16_local_function_p (const_rtx x) 1843{ 1844 return (GET_CODE (x) == SYMBOL_REF 1845 && SYMBOL_REF_LOCAL_P (x) 1846 && !SYMBOL_REF_EXTERNAL_P (x) 1847 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16)); 1848} 1849 1850/* Return true if SYMBOL_REF X binds locally. */ 1851 1852static bool 1853mips_symbol_binds_local_p (const_rtx x) 1854{ 1855 return (SYMBOL_REF_DECL (x) 1856 ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) 1857 : SYMBOL_REF_LOCAL_P (x)); 1858} 1859 1860/* Return true if rtx constants of mode MODE should be put into a small 1861 data section. */ 1862 1863static bool 1864mips_rtx_constant_in_small_data_p (machine_mode mode) 1865{ 1866 return (!TARGET_EMBEDDED_DATA 1867 && TARGET_LOCAL_SDATA 1868 && GET_MODE_SIZE (mode) <= mips_small_data_threshold); 1869} 1870 1871/* Return true if X should not be moved directly into register $25. 1872 We need this because many versions of GAS will treat "la $25,foo" as 1873 part of a call sequence and so allow a global "foo" to be lazily bound. */ 1874 1875bool 1876mips_dangerous_for_la25_p (rtx x) 1877{ 1878 return (!TARGET_EXPLICIT_RELOCS 1879 && TARGET_USE_GOT 1880 && GET_CODE (x) == SYMBOL_REF 1881 && mips_global_symbol_p (x)); 1882} 1883 1884/* Return true if calls to X might need $25 to be valid on entry. */ 1885 1886bool 1887mips_use_pic_fn_addr_reg_p (const_rtx x) 1888{ 1889 if (!TARGET_USE_PIC_FN_ADDR_REG) 1890 return false; 1891 1892 /* MIPS16 stub functions are guaranteed not to use $25. */ 1893 if (mips16_stub_function_p (x)) 1894 return false; 1895 1896 if (GET_CODE (x) == SYMBOL_REF) 1897 { 1898 /* If PLTs and copy relocations are available, the static linker 1899 will make sure that $25 is valid on entry to the target function. */ 1900 if (TARGET_ABICALLS_PIC0) 1901 return false; 1902 1903 /* Locally-defined functions use absolute accesses to set up 1904 the global pointer. */ 1905 if (TARGET_ABSOLUTE_ABICALLS 1906 && mips_symbol_binds_local_p (x) 1907 && !SYMBOL_REF_EXTERNAL_P (x)) 1908 return false; 1909 } 1910 1911 return true; 1912} 1913 1914/* Return the method that should be used to access SYMBOL_REF or 1915 LABEL_REF X in context CONTEXT. */ 1916 1917static enum mips_symbol_type 1918mips_classify_symbol (const_rtx x, enum mips_symbol_context context) 1919{ 1920 if (TARGET_RTP_PIC) 1921 return SYMBOL_GOT_DISP; 1922 1923 if (GET_CODE (x) == LABEL_REF) 1924 { 1925 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16 1926 code and if we know that the label is in the current function's 1927 text section. LABEL_REFs are used for jump tables as well as 1928 text labels, so we must check whether jump tables live in the 1929 text section. */ 1930 if (TARGET_MIPS16_SHORT_JUMP_TABLES 1931 && !LABEL_REF_NONLOCAL_P (x)) 1932 return SYMBOL_PC_RELATIVE; 1933 1934 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 1935 return SYMBOL_GOT_PAGE_OFST; 1936 1937 return SYMBOL_ABSOLUTE; 1938 } 1939 1940 gcc_assert (GET_CODE (x) == SYMBOL_REF); 1941 1942 if (SYMBOL_REF_TLS_MODEL (x)) 1943 return SYMBOL_TLS; 1944 1945 if (CONSTANT_POOL_ADDRESS_P (x)) 1946 { 1947 if (TARGET_MIPS16_TEXT_LOADS) 1948 return SYMBOL_PC_RELATIVE; 1949 1950 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM) 1951 return SYMBOL_PC_RELATIVE; 1952 1953 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x))) 1954 return SYMBOL_GP_RELATIVE; 1955 } 1956 1957 /* Do not use small-data accesses for weak symbols; they may end up 1958 being zero. */ 1959 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x)) 1960 return SYMBOL_GP_RELATIVE; 1961 1962 /* Don't use GOT accesses for locally-binding symbols when -mno-shared 1963 is in effect. */ 1964 if (TARGET_ABICALLS_PIC2 1965 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))) 1966 { 1967 /* There are three cases to consider: 1968 1969 - o32 PIC (either with or without explicit relocs) 1970 - n32/n64 PIC without explicit relocs 1971 - n32/n64 PIC with explicit relocs 1972 1973 In the first case, both local and global accesses will use an 1974 R_MIPS_GOT16 relocation. We must correctly predict which of 1975 the two semantics (local or global) the assembler and linker 1976 will apply. The choice depends on the symbol's binding rather 1977 than its visibility. 1978 1979 In the second case, the assembler will not use R_MIPS_GOT16 1980 relocations, but it chooses between local and global accesses 1981 in the same way as for o32 PIC. 1982 1983 In the third case we have more freedom since both forms of 1984 access will work for any kind of symbol. However, there seems 1985 little point in doing things differently. */ 1986 if (mips_global_symbol_p (x)) 1987 return SYMBOL_GOT_DISP; 1988 1989 return SYMBOL_GOT_PAGE_OFST; 1990 } 1991 1992 return SYMBOL_ABSOLUTE; 1993} 1994 1995/* Classify the base of symbolic expression X, given that X appears in 1996 context CONTEXT. */ 1997 1998static enum mips_symbol_type 1999mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context) 2000{ 2001 rtx offset; 2002 2003 split_const (x, &x, &offset); 2004 if (UNSPEC_ADDRESS_P (x)) 2005 return UNSPEC_ADDRESS_TYPE (x); 2006 2007 return mips_classify_symbol (x, context); 2008} 2009 2010/* Return true if OFFSET is within the range [0, ALIGN), where ALIGN 2011 is the alignment in bytes of SYMBOL_REF X. */ 2012 2013static bool 2014mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset) 2015{ 2016 HOST_WIDE_INT align; 2017 2018 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1; 2019 return IN_RANGE (offset, 0, align - 1); 2020} 2021 2022/* Return true if X is a symbolic constant that can be used in context 2023 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ 2024 2025bool 2026mips_symbolic_constant_p (rtx x, enum mips_symbol_context context, 2027 enum mips_symbol_type *symbol_type) 2028{ 2029 rtx offset; 2030 2031 split_const (x, &x, &offset); 2032 if (UNSPEC_ADDRESS_P (x)) 2033 { 2034 *symbol_type = UNSPEC_ADDRESS_TYPE (x); 2035 x = UNSPEC_ADDRESS (x); 2036 } 2037 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 2038 { 2039 *symbol_type = mips_classify_symbol (x, context); 2040 if (*symbol_type == SYMBOL_TLS) 2041 return false; 2042 } 2043 else 2044 return false; 2045 2046 if (offset == const0_rtx) 2047 return true; 2048 2049 /* Check whether a nonzero offset is valid for the underlying 2050 relocations. */ 2051 switch (*symbol_type) 2052 { 2053 case SYMBOL_ABSOLUTE: 2054 case SYMBOL_64_HIGH: 2055 case SYMBOL_64_MID: 2056 case SYMBOL_64_LOW: 2057 /* If the target has 64-bit pointers and the object file only 2058 supports 32-bit symbols, the values of those symbols will be 2059 sign-extended. In this case we can't allow an arbitrary offset 2060 in case the 32-bit value X + OFFSET has a different sign from X. */ 2061 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS) 2062 return offset_within_block_p (x, INTVAL (offset)); 2063 2064 /* In other cases the relocations can handle any offset. */ 2065 return true; 2066 2067 case SYMBOL_PC_RELATIVE: 2068 /* Allow constant pool references to be converted to LABEL+CONSTANT. 2069 In this case, we no longer have access to the underlying constant, 2070 but the original symbol-based access was known to be valid. */ 2071 if (GET_CODE (x) == LABEL_REF) 2072 return true; 2073 2074 /* Fall through. */ 2075 2076 case SYMBOL_GP_RELATIVE: 2077 /* Make sure that the offset refers to something within the 2078 same object block. This should guarantee that the final 2079 PC- or GP-relative offset is within the 16-bit limit. */ 2080 return offset_within_block_p (x, INTVAL (offset)); 2081 2082 case SYMBOL_GOT_PAGE_OFST: 2083 case SYMBOL_GOTOFF_PAGE: 2084 /* If the symbol is global, the GOT entry will contain the symbol's 2085 address, and we will apply a 16-bit offset after loading it. 2086 If the symbol is local, the linker should provide enough local 2087 GOT entries for a 16-bit offset, but larger offsets may lead 2088 to GOT overflow. */ 2089 return SMALL_INT (offset); 2090 2091 case SYMBOL_TPREL: 2092 case SYMBOL_DTPREL: 2093 /* There is no carry between the HI and LO REL relocations, so the 2094 offset is only valid if we know it won't lead to such a carry. */ 2095 return mips_offset_within_alignment_p (x, INTVAL (offset)); 2096 2097 case SYMBOL_GOT_DISP: 2098 case SYMBOL_GOTOFF_DISP: 2099 case SYMBOL_GOTOFF_CALL: 2100 case SYMBOL_GOTOFF_LOADGP: 2101 case SYMBOL_TLSGD: 2102 case SYMBOL_TLSLDM: 2103 case SYMBOL_GOTTPREL: 2104 case SYMBOL_TLS: 2105 case SYMBOL_HALF: 2106 return false; 2107 } 2108 gcc_unreachable (); 2109} 2110 2111/* Like mips_symbol_insns, but treat extended MIPS16 instructions as a 2112 single instruction. We rely on the fact that, in the worst case, 2113 all instructions involved in a MIPS16 address calculation are usually 2114 extended ones. */ 2115 2116static int 2117mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode) 2118{ 2119 if (mips_use_pcrel_pool_p[(int) type]) 2120 { 2121 if (mode == MAX_MACHINE_MODE) 2122 /* LEAs will be converted into constant-pool references by 2123 mips_reorg. */ 2124 type = SYMBOL_PC_RELATIVE; 2125 else 2126 /* The constant must be loaded and then dereferenced. */ 2127 return 0; 2128 } 2129 2130 switch (type) 2131 { 2132 case SYMBOL_ABSOLUTE: 2133 /* When using 64-bit symbols, we need 5 preparatory instructions, 2134 such as: 2135 2136 lui $at,%highest(symbol) 2137 daddiu $at,$at,%higher(symbol) 2138 dsll $at,$at,16 2139 daddiu $at,$at,%hi(symbol) 2140 dsll $at,$at,16 2141 2142 The final address is then $at + %lo(symbol). With 32-bit 2143 symbols we just need a preparatory LUI for normal mode and 2144 a preparatory LI and SLL for MIPS16. */ 2145 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; 2146 2147 case SYMBOL_GP_RELATIVE: 2148 /* Treat GP-relative accesses as taking a single instruction on 2149 MIPS16 too; the copy of $gp can often be shared. */ 2150 return 1; 2151 2152 case SYMBOL_PC_RELATIVE: 2153 /* PC-relative constants can be only be used with ADDIUPC, 2154 DADDIUPC, LWPC and LDPC. */ 2155 if (mode == MAX_MACHINE_MODE 2156 || GET_MODE_SIZE (mode) == 4 2157 || GET_MODE_SIZE (mode) == 8) 2158 return 1; 2159 2160 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */ 2161 return 0; 2162 2163 case SYMBOL_GOT_DISP: 2164 /* The constant will have to be loaded from the GOT before it 2165 is used in an address. */ 2166 if (mode != MAX_MACHINE_MODE) 2167 return 0; 2168 2169 /* Fall through. */ 2170 2171 case SYMBOL_GOT_PAGE_OFST: 2172 /* Unless -funit-at-a-time is in effect, we can't be sure whether the 2173 local/global classification is accurate. The worst cases are: 2174 2175 (1) For local symbols when generating o32 or o64 code. The assembler 2176 will use: 2177 2178 lw $at,%got(symbol) 2179 nop 2180 2181 ...and the final address will be $at + %lo(symbol). 2182 2183 (2) For global symbols when -mxgot. The assembler will use: 2184 2185 lui $at,%got_hi(symbol) 2186 (d)addu $at,$at,$gp 2187 2188 ...and the final address will be $at + %got_lo(symbol). */ 2189 return 3; 2190 2191 case SYMBOL_GOTOFF_PAGE: 2192 case SYMBOL_GOTOFF_DISP: 2193 case SYMBOL_GOTOFF_CALL: 2194 case SYMBOL_GOTOFF_LOADGP: 2195 case SYMBOL_64_HIGH: 2196 case SYMBOL_64_MID: 2197 case SYMBOL_64_LOW: 2198 case SYMBOL_TLSGD: 2199 case SYMBOL_TLSLDM: 2200 case SYMBOL_DTPREL: 2201 case SYMBOL_GOTTPREL: 2202 case SYMBOL_TPREL: 2203 case SYMBOL_HALF: 2204 /* A 16-bit constant formed by a single relocation, or a 32-bit 2205 constant formed from a high 16-bit relocation and a low 16-bit 2206 relocation. Use mips_split_p to determine which. 32-bit 2207 constants need an "lui; addiu" sequence for normal mode and 2208 an "li; sll; addiu" sequence for MIPS16 mode. */ 2209 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2; 2210 2211 case SYMBOL_TLS: 2212 /* We don't treat a bare TLS symbol as a constant. */ 2213 return 0; 2214 } 2215 gcc_unreachable (); 2216} 2217 2218/* If MODE is MAX_MACHINE_MODE, return the number of instructions needed 2219 to load symbols of type TYPE into a register. Return 0 if the given 2220 type of symbol cannot be used as an immediate operand. 2221 2222 Otherwise, return the number of instructions needed to load or store 2223 values of mode MODE to or from addresses of type TYPE. Return 0 if 2224 the given type of symbol is not valid in addresses. 2225 2226 In both cases, instruction counts are based off BASE_INSN_LENGTH. */ 2227 2228static int 2229mips_symbol_insns (enum mips_symbol_type type, machine_mode mode) 2230{ 2231 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1); 2232} 2233 2234/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 2235 2236static bool 2237mips_cannot_force_const_mem (machine_mode mode, rtx x) 2238{ 2239 enum mips_symbol_type type; 2240 rtx base, offset; 2241 2242 /* There is no assembler syntax for expressing an address-sized 2243 high part. */ 2244 if (GET_CODE (x) == HIGH) 2245 return true; 2246 2247 /* As an optimization, reject constants that mips_legitimize_move 2248 can expand inline. 2249 2250 Suppose we have a multi-instruction sequence that loads constant C 2251 into register R. If R does not get allocated a hard register, and 2252 R is used in an operand that allows both registers and memory 2253 references, reload will consider forcing C into memory and using 2254 one of the instruction's memory alternatives. Returning false 2255 here will force it to use an input reload instead. */ 2256 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x)) 2257 return true; 2258 2259 split_const (x, &base, &offset); 2260 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)) 2261 { 2262 /* See whether we explicitly want these symbols in the pool. */ 2263 if (mips_use_pcrel_pool_p[(int) type]) 2264 return false; 2265 2266 /* The same optimization as for CONST_INT. */ 2267 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0) 2268 return true; 2269 2270 /* If MIPS16 constant pools live in the text section, they should 2271 not refer to anything that might need run-time relocation. */ 2272 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type)) 2273 return true; 2274 } 2275 2276 /* TLS symbols must be computed by mips_legitimize_move. */ 2277 if (tls_referenced_p (x)) 2278 return true; 2279 2280 return false; 2281} 2282 2283/* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for 2284 constants when we're using a per-function constant pool. */ 2285 2286static bool 2287mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED, 2288 const_rtx x ATTRIBUTE_UNUSED) 2289{ 2290 return !TARGET_MIPS16_PCREL_LOADS; 2291} 2292 2293/* Return true if register REGNO is a valid base register for mode MODE. 2294 STRICT_P is true if REG_OK_STRICT is in effect. */ 2295 2296int 2297mips_regno_mode_ok_for_base_p (int regno, machine_mode mode, 2298 bool strict_p) 2299{ 2300 if (!HARD_REGISTER_NUM_P (regno)) 2301 { 2302 if (!strict_p) 2303 return true; 2304 regno = reg_renumber[regno]; 2305 } 2306 2307 /* These fake registers will be eliminated to either the stack or 2308 hard frame pointer, both of which are usually valid base registers. 2309 Reload deals with the cases where the eliminated form isn't valid. */ 2310 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) 2311 return true; 2312 2313 /* In MIPS16 mode, the stack pointer can only address word and doubleword 2314 values, nothing smaller. */ 2315 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) 2316 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; 2317 2318 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); 2319} 2320 2321/* Return true if X is a valid base register for mode MODE. 2322 STRICT_P is true if REG_OK_STRICT is in effect. */ 2323 2324static bool 2325mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p) 2326{ 2327 if (!strict_p && GET_CODE (x) == SUBREG) 2328 x = SUBREG_REG (x); 2329 2330 return (REG_P (x) 2331 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); 2332} 2333 2334/* Return true if, for every base register BASE_REG, (plus BASE_REG X) 2335 can address a value of mode MODE. */ 2336 2337static bool 2338mips_valid_offset_p (rtx x, machine_mode mode) 2339{ 2340 /* Check that X is a signed 16-bit number. */ 2341 if (!const_arith_operand (x, Pmode)) 2342 return false; 2343 2344 /* We may need to split multiword moves, so make sure that every word 2345 is accessible. */ 2346 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 2347 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) 2348 return false; 2349 2350 return true; 2351} 2352 2353/* Return true if a LO_SUM can address a value of mode MODE when the 2354 LO_SUM symbol has type SYMBOL_TYPE. */ 2355 2356static bool 2357mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, machine_mode mode) 2358{ 2359 /* Check that symbols of type SYMBOL_TYPE can be used to access values 2360 of mode MODE. */ 2361 if (mips_symbol_insns (symbol_type, mode) == 0) 2362 return false; 2363 2364 /* Check that there is a known low-part relocation. */ 2365 if (mips_lo_relocs[symbol_type] == NULL) 2366 return false; 2367 2368 /* We may need to split multiword moves, so make sure that each word 2369 can be accessed without inducing a carry. This is mainly needed 2370 for o64, which has historically only guaranteed 64-bit alignment 2371 for 128-bit types. */ 2372 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 2373 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) 2374 return false; 2375 2376 return true; 2377} 2378 2379/* Return true if X is a valid address for machine mode MODE. If it is, 2380 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in 2381 effect. */ 2382 2383static bool 2384mips_classify_address (struct mips_address_info *info, rtx x, 2385 machine_mode mode, bool strict_p) 2386{ 2387 switch (GET_CODE (x)) 2388 { 2389 case REG: 2390 case SUBREG: 2391 info->type = ADDRESS_REG; 2392 info->reg = x; 2393 info->offset = const0_rtx; 2394 return mips_valid_base_register_p (info->reg, mode, strict_p); 2395 2396 case PLUS: 2397 info->type = ADDRESS_REG; 2398 info->reg = XEXP (x, 0); 2399 info->offset = XEXP (x, 1); 2400 return (mips_valid_base_register_p (info->reg, mode, strict_p) 2401 && mips_valid_offset_p (info->offset, mode)); 2402 2403 case LO_SUM: 2404 info->type = ADDRESS_LO_SUM; 2405 info->reg = XEXP (x, 0); 2406 info->offset = XEXP (x, 1); 2407 /* We have to trust the creator of the LO_SUM to do something vaguely 2408 sane. Target-independent code that creates a LO_SUM should also 2409 create and verify the matching HIGH. Target-independent code that 2410 adds an offset to a LO_SUM must prove that the offset will not 2411 induce a carry. Failure to do either of these things would be 2412 a bug, and we are not required to check for it here. The MIPS 2413 backend itself should only create LO_SUMs for valid symbolic 2414 constants, with the high part being either a HIGH or a copy 2415 of _gp. */ 2416 info->symbol_type 2417 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM); 2418 return (mips_valid_base_register_p (info->reg, mode, strict_p) 2419 && mips_valid_lo_sum_p (info->symbol_type, mode)); 2420 2421 case CONST_INT: 2422 /* Small-integer addresses don't occur very often, but they 2423 are legitimate if $0 is a valid base register. */ 2424 info->type = ADDRESS_CONST_INT; 2425 return !TARGET_MIPS16 && SMALL_INT (x); 2426 2427 case CONST: 2428 case LABEL_REF: 2429 case SYMBOL_REF: 2430 info->type = ADDRESS_SYMBOLIC; 2431 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM, 2432 &info->symbol_type) 2433 && mips_symbol_insns (info->symbol_type, mode) > 0 2434 && !mips_split_p[info->symbol_type]); 2435 2436 default: 2437 return false; 2438 } 2439} 2440 2441/* Implement TARGET_LEGITIMATE_ADDRESS_P. */ 2442 2443static bool 2444mips_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) 2445{ 2446 struct mips_address_info addr; 2447 2448 return mips_classify_address (&addr, x, mode, strict_p); 2449} 2450 2451/* Return true if X is a legitimate $sp-based address for mode MDOE. */ 2452 2453bool 2454mips_stack_address_p (rtx x, machine_mode mode) 2455{ 2456 struct mips_address_info addr; 2457 2458 return (mips_classify_address (&addr, x, mode, false) 2459 && addr.type == ADDRESS_REG 2460 && addr.reg == stack_pointer_rtx); 2461} 2462 2463/* Return true if ADDR matches the pattern for the LWXS load scaled indexed 2464 address instruction. Note that such addresses are not considered 2465 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use 2466 is so restricted. */ 2467 2468static bool 2469mips_lwxs_address_p (rtx addr) 2470{ 2471 if (ISA_HAS_LWXS 2472 && GET_CODE (addr) == PLUS 2473 && REG_P (XEXP (addr, 1))) 2474 { 2475 rtx offset = XEXP (addr, 0); 2476 if (GET_CODE (offset) == MULT 2477 && REG_P (XEXP (offset, 0)) 2478 && CONST_INT_P (XEXP (offset, 1)) 2479 && INTVAL (XEXP (offset, 1)) == 4) 2480 return true; 2481 } 2482 return false; 2483} 2484 2485/* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load 2486 indexed address instruction. Note that such addresses are 2487 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P 2488 sense, because their use is so restricted. */ 2489 2490static bool 2491mips_lx_address_p (rtx addr, machine_mode mode) 2492{ 2493 if (GET_CODE (addr) != PLUS 2494 || !REG_P (XEXP (addr, 0)) 2495 || !REG_P (XEXP (addr, 1))) 2496 return false; 2497 if (ISA_HAS_LBX && mode == QImode) 2498 return true; 2499 if (ISA_HAS_LHX && mode == HImode) 2500 return true; 2501 if (ISA_HAS_LWX && mode == SImode) 2502 return true; 2503 if (ISA_HAS_LDX && mode == DImode) 2504 return true; 2505 return false; 2506} 2507 2508/* Return true if a value at OFFSET bytes from base register BASE can be 2509 accessed using an unextended MIPS16 instruction. MODE is the mode of 2510 the value. 2511 2512 Usually the offset in an unextended instruction is a 5-bit field. 2513 The offset is unsigned and shifted left once for LH and SH, twice 2514 for LW and SW, and so on. An exception is LWSP and SWSP, which have 2515 an 8-bit immediate field that's shifted left twice. */ 2516 2517static bool 2518mips16_unextended_reference_p (machine_mode mode, rtx base, 2519 unsigned HOST_WIDE_INT offset) 2520{ 2521 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0) 2522 { 2523 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) 2524 return offset < 256U * GET_MODE_SIZE (mode); 2525 return offset < 32U * GET_MODE_SIZE (mode); 2526 } 2527 return false; 2528} 2529 2530/* Return the number of instructions needed to load or store a value 2531 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the 2532 length of one instruction. Return 0 if X isn't valid for MODE. 2533 Assume that multiword moves may need to be split into word moves 2534 if MIGHT_SPLIT_P, otherwise assume that a single load or store is 2535 enough. */ 2536 2537int 2538mips_address_insns (rtx x, machine_mode mode, bool might_split_p) 2539{ 2540 struct mips_address_info addr; 2541 int factor; 2542 2543 /* BLKmode is used for single unaligned loads and stores and should 2544 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty 2545 meaningless, so we have to single it out as a special case one way 2546 or the other.) */ 2547 if (mode != BLKmode && might_split_p) 2548 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 2549 else 2550 factor = 1; 2551 2552 if (mips_classify_address (&addr, x, mode, false)) 2553 switch (addr.type) 2554 { 2555 case ADDRESS_REG: 2556 if (TARGET_MIPS16 2557 && !mips16_unextended_reference_p (mode, addr.reg, 2558 UINTVAL (addr.offset))) 2559 return factor * 2; 2560 return factor; 2561 2562 case ADDRESS_LO_SUM: 2563 return TARGET_MIPS16 ? factor * 2 : factor; 2564 2565 case ADDRESS_CONST_INT: 2566 return factor; 2567 2568 case ADDRESS_SYMBOLIC: 2569 return factor * mips_symbol_insns (addr.symbol_type, mode); 2570 } 2571 return 0; 2572} 2573 2574/* Return true if X fits within an unsigned field of BITS bits that is 2575 shifted left SHIFT bits before being used. */ 2576 2577bool 2578mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0) 2579{ 2580 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits)); 2581} 2582 2583/* Return true if X fits within a signed field of BITS bits that is 2584 shifted left SHIFT bits before being used. */ 2585 2586bool 2587mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0) 2588{ 2589 x += 1 << (bits + shift - 1); 2590 return mips_unsigned_immediate_p (x, bits, shift); 2591} 2592 2593/* Return true if X is legitimate for accessing values of mode MODE, 2594 if it is based on a MIPS16 register, and if the offset satisfies 2595 OFFSET_PREDICATE. */ 2596 2597bool 2598m16_based_address_p (rtx x, machine_mode mode, 2599 insn_operand_predicate_fn offset_predicate) 2600{ 2601 struct mips_address_info addr; 2602 2603 return (mips_classify_address (&addr, x, mode, false) 2604 && addr.type == ADDRESS_REG 2605 && M16_REG_P (REGNO (addr.reg)) 2606 && offset_predicate (addr.offset, mode)); 2607} 2608 2609/* Return true if X is a legitimate address that conforms to the requirements 2610 for a microMIPS LWSP or SWSP insn. */ 2611 2612bool 2613lwsp_swsp_address_p (rtx x, machine_mode mode) 2614{ 2615 struct mips_address_info addr; 2616 2617 return (mips_classify_address (&addr, x, mode, false) 2618 && addr.type == ADDRESS_REG 2619 && REGNO (addr.reg) == STACK_POINTER_REGNUM 2620 && uw5_operand (addr.offset, mode)); 2621} 2622 2623/* Return true if X is a legitimate address with a 12-bit offset. 2624 MODE is the mode of the value being accessed. */ 2625 2626bool 2627umips_12bit_offset_address_p (rtx x, machine_mode mode) 2628{ 2629 struct mips_address_info addr; 2630 2631 return (mips_classify_address (&addr, x, mode, false) 2632 && addr.type == ADDRESS_REG 2633 && CONST_INT_P (addr.offset) 2634 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset))); 2635} 2636 2637/* Return true if X is a legitimate address with a 9-bit offset. 2638 MODE is the mode of the value being accessed. */ 2639 2640bool 2641mips_9bit_offset_address_p (rtx x, machine_mode mode) 2642{ 2643 struct mips_address_info addr; 2644 2645 return (mips_classify_address (&addr, x, mode, false) 2646 && addr.type == ADDRESS_REG 2647 && CONST_INT_P (addr.offset) 2648 && MIPS_9BIT_OFFSET_P (INTVAL (addr.offset))); 2649} 2650 2651/* Return the number of instructions needed to load constant X, 2652 assuming that BASE_INSN_LENGTH is the length of one instruction. 2653 Return 0 if X isn't a valid constant. */ 2654 2655int 2656mips_const_insns (rtx x) 2657{ 2658 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; 2659 enum mips_symbol_type symbol_type; 2660 rtx offset; 2661 2662 switch (GET_CODE (x)) 2663 { 2664 case HIGH: 2665 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA, 2666 &symbol_type) 2667 || !mips_split_p[symbol_type]) 2668 return 0; 2669 2670 /* This is simply an LUI for normal mode. It is an extended 2671 LI followed by an extended SLL for MIPS16. */ 2672 return TARGET_MIPS16 ? 4 : 1; 2673 2674 case CONST_INT: 2675 if (TARGET_MIPS16) 2676 /* Unsigned 8-bit constants can be loaded using an unextended 2677 LI instruction. Unsigned 16-bit constants can be loaded 2678 using an extended LI. Negative constants must be loaded 2679 using LI and then negated. */ 2680 return (IN_RANGE (INTVAL (x), 0, 255) ? 1 2681 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 2682 : IN_RANGE (-INTVAL (x), 0, 255) ? 2 2683 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 2684 : 0); 2685 2686 return mips_build_integer (codes, INTVAL (x)); 2687 2688 case CONST_DOUBLE: 2689 case CONST_VECTOR: 2690 /* Allow zeros for normal mode, where we can use $0. */ 2691 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; 2692 2693 case CONST: 2694 if (CONST_GP_P (x)) 2695 return 1; 2696 2697 /* See if we can refer to X directly. */ 2698 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type)) 2699 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE); 2700 2701 /* Otherwise try splitting the constant into a base and offset. 2702 If the offset is a 16-bit value, we can load the base address 2703 into a register and then use (D)ADDIU to add in the offset. 2704 If the offset is larger, we can load the base and offset 2705 into separate registers and add them together with (D)ADDU. 2706 However, the latter is only possible before reload; during 2707 and after reload, we must have the option of forcing the 2708 constant into the pool instead. */ 2709 split_const (x, &x, &offset); 2710 if (offset != 0) 2711 { 2712 int n = mips_const_insns (x); 2713 if (n != 0) 2714 { 2715 if (SMALL_INT (offset)) 2716 return n + 1; 2717 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x)) 2718 return n + 1 + mips_build_integer (codes, INTVAL (offset)); 2719 } 2720 } 2721 return 0; 2722 2723 case SYMBOL_REF: 2724 case LABEL_REF: 2725 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA), 2726 MAX_MACHINE_MODE); 2727 2728 default: 2729 return 0; 2730 } 2731} 2732 2733/* X is a doubleword constant that can be handled by splitting it into 2734 two words and loading each word separately. Return the number of 2735 instructions required to do this, assuming that BASE_INSN_LENGTH 2736 is the length of one instruction. */ 2737 2738int 2739mips_split_const_insns (rtx x) 2740{ 2741 unsigned int low, high; 2742 2743 low = mips_const_insns (mips_subword (x, false)); 2744 high = mips_const_insns (mips_subword (x, true)); 2745 gcc_assert (low > 0 && high > 0); 2746 return low + high; 2747} 2748 2749/* Return the number of instructions needed to implement INSN, 2750 given that it loads from or stores to MEM. Assume that 2751 BASE_INSN_LENGTH is the length of one instruction. */ 2752 2753int 2754mips_load_store_insns (rtx mem, rtx_insn *insn) 2755{ 2756 machine_mode mode; 2757 bool might_split_p; 2758 rtx set; 2759 2760 gcc_assert (MEM_P (mem)); 2761 mode = GET_MODE (mem); 2762 2763 /* Try to prove that INSN does not need to be split. */ 2764 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD; 2765 if (might_split_p) 2766 { 2767 set = single_set (insn); 2768 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn)) 2769 might_split_p = false; 2770 } 2771 2772 return mips_address_insns (XEXP (mem, 0), mode, might_split_p); 2773} 2774 2775/* Return the number of instructions needed for an integer division, 2776 assuming that BASE_INSN_LENGTH is the length of one instruction. */ 2777 2778int 2779mips_idiv_insns (void) 2780{ 2781 int count; 2782 2783 count = 1; 2784 if (TARGET_CHECK_ZERO_DIV) 2785 { 2786 if (GENERATE_DIVIDE_TRAPS) 2787 count++; 2788 else 2789 count += 2; 2790 } 2791 2792 if (TARGET_FIX_R4000 || TARGET_FIX_R4400) 2793 count++; 2794 return count; 2795} 2796 2797/* Emit a move from SRC to DEST. Assume that the move expanders can 2798 handle all moves if !can_create_pseudo_p (). The distinction is 2799 important because, unlike emit_move_insn, the move expanders know 2800 how to force Pmode objects into the constant pool even when the 2801 constant pool address is not itself legitimate. */ 2802 2803rtx_insn * 2804mips_emit_move (rtx dest, rtx src) 2805{ 2806 return (can_create_pseudo_p () 2807 ? emit_move_insn (dest, src) 2808 : emit_move_insn_1 (dest, src)); 2809} 2810 2811/* Emit a move from SRC to DEST, splitting compound moves into individual 2812 instructions. SPLIT_TYPE is the type of split to perform. */ 2813 2814static void 2815mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type) 2816{ 2817 if (mips_split_move_p (dest, src, split_type)) 2818 mips_split_move (dest, src, split_type); 2819 else 2820 mips_emit_move (dest, src); 2821} 2822 2823/* Emit an instruction of the form (set TARGET (CODE OP0)). */ 2824 2825static void 2826mips_emit_unary (enum rtx_code code, rtx target, rtx op0) 2827{ 2828 emit_insn (gen_rtx_SET (VOIDmode, target, 2829 gen_rtx_fmt_e (code, GET_MODE (op0), op0))); 2830} 2831 2832/* Compute (CODE OP0) and store the result in a new register of mode MODE. 2833 Return that new register. */ 2834 2835static rtx 2836mips_force_unary (machine_mode mode, enum rtx_code code, rtx op0) 2837{ 2838 rtx reg; 2839 2840 reg = gen_reg_rtx (mode); 2841 mips_emit_unary (code, reg, op0); 2842 return reg; 2843} 2844 2845/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ 2846 2847void 2848mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) 2849{ 2850 emit_insn (gen_rtx_SET (VOIDmode, target, 2851 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); 2852} 2853 2854/* Compute (CODE OP0 OP1) and store the result in a new register 2855 of mode MODE. Return that new register. */ 2856 2857static rtx 2858mips_force_binary (machine_mode mode, enum rtx_code code, rtx op0, rtx op1) 2859{ 2860 rtx reg; 2861 2862 reg = gen_reg_rtx (mode); 2863 mips_emit_binary (code, reg, op0, op1); 2864 return reg; 2865} 2866 2867/* Copy VALUE to a register and return that register. If new pseudos 2868 are allowed, copy it into a new register, otherwise use DEST. */ 2869 2870static rtx 2871mips_force_temporary (rtx dest, rtx value) 2872{ 2873 if (can_create_pseudo_p ()) 2874 return force_reg (Pmode, value); 2875 else 2876 { 2877 mips_emit_move (dest, value); 2878 return dest; 2879 } 2880} 2881 2882/* Emit a call sequence with call pattern PATTERN and return the call 2883 instruction itself (which is not necessarily the last instruction 2884 emitted). ORIG_ADDR is the original, unlegitimized address, 2885 ADDR is the legitimized form, and LAZY_P is true if the call 2886 address is lazily-bound. */ 2887 2888static rtx_insn * 2889mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p) 2890{ 2891 rtx_insn *insn; 2892 rtx reg; 2893 2894 insn = emit_call_insn (pattern); 2895 2896 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr)) 2897 { 2898 /* MIPS16 JALRs only take MIPS16 registers. If the target 2899 function requires $25 to be valid on entry, we must copy it 2900 there separately. The move instruction can be put in the 2901 call's delay slot. */ 2902 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 2903 emit_insn_before (gen_move_insn (reg, addr), insn); 2904 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); 2905 } 2906 2907 if (lazy_p) 2908 /* Lazy-binding stubs require $gp to be valid on entry. */ 2909 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 2910 2911 if (TARGET_USE_GOT) 2912 { 2913 /* See the comment above load_call<mode> for details. */ 2914 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), 2915 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM)); 2916 emit_insn (gen_update_got_version ()); 2917 } 2918 2919 if (TARGET_MIPS16 2920 && TARGET_EXPLICIT_RELOCS 2921 && TARGET_CALL_CLOBBERED_GP) 2922 { 2923 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG); 2924 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg); 2925 } 2926 2927 return insn; 2928} 2929 2930/* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, 2931 then add CONST_INT OFFSET to the result. */ 2932 2933static rtx 2934mips_unspec_address_offset (rtx base, rtx offset, 2935 enum mips_symbol_type symbol_type) 2936{ 2937 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 2938 UNSPEC_ADDRESS_FIRST + symbol_type); 2939 if (offset != const0_rtx) 2940 base = gen_rtx_PLUS (Pmode, base, offset); 2941 return gen_rtx_CONST (Pmode, base); 2942} 2943 2944/* Return an UNSPEC address with underlying address ADDRESS and symbol 2945 type SYMBOL_TYPE. */ 2946 2947rtx 2948mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) 2949{ 2950 rtx base, offset; 2951 2952 split_const (address, &base, &offset); 2953 return mips_unspec_address_offset (base, offset, symbol_type); 2954} 2955 2956/* If OP is an UNSPEC address, return the address to which it refers, 2957 otherwise return OP itself. */ 2958 2959rtx 2960mips_strip_unspec_address (rtx op) 2961{ 2962 rtx base, offset; 2963 2964 split_const (op, &base, &offset); 2965 if (UNSPEC_ADDRESS_P (base)) 2966 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset)); 2967 return op; 2968} 2969 2970/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the 2971 high part to BASE and return the result. Just return BASE otherwise. 2972 TEMP is as for mips_force_temporary. 2973 2974 The returned expression can be used as the first operand to a LO_SUM. */ 2975 2976static rtx 2977mips_unspec_offset_high (rtx temp, rtx base, rtx addr, 2978 enum mips_symbol_type symbol_type) 2979{ 2980 if (mips_split_p[symbol_type]) 2981 { 2982 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); 2983 addr = mips_force_temporary (temp, addr); 2984 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base)); 2985 } 2986 return base; 2987} 2988 2989/* Return an instruction that copies $gp into register REG. We want 2990 GCC to treat the register's value as constant, so that its value 2991 can be rematerialized on demand. */ 2992 2993static rtx 2994gen_load_const_gp (rtx reg) 2995{ 2996 return PMODE_INSN (gen_load_const_gp, (reg)); 2997} 2998 2999/* Return a pseudo register that contains the value of $gp throughout 3000 the current function. Such registers are needed by MIPS16 functions, 3001 for which $gp itself is not a valid base register or addition operand. */ 3002 3003static rtx 3004mips16_gp_pseudo_reg (void) 3005{ 3006 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) 3007 { 3008 rtx_insn *scan; 3009 3010 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); 3011 3012 push_topmost_sequence (); 3013 3014 scan = get_insns (); 3015 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan))) 3016 scan = NEXT_INSN (scan); 3017 3018 rtx set = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); 3019 rtx_insn *insn = emit_insn_after (set, scan); 3020 INSN_LOCATION (insn) = 0; 3021 3022 pop_topmost_sequence (); 3023 } 3024 3025 return cfun->machine->mips16_gp_pseudo_rtx; 3026} 3027 3028/* Return a base register that holds pic_offset_table_rtx. 3029 TEMP, if nonnull, is a scratch Pmode base register. */ 3030 3031rtx 3032mips_pic_base_register (rtx temp) 3033{ 3034 if (!TARGET_MIPS16) 3035 return pic_offset_table_rtx; 3036 3037 if (currently_expanding_to_rtl) 3038 return mips16_gp_pseudo_reg (); 3039 3040 if (can_create_pseudo_p ()) 3041 temp = gen_reg_rtx (Pmode); 3042 3043 if (TARGET_USE_GOT) 3044 /* The first post-reload split exposes all references to $gp 3045 (both uses and definitions). All references must remain 3046 explicit after that point. 3047 3048 It is safe to introduce uses of $gp at any time, so for 3049 simplicity, we do that before the split too. */ 3050 mips_emit_move (temp, pic_offset_table_rtx); 3051 else 3052 emit_insn (gen_load_const_gp (temp)); 3053 return temp; 3054} 3055 3056/* Return the RHS of a load_call<mode> insn. */ 3057 3058static rtx 3059mips_unspec_call (rtx reg, rtx symbol) 3060{ 3061 rtvec vec; 3062 3063 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM)); 3064 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL); 3065} 3066 3067/* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol 3068 reference. Return NULL_RTX otherwise. */ 3069 3070static rtx 3071mips_strip_unspec_call (rtx src) 3072{ 3073 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL) 3074 return mips_strip_unspec_address (XVECEXP (src, 0, 1)); 3075 return NULL_RTX; 3076} 3077 3078/* Create and return a GOT reference of type TYPE for address ADDR. 3079 TEMP, if nonnull, is a scratch Pmode base register. */ 3080 3081rtx 3082mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type) 3083{ 3084 rtx base, high, lo_sum_symbol; 3085 3086 base = mips_pic_base_register (temp); 3087 3088 /* If we used the temporary register to load $gp, we can't use 3089 it for the high part as well. */ 3090 if (temp != NULL && reg_overlap_mentioned_p (base, temp)) 3091 temp = NULL; 3092 3093 high = mips_unspec_offset_high (temp, base, addr, type); 3094 lo_sum_symbol = mips_unspec_address (addr, type); 3095 3096 if (type == SYMBOL_GOTOFF_CALL) 3097 return mips_unspec_call (high, lo_sum_symbol); 3098 else 3099 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol)); 3100} 3101 3102/* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise 3103 it appears in a MEM of that mode. Return true if ADDR is a legitimate 3104 constant in that context and can be split into high and low parts. 3105 If so, and if LOW_OUT is nonnull, emit the high part and store the 3106 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. 3107 3108 TEMP is as for mips_force_temporary and is used to load the high 3109 part into a register. 3110 3111 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be 3112 a legitimize SET_SRC for an .md pattern, otherwise the low part 3113 is guaranteed to be a legitimate address for mode MODE. */ 3114 3115bool 3116mips_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) 3117{ 3118 enum mips_symbol_context context; 3119 enum mips_symbol_type symbol_type; 3120 rtx high; 3121 3122 context = (mode == MAX_MACHINE_MODE 3123 ? SYMBOL_CONTEXT_LEA 3124 : SYMBOL_CONTEXT_MEM); 3125 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA) 3126 { 3127 addr = XEXP (addr, 0); 3128 if (mips_symbolic_constant_p (addr, context, &symbol_type) 3129 && mips_symbol_insns (symbol_type, mode) > 0 3130 && mips_split_hi_p[symbol_type]) 3131 { 3132 if (low_out) 3133 switch (symbol_type) 3134 { 3135 case SYMBOL_GOT_PAGE_OFST: 3136 /* The high part of a page/ofst pair is loaded from the GOT. */ 3137 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE); 3138 break; 3139 3140 default: 3141 gcc_unreachable (); 3142 } 3143 return true; 3144 } 3145 } 3146 else 3147 { 3148 if (mips_symbolic_constant_p (addr, context, &symbol_type) 3149 && mips_symbol_insns (symbol_type, mode) > 0 3150 && mips_split_p[symbol_type]) 3151 { 3152 if (low_out) 3153 switch (symbol_type) 3154 { 3155 case SYMBOL_GOT_DISP: 3156 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */ 3157 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP); 3158 break; 3159 3160 case SYMBOL_GP_RELATIVE: 3161 high = mips_pic_base_register (temp); 3162 *low_out = gen_rtx_LO_SUM (Pmode, high, addr); 3163 break; 3164 3165 default: 3166 high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); 3167 high = mips_force_temporary (temp, high); 3168 *low_out = gen_rtx_LO_SUM (Pmode, high, addr); 3169 break; 3170 } 3171 return true; 3172 } 3173 } 3174 return false; 3175} 3176 3177/* Return a legitimate address for REG + OFFSET. TEMP is as for 3178 mips_force_temporary; it is only needed when OFFSET is not a 3179 SMALL_OPERAND. */ 3180 3181static rtx 3182mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 3183{ 3184 if (!SMALL_OPERAND (offset)) 3185 { 3186 rtx high; 3187 3188 if (TARGET_MIPS16) 3189 { 3190 /* Load the full offset into a register so that we can use 3191 an unextended instruction for the address itself. */ 3192 high = GEN_INT (offset); 3193 offset = 0; 3194 } 3195 else 3196 { 3197 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. 3198 The addition inside the macro CONST_HIGH_PART may cause an 3199 overflow, so we need to force a sign-extension check. */ 3200 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); 3201 offset = CONST_LOW_PART (offset); 3202 } 3203 high = mips_force_temporary (temp, high); 3204 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); 3205 } 3206 return plus_constant (Pmode, reg, offset); 3207} 3208 3209/* The __tls_get_attr symbol. */ 3210static GTY(()) rtx mips_tls_symbol; 3211 3212/* Return an instruction sequence that calls __tls_get_addr. SYM is 3213 the TLS symbol we are referencing and TYPE is the symbol type to use 3214 (either global dynamic or local dynamic). V0 is an RTX for the 3215 return value location. */ 3216 3217static rtx 3218mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0) 3219{ 3220 rtx insn, loc, a0; 3221 3222 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); 3223 3224 if (!mips_tls_symbol) 3225 mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); 3226 3227 loc = mips_unspec_address (sym, type); 3228 3229 start_sequence (); 3230 3231 emit_insn (gen_rtx_SET (Pmode, a0, 3232 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); 3233 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol, 3234 const0_rtx, NULL_RTX, false); 3235 RTL_CONST_CALL_P (insn) = 1; 3236 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); 3237 insn = get_insns (); 3238 3239 end_sequence (); 3240 3241 return insn; 3242} 3243 3244/* Return a pseudo register that contains the current thread pointer. */ 3245 3246rtx 3247mips_expand_thread_pointer (rtx tp) 3248{ 3249 rtx fn; 3250 3251 if (TARGET_MIPS16) 3252 { 3253 if (!mips16_rdhwr_stub) 3254 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub (); 3255 fn = mips16_stub_call_address (mips16_rdhwr_stub); 3256 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn))); 3257 } 3258 else 3259 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp))); 3260 return tp; 3261} 3262 3263static rtx 3264mips_get_tp (void) 3265{ 3266 return mips_expand_thread_pointer (gen_reg_rtx (Pmode)); 3267} 3268 3269/* Generate the code to access LOC, a thread-local SYMBOL_REF, and return 3270 its address. The return value will be both a valid address and a valid 3271 SET_SRC (either a REG or a LO_SUM). */ 3272 3273static rtx 3274mips_legitimize_tls_address (rtx loc) 3275{ 3276 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset; 3277 enum tls_model model; 3278 3279 model = SYMBOL_REF_TLS_MODEL (loc); 3280 /* Only TARGET_ABICALLS code can have more than one module; other 3281 code must be be static and should not use a GOT. All TLS models 3282 reduce to local exec in this situation. */ 3283 if (!TARGET_ABICALLS) 3284 model = TLS_MODEL_LOCAL_EXEC; 3285 3286 switch (model) 3287 { 3288 case TLS_MODEL_GLOBAL_DYNAMIC: 3289 v0 = gen_rtx_REG (Pmode, GP_RETURN); 3290 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0); 3291 dest = gen_reg_rtx (Pmode); 3292 emit_libcall_block (insn, dest, v0, loc); 3293 break; 3294 3295 case TLS_MODEL_LOCAL_DYNAMIC: 3296 v0 = gen_rtx_REG (Pmode, GP_RETURN); 3297 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0); 3298 tmp1 = gen_reg_rtx (Pmode); 3299 3300 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to 3301 share the LDM result with other LD model accesses. */ 3302 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 3303 UNSPEC_TLS_LDM); 3304 emit_libcall_block (insn, tmp1, v0, eqv); 3305 3306 offset = mips_unspec_address (loc, SYMBOL_DTPREL); 3307 if (mips_split_p[SYMBOL_DTPREL]) 3308 { 3309 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL); 3310 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset); 3311 } 3312 else 3313 dest = expand_binop (Pmode, add_optab, tmp1, offset, 3314 0, 0, OPTAB_DIRECT); 3315 break; 3316 3317 case TLS_MODEL_INITIAL_EXEC: 3318 tp = mips_get_tp (); 3319 tmp1 = gen_reg_rtx (Pmode); 3320 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); 3321 if (Pmode == DImode) 3322 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); 3323 else 3324 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); 3325 dest = gen_reg_rtx (Pmode); 3326 emit_insn (gen_add3_insn (dest, tmp1, tp)); 3327 break; 3328 3329 case TLS_MODEL_LOCAL_EXEC: 3330 tmp1 = mips_get_tp (); 3331 offset = mips_unspec_address (loc, SYMBOL_TPREL); 3332 if (mips_split_p[SYMBOL_TPREL]) 3333 { 3334 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL); 3335 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset); 3336 } 3337 else 3338 dest = expand_binop (Pmode, add_optab, tmp1, offset, 3339 0, 0, OPTAB_DIRECT); 3340 break; 3341 3342 default: 3343 gcc_unreachable (); 3344 } 3345 return dest; 3346} 3347 3348/* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16, 3349 using a stub. */ 3350 3351void 3352mips16_expand_get_fcsr (rtx target) 3353{ 3354 if (!mips16_get_fcsr_stub) 3355 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub (); 3356 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub); 3357 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn))); 3358 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM)); 3359} 3360 3361/* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */ 3362 3363void 3364mips16_expand_set_fcsr (rtx newval) 3365{ 3366 if (!mips16_set_fcsr_stub) 3367 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub (); 3368 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub); 3369 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval); 3370 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn))); 3371} 3372 3373/* If X is not a valid address for mode MODE, force it into a register. */ 3374 3375static rtx 3376mips_force_address (rtx x, machine_mode mode) 3377{ 3378 if (!mips_legitimate_address_p (mode, x, false)) 3379 x = force_reg (Pmode, x); 3380 return x; 3381} 3382 3383/* This function is used to implement LEGITIMIZE_ADDRESS. If X can 3384 be legitimized in a way that the generic machinery might not expect, 3385 return a new address, otherwise return NULL. MODE is the mode of 3386 the memory being accessed. */ 3387 3388static rtx 3389mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 3390 machine_mode mode) 3391{ 3392 rtx base, addr; 3393 HOST_WIDE_INT offset; 3394 3395 if (mips_tls_symbol_p (x)) 3396 return mips_legitimize_tls_address (x); 3397 3398 /* See if the address can split into a high part and a LO_SUM. */ 3399 if (mips_split_symbol (NULL, x, mode, &addr)) 3400 return mips_force_address (addr, mode); 3401 3402 /* Handle BASE + OFFSET using mips_add_offset. */ 3403 mips_split_plus (x, &base, &offset); 3404 if (offset != 0) 3405 { 3406 if (!mips_valid_base_register_p (base, mode, false)) 3407 base = copy_to_mode_reg (Pmode, base); 3408 addr = mips_add_offset (NULL, base, offset); 3409 return mips_force_address (addr, mode); 3410 } 3411 3412 return x; 3413} 3414 3415/* Load VALUE into DEST. TEMP is as for mips_force_temporary. */ 3416 3417void 3418mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) 3419{ 3420 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; 3421 machine_mode mode; 3422 unsigned int i, num_ops; 3423 rtx x; 3424 3425 mode = GET_MODE (dest); 3426 num_ops = mips_build_integer (codes, value); 3427 3428 /* Apply each binary operation to X. Invariant: X is a legitimate 3429 source operand for a SET pattern. */ 3430 x = GEN_INT (codes[0].value); 3431 for (i = 1; i < num_ops; i++) 3432 { 3433 if (!can_create_pseudo_p ()) 3434 { 3435 emit_insn (gen_rtx_SET (VOIDmode, temp, x)); 3436 x = temp; 3437 } 3438 else 3439 x = force_reg (mode, x); 3440 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); 3441 } 3442 3443 emit_insn (gen_rtx_SET (VOIDmode, dest, x)); 3444} 3445 3446/* Subroutine of mips_legitimize_move. Move constant SRC into register 3447 DEST given that SRC satisfies immediate_operand but doesn't satisfy 3448 move_operand. */ 3449 3450static void 3451mips_legitimize_const_move (machine_mode mode, rtx dest, rtx src) 3452{ 3453 rtx base, offset; 3454 3455 /* Split moves of big integers into smaller pieces. */ 3456 if (splittable_const_int_operand (src, mode)) 3457 { 3458 mips_move_integer (dest, dest, INTVAL (src)); 3459 return; 3460 } 3461 3462 /* Split moves of symbolic constants into high/low pairs. */ 3463 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) 3464 { 3465 emit_insn (gen_rtx_SET (VOIDmode, dest, src)); 3466 return; 3467 } 3468 3469 /* Generate the appropriate access sequences for TLS symbols. */ 3470 if (mips_tls_symbol_p (src)) 3471 { 3472 mips_emit_move (dest, mips_legitimize_tls_address (src)); 3473 return; 3474 } 3475 3476 /* If we have (const (plus symbol offset)), and that expression cannot 3477 be forced into memory, load the symbol first and add in the offset. 3478 In non-MIPS16 mode, prefer to do this even if the constant _can_ be 3479 forced into memory, as it usually produces better code. */ 3480 split_const (src, &base, &offset); 3481 if (offset != const0_rtx 3482 && (targetm.cannot_force_const_mem (mode, src) 3483 || (!TARGET_MIPS16 && can_create_pseudo_p ()))) 3484 { 3485 base = mips_force_temporary (dest, base); 3486 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset))); 3487 return; 3488 } 3489 3490 src = force_const_mem (mode, src); 3491 3492 /* When using explicit relocs, constant pool references are sometimes 3493 not legitimate addresses. */ 3494 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); 3495 mips_emit_move (dest, src); 3496} 3497 3498/* If (set DEST SRC) is not a valid move instruction, emit an equivalent 3499 sequence that is valid. */ 3500 3501bool 3502mips_legitimize_move (machine_mode mode, rtx dest, rtx src) 3503{ 3504 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) 3505 { 3506 mips_emit_move (dest, force_reg (mode, src)); 3507 return true; 3508 } 3509 3510 /* We need to deal with constants that would be legitimate 3511 immediate_operands but aren't legitimate move_operands. */ 3512 if (CONSTANT_P (src) && !move_operand (src, mode)) 3513 { 3514 mips_legitimize_const_move (mode, dest, src); 3515 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); 3516 return true; 3517 } 3518 return false; 3519} 3520 3521/* Return true if value X in context CONTEXT is a small-data address 3522 that can be rewritten as a LO_SUM. */ 3523 3524static bool 3525mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context) 3526{ 3527 enum mips_symbol_type symbol_type; 3528 3529 return (mips_lo_relocs[SYMBOL_GP_RELATIVE] 3530 && !mips_split_p[SYMBOL_GP_RELATIVE] 3531 && mips_symbolic_constant_p (x, context, &symbol_type) 3532 && symbol_type == SYMBOL_GP_RELATIVE); 3533} 3534 3535/* Return true if OP refers to small data symbols directly, not through 3536 a LO_SUM. CONTEXT is the context in which X appears. */ 3537 3538static int 3539mips_small_data_pattern_1 (rtx x, enum mips_symbol_context context) 3540{ 3541 subrtx_var_iterator::array_type array; 3542 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL) 3543 { 3544 rtx x = *iter; 3545 3546 /* Ignore things like "g" constraints in asms. We make no particular 3547 guarantee about which symbolic constants are acceptable as asm operands 3548 versus which must be forced into a GPR. */ 3549 if (GET_CODE (x) == LO_SUM || GET_CODE (x) == ASM_OPERANDS) 3550 iter.skip_subrtxes (); 3551 else if (MEM_P (x)) 3552 { 3553 if (mips_small_data_pattern_1 (XEXP (x, 0), SYMBOL_CONTEXT_MEM)) 3554 return true; 3555 iter.skip_subrtxes (); 3556 } 3557 else if (mips_rewrite_small_data_p (x, context)) 3558 return true; 3559 } 3560 return false; 3561} 3562 3563/* Return true if OP refers to small data symbols directly, not through 3564 a LO_SUM. */ 3565 3566bool 3567mips_small_data_pattern_p (rtx op) 3568{ 3569 return mips_small_data_pattern_1 (op, SYMBOL_CONTEXT_LEA); 3570} 3571 3572/* Rewrite *LOC so that it refers to small data using explicit 3573 relocations. CONTEXT is the context in which *LOC appears. */ 3574 3575static void 3576mips_rewrite_small_data_1 (rtx *loc, enum mips_symbol_context context) 3577{ 3578 subrtx_ptr_iterator::array_type array; 3579 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL) 3580 { 3581 rtx *loc = *iter; 3582 if (MEM_P (*loc)) 3583 { 3584 mips_rewrite_small_data_1 (&XEXP (*loc, 0), SYMBOL_CONTEXT_MEM); 3585 iter.skip_subrtxes (); 3586 } 3587 else if (mips_rewrite_small_data_p (*loc, context)) 3588 { 3589 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc); 3590 iter.skip_subrtxes (); 3591 } 3592 else if (GET_CODE (*loc) == LO_SUM) 3593 iter.skip_subrtxes (); 3594 } 3595} 3596 3597/* Rewrite instruction pattern PATTERN so that it refers to small data 3598 using explicit relocations. */ 3599 3600rtx 3601mips_rewrite_small_data (rtx pattern) 3602{ 3603 pattern = copy_insn (pattern); 3604 mips_rewrite_small_data_1 (&pattern, SYMBOL_CONTEXT_LEA); 3605 return pattern; 3606} 3607 3608/* The cost of loading values from the constant pool. It should be 3609 larger than the cost of any constant we want to synthesize inline. */ 3610#define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8) 3611 3612/* Return the cost of X when used as an operand to the MIPS16 instruction 3613 that implements CODE. Return -1 if there is no such instruction, or if 3614 X is not a valid immediate operand for it. */ 3615 3616static int 3617mips16_constant_cost (int code, HOST_WIDE_INT x) 3618{ 3619 switch (code) 3620 { 3621 case ASHIFT: 3622 case ASHIFTRT: 3623 case LSHIFTRT: 3624 /* Shifts by between 1 and 8 bits (inclusive) are unextended, 3625 other shifts are extended. The shift patterns truncate the shift 3626 count to the right size, so there are no out-of-range values. */ 3627 if (IN_RANGE (x, 1, 8)) 3628 return 0; 3629 return COSTS_N_INSNS (1); 3630 3631 case PLUS: 3632 if (IN_RANGE (x, -128, 127)) 3633 return 0; 3634 if (SMALL_OPERAND (x)) 3635 return COSTS_N_INSNS (1); 3636 return -1; 3637 3638 case LEU: 3639 /* Like LE, but reject the always-true case. */ 3640 if (x == -1) 3641 return -1; 3642 case LE: 3643 /* We add 1 to the immediate and use SLT. */ 3644 x += 1; 3645 case XOR: 3646 /* We can use CMPI for an xor with an unsigned 16-bit X. */ 3647 case LT: 3648 case LTU: 3649 if (IN_RANGE (x, 0, 255)) 3650 return 0; 3651 if (SMALL_OPERAND_UNSIGNED (x)) 3652 return COSTS_N_INSNS (1); 3653 return -1; 3654 3655 case EQ: 3656 case NE: 3657 /* Equality comparisons with 0 are cheap. */ 3658 if (x == 0) 3659 return 0; 3660 return -1; 3661 3662 default: 3663 return -1; 3664 } 3665} 3666 3667/* Return true if there is a non-MIPS16 instruction that implements CODE 3668 and if that instruction accepts X as an immediate operand. */ 3669 3670static int 3671mips_immediate_operand_p (int code, HOST_WIDE_INT x) 3672{ 3673 switch (code) 3674 { 3675 case ASHIFT: 3676 case ASHIFTRT: 3677 case LSHIFTRT: 3678 /* All shift counts are truncated to a valid constant. */ 3679 return true; 3680 3681 case ROTATE: 3682 case ROTATERT: 3683 /* Likewise rotates, if the target supports rotates at all. */ 3684 return ISA_HAS_ROR; 3685 3686 case AND: 3687 case IOR: 3688 case XOR: 3689 /* These instructions take 16-bit unsigned immediates. */ 3690 return SMALL_OPERAND_UNSIGNED (x); 3691 3692 case PLUS: 3693 case LT: 3694 case LTU: 3695 /* These instructions take 16-bit signed immediates. */ 3696 return SMALL_OPERAND (x); 3697 3698 case EQ: 3699 case NE: 3700 case GT: 3701 case GTU: 3702 /* The "immediate" forms of these instructions are really 3703 implemented as comparisons with register 0. */ 3704 return x == 0; 3705 3706 case GE: 3707 case GEU: 3708 /* Likewise, meaning that the only valid immediate operand is 1. */ 3709 return x == 1; 3710 3711 case LE: 3712 /* We add 1 to the immediate and use SLT. */ 3713 return SMALL_OPERAND (x + 1); 3714 3715 case LEU: 3716 /* Likewise SLTU, but reject the always-true case. */ 3717 return SMALL_OPERAND (x + 1) && x + 1 != 0; 3718 3719 case SIGN_EXTRACT: 3720 case ZERO_EXTRACT: 3721 /* The bit position and size are immediate operands. */ 3722 return ISA_HAS_EXT_INS; 3723 3724 default: 3725 /* By default assume that $0 can be used for 0. */ 3726 return x == 0; 3727 } 3728} 3729 3730/* Return the cost of binary operation X, given that the instruction 3731 sequence for a word-sized or smaller operation has cost SINGLE_COST 3732 and that the sequence of a double-word operation has cost DOUBLE_COST. 3733 If SPEED is true, optimize for speed otherwise optimize for size. */ 3734 3735static int 3736mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) 3737{ 3738 int cost; 3739 3740 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) 3741 cost = double_cost; 3742 else 3743 cost = single_cost; 3744 return (cost 3745 + set_src_cost (XEXP (x, 0), speed) 3746 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed)); 3747} 3748 3749/* Return the cost of floating-point multiplications of mode MODE. */ 3750 3751static int 3752mips_fp_mult_cost (machine_mode mode) 3753{ 3754 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; 3755} 3756 3757/* Return the cost of floating-point divisions of mode MODE. */ 3758 3759static int 3760mips_fp_div_cost (machine_mode mode) 3761{ 3762 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; 3763} 3764 3765/* Return the cost of sign-extending OP to mode MODE, not including the 3766 cost of OP itself. */ 3767 3768static int 3769mips_sign_extend_cost (machine_mode mode, rtx op) 3770{ 3771 if (MEM_P (op)) 3772 /* Extended loads are as cheap as unextended ones. */ 3773 return 0; 3774 3775 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) 3776 /* A sign extension from SImode to DImode in 64-bit mode is free. */ 3777 return 0; 3778 3779 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E) 3780 /* We can use SEB or SEH. */ 3781 return COSTS_N_INSNS (1); 3782 3783 /* We need to use a shift left and a shift right. */ 3784 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); 3785} 3786 3787/* Return the cost of zero-extending OP to mode MODE, not including the 3788 cost of OP itself. */ 3789 3790static int 3791mips_zero_extend_cost (machine_mode mode, rtx op) 3792{ 3793 if (MEM_P (op)) 3794 /* Extended loads are as cheap as unextended ones. */ 3795 return 0; 3796 3797 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) 3798 /* We need a shift left by 32 bits and a shift right by 32 bits. */ 3799 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); 3800 3801 if (GENERATE_MIPS16E) 3802 /* We can use ZEB or ZEH. */ 3803 return COSTS_N_INSNS (1); 3804 3805 if (TARGET_MIPS16) 3806 /* We need to load 0xff or 0xffff into a register and use AND. */ 3807 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3); 3808 3809 /* We can use ANDI. */ 3810 return COSTS_N_INSNS (1); 3811} 3812 3813/* Return the cost of moving between two registers of mode MODE, 3814 assuming that the move will be in pieces of at most UNITS bytes. */ 3815 3816static int 3817mips_set_reg_reg_piece_cost (machine_mode mode, unsigned int units) 3818{ 3819 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units); 3820} 3821 3822/* Return the cost of moving between two registers of mode MODE. */ 3823 3824static int 3825mips_set_reg_reg_cost (machine_mode mode) 3826{ 3827 switch (GET_MODE_CLASS (mode)) 3828 { 3829 case MODE_CC: 3830 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode)); 3831 3832 case MODE_FLOAT: 3833 case MODE_COMPLEX_FLOAT: 3834 case MODE_VECTOR_FLOAT: 3835 if (TARGET_HARD_FLOAT) 3836 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE); 3837 /* Fall through */ 3838 3839 default: 3840 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD); 3841 } 3842} 3843 3844/* Implement TARGET_RTX_COSTS. */ 3845 3846static bool 3847mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, 3848 int *total, bool speed) 3849{ 3850 machine_mode mode = GET_MODE (x); 3851 bool float_mode_p = FLOAT_MODE_P (mode); 3852 int cost; 3853 rtx addr; 3854 3855 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't 3856 appear in the instruction stream, and the cost of a comparison is 3857 really the cost of the branch or scc condition. At the time of 3858 writing, GCC only uses an explicit outer COMPARE code when optabs 3859 is testing whether a constant is expensive enough to force into a 3860 register. We want optabs to pass such constants through the MIPS 3861 expanders instead, so make all constants very cheap here. */ 3862 if (outer_code == COMPARE) 3863 { 3864 gcc_assert (CONSTANT_P (x)); 3865 *total = 0; 3866 return true; 3867 } 3868 3869 switch (code) 3870 { 3871 case CONST_INT: 3872 /* Treat *clear_upper32-style ANDs as having zero cost in the 3873 second operand. The cost is entirely in the first operand. 3874 3875 ??? This is needed because we would otherwise try to CSE 3876 the constant operand. Although that's the right thing for 3877 instructions that continue to be a register operation throughout 3878 compilation, it is disastrous for instructions that could 3879 later be converted into a memory operation. */ 3880 if (TARGET_64BIT 3881 && outer_code == AND 3882 && UINTVAL (x) == 0xffffffff) 3883 { 3884 *total = 0; 3885 return true; 3886 } 3887 3888 if (TARGET_MIPS16) 3889 { 3890 cost = mips16_constant_cost (outer_code, INTVAL (x)); 3891 if (cost >= 0) 3892 { 3893 *total = cost; 3894 return true; 3895 } 3896 } 3897 else 3898 { 3899 /* When not optimizing for size, we care more about the cost 3900 of hot code, and hot code is often in a loop. If a constant 3901 operand needs to be forced into a register, we will often be 3902 able to hoist the constant load out of the loop, so the load 3903 should not contribute to the cost. */ 3904 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x))) 3905 { 3906 *total = 0; 3907 return true; 3908 } 3909 } 3910 /* Fall through. */ 3911 3912 case CONST: 3913 case SYMBOL_REF: 3914 case LABEL_REF: 3915 case CONST_DOUBLE: 3916 if (force_to_mem_operand (x, VOIDmode)) 3917 { 3918 *total = COSTS_N_INSNS (1); 3919 return true; 3920 } 3921 cost = mips_const_insns (x); 3922 if (cost > 0) 3923 { 3924 /* If the constant is likely to be stored in a GPR, SETs of 3925 single-insn constants are as cheap as register sets; we 3926 never want to CSE them. 3927 3928 Don't reduce the cost of storing a floating-point zero in 3929 FPRs. If we have a zero in an FPR for other reasons, we 3930 can get better cfg-cleanup and delayed-branch results by 3931 using it consistently, rather than using $0 sometimes and 3932 an FPR at other times. Also, moves between floating-point 3933 registers are sometimes cheaper than (D)MTC1 $0. */ 3934 if (cost == 1 3935 && outer_code == SET 3936 && !(float_mode_p && TARGET_HARD_FLOAT)) 3937 cost = 0; 3938 /* When non-MIPS16 code loads a constant N>1 times, we rarely 3939 want to CSE the constant itself. It is usually better to 3940 have N copies of the last operation in the sequence and one 3941 shared copy of the other operations. (Note that this is 3942 not true for MIPS16 code, where the final operation in the 3943 sequence is often an extended instruction.) 3944 3945 Also, if we have a CONST_INT, we don't know whether it is 3946 for a word or doubleword operation, so we cannot rely on 3947 the result of mips_build_integer. */ 3948 else if (!TARGET_MIPS16 3949 && (outer_code == SET || mode == VOIDmode)) 3950 cost = 1; 3951 *total = COSTS_N_INSNS (cost); 3952 return true; 3953 } 3954 /* The value will need to be fetched from the constant pool. */ 3955 *total = CONSTANT_POOL_COST; 3956 return true; 3957 3958 case MEM: 3959 /* If the address is legitimate, return the number of 3960 instructions it needs. */ 3961 addr = XEXP (x, 0); 3962 cost = mips_address_insns (addr, mode, true); 3963 if (cost > 0) 3964 { 3965 *total = COSTS_N_INSNS (cost + 1); 3966 return true; 3967 } 3968 /* Check for a scaled indexed address. */ 3969 if (mips_lwxs_address_p (addr) 3970 || mips_lx_address_p (addr, mode)) 3971 { 3972 *total = COSTS_N_INSNS (2); 3973 return true; 3974 } 3975 /* Otherwise use the default handling. */ 3976 return false; 3977 3978 case FFS: 3979 *total = COSTS_N_INSNS (6); 3980 return false; 3981 3982 case NOT: 3983 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); 3984 return false; 3985 3986 case AND: 3987 /* Check for a *clear_upper32 pattern and treat it like a zero 3988 extension. See the pattern's comment for details. */ 3989 if (TARGET_64BIT 3990 && mode == DImode 3991 && CONST_INT_P (XEXP (x, 1)) 3992 && UINTVAL (XEXP (x, 1)) == 0xffffffff) 3993 { 3994 *total = (mips_zero_extend_cost (mode, XEXP (x, 0)) 3995 + set_src_cost (XEXP (x, 0), speed)); 3996 return true; 3997 } 3998 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1))) 3999 { 4000 rtx op = XEXP (x, 0); 4001 if (GET_CODE (op) == ASHIFT 4002 && CONST_INT_P (XEXP (op, 1)) 4003 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32)) 4004 { 4005 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed); 4006 return true; 4007 } 4008 } 4009 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in 4010 a single instruction. */ 4011 if (!TARGET_MIPS16 4012 && GET_CODE (XEXP (x, 0)) == NOT 4013 && GET_CODE (XEXP (x, 1)) == NOT) 4014 { 4015 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1; 4016 *total = (COSTS_N_INSNS (cost) 4017 + set_src_cost (XEXP (XEXP (x, 0), 0), speed) 4018 + set_src_cost (XEXP (XEXP (x, 1), 0), speed)); 4019 return true; 4020 } 4021 4022 /* Fall through. */ 4023 4024 case IOR: 4025 case XOR: 4026 /* Double-word operations use two single-word operations. */ 4027 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2), 4028 speed); 4029 return true; 4030 4031 case ASHIFT: 4032 case ASHIFTRT: 4033 case LSHIFTRT: 4034 case ROTATE: 4035 case ROTATERT: 4036 if (CONSTANT_P (XEXP (x, 1))) 4037 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), 4038 speed); 4039 else 4040 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12), 4041 speed); 4042 return true; 4043 4044 case ABS: 4045 if (float_mode_p) 4046 *total = mips_cost->fp_add; 4047 else 4048 *total = COSTS_N_INSNS (4); 4049 return false; 4050 4051 case LO_SUM: 4052 /* Low-part immediates need an extended MIPS16 instruction. */ 4053 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1) 4054 + set_src_cost (XEXP (x, 0), speed)); 4055 return true; 4056 4057 case LT: 4058 case LTU: 4059 case LE: 4060 case LEU: 4061 case GT: 4062 case GTU: 4063 case GE: 4064 case GEU: 4065 case EQ: 4066 case NE: 4067 case UNORDERED: 4068 case LTGT: 4069 /* Branch comparisons have VOIDmode, so use the first operand's 4070 mode instead. */ 4071 mode = GET_MODE (XEXP (x, 0)); 4072 if (FLOAT_MODE_P (mode)) 4073 { 4074 *total = mips_cost->fp_add; 4075 return false; 4076 } 4077 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), 4078 speed); 4079 return true; 4080 4081 case MINUS: 4082 if (float_mode_p 4083 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3) 4084 && TARGET_FUSED_MADD 4085 && !HONOR_NANS (mode) 4086 && !HONOR_SIGNED_ZEROS (mode)) 4087 { 4088 /* See if we can use NMADD or NMSUB. See mips.md for the 4089 associated patterns. */ 4090 rtx op0 = XEXP (x, 0); 4091 rtx op1 = XEXP (x, 1); 4092 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) 4093 { 4094 *total = (mips_fp_mult_cost (mode) 4095 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed) 4096 + set_src_cost (XEXP (op0, 1), speed) 4097 + set_src_cost (op1, speed)); 4098 return true; 4099 } 4100 if (GET_CODE (op1) == MULT) 4101 { 4102 *total = (mips_fp_mult_cost (mode) 4103 + set_src_cost (op0, speed) 4104 + set_src_cost (XEXP (op1, 0), speed) 4105 + set_src_cost (XEXP (op1, 1), speed)); 4106 return true; 4107 } 4108 } 4109 /* Fall through. */ 4110 4111 case PLUS: 4112 if (float_mode_p) 4113 { 4114 /* If this is part of a MADD or MSUB, treat the PLUS as 4115 being free. */ 4116 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3) 4117 && TARGET_FUSED_MADD 4118 && GET_CODE (XEXP (x, 0)) == MULT) 4119 *total = 0; 4120 else 4121 *total = mips_cost->fp_add; 4122 return false; 4123 } 4124 4125 /* If it's an add + mult (which is equivalent to shift left) and 4126 it's immediate operand satisfies const_immlsa_operand predicate. */ 4127 if (((ISA_HAS_LSA && mode == SImode) 4128 || (ISA_HAS_DLSA && mode == DImode)) 4129 && GET_CODE (XEXP (x, 0)) == MULT) 4130 { 4131 rtx op2 = XEXP (XEXP (x, 0), 1); 4132 if (const_immlsa_operand (op2, mode)) 4133 { 4134 *total = (COSTS_N_INSNS (1) 4135 + set_src_cost (XEXP (XEXP (x, 0), 0), speed) 4136 + set_src_cost (XEXP (x, 1), speed)); 4137 return true; 4138 } 4139 } 4140 4141 /* Double-word operations require three single-word operations and 4142 an SLTU. The MIPS16 version then needs to move the result of 4143 the SLTU from $24 to a MIPS16 register. */ 4144 *total = mips_binary_cost (x, COSTS_N_INSNS (1), 4145 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4), 4146 speed); 4147 return true; 4148 4149 case NEG: 4150 if (float_mode_p 4151 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3) 4152 && TARGET_FUSED_MADD 4153 && !HONOR_NANS (mode) 4154 && HONOR_SIGNED_ZEROS (mode)) 4155 { 4156 /* See if we can use NMADD or NMSUB. See mips.md for the 4157 associated patterns. */ 4158 rtx op = XEXP (x, 0); 4159 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) 4160 && GET_CODE (XEXP (op, 0)) == MULT) 4161 { 4162 *total = (mips_fp_mult_cost (mode) 4163 + set_src_cost (XEXP (XEXP (op, 0), 0), speed) 4164 + set_src_cost (XEXP (XEXP (op, 0), 1), speed) 4165 + set_src_cost (XEXP (op, 1), speed)); 4166 return true; 4167 } 4168 } 4169 4170 if (float_mode_p) 4171 *total = mips_cost->fp_add; 4172 else 4173 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); 4174 return false; 4175 4176 case FMA: 4177 if (ISA_HAS_FP_MADDF_MSUBF) 4178 *total = mips_fp_mult_cost (mode); 4179 return false; 4180 4181 case MULT: 4182 if (float_mode_p) 4183 *total = mips_fp_mult_cost (mode); 4184 else if (mode == DImode && !TARGET_64BIT) 4185 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions, 4186 where the mulsidi3 always includes an MFHI and an MFLO. */ 4187 *total = (speed 4188 ? mips_cost->int_mult_si * 3 + 6 4189 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)); 4190 else if (!speed) 4191 *total = COSTS_N_INSNS ((ISA_HAS_MUL3 || ISA_HAS_R6MUL) ? 1 : 2) + 1; 4192 else if (mode == DImode) 4193 *total = mips_cost->int_mult_di; 4194 else 4195 *total = mips_cost->int_mult_si; 4196 return false; 4197 4198 case DIV: 4199 /* Check for a reciprocal. */ 4200 if (float_mode_p 4201 && ISA_HAS_FP_RECIP_RSQRT (mode) 4202 && flag_unsafe_math_optimizations 4203 && XEXP (x, 0) == CONST1_RTX (mode)) 4204 { 4205 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) 4206 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the 4207 division as being free. */ 4208 *total = set_src_cost (XEXP (x, 1), speed); 4209 else 4210 *total = (mips_fp_div_cost (mode) 4211 + set_src_cost (XEXP (x, 1), speed)); 4212 return true; 4213 } 4214 /* Fall through. */ 4215 4216 case SQRT: 4217 case MOD: 4218 if (float_mode_p) 4219 { 4220 *total = mips_fp_div_cost (mode); 4221 return false; 4222 } 4223 /* Fall through. */ 4224 4225 case UDIV: 4226 case UMOD: 4227 if (!speed) 4228 { 4229 /* It is our responsibility to make division by a power of 2 4230 as cheap as 2 register additions if we want the division 4231 expanders to be used for such operations; see the setting 4232 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16 4233 should always produce shorter code than using 4234 expand_sdiv2_pow2. */ 4235 if (TARGET_MIPS16 4236 && CONST_INT_P (XEXP (x, 1)) 4237 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) 4238 { 4239 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed); 4240 return true; 4241 } 4242 *total = COSTS_N_INSNS (mips_idiv_insns ()); 4243 } 4244 else if (mode == DImode) 4245 *total = mips_cost->int_div_di; 4246 else 4247 *total = mips_cost->int_div_si; 4248 return false; 4249 4250 case SIGN_EXTEND: 4251 *total = mips_sign_extend_cost (mode, XEXP (x, 0)); 4252 return false; 4253 4254 case ZERO_EXTEND: 4255 if (outer_code == SET 4256 && ISA_HAS_BADDU 4257 && (GET_CODE (XEXP (x, 0)) == TRUNCATE 4258 || GET_CODE (XEXP (x, 0)) == SUBREG) 4259 && GET_MODE (XEXP (x, 0)) == QImode 4260 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) 4261 { 4262 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed); 4263 return true; 4264 } 4265 *total = mips_zero_extend_cost (mode, XEXP (x, 0)); 4266 return false; 4267 case TRUNCATE: 4268 /* Costings for highpart multiplies. Matching patterns of the form: 4269 4270 (lshiftrt:DI (mult:DI (sign_extend:DI (...) 4271 (sign_extend:DI (...)) 4272 (const_int 32) 4273 */ 4274 if (ISA_HAS_R6MUL 4275 && (GET_CODE (XEXP (x, 0)) == ASHIFTRT 4276 || GET_CODE (XEXP (x, 0)) == LSHIFTRT) 4277 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 4278 && ((INTVAL (XEXP (XEXP (x, 0), 1)) == 32 4279 && GET_MODE (XEXP (x, 0)) == DImode) 4280 || (ISA_HAS_R6DMUL 4281 && INTVAL (XEXP (XEXP (x, 0), 1)) == 64 4282 && GET_MODE (XEXP (x, 0)) == TImode)) 4283 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 4284 && ((GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND 4285 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SIGN_EXTEND) 4286 || (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND 4287 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) 4288 == ZERO_EXTEND)))) 4289 { 4290 if (!speed) 4291 *total = COSTS_N_INSNS (1) + 1; 4292 else if (mode == DImode) 4293 *total = mips_cost->int_mult_di; 4294 else 4295 *total = mips_cost->int_mult_si; 4296 4297 /* Sign extension is free, zero extension costs for DImode when 4298 on a 64bit core / when DMUL is present. */ 4299 for (int i = 0; i < 2; ++i) 4300 { 4301 rtx op = XEXP (XEXP (XEXP (x, 0), 0), i); 4302 if (ISA_HAS_R6DMUL 4303 && GET_CODE (op) == ZERO_EXTEND 4304 && GET_MODE (op) == DImode) 4305 *total += rtx_cost (op, MULT, i, speed); 4306 else 4307 *total += rtx_cost (XEXP (op, 0), GET_CODE (op), 0, speed); 4308 } 4309 4310 return true; 4311 } 4312 return false; 4313 4314 case FLOAT: 4315 case UNSIGNED_FLOAT: 4316 case FIX: 4317 case FLOAT_EXTEND: 4318 case FLOAT_TRUNCATE: 4319 *total = mips_cost->fp_add; 4320 return false; 4321 4322 case SET: 4323 if (register_operand (SET_DEST (x), VOIDmode) 4324 && reg_or_0_operand (SET_SRC (x), VOIDmode)) 4325 { 4326 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x))); 4327 return true; 4328 } 4329 return false; 4330 4331 default: 4332 return false; 4333 } 4334} 4335 4336/* Implement TARGET_ADDRESS_COST. */ 4337 4338static int 4339mips_address_cost (rtx addr, machine_mode mode, 4340 addr_space_t as ATTRIBUTE_UNUSED, 4341 bool speed ATTRIBUTE_UNUSED) 4342{ 4343 return mips_address_insns (addr, mode, false); 4344} 4345 4346/* Information about a single instruction in a multi-instruction 4347 asm sequence. */ 4348struct mips_multi_member { 4349 /* True if this is a label, false if it is code. */ 4350 bool is_label_p; 4351 4352 /* The output_asm_insn format of the instruction. */ 4353 const char *format; 4354 4355 /* The operands to the instruction. */ 4356 rtx operands[MAX_RECOG_OPERANDS]; 4357}; 4358typedef struct mips_multi_member mips_multi_member; 4359 4360/* The instructions that make up the current multi-insn sequence. */ 4361static vec<mips_multi_member> mips_multi_members; 4362 4363/* How many instructions (as opposed to labels) are in the current 4364 multi-insn sequence. */ 4365static unsigned int mips_multi_num_insns; 4366 4367/* Start a new multi-insn sequence. */ 4368 4369static void 4370mips_multi_start (void) 4371{ 4372 mips_multi_members.truncate (0); 4373 mips_multi_num_insns = 0; 4374} 4375 4376/* Add a new, uninitialized member to the current multi-insn sequence. */ 4377 4378static struct mips_multi_member * 4379mips_multi_add (void) 4380{ 4381 mips_multi_member empty; 4382 return mips_multi_members.safe_push (empty); 4383} 4384 4385/* Add a normal insn with the given asm format to the current multi-insn 4386 sequence. The other arguments are a null-terminated list of operands. */ 4387 4388static void 4389mips_multi_add_insn (const char *format, ...) 4390{ 4391 struct mips_multi_member *member; 4392 va_list ap; 4393 unsigned int i; 4394 rtx op; 4395 4396 member = mips_multi_add (); 4397 member->is_label_p = false; 4398 member->format = format; 4399 va_start (ap, format); 4400 i = 0; 4401 while ((op = va_arg (ap, rtx))) 4402 member->operands[i++] = op; 4403 va_end (ap); 4404 mips_multi_num_insns++; 4405} 4406 4407/* Add the given label definition to the current multi-insn sequence. 4408 The definition should include the colon. */ 4409 4410static void 4411mips_multi_add_label (const char *label) 4412{ 4413 struct mips_multi_member *member; 4414 4415 member = mips_multi_add (); 4416 member->is_label_p = true; 4417 member->format = label; 4418} 4419 4420/* Return the index of the last member of the current multi-insn sequence. */ 4421 4422static unsigned int 4423mips_multi_last_index (void) 4424{ 4425 return mips_multi_members.length () - 1; 4426} 4427 4428/* Add a copy of an existing instruction to the current multi-insn 4429 sequence. I is the index of the instruction that should be copied. */ 4430 4431static void 4432mips_multi_copy_insn (unsigned int i) 4433{ 4434 struct mips_multi_member *member; 4435 4436 member = mips_multi_add (); 4437 memcpy (member, &mips_multi_members[i], sizeof (*member)); 4438 gcc_assert (!member->is_label_p); 4439} 4440 4441/* Change the operand of an existing instruction in the current 4442 multi-insn sequence. I is the index of the instruction, 4443 OP is the index of the operand, and X is the new value. */ 4444 4445static void 4446mips_multi_set_operand (unsigned int i, unsigned int op, rtx x) 4447{ 4448 mips_multi_members[i].operands[op] = x; 4449} 4450 4451/* Write out the asm code for the current multi-insn sequence. */ 4452 4453static void 4454mips_multi_write (void) 4455{ 4456 struct mips_multi_member *member; 4457 unsigned int i; 4458 4459 FOR_EACH_VEC_ELT (mips_multi_members, i, member) 4460 if (member->is_label_p) 4461 fprintf (asm_out_file, "%s\n", member->format); 4462 else 4463 output_asm_insn (member->format, member->operands); 4464} 4465 4466/* Return one word of double-word value OP, taking into account the fixed 4467 endianness of certain registers. HIGH_P is true to select the high part, 4468 false to select the low part. */ 4469 4470rtx 4471mips_subword (rtx op, bool high_p) 4472{ 4473 unsigned int byte, offset; 4474 machine_mode mode; 4475 4476 mode = GET_MODE (op); 4477 if (mode == VOIDmode) 4478 mode = TARGET_64BIT ? TImode : DImode; 4479 4480 if (TARGET_BIG_ENDIAN ? !high_p : high_p) 4481 byte = UNITS_PER_WORD; 4482 else 4483 byte = 0; 4484 4485 if (FP_REG_RTX_P (op)) 4486 { 4487 /* Paired FPRs are always ordered little-endian. */ 4488 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0); 4489 return gen_rtx_REG (word_mode, REGNO (op) + offset); 4490 } 4491 4492 if (MEM_P (op)) 4493 return mips_rewrite_small_data (adjust_address (op, word_mode, byte)); 4494 4495 return simplify_gen_subreg (word_mode, op, mode, byte); 4496} 4497 4498/* Return true if SRC should be moved into DEST using "MULT $0, $0". 4499 SPLIT_TYPE is the condition under which moves should be split. */ 4500 4501static bool 4502mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type) 4503{ 4504 return ((split_type != SPLIT_FOR_SPEED 4505 || mips_tuning_info.fast_mult_zero_zero_p) 4506 && src == const0_rtx 4507 && REG_P (dest) 4508 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD 4509 && (ISA_HAS_DSP_MULT 4510 ? ACC_REG_P (REGNO (dest)) 4511 : MD_REG_P (REGNO (dest)))); 4512} 4513 4514/* Return true if a move from SRC to DEST should be split into two. 4515 SPLIT_TYPE describes the split condition. */ 4516 4517bool 4518mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type) 4519{ 4520 /* Check whether the move can be done using some variant of MULT $0,$0. */ 4521 if (mips_mult_move_p (dest, src, split_type)) 4522 return false; 4523 4524 /* FPR-to-FPR moves can be done in a single instruction, if they're 4525 allowed at all. */ 4526 unsigned int size = GET_MODE_SIZE (GET_MODE (dest)); 4527 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) 4528 return false; 4529 4530 /* Check for floating-point loads and stores. */ 4531 if (size == 8 && ISA_HAS_LDC1_SDC1) 4532 { 4533 if (FP_REG_RTX_P (dest) && MEM_P (src)) 4534 return false; 4535 if (FP_REG_RTX_P (src) && MEM_P (dest)) 4536 return false; 4537 } 4538 4539 /* Otherwise split all multiword moves. */ 4540 return size > UNITS_PER_WORD; 4541} 4542 4543/* Split a move from SRC to DEST, given that mips_split_move_p holds. 4544 SPLIT_TYPE describes the split condition. */ 4545 4546void 4547mips_split_move (rtx dest, rtx src, enum mips_split_type split_type) 4548{ 4549 rtx low_dest; 4550 4551 gcc_checking_assert (mips_split_move_p (dest, src, split_type)); 4552 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) 4553 { 4554 if (!TARGET_64BIT && GET_MODE (dest) == DImode) 4555 emit_insn (gen_move_doubleword_fprdi (dest, src)); 4556 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode) 4557 emit_insn (gen_move_doubleword_fprdf (dest, src)); 4558 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode) 4559 emit_insn (gen_move_doubleword_fprv2sf (dest, src)); 4560 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode) 4561 emit_insn (gen_move_doubleword_fprv2si (dest, src)); 4562 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode) 4563 emit_insn (gen_move_doubleword_fprv4hi (dest, src)); 4564 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode) 4565 emit_insn (gen_move_doubleword_fprv8qi (dest, src)); 4566 else if (TARGET_64BIT && GET_MODE (dest) == TFmode) 4567 emit_insn (gen_move_doubleword_fprtf (dest, src)); 4568 else 4569 gcc_unreachable (); 4570 } 4571 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) 4572 { 4573 low_dest = mips_subword (dest, false); 4574 mips_emit_move (low_dest, mips_subword (src, false)); 4575 if (TARGET_64BIT) 4576 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); 4577 else 4578 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); 4579 } 4580 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) 4581 { 4582 mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); 4583 if (TARGET_64BIT) 4584 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); 4585 else 4586 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); 4587 } 4588 else 4589 { 4590 /* The operation can be split into two normal moves. Decide in 4591 which order to do them. */ 4592 low_dest = mips_subword (dest, false); 4593 if (REG_P (low_dest) 4594 && reg_overlap_mentioned_p (low_dest, src)) 4595 { 4596 mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); 4597 mips_emit_move (low_dest, mips_subword (src, false)); 4598 } 4599 else 4600 { 4601 mips_emit_move (low_dest, mips_subword (src, false)); 4602 mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); 4603 } 4604 } 4605} 4606 4607/* Return the split type for instruction INSN. */ 4608 4609static enum mips_split_type 4610mips_insn_split_type (rtx insn) 4611{ 4612 basic_block bb = BLOCK_FOR_INSN (insn); 4613 if (bb) 4614 { 4615 if (optimize_bb_for_speed_p (bb)) 4616 return SPLIT_FOR_SPEED; 4617 else 4618 return SPLIT_FOR_SIZE; 4619 } 4620 /* Once CFG information has been removed, we should trust the optimization 4621 decisions made by previous passes and only split where necessary. */ 4622 return SPLIT_IF_NECESSARY; 4623} 4624 4625/* Return true if a move from SRC to DEST in INSN should be split. */ 4626 4627bool 4628mips_split_move_insn_p (rtx dest, rtx src, rtx insn) 4629{ 4630 return mips_split_move_p (dest, src, mips_insn_split_type (insn)); 4631} 4632 4633/* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p 4634 holds. */ 4635 4636void 4637mips_split_move_insn (rtx dest, rtx src, rtx insn) 4638{ 4639 mips_split_move (dest, src, mips_insn_split_type (insn)); 4640} 4641 4642/* Return the appropriate instructions to move SRC into DEST. Assume 4643 that SRC is operand 1 and DEST is operand 0. */ 4644 4645const char * 4646mips_output_move (rtx dest, rtx src) 4647{ 4648 enum rtx_code dest_code, src_code; 4649 machine_mode mode; 4650 enum mips_symbol_type symbol_type; 4651 bool dbl_p; 4652 4653 dest_code = GET_CODE (dest); 4654 src_code = GET_CODE (src); 4655 mode = GET_MODE (dest); 4656 dbl_p = (GET_MODE_SIZE (mode) == 8); 4657 4658 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY)) 4659 return "#"; 4660 4661 if ((src_code == REG && GP_REG_P (REGNO (src))) 4662 || (!TARGET_MIPS16 && src == CONST0_RTX (mode))) 4663 { 4664 if (dest_code == REG) 4665 { 4666 if (GP_REG_P (REGNO (dest))) 4667 return "move\t%0,%z1"; 4668 4669 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY)) 4670 { 4671 if (ISA_HAS_DSP_MULT) 4672 return "mult\t%q0,%.,%."; 4673 else 4674 return "mult\t%.,%."; 4675 } 4676 4677 /* Moves to HI are handled by special .md insns. */ 4678 if (REGNO (dest) == LO_REGNUM) 4679 return "mtlo\t%z1"; 4680 4681 if (DSP_ACC_REG_P (REGNO (dest))) 4682 { 4683 static char retval[] = "mt__\t%z1,%q0"; 4684 4685 retval[2] = reg_names[REGNO (dest)][4]; 4686 retval[3] = reg_names[REGNO (dest)][5]; 4687 return retval; 4688 } 4689 4690 if (FP_REG_P (REGNO (dest))) 4691 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0"; 4692 4693 if (ALL_COP_REG_P (REGNO (dest))) 4694 { 4695 static char retval[] = "dmtc_\t%z1,%0"; 4696 4697 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); 4698 return dbl_p ? retval : retval + 1; 4699 } 4700 } 4701 if (dest_code == MEM) 4702 switch (GET_MODE_SIZE (mode)) 4703 { 4704 case 1: return "sb\t%z1,%0"; 4705 case 2: return "sh\t%z1,%0"; 4706 case 4: return "sw\t%z1,%0"; 4707 case 8: return "sd\t%z1,%0"; 4708 } 4709 } 4710 if (dest_code == REG && GP_REG_P (REGNO (dest))) 4711 { 4712 if (src_code == REG) 4713 { 4714 /* Moves from HI are handled by special .md insns. */ 4715 if (REGNO (src) == LO_REGNUM) 4716 { 4717 /* When generating VR4120 or VR4130 code, we use MACC and 4718 DMACC instead of MFLO. This avoids both the normal 4719 MIPS III HI/LO hazards and the errata related to 4720 -mfix-vr4130. */ 4721 if (ISA_HAS_MACCHI) 4722 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; 4723 return "mflo\t%0"; 4724 } 4725 4726 if (DSP_ACC_REG_P (REGNO (src))) 4727 { 4728 static char retval[] = "mf__\t%0,%q1"; 4729 4730 retval[2] = reg_names[REGNO (src)][4]; 4731 retval[3] = reg_names[REGNO (src)][5]; 4732 return retval; 4733 } 4734 4735 if (FP_REG_P (REGNO (src))) 4736 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1"; 4737 4738 if (ALL_COP_REG_P (REGNO (src))) 4739 { 4740 static char retval[] = "dmfc_\t%0,%1"; 4741 4742 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); 4743 return dbl_p ? retval : retval + 1; 4744 } 4745 } 4746 4747 if (src_code == MEM) 4748 switch (GET_MODE_SIZE (mode)) 4749 { 4750 case 1: return "lbu\t%0,%1"; 4751 case 2: return "lhu\t%0,%1"; 4752 case 4: return "lw\t%0,%1"; 4753 case 8: return "ld\t%0,%1"; 4754 } 4755 4756 if (src_code == CONST_INT) 4757 { 4758 /* Don't use the X format for the operand itself, because that 4759 will give out-of-range numbers for 64-bit hosts and 32-bit 4760 targets. */ 4761 if (!TARGET_MIPS16) 4762 return "li\t%0,%1\t\t\t# %X1"; 4763 4764 if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) 4765 return "li\t%0,%1"; 4766 4767 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src))) 4768 return "#"; 4769 } 4770 4771 if (src_code == HIGH) 4772 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; 4773 4774 if (CONST_GP_P (src)) 4775 return "move\t%0,%1"; 4776 4777 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type) 4778 && mips_lo_relocs[symbol_type] != 0) 4779 { 4780 /* A signed 16-bit constant formed by applying a relocation 4781 operator to a symbolic address. */ 4782 gcc_assert (!mips_split_p[symbol_type]); 4783 return "li\t%0,%R1"; 4784 } 4785 4786 if (symbolic_operand (src, VOIDmode)) 4787 { 4788 gcc_assert (TARGET_MIPS16 4789 ? TARGET_MIPS16_TEXT_LOADS 4790 : !TARGET_EXPLICIT_RELOCS); 4791 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1"; 4792 } 4793 } 4794 if (src_code == REG && FP_REG_P (REGNO (src))) 4795 { 4796 if (dest_code == REG && FP_REG_P (REGNO (dest))) 4797 { 4798 if (GET_MODE (dest) == V2SFmode) 4799 return "mov.ps\t%0,%1"; 4800 else 4801 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1"; 4802 } 4803 4804 if (dest_code == MEM) 4805 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0"; 4806 } 4807 if (dest_code == REG && FP_REG_P (REGNO (dest))) 4808 { 4809 if (src_code == MEM) 4810 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1"; 4811 } 4812 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM) 4813 { 4814 static char retval[] = "l_c_\t%0,%1"; 4815 4816 retval[1] = (dbl_p ? 'd' : 'w'); 4817 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); 4818 return retval; 4819 } 4820 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src))) 4821 { 4822 static char retval[] = "s_c_\t%1,%0"; 4823 4824 retval[1] = (dbl_p ? 'd' : 'w'); 4825 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); 4826 return retval; 4827 } 4828 gcc_unreachable (); 4829} 4830 4831/* Return true if CMP1 is a suitable second operand for integer ordering 4832 test CODE. See also the *sCC patterns in mips.md. */ 4833 4834static bool 4835mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) 4836{ 4837 switch (code) 4838 { 4839 case GT: 4840 case GTU: 4841 return reg_or_0_operand (cmp1, VOIDmode); 4842 4843 case GE: 4844 case GEU: 4845 return !TARGET_MIPS16 && cmp1 == const1_rtx; 4846 4847 case LT: 4848 case LTU: 4849 return arith_operand (cmp1, VOIDmode); 4850 4851 case LE: 4852 return sle_operand (cmp1, VOIDmode); 4853 4854 case LEU: 4855 return sleu_operand (cmp1, VOIDmode); 4856 4857 default: 4858 gcc_unreachable (); 4859 } 4860} 4861 4862/* Return true if *CMP1 (of mode MODE) is a valid second operand for 4863 integer ordering test *CODE, or if an equivalent combination can 4864 be formed by adjusting *CODE and *CMP1. When returning true, update 4865 *CODE and *CMP1 with the chosen code and operand, otherwise leave 4866 them alone. */ 4867 4868static bool 4869mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, 4870 machine_mode mode) 4871{ 4872 HOST_WIDE_INT plus_one; 4873 4874 if (mips_int_order_operand_ok_p (*code, *cmp1)) 4875 return true; 4876 4877 if (CONST_INT_P (*cmp1)) 4878 switch (*code) 4879 { 4880 case LE: 4881 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 4882 if (INTVAL (*cmp1) < plus_one) 4883 { 4884 *code = LT; 4885 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 4886 return true; 4887 } 4888 break; 4889 4890 case LEU: 4891 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 4892 if (plus_one != 0) 4893 { 4894 *code = LTU; 4895 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 4896 return true; 4897 } 4898 break; 4899 4900 default: 4901 break; 4902 } 4903 return false; 4904} 4905 4906/* Compare CMP0 and CMP1 using ordering test CODE and store the result 4907 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR 4908 is nonnull, it's OK to set TARGET to the inverse of the result and 4909 flip *INVERT_PTR instead. */ 4910 4911static void 4912mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, 4913 rtx target, rtx cmp0, rtx cmp1) 4914{ 4915 machine_mode mode; 4916 4917 /* First see if there is a MIPS instruction that can do this operation. 4918 If not, try doing the same for the inverse operation. If that also 4919 fails, force CMP1 into a register and try again. */ 4920 mode = GET_MODE (cmp0); 4921 if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) 4922 mips_emit_binary (code, target, cmp0, cmp1); 4923 else 4924 { 4925 enum rtx_code inv_code = reverse_condition (code); 4926 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode)) 4927 { 4928 cmp1 = force_reg (mode, cmp1); 4929 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); 4930 } 4931 else if (invert_ptr == 0) 4932 { 4933 rtx inv_target; 4934 4935 inv_target = mips_force_binary (GET_MODE (target), 4936 inv_code, cmp0, cmp1); 4937 mips_emit_binary (XOR, target, inv_target, const1_rtx); 4938 } 4939 else 4940 { 4941 *invert_ptr = !*invert_ptr; 4942 mips_emit_binary (inv_code, target, cmp0, cmp1); 4943 } 4944 } 4945} 4946 4947/* Return a register that is zero iff CMP0 and CMP1 are equal. 4948 The register will have the same mode as CMP0. */ 4949 4950static rtx 4951mips_zero_if_equal (rtx cmp0, rtx cmp1) 4952{ 4953 if (cmp1 == const0_rtx) 4954 return cmp0; 4955 4956 if (uns_arith_operand (cmp1, VOIDmode)) 4957 return expand_binop (GET_MODE (cmp0), xor_optab, 4958 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 4959 4960 return expand_binop (GET_MODE (cmp0), sub_optab, 4961 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 4962} 4963 4964/* Convert *CODE into a code that can be used in a floating-point 4965 scc instruction (C.cond.fmt). Return true if the values of 4966 the condition code registers will be inverted, with 0 indicating 4967 that the condition holds. */ 4968 4969static bool 4970mips_reversed_fp_cond (enum rtx_code *code) 4971{ 4972 switch (*code) 4973 { 4974 case NE: 4975 case LTGT: 4976 case ORDERED: 4977 *code = reverse_condition_maybe_unordered (*code); 4978 return true; 4979 4980 default: 4981 return false; 4982 } 4983} 4984 4985/* Allocate a floating-point condition-code register of mode MODE. 4986 4987 These condition code registers are used for certain kinds 4988 of compound operation, such as compare and branches, vconds, 4989 and built-in functions. At expand time, their use is entirely 4990 controlled by MIPS-specific code and is entirely internal 4991 to these compound operations. 4992 4993 We could (and did in the past) expose condition-code values 4994 as pseudo registers and leave the register allocator to pick 4995 appropriate registers. The problem is that it is not practically 4996 possible for the rtl optimizers to guarantee that no spills will 4997 be needed, even when AVOID_CCMODE_COPIES is defined. We would 4998 therefore need spill and reload sequences to handle the worst case. 4999 5000 Although such sequences do exist, they are very expensive and are 5001 not something we'd want to use. This is especially true of CCV2 and 5002 CCV4, where all the shuffling would greatly outweigh whatever benefit 5003 the vectorization itself provides. 5004 5005 The main benefit of having more than one condition-code register 5006 is to allow the pipelining of operations, especially those involving 5007 comparisons and conditional moves. We don't really expect the 5008 registers to be live for long periods, and certainly never want 5009 them to be live across calls. 5010 5011 Also, there should be no penalty attached to using all the available 5012 registers. They are simply bits in the same underlying FPU control 5013 register. 5014 5015 We therefore expose the hardware registers from the outset and use 5016 a simple round-robin allocation scheme. */ 5017 5018static rtx 5019mips_allocate_fcc (machine_mode mode) 5020{ 5021 unsigned int regno, count; 5022 5023 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC); 5024 5025 if (mode == CCmode) 5026 count = 1; 5027 else if (mode == CCV2mode) 5028 count = 2; 5029 else if (mode == CCV4mode) 5030 count = 4; 5031 else 5032 gcc_unreachable (); 5033 5034 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1); 5035 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST) 5036 cfun->machine->next_fcc = 0; 5037 regno = ST_REG_FIRST + cfun->machine->next_fcc; 5038 cfun->machine->next_fcc += count; 5039 return gen_rtx_REG (mode, regno); 5040} 5041 5042/* Convert a comparison into something that can be used in a branch or 5043 conditional move. On entry, *OP0 and *OP1 are the values being 5044 compared and *CODE is the code used to compare them. 5045 5046 Update *CODE, *OP0 and *OP1 so that they describe the final comparison. 5047 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible, 5048 otherwise any standard branch condition can be used. The standard branch 5049 conditions are: 5050 5051 - EQ or NE between two registers. 5052 - any comparison between a register and zero. */ 5053 5054static void 5055mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) 5056{ 5057 rtx cmp_op0 = *op0; 5058 rtx cmp_op1 = *op1; 5059 5060 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) 5061 { 5062 if (!need_eq_ne_p && *op1 == const0_rtx) 5063 ; 5064 else if (*code == EQ || *code == NE) 5065 { 5066 if (need_eq_ne_p) 5067 { 5068 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1); 5069 *op1 = const0_rtx; 5070 } 5071 else 5072 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); 5073 } 5074 else 5075 { 5076 /* The comparison needs a separate scc instruction. Store the 5077 result of the scc in *OP0 and compare it against zero. */ 5078 bool invert = false; 5079 *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); 5080 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1); 5081 *code = (invert ? EQ : NE); 5082 *op1 = const0_rtx; 5083 } 5084 } 5085 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0))) 5086 { 5087 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM); 5088 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1); 5089 *code = NE; 5090 *op1 = const0_rtx; 5091 } 5092 else 5093 { 5094 enum rtx_code cmp_code; 5095 5096 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt 5097 comparison to set a register. The branch or conditional move will 5098 then compare that register against zero. 5099 5100 Set CMP_CODE to the code of the comparison instruction and 5101 *CODE to the code that the branch or move should use. */ 5102 cmp_code = *code; 5103 if (ISA_HAS_CCF) 5104 { 5105 /* All FP conditions can be implemented directly with CMP.cond.fmt 5106 or by reversing the operands. */ 5107 *code = NE; 5108 *op0 = gen_reg_rtx (CCFmode); 5109 } 5110 else 5111 { 5112 /* Three FP conditions cannot be implemented by reversing the 5113 operands for C.cond.fmt, instead a reversed condition code is 5114 required and a test for false. */ 5115 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; 5116 if (ISA_HAS_8CC) 5117 *op0 = mips_allocate_fcc (CCmode); 5118 else 5119 *op0 = gen_rtx_REG (CCmode, FPSW_REGNUM); 5120 } 5121 5122 *op1 = const0_rtx; 5123 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); 5124 } 5125} 5126 5127/* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] 5128 and OPERAND[3]. Store the result in OPERANDS[0]. 5129 5130 On 64-bit targets, the mode of the comparison and target will always be 5131 SImode, thus possibly narrower than that of the comparison's operands. */ 5132 5133void 5134mips_expand_scc (rtx operands[]) 5135{ 5136 rtx target = operands[0]; 5137 enum rtx_code code = GET_CODE (operands[1]); 5138 rtx op0 = operands[2]; 5139 rtx op1 = operands[3]; 5140 5141 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); 5142 5143 if (code == EQ || code == NE) 5144 { 5145 if (ISA_HAS_SEQ_SNE 5146 && reg_imm10_operand (op1, GET_MODE (op1))) 5147 mips_emit_binary (code, target, op0, op1); 5148 else 5149 { 5150 rtx zie = mips_zero_if_equal (op0, op1); 5151 mips_emit_binary (code, target, zie, const0_rtx); 5152 } 5153 } 5154 else 5155 mips_emit_int_order_test (code, 0, target, op0, op1); 5156} 5157 5158/* Compare OPERANDS[1] with OPERANDS[2] using comparison code 5159 CODE and jump to OPERANDS[3] if the condition holds. */ 5160 5161void 5162mips_expand_conditional_branch (rtx *operands) 5163{ 5164 enum rtx_code code = GET_CODE (operands[0]); 5165 rtx op0 = operands[1]; 5166 rtx op1 = operands[2]; 5167 rtx condition; 5168 5169 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16); 5170 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 5171 emit_jump_insn (gen_condjump (condition, operands[3])); 5172} 5173 5174/* Implement: 5175 5176 (set temp (COND:CCV2 CMP_OP0 CMP_OP1)) 5177 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */ 5178 5179void 5180mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src, 5181 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1) 5182{ 5183 rtx cmp_result; 5184 bool reversed_p; 5185 5186 reversed_p = mips_reversed_fp_cond (&cond); 5187 cmp_result = mips_allocate_fcc (CCV2mode); 5188 emit_insn (gen_scc_ps (cmp_result, 5189 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1))); 5190 if (reversed_p) 5191 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src, 5192 cmp_result)); 5193 else 5194 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src, 5195 cmp_result)); 5196} 5197 5198/* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] 5199 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */ 5200 5201void 5202mips_expand_conditional_move (rtx *operands) 5203{ 5204 rtx cond; 5205 enum rtx_code code = GET_CODE (operands[1]); 5206 rtx op0 = XEXP (operands[1], 0); 5207 rtx op1 = XEXP (operands[1], 1); 5208 5209 mips_emit_compare (&code, &op0, &op1, true); 5210 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); 5211 5212 /* There is no direct support for general conditional GP move involving 5213 two registers using SEL. */ 5214 if (ISA_HAS_SEL 5215 && INTEGRAL_MODE_P (GET_MODE (operands[2])) 5216 && register_operand (operands[2], VOIDmode) 5217 && register_operand (operands[3], VOIDmode)) 5218 { 5219 machine_mode mode = GET_MODE (operands[0]); 5220 rtx temp = gen_reg_rtx (mode); 5221 rtx temp2 = gen_reg_rtx (mode); 5222 5223 emit_insn (gen_rtx_SET (VOIDmode, temp, 5224 gen_rtx_IF_THEN_ELSE (mode, cond, 5225 operands[2], const0_rtx))); 5226 5227 /* Flip the test for the second operand. */ 5228 cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1); 5229 5230 emit_insn (gen_rtx_SET (VOIDmode, temp2, 5231 gen_rtx_IF_THEN_ELSE (mode, cond, 5232 operands[3], const0_rtx))); 5233 5234 /* Merge the two results, at least one is guaranteed to be zero. */ 5235 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 5236 gen_rtx_IOR (mode, temp, temp2))); 5237 } 5238 else 5239 { 5240 if (FLOAT_MODE_P (GET_MODE (operands[2])) && !ISA_HAS_SEL) 5241 { 5242 operands[2] = force_reg (GET_MODE (operands[0]), operands[2]); 5243 operands[3] = force_reg (GET_MODE (operands[0]), operands[3]); 5244 } 5245 5246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 5247 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond, 5248 operands[2], operands[3]))); 5249 } 5250} 5251 5252/* Perform the comparison in COMPARISON, then trap if the condition holds. */ 5253 5254void 5255mips_expand_conditional_trap (rtx comparison) 5256{ 5257 rtx op0, op1; 5258 machine_mode mode; 5259 enum rtx_code code; 5260 5261 /* MIPS conditional trap instructions don't have GT or LE flavors, 5262 so we must swap the operands and convert to LT and GE respectively. */ 5263 code = GET_CODE (comparison); 5264 switch (code) 5265 { 5266 case GT: 5267 case LE: 5268 case GTU: 5269 case LEU: 5270 code = swap_condition (code); 5271 op0 = XEXP (comparison, 1); 5272 op1 = XEXP (comparison, 0); 5273 break; 5274 5275 default: 5276 op0 = XEXP (comparison, 0); 5277 op1 = XEXP (comparison, 1); 5278 break; 5279 } 5280 5281 mode = GET_MODE (XEXP (comparison, 0)); 5282 op0 = force_reg (mode, op0); 5283 if (!(ISA_HAS_COND_TRAPI 5284 ? arith_operand (op1, mode) 5285 : reg_or_0_operand (op1, mode))) 5286 op1 = force_reg (mode, op1); 5287 5288 emit_insn (gen_rtx_TRAP_IF (VOIDmode, 5289 gen_rtx_fmt_ee (code, mode, op0, op1), 5290 const0_rtx)); 5291} 5292 5293/* Initialize *CUM for a call to a function of type FNTYPE. */ 5294 5295void 5296mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype) 5297{ 5298 memset (cum, 0, sizeof (*cum)); 5299 cum->prototype = (fntype && prototype_p (fntype)); 5300 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype)); 5301} 5302 5303/* Fill INFO with information about a single argument. CUM is the 5304 cumulative state for earlier arguments. MODE is the mode of this 5305 argument and TYPE is its type (if known). NAMED is true if this 5306 is a named (fixed) argument rather than a variable one. */ 5307 5308static void 5309mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum, 5310 machine_mode mode, const_tree type, bool named) 5311{ 5312 bool doubleword_aligned_p; 5313 unsigned int num_bytes, num_words, max_regs; 5314 5315 /* Work out the size of the argument. */ 5316 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 5317 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 5318 5319 /* Decide whether it should go in a floating-point register, assuming 5320 one is free. Later code checks for availability. 5321 5322 The checks against UNITS_PER_FPVALUE handle the soft-float and 5323 single-float cases. */ 5324 switch (mips_abi) 5325 { 5326 case ABI_EABI: 5327 /* The EABI conventions have traditionally been defined in terms 5328 of TYPE_MODE, regardless of the actual type. */ 5329 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT 5330 || mode == V2SFmode) 5331 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); 5332 break; 5333 5334 case ABI_32: 5335 case ABI_O64: 5336 /* Only leading floating-point scalars are passed in 5337 floating-point registers. We also handle vector floats the same 5338 say, which is OK because they are not covered by the standard ABI. */ 5339 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode); 5340 info->fpr_p = (!cum->gp_reg_found 5341 && cum->arg_number < 2 5342 && (type == 0 5343 || SCALAR_FLOAT_TYPE_P (type) 5344 || VECTOR_FLOAT_TYPE_P (type)) 5345 && (GET_MODE_CLASS (mode) == MODE_FLOAT 5346 || mode == V2SFmode) 5347 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); 5348 break; 5349 5350 case ABI_N32: 5351 case ABI_64: 5352 /* Scalar, complex and vector floating-point types are passed in 5353 floating-point registers, as long as this is a named rather 5354 than a variable argument. */ 5355 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode); 5356 info->fpr_p = (named 5357 && (type == 0 || FLOAT_TYPE_P (type)) 5358 && (GET_MODE_CLASS (mode) == MODE_FLOAT 5359 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5360 || mode == V2SFmode) 5361 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); 5362 5363 /* ??? According to the ABI documentation, the real and imaginary 5364 parts of complex floats should be passed in individual registers. 5365 The real and imaginary parts of stack arguments are supposed 5366 to be contiguous and there should be an extra word of padding 5367 at the end. 5368 5369 This has two problems. First, it makes it impossible to use a 5370 single "void *" va_list type, since register and stack arguments 5371 are passed differently. (At the time of writing, MIPSpro cannot 5372 handle complex float varargs correctly.) Second, it's unclear 5373 what should happen when there is only one register free. 5374 5375 For now, we assume that named complex floats should go into FPRs 5376 if there are two FPRs free, otherwise they should be passed in the 5377 same way as a struct containing two floats. */ 5378 if (info->fpr_p 5379 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5380 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) 5381 { 5382 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) 5383 info->fpr_p = false; 5384 else 5385 num_words = 2; 5386 } 5387 break; 5388 5389 default: 5390 gcc_unreachable (); 5391 } 5392 5393 /* See whether the argument has doubleword alignment. */ 5394 doubleword_aligned_p = (mips_function_arg_boundary (mode, type) 5395 > BITS_PER_WORD); 5396 5397 /* Set REG_OFFSET to the register count we're interested in. 5398 The EABI allocates the floating-point registers separately, 5399 but the other ABIs allocate them like integer registers. */ 5400 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p 5401 ? cum->num_fprs 5402 : cum->num_gprs); 5403 5404 /* Advance to an even register if the argument is doubleword-aligned. */ 5405 if (doubleword_aligned_p) 5406 info->reg_offset += info->reg_offset & 1; 5407 5408 /* Work out the offset of a stack argument. */ 5409 info->stack_offset = cum->stack_words; 5410 if (doubleword_aligned_p) 5411 info->stack_offset += info->stack_offset & 1; 5412 5413 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; 5414 5415 /* Partition the argument between registers and stack. */ 5416 info->reg_words = MIN (num_words, max_regs); 5417 info->stack_words = num_words - info->reg_words; 5418} 5419 5420/* INFO describes a register argument that has the normal format for the 5421 argument's mode. Return the register it uses, assuming that FPRs are 5422 available if HARD_FLOAT_P. */ 5423 5424static unsigned int 5425mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p) 5426{ 5427 if (!info->fpr_p || !hard_float_p) 5428 return GP_ARG_FIRST + info->reg_offset; 5429 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0) 5430 /* In o32, the second argument is always passed in $f14 5431 for TARGET_DOUBLE_FLOAT, regardless of whether the 5432 first argument was a word or doubleword. */ 5433 return FP_ARG_FIRST + 2; 5434 else 5435 return FP_ARG_FIRST + info->reg_offset; 5436} 5437 5438/* Implement TARGET_STRICT_ARGUMENT_NAMING. */ 5439 5440static bool 5441mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) 5442{ 5443 return !TARGET_OLDABI; 5444} 5445 5446/* Implement TARGET_FUNCTION_ARG. */ 5447 5448static rtx 5449mips_function_arg (cumulative_args_t cum_v, machine_mode mode, 5450 const_tree type, bool named) 5451{ 5452 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 5453 struct mips_arg_info info; 5454 5455 /* We will be called with a mode of VOIDmode after the last argument 5456 has been seen. Whatever we return will be passed to the call expander. 5457 If we need a MIPS16 fp_code, return a REG with the code stored as 5458 the mode. */ 5459 if (mode == VOIDmode) 5460 { 5461 if (TARGET_MIPS16 && cum->fp_code != 0) 5462 return gen_rtx_REG ((machine_mode) cum->fp_code, 0); 5463 else 5464 return NULL; 5465 } 5466 5467 mips_get_arg_info (&info, cum, mode, type, named); 5468 5469 /* Return straight away if the whole argument is passed on the stack. */ 5470 if (info.reg_offset == MAX_ARGS_IN_REGISTERS) 5471 return NULL; 5472 5473 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure 5474 contains a double in its entirety, then that 64-bit chunk is passed 5475 in a floating-point register. */ 5476 if (TARGET_NEWABI 5477 && TARGET_HARD_FLOAT 5478 && named 5479 && type != 0 5480 && TREE_CODE (type) == RECORD_TYPE 5481 && TYPE_SIZE_UNIT (type) 5482 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type))) 5483 { 5484 tree field; 5485 5486 /* First check to see if there is any such field. */ 5487 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) 5488 if (TREE_CODE (field) == FIELD_DECL 5489 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) 5490 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD 5491 && tree_fits_shwi_p (bit_position (field)) 5492 && int_bit_position (field) % BITS_PER_WORD == 0) 5493 break; 5494 5495 if (field != 0) 5496 { 5497 /* Now handle the special case by returning a PARALLEL 5498 indicating where each 64-bit chunk goes. INFO.REG_WORDS 5499 chunks are passed in registers. */ 5500 unsigned int i; 5501 HOST_WIDE_INT bitpos; 5502 rtx ret; 5503 5504 /* assign_parms checks the mode of ENTRY_PARM, so we must 5505 use the actual mode here. */ 5506 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); 5507 5508 bitpos = 0; 5509 field = TYPE_FIELDS (type); 5510 for (i = 0; i < info.reg_words; i++) 5511 { 5512 rtx reg; 5513 5514 for (; field; field = DECL_CHAIN (field)) 5515 if (TREE_CODE (field) == FIELD_DECL 5516 && int_bit_position (field) >= bitpos) 5517 break; 5518 5519 if (field 5520 && int_bit_position (field) == bitpos 5521 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) 5522 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) 5523 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); 5524 else 5525 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); 5526 5527 XVECEXP (ret, 0, i) 5528 = gen_rtx_EXPR_LIST (VOIDmode, reg, 5529 GEN_INT (bitpos / BITS_PER_UNIT)); 5530 5531 bitpos += BITS_PER_WORD; 5532 } 5533 return ret; 5534 } 5535 } 5536 5537 /* Handle the n32/n64 conventions for passing complex floating-point 5538 arguments in FPR pairs. The real part goes in the lower register 5539 and the imaginary part goes in the upper register. */ 5540 if (TARGET_NEWABI 5541 && info.fpr_p 5542 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5543 { 5544 rtx real, imag; 5545 machine_mode inner; 5546 unsigned int regno; 5547 5548 inner = GET_MODE_INNER (mode); 5549 regno = FP_ARG_FIRST + info.reg_offset; 5550 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) 5551 { 5552 /* Real part in registers, imaginary part on stack. */ 5553 gcc_assert (info.stack_words == info.reg_words); 5554 return gen_rtx_REG (inner, regno); 5555 } 5556 else 5557 { 5558 gcc_assert (info.stack_words == 0); 5559 real = gen_rtx_EXPR_LIST (VOIDmode, 5560 gen_rtx_REG (inner, regno), 5561 const0_rtx); 5562 imag = gen_rtx_EXPR_LIST (VOIDmode, 5563 gen_rtx_REG (inner, 5564 regno + info.reg_words / 2), 5565 GEN_INT (GET_MODE_SIZE (inner))); 5566 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); 5567 } 5568 } 5569 5570 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); 5571} 5572 5573/* Implement TARGET_FUNCTION_ARG_ADVANCE. */ 5574 5575static void 5576mips_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 5577 const_tree type, bool named) 5578{ 5579 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 5580 struct mips_arg_info info; 5581 5582 mips_get_arg_info (&info, cum, mode, type, named); 5583 5584 if (!info.fpr_p) 5585 cum->gp_reg_found = true; 5586 5587 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for 5588 an explanation of what this code does. It assumes that we're using 5589 either the o32 or the o64 ABI, both of which pass at most 2 arguments 5590 in FPRs. */ 5591 if (cum->arg_number < 2 && info.fpr_p) 5592 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2); 5593 5594 /* Advance the register count. This has the effect of setting 5595 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned 5596 argument required us to skip the final GPR and pass the whole 5597 argument on the stack. */ 5598 if (mips_abi != ABI_EABI || !info.fpr_p) 5599 cum->num_gprs = info.reg_offset + info.reg_words; 5600 else if (info.reg_words > 0) 5601 cum->num_fprs += MAX_FPRS_PER_FMT; 5602 5603 /* Advance the stack word count. */ 5604 if (info.stack_words > 0) 5605 cum->stack_words = info.stack_offset + info.stack_words; 5606 5607 cum->arg_number++; 5608} 5609 5610/* Implement TARGET_ARG_PARTIAL_BYTES. */ 5611 5612static int 5613mips_arg_partial_bytes (cumulative_args_t cum, 5614 machine_mode mode, tree type, bool named) 5615{ 5616 struct mips_arg_info info; 5617 5618 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named); 5619 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; 5620} 5621 5622/* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at 5623 least PARM_BOUNDARY bits of alignment, but will be given anything up 5624 to STACK_BOUNDARY bits if the type requires it. */ 5625 5626static unsigned int 5627mips_function_arg_boundary (machine_mode mode, const_tree type) 5628{ 5629 unsigned int alignment; 5630 5631 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 5632 if (alignment < PARM_BOUNDARY) 5633 alignment = PARM_BOUNDARY; 5634 if (alignment > STACK_BOUNDARY) 5635 alignment = STACK_BOUNDARY; 5636 return alignment; 5637} 5638 5639/* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */ 5640 5641static machine_mode 5642mips_get_reg_raw_mode (int regno) 5643{ 5644 if (TARGET_FLOATXX && FP_REG_P (regno)) 5645 return DFmode; 5646 return default_get_reg_raw_mode (regno); 5647} 5648 5649/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return 5650 upward rather than downward. In other words, return true if the 5651 first byte of the stack slot has useful data, false if the last 5652 byte does. */ 5653 5654bool 5655mips_pad_arg_upward (machine_mode mode, const_tree type) 5656{ 5657 /* On little-endian targets, the first byte of every stack argument 5658 is passed in the first byte of the stack slot. */ 5659 if (!BYTES_BIG_ENDIAN) 5660 return true; 5661 5662 /* Otherwise, integral types are padded downward: the last byte of a 5663 stack argument is passed in the last byte of the stack slot. */ 5664 if (type != 0 5665 ? (INTEGRAL_TYPE_P (type) 5666 || POINTER_TYPE_P (type) 5667 || FIXED_POINT_TYPE_P (type)) 5668 : (SCALAR_INT_MODE_P (mode) 5669 || ALL_SCALAR_FIXED_POINT_MODE_P (mode))) 5670 return false; 5671 5672 /* Big-endian o64 pads floating-point arguments downward. */ 5673 if (mips_abi == ABI_O64) 5674 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) 5675 return false; 5676 5677 /* Other types are padded upward for o32, o64, n32 and n64. */ 5678 if (mips_abi != ABI_EABI) 5679 return true; 5680 5681 /* Arguments smaller than a stack slot are padded downward. */ 5682 if (mode != BLKmode) 5683 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY; 5684 else 5685 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT); 5686} 5687 5688/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN 5689 if the least significant byte of the register has useful data. Return 5690 the opposite if the most significant byte does. */ 5691 5692bool 5693mips_pad_reg_upward (machine_mode mode, tree type) 5694{ 5695 /* No shifting is required for floating-point arguments. */ 5696 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) 5697 return !BYTES_BIG_ENDIAN; 5698 5699 /* Otherwise, apply the same padding to register arguments as we do 5700 to stack arguments. */ 5701 return mips_pad_arg_upward (mode, type); 5702} 5703 5704/* Return nonzero when an argument must be passed by reference. */ 5705 5706static bool 5707mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, 5708 machine_mode mode, const_tree type, 5709 bool named ATTRIBUTE_UNUSED) 5710{ 5711 if (mips_abi == ABI_EABI) 5712 { 5713 int size; 5714 5715 /* ??? How should SCmode be handled? */ 5716 if (mode == DImode || mode == DFmode 5717 || mode == DQmode || mode == UDQmode 5718 || mode == DAmode || mode == UDAmode) 5719 return 0; 5720 5721 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 5722 return size == -1 || size > UNITS_PER_WORD; 5723 } 5724 else 5725 { 5726 /* If we have a variable-sized parameter, we have no choice. */ 5727 return targetm.calls.must_pass_in_stack (mode, type); 5728 } 5729} 5730 5731/* Implement TARGET_CALLEE_COPIES. */ 5732 5733static bool 5734mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED, 5735 machine_mode mode ATTRIBUTE_UNUSED, 5736 const_tree type ATTRIBUTE_UNUSED, bool named) 5737{ 5738 return mips_abi == ABI_EABI && named; 5739} 5740 5741/* See whether VALTYPE is a record whose fields should be returned in 5742 floating-point registers. If so, return the number of fields and 5743 list them in FIELDS (which should have two elements). Return 0 5744 otherwise. 5745 5746 For n32 & n64, a structure with one or two fields is returned in 5747 floating-point registers as long as every field has a floating-point 5748 type. */ 5749 5750static int 5751mips_fpr_return_fields (const_tree valtype, tree *fields) 5752{ 5753 tree field; 5754 int i; 5755 5756 if (!TARGET_NEWABI) 5757 return 0; 5758 5759 if (TREE_CODE (valtype) != RECORD_TYPE) 5760 return 0; 5761 5762 i = 0; 5763 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field)) 5764 { 5765 if (TREE_CODE (field) != FIELD_DECL) 5766 continue; 5767 5768 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) 5769 return 0; 5770 5771 if (i == 2) 5772 return 0; 5773 5774 fields[i++] = field; 5775 } 5776 return i; 5777} 5778 5779/* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return 5780 a value in the most significant part of $2/$3 if: 5781 5782 - the target is big-endian; 5783 5784 - the value has a structure or union type (we generalize this to 5785 cover aggregates from other languages too); and 5786 5787 - the structure is not returned in floating-point registers. */ 5788 5789static bool 5790mips_return_in_msb (const_tree valtype) 5791{ 5792 tree fields[2]; 5793 5794 return (TARGET_NEWABI 5795 && TARGET_BIG_ENDIAN 5796 && AGGREGATE_TYPE_P (valtype) 5797 && mips_fpr_return_fields (valtype, fields) == 0); 5798} 5799 5800/* Return true if the function return value MODE will get returned in a 5801 floating-point register. */ 5802 5803static bool 5804mips_return_mode_in_fpr_p (machine_mode mode) 5805{ 5806 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT || mode != V2SFmode); 5807 return ((GET_MODE_CLASS (mode) == MODE_FLOAT 5808 || mode == V2SFmode 5809 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5810 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); 5811} 5812 5813/* Return the representation of an FPR return register when the 5814 value being returned in FP_RETURN has mode VALUE_MODE and the 5815 return type itself has mode TYPE_MODE. On NewABI targets, 5816 the two modes may be different for structures like: 5817 5818 struct __attribute__((packed)) foo { float f; } 5819 5820 where we return the SFmode value of "f" in FP_RETURN, but where 5821 the structure itself has mode BLKmode. */ 5822 5823static rtx 5824mips_return_fpr_single (machine_mode type_mode, 5825 machine_mode value_mode) 5826{ 5827 rtx x; 5828 5829 x = gen_rtx_REG (value_mode, FP_RETURN); 5830 if (type_mode != value_mode) 5831 { 5832 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); 5833 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); 5834 } 5835 return x; 5836} 5837 5838/* Return a composite value in a pair of floating-point registers. 5839 MODE1 and OFFSET1 are the mode and byte offset for the first value, 5840 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the 5841 complete value. 5842 5843 For n32 & n64, $f0 always holds the first value and $f2 the second. 5844 Otherwise the values are packed together as closely as possible. */ 5845 5846static rtx 5847mips_return_fpr_pair (machine_mode mode, 5848 machine_mode mode1, HOST_WIDE_INT offset1, 5849 machine_mode mode2, HOST_WIDE_INT offset2) 5850{ 5851 int inc; 5852 5853 inc = (TARGET_NEWABI || mips_abi == ABI_32 ? 2 : MAX_FPRS_PER_FMT); 5854 return gen_rtx_PARALLEL 5855 (mode, 5856 gen_rtvec (2, 5857 gen_rtx_EXPR_LIST (VOIDmode, 5858 gen_rtx_REG (mode1, FP_RETURN), 5859 GEN_INT (offset1)), 5860 gen_rtx_EXPR_LIST (VOIDmode, 5861 gen_rtx_REG (mode2, FP_RETURN + inc), 5862 GEN_INT (offset2)))); 5863 5864} 5865 5866/* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE. 5867 For normal calls, VALTYPE is the return type and MODE is VOIDmode. 5868 For libcalls, VALTYPE is null and MODE is the mode of the return value. */ 5869 5870static rtx 5871mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type, 5872 machine_mode mode) 5873{ 5874 if (valtype) 5875 { 5876 tree fields[2]; 5877 int unsigned_p; 5878 const_tree func; 5879 5880 if (fn_decl_or_type && DECL_P (fn_decl_or_type)) 5881 func = fn_decl_or_type; 5882 else 5883 func = NULL; 5884 5885 mode = TYPE_MODE (valtype); 5886 unsigned_p = TYPE_UNSIGNED (valtype); 5887 5888 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, 5889 return values, promote the mode here too. */ 5890 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); 5891 5892 /* Handle structures whose fields are returned in $f0/$f2. */ 5893 switch (mips_fpr_return_fields (valtype, fields)) 5894 { 5895 case 1: 5896 return mips_return_fpr_single (mode, 5897 TYPE_MODE (TREE_TYPE (fields[0]))); 5898 5899 case 2: 5900 return mips_return_fpr_pair (mode, 5901 TYPE_MODE (TREE_TYPE (fields[0])), 5902 int_byte_position (fields[0]), 5903 TYPE_MODE (TREE_TYPE (fields[1])), 5904 int_byte_position (fields[1])); 5905 } 5906 5907 /* If a value is passed in the most significant part of a register, see 5908 whether we have to round the mode up to a whole number of words. */ 5909 if (mips_return_in_msb (valtype)) 5910 { 5911 HOST_WIDE_INT size = int_size_in_bytes (valtype); 5912 if (size % UNITS_PER_WORD != 0) 5913 { 5914 size += UNITS_PER_WORD - size % UNITS_PER_WORD; 5915 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 5916 } 5917 } 5918 5919 /* For EABI, the class of return register depends entirely on MODE. 5920 For example, "struct { some_type x; }" and "union { some_type x; }" 5921 are returned in the same way as a bare "some_type" would be. 5922 Other ABIs only use FPRs for scalar, complex or vector types. */ 5923 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype)) 5924 return gen_rtx_REG (mode, GP_RETURN); 5925 } 5926 5927 if (!TARGET_MIPS16) 5928 { 5929 /* Handle long doubles for n32 & n64. */ 5930 if (mode == TFmode) 5931 return mips_return_fpr_pair (mode, 5932 DImode, 0, 5933 DImode, GET_MODE_SIZE (mode) / 2); 5934 5935 if (mips_return_mode_in_fpr_p (mode)) 5936 { 5937 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5938 return mips_return_fpr_pair (mode, 5939 GET_MODE_INNER (mode), 0, 5940 GET_MODE_INNER (mode), 5941 GET_MODE_SIZE (mode) / 2); 5942 else 5943 return gen_rtx_REG (mode, FP_RETURN); 5944 } 5945 } 5946 5947 return gen_rtx_REG (mode, GP_RETURN); 5948} 5949 5950/* Implement TARGET_FUNCTION_VALUE. */ 5951 5952static rtx 5953mips_function_value (const_tree valtype, const_tree fn_decl_or_type, 5954 bool outgoing ATTRIBUTE_UNUSED) 5955{ 5956 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode); 5957} 5958 5959/* Implement TARGET_LIBCALL_VALUE. */ 5960 5961static rtx 5962mips_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) 5963{ 5964 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode); 5965} 5966 5967/* Implement TARGET_FUNCTION_VALUE_REGNO_P. 5968 5969 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */ 5970 5971static bool 5972mips_function_value_regno_p (const unsigned int regno) 5973{ 5974 /* Most types only require one GPR or one FPR for return values but for 5975 hard-float two FPRs can be used for _Complex types (for all ABIs) 5976 and long doubles (for n64). */ 5977 if (regno == GP_RETURN 5978 || regno == FP_RETURN 5979 || (FP_RETURN != GP_RETURN 5980 && regno == FP_RETURN + 2)) 5981 return true; 5982 5983 /* For o32 FP32, _Complex double will be returned in four 32-bit registers. 5984 This does not apply to o32 FPXX as floating-point function argument and 5985 return registers are described as 64-bit even though floating-point 5986 registers are primarily described as 32-bit internally. 5987 See: mips_get_reg_raw_mode. */ 5988 if ((mips_abi == ABI_32 && TARGET_FLOAT32) 5989 && FP_RETURN != GP_RETURN 5990 && (regno == FP_RETURN + 1 5991 || regno == FP_RETURN + 3)) 5992 return true; 5993 5994 return false; 5995} 5996 5997/* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs, 5998 all BLKmode objects are returned in memory. Under the n32, n64 5999 and embedded ABIs, small structures are returned in a register. 6000 Objects with varying size must still be returned in memory, of 6001 course. */ 6002 6003static bool 6004mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) 6005{ 6006 return (TARGET_OLDABI 6007 ? TYPE_MODE (type) == BLKmode 6008 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD)); 6009} 6010 6011/* Implement TARGET_SETUP_INCOMING_VARARGS. */ 6012 6013static void 6014mips_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode, 6015 tree type, int *pretend_size ATTRIBUTE_UNUSED, 6016 int no_rtl) 6017{ 6018 CUMULATIVE_ARGS local_cum; 6019 int gp_saved, fp_saved; 6020 6021 /* The caller has advanced CUM up to, but not beyond, the last named 6022 argument. Advance a local copy of CUM past the last "real" named 6023 argument, to find out how many registers are left over. */ 6024 local_cum = *get_cumulative_args (cum); 6025 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, 6026 true); 6027 6028 /* Found out how many registers we need to save. */ 6029 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 6030 fp_saved = (EABI_FLOAT_VARARGS_P 6031 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs 6032 : 0); 6033 6034 if (!no_rtl) 6035 { 6036 if (gp_saved > 0) 6037 { 6038 rtx ptr, mem; 6039 6040 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, 6041 REG_PARM_STACK_SPACE (cfun->decl) 6042 - gp_saved * UNITS_PER_WORD); 6043 mem = gen_frame_mem (BLKmode, ptr); 6044 set_mem_alias_set (mem, get_varargs_alias_set ()); 6045 6046 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, 6047 mem, gp_saved); 6048 } 6049 if (fp_saved > 0) 6050 { 6051 /* We can't use move_block_from_reg, because it will use 6052 the wrong mode. */ 6053 machine_mode mode; 6054 int off, i; 6055 6056 /* Set OFF to the offset from virtual_incoming_args_rtx of 6057 the first float register. The FP save area lies below 6058 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */ 6059 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE; 6060 off -= fp_saved * UNITS_PER_FPREG; 6061 6062 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; 6063 6064 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; 6065 i += MAX_FPRS_PER_FMT) 6066 { 6067 rtx ptr, mem; 6068 6069 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off); 6070 mem = gen_frame_mem (mode, ptr); 6071 set_mem_alias_set (mem, get_varargs_alias_set ()); 6072 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i)); 6073 off += UNITS_PER_HWFPVALUE; 6074 } 6075 } 6076 } 6077 if (REG_PARM_STACK_SPACE (cfun->decl) == 0) 6078 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD 6079 + fp_saved * UNITS_PER_FPREG); 6080} 6081 6082/* Implement TARGET_BUILTIN_VA_LIST. */ 6083 6084static tree 6085mips_build_builtin_va_list (void) 6086{ 6087 if (EABI_FLOAT_VARARGS_P) 6088 { 6089 /* We keep 3 pointers, and two offsets. 6090 6091 Two pointers are to the overflow area, which starts at the CFA. 6092 One of these is constant, for addressing into the GPR save area 6093 below it. The other is advanced up the stack through the 6094 overflow region. 6095 6096 The third pointer is to the bottom of the GPR save area. 6097 Since the FPR save area is just below it, we can address 6098 FPR slots off this pointer. 6099 6100 We also keep two one-byte offsets, which are to be subtracted 6101 from the constant pointers to yield addresses in the GPR and 6102 FPR save areas. These are downcounted as float or non-float 6103 arguments are used, and when they get to zero, the argument 6104 must be obtained from the overflow region. */ 6105 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record; 6106 tree array, index; 6107 6108 record = lang_hooks.types.make_type (RECORD_TYPE); 6109 6110 f_ovfl = build_decl (BUILTINS_LOCATION, 6111 FIELD_DECL, get_identifier ("__overflow_argptr"), 6112 ptr_type_node); 6113 f_gtop = build_decl (BUILTINS_LOCATION, 6114 FIELD_DECL, get_identifier ("__gpr_top"), 6115 ptr_type_node); 6116 f_ftop = build_decl (BUILTINS_LOCATION, 6117 FIELD_DECL, get_identifier ("__fpr_top"), 6118 ptr_type_node); 6119 f_goff = build_decl (BUILTINS_LOCATION, 6120 FIELD_DECL, get_identifier ("__gpr_offset"), 6121 unsigned_char_type_node); 6122 f_foff = build_decl (BUILTINS_LOCATION, 6123 FIELD_DECL, get_identifier ("__fpr_offset"), 6124 unsigned_char_type_node); 6125 /* Explicitly pad to the size of a pointer, so that -Wpadded won't 6126 warn on every user file. */ 6127 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1); 6128 array = build_array_type (unsigned_char_type_node, 6129 build_index_type (index)); 6130 f_res = build_decl (BUILTINS_LOCATION, 6131 FIELD_DECL, get_identifier ("__reserved"), array); 6132 6133 DECL_FIELD_CONTEXT (f_ovfl) = record; 6134 DECL_FIELD_CONTEXT (f_gtop) = record; 6135 DECL_FIELD_CONTEXT (f_ftop) = record; 6136 DECL_FIELD_CONTEXT (f_goff) = record; 6137 DECL_FIELD_CONTEXT (f_foff) = record; 6138 DECL_FIELD_CONTEXT (f_res) = record; 6139 6140 TYPE_FIELDS (record) = f_ovfl; 6141 DECL_CHAIN (f_ovfl) = f_gtop; 6142 DECL_CHAIN (f_gtop) = f_ftop; 6143 DECL_CHAIN (f_ftop) = f_goff; 6144 DECL_CHAIN (f_goff) = f_foff; 6145 DECL_CHAIN (f_foff) = f_res; 6146 6147 layout_type (record); 6148 return record; 6149 } 6150 else 6151 /* Otherwise, we use 'void *'. */ 6152 return ptr_type_node; 6153} 6154 6155/* Implement TARGET_EXPAND_BUILTIN_VA_START. */ 6156 6157static void 6158mips_va_start (tree valist, rtx nextarg) 6159{ 6160 if (EABI_FLOAT_VARARGS_P) 6161 { 6162 const CUMULATIVE_ARGS *cum; 6163 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; 6164 tree ovfl, gtop, ftop, goff, foff; 6165 tree t; 6166 int gpr_save_area_size; 6167 int fpr_save_area_size; 6168 int fpr_offset; 6169 6170 cum = &crtl->args.info; 6171 gpr_save_area_size 6172 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD; 6173 fpr_save_area_size 6174 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG; 6175 6176 f_ovfl = TYPE_FIELDS (va_list_type_node); 6177 f_gtop = DECL_CHAIN (f_ovfl); 6178 f_ftop = DECL_CHAIN (f_gtop); 6179 f_goff = DECL_CHAIN (f_ftop); 6180 f_foff = DECL_CHAIN (f_goff); 6181 6182 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, 6183 NULL_TREE); 6184 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, 6185 NULL_TREE); 6186 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, 6187 NULL_TREE); 6188 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, 6189 NULL_TREE); 6190 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, 6191 NULL_TREE); 6192 6193 /* Emit code to initialize OVFL, which points to the next varargs 6194 stack argument. CUM->STACK_WORDS gives the number of stack 6195 words used by named arguments. */ 6196 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); 6197 if (cum->stack_words > 0) 6198 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD); 6199 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); 6200 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 6201 6202 /* Emit code to initialize GTOP, the top of the GPR save area. */ 6203 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); 6204 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); 6205 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 6206 6207 /* Emit code to initialize FTOP, the top of the FPR save area. 6208 This address is gpr_save_area_bytes below GTOP, rounded 6209 down to the next fp-aligned boundary. */ 6210 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); 6211 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1; 6212 fpr_offset &= -UNITS_PER_FPVALUE; 6213 if (fpr_offset) 6214 t = fold_build_pointer_plus_hwi (t, -fpr_offset); 6215 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t); 6216 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 6217 6218 /* Emit code to initialize GOFF, the offset from GTOP of the 6219 next GPR argument. */ 6220 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff, 6221 build_int_cst (TREE_TYPE (goff), gpr_save_area_size)); 6222 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 6223 6224 /* Likewise emit code to initialize FOFF, the offset from FTOP 6225 of the next FPR argument. */ 6226 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff, 6227 build_int_cst (TREE_TYPE (foff), fpr_save_area_size)); 6228 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 6229 } 6230 else 6231 { 6232 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size); 6233 std_expand_builtin_va_start (valist, nextarg); 6234 } 6235} 6236 6237/* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized 6238 types as well. */ 6239 6240static tree 6241mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, 6242 gimple_seq *post_p) 6243{ 6244 tree addr, t, type_size, rounded_size, valist_tmp; 6245 unsigned HOST_WIDE_INT align, boundary; 6246 bool indirect; 6247 6248 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); 6249 if (indirect) 6250 type = build_pointer_type (type); 6251 6252 align = PARM_BOUNDARY / BITS_PER_UNIT; 6253 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type); 6254 6255 /* When we align parameter on stack for caller, if the parameter 6256 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be 6257 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee 6258 here with caller. */ 6259 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT) 6260 boundary = MAX_SUPPORTED_STACK_ALIGNMENT; 6261 6262 boundary /= BITS_PER_UNIT; 6263 6264 /* Hoist the valist value into a temporary for the moment. */ 6265 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL); 6266 6267 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually 6268 requires greater alignment, we must perform dynamic alignment. */ 6269 if (boundary > align) 6270 { 6271 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, 6272 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1)); 6273 gimplify_and_add (t, pre_p); 6274 6275 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, 6276 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist), 6277 valist_tmp, 6278 build_int_cst (TREE_TYPE (valist), -boundary))); 6279 gimplify_and_add (t, pre_p); 6280 } 6281 else 6282 boundary = align; 6283 6284 /* If the actual alignment is less than the alignment of the type, 6285 adjust the type accordingly so that we don't assume strict alignment 6286 when dereferencing the pointer. */ 6287 boundary *= BITS_PER_UNIT; 6288 if (boundary < TYPE_ALIGN (type)) 6289 { 6290 type = build_variant_type_copy (type); 6291 TYPE_ALIGN (type) = boundary; 6292 } 6293 6294 /* Compute the rounded size of the type. */ 6295 type_size = size_in_bytes (type); 6296 rounded_size = round_up (type_size, align); 6297 6298 /* Reduce rounded_size so it's sharable with the postqueue. */ 6299 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue); 6300 6301 /* Get AP. */ 6302 addr = valist_tmp; 6303 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size)) 6304 { 6305 /* Small args are padded downward. */ 6306 t = fold_build2_loc (input_location, GT_EXPR, sizetype, 6307 rounded_size, size_int (align)); 6308 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node, 6309 size_binop (MINUS_EXPR, rounded_size, type_size)); 6310 addr = fold_build_pointer_plus (addr, t); 6311 } 6312 6313 /* Compute new value for AP. */ 6314 t = fold_build_pointer_plus (valist_tmp, rounded_size); 6315 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t); 6316 gimplify_and_add (t, pre_p); 6317 6318 addr = fold_convert (build_pointer_type (type), addr); 6319 6320 if (indirect) 6321 addr = build_va_arg_indirect_ref (addr); 6322 6323 return build_va_arg_indirect_ref (addr); 6324} 6325 6326/* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ 6327 6328static tree 6329mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, 6330 gimple_seq *post_p) 6331{ 6332 tree addr; 6333 bool indirect_p; 6334 6335 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0); 6336 if (indirect_p) 6337 type = build_pointer_type (type); 6338 6339 if (!EABI_FLOAT_VARARGS_P) 6340 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p); 6341 else 6342 { 6343 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; 6344 tree ovfl, top, off, align; 6345 HOST_WIDE_INT size, rsize, osize; 6346 tree t, u; 6347 6348 f_ovfl = TYPE_FIELDS (va_list_type_node); 6349 f_gtop = DECL_CHAIN (f_ovfl); 6350 f_ftop = DECL_CHAIN (f_gtop); 6351 f_goff = DECL_CHAIN (f_ftop); 6352 f_foff = DECL_CHAIN (f_goff); 6353 6354 /* Let: 6355 6356 TOP be the top of the GPR or FPR save area; 6357 OFF be the offset from TOP of the next register; 6358 ADDR_RTX be the address of the argument; 6359 SIZE be the number of bytes in the argument type; 6360 RSIZE be the number of bytes used to store the argument 6361 when it's in the register save area; and 6362 OSIZE be the number of bytes used to store it when it's 6363 in the stack overflow area. 6364 6365 The code we want is: 6366 6367 1: off &= -rsize; // round down 6368 2: if (off != 0) 6369 3: { 6370 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0); 6371 5: off -= rsize; 6372 6: } 6373 7: else 6374 8: { 6375 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize; 6376 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0); 6377 11: ovfl += osize; 6378 14: } 6379 6380 [1] and [9] can sometimes be optimized away. */ 6381 6382 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, 6383 NULL_TREE); 6384 size = int_size_in_bytes (type); 6385 6386 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT 6387 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE) 6388 { 6389 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), 6390 unshare_expr (valist), f_ftop, NULL_TREE); 6391 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), 6392 unshare_expr (valist), f_foff, NULL_TREE); 6393 6394 /* When va_start saves FPR arguments to the stack, each slot 6395 takes up UNITS_PER_HWFPVALUE bytes, regardless of the 6396 argument's precision. */ 6397 rsize = UNITS_PER_HWFPVALUE; 6398 6399 /* Overflow arguments are padded to UNITS_PER_WORD bytes 6400 (= PARM_BOUNDARY bits). This can be different from RSIZE 6401 in two cases: 6402 6403 (1) On 32-bit targets when TYPE is a structure such as: 6404 6405 struct s { float f; }; 6406 6407 Such structures are passed in paired FPRs, so RSIZE 6408 will be 8 bytes. However, the structure only takes 6409 up 4 bytes of memory, so OSIZE will only be 4. 6410 6411 (2) In combinations such as -mgp64 -msingle-float 6412 -fshort-double. Doubles passed in registers will then take 6413 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the 6414 stack take up UNITS_PER_WORD bytes. */ 6415 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD); 6416 } 6417 else 6418 { 6419 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), 6420 unshare_expr (valist), f_gtop, NULL_TREE); 6421 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), 6422 unshare_expr (valist), f_goff, NULL_TREE); 6423 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 6424 if (rsize > UNITS_PER_WORD) 6425 { 6426 /* [1] Emit code for: off &= -rsize. */ 6427 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off), 6428 build_int_cst (TREE_TYPE (off), -rsize)); 6429 gimplify_assign (unshare_expr (off), t, pre_p); 6430 } 6431 osize = rsize; 6432 } 6433 6434 /* [2] Emit code to branch if off == 0. */ 6435 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off), 6436 build_int_cst (TREE_TYPE (off), 0)); 6437 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); 6438 6439 /* [5] Emit code for: off -= rsize. We do this as a form of 6440 post-decrement not available to C. */ 6441 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize)); 6442 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t); 6443 6444 /* [4] Emit code for: 6445 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */ 6446 t = fold_convert (sizetype, t); 6447 t = fold_build1 (NEGATE_EXPR, sizetype, t); 6448 t = fold_build_pointer_plus (top, t); 6449 if (BYTES_BIG_ENDIAN && rsize > size) 6450 t = fold_build_pointer_plus_hwi (t, rsize - size); 6451 COND_EXPR_THEN (addr) = t; 6452 6453 if (osize > UNITS_PER_WORD) 6454 { 6455 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */ 6456 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1); 6457 u = build_int_cst (TREE_TYPE (t), -osize); 6458 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u); 6459 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), 6460 unshare_expr (ovfl), t); 6461 } 6462 else 6463 align = NULL; 6464 6465 /* [10, 11] Emit code for: 6466 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0) 6467 ovfl += osize. */ 6468 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize)); 6469 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u); 6470 if (BYTES_BIG_ENDIAN && osize > size) 6471 t = fold_build_pointer_plus_hwi (t, osize - size); 6472 6473 /* String [9] and [10, 11] together. */ 6474 if (align) 6475 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t); 6476 COND_EXPR_ELSE (addr) = t; 6477 6478 addr = fold_convert (build_pointer_type (type), addr); 6479 addr = build_va_arg_indirect_ref (addr); 6480 } 6481 6482 if (indirect_p) 6483 addr = build_va_arg_indirect_ref (addr); 6484 6485 return addr; 6486} 6487 6488/* Declare a unique, locally-binding function called NAME, then start 6489 its definition. */ 6490 6491static void 6492mips_start_unique_function (const char *name) 6493{ 6494 tree decl; 6495 6496 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, 6497 get_identifier (name), 6498 build_function_type_list (void_type_node, NULL_TREE)); 6499 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL, 6500 NULL_TREE, void_type_node); 6501 TREE_PUBLIC (decl) = 1; 6502 TREE_STATIC (decl) = 1; 6503 6504 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl)); 6505 6506 targetm.asm_out.unique_section (decl, 0); 6507 switch_to_section (get_named_section (decl, NULL, 0)); 6508 6509 targetm.asm_out.globalize_label (asm_out_file, name); 6510 fputs ("\t.hidden\t", asm_out_file); 6511 assemble_name (asm_out_file, name); 6512 putc ('\n', asm_out_file); 6513} 6514 6515/* Start a definition of function NAME. MIPS16_P indicates whether the 6516 function contains MIPS16 code. */ 6517 6518static void 6519mips_start_function_definition (const char *name, bool mips16_p) 6520{ 6521 if (mips16_p) 6522 fprintf (asm_out_file, "\t.set\tmips16\n"); 6523 else 6524 fprintf (asm_out_file, "\t.set\tnomips16\n"); 6525 6526 if (TARGET_MICROMIPS) 6527 fprintf (asm_out_file, "\t.set\tmicromips\n"); 6528#ifdef HAVE_GAS_MICROMIPS 6529 else 6530 fprintf (asm_out_file, "\t.set\tnomicromips\n"); 6531#endif 6532 6533 if (!flag_inhibit_size_directive) 6534 { 6535 fputs ("\t.ent\t", asm_out_file); 6536 assemble_name (asm_out_file, name); 6537 fputs ("\n", asm_out_file); 6538 } 6539 6540 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function"); 6541 6542 /* Start the definition proper. */ 6543 assemble_name (asm_out_file, name); 6544 fputs (":\n", asm_out_file); 6545} 6546 6547/* End a function definition started by mips_start_function_definition. */ 6548 6549static void 6550mips_end_function_definition (const char *name) 6551{ 6552 if (!flag_inhibit_size_directive) 6553 { 6554 fputs ("\t.end\t", asm_out_file); 6555 assemble_name (asm_out_file, name); 6556 fputs ("\n", asm_out_file); 6557 } 6558} 6559 6560/* If *STUB_PTR points to a stub, output a comdat-style definition for it, 6561 then free *STUB_PTR. */ 6562 6563static void 6564mips_finish_stub (mips_one_only_stub **stub_ptr) 6565{ 6566 mips_one_only_stub *stub = *stub_ptr; 6567 if (!stub) 6568 return; 6569 6570 const char *name = stub->get_name (); 6571 mips_start_unique_function (name); 6572 mips_start_function_definition (name, false); 6573 stub->output_body (); 6574 mips_end_function_definition (name); 6575 delete stub; 6576 *stub_ptr = 0; 6577} 6578 6579/* Return true if calls to X can use R_MIPS_CALL* relocations. */ 6580 6581static bool 6582mips_ok_for_lazy_binding_p (rtx x) 6583{ 6584 return (TARGET_USE_GOT 6585 && GET_CODE (x) == SYMBOL_REF 6586 && !SYMBOL_REF_BIND_NOW_P (x) 6587 && !mips_symbol_binds_local_p (x)); 6588} 6589 6590/* Load function address ADDR into register DEST. TYPE is as for 6591 mips_expand_call. Return true if we used an explicit lazy-binding 6592 sequence. */ 6593 6594static bool 6595mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr) 6596{ 6597 /* If we're generating PIC, and this call is to a global function, 6598 try to allow its address to be resolved lazily. This isn't 6599 possible for sibcalls when $gp is call-saved because the value 6600 of $gp on entry to the stub would be our caller's gp, not ours. */ 6601 if (TARGET_EXPLICIT_RELOCS 6602 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP) 6603 && mips_ok_for_lazy_binding_p (addr)) 6604 { 6605 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL); 6606 emit_insn (gen_rtx_SET (VOIDmode, dest, addr)); 6607 return true; 6608 } 6609 else 6610 { 6611 mips_emit_move (dest, addr); 6612 return false; 6613 } 6614} 6615 6616struct local_alias_traits : default_hashmap_traits 6617{ 6618 static hashval_t hash (rtx); 6619 static bool equal_keys (rtx, rtx); 6620}; 6621 6622/* Each locally-defined hard-float MIPS16 function has a local symbol 6623 associated with it. This hash table maps the function symbol (FUNC) 6624 to the local symbol (LOCAL). */ 6625static GTY (()) hash_map<rtx, rtx, local_alias_traits> *mips16_local_aliases; 6626 6627/* Hash table callbacks for mips16_local_aliases. */ 6628 6629hashval_t 6630local_alias_traits::hash (rtx func) 6631{ 6632 return htab_hash_string (XSTR (func, 0)); 6633} 6634 6635bool 6636local_alias_traits::equal_keys (rtx func1, rtx func2) 6637{ 6638 return rtx_equal_p (func1, func2); 6639} 6640 6641/* FUNC is the symbol for a locally-defined hard-float MIPS16 function. 6642 Return a local alias for it, creating a new one if necessary. */ 6643 6644static rtx 6645mips16_local_alias (rtx func) 6646{ 6647 /* Create the hash table if this is the first call. */ 6648 if (mips16_local_aliases == NULL) 6649 mips16_local_aliases 6650 = hash_map<rtx, rtx, local_alias_traits>::create_ggc (37); 6651 6652 /* Look up the function symbol, creating a new entry if need be. */ 6653 bool existed; 6654 rtx *slot = &mips16_local_aliases->get_or_insert (func, &existed); 6655 gcc_assert (slot != NULL); 6656 6657 if (!existed) 6658 { 6659 const char *func_name, *local_name; 6660 rtx local; 6661 6662 /* Create a new SYMBOL_REF for the local symbol. The choice of 6663 __fn_local_* is based on the __fn_stub_* names that we've 6664 traditionally used for the non-MIPS16 stub. */ 6665 func_name = targetm.strip_name_encoding (XSTR (func, 0)); 6666 local_name = ACONCAT (("__fn_local_", func_name, NULL)); 6667 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name)); 6668 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL; 6669 6670 /* Create a new structure to represent the mapping. */ 6671 *slot = local; 6672 } 6673 return *slot; 6674} 6675 6676/* A chained list of functions for which mips16_build_call_stub has already 6677 generated a stub. NAME is the name of the function and FP_RET_P is true 6678 if the function returns a value in floating-point registers. */ 6679struct mips16_stub { 6680 struct mips16_stub *next; 6681 char *name; 6682 bool fp_ret_p; 6683}; 6684static struct mips16_stub *mips16_stubs; 6685 6686/* Return the two-character string that identifies floating-point 6687 return mode MODE in the name of a MIPS16 function stub. */ 6688 6689static const char * 6690mips16_call_stub_mode_suffix (machine_mode mode) 6691{ 6692 if (mode == SFmode) 6693 return "sf"; 6694 else if (mode == DFmode) 6695 return "df"; 6696 else if (mode == SCmode) 6697 return "sc"; 6698 else if (mode == DCmode) 6699 return "dc"; 6700 else if (mode == V2SFmode) 6701 { 6702 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT); 6703 return "df"; 6704 } 6705 else 6706 gcc_unreachable (); 6707} 6708 6709/* Write instructions to move a 32-bit value between general register 6710 GPREG and floating-point register FPREG. DIRECTION is 't' to move 6711 from GPREG to FPREG and 'f' to move in the opposite direction. */ 6712 6713static void 6714mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) 6715{ 6716 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, 6717 reg_names[gpreg], reg_names[fpreg]); 6718} 6719 6720/* Likewise for 64-bit values. */ 6721 6722static void 6723mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) 6724{ 6725 if (TARGET_64BIT) 6726 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction, 6727 reg_names[gpreg], reg_names[fpreg]); 6728 else if (ISA_HAS_MXHC1) 6729 { 6730 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, 6731 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); 6732 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction, 6733 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]); 6734 } 6735 else if (TARGET_FLOATXX && direction == 't') 6736 { 6737 /* Use the argument save area to move via memory. */ 6738 fprintf (asm_out_file, "\tsw\t%s,0($sp)\n", reg_names[gpreg]); 6739 fprintf (asm_out_file, "\tsw\t%s,4($sp)\n", reg_names[gpreg + 1]); 6740 fprintf (asm_out_file, "\tldc1\t%s,0($sp)\n", reg_names[fpreg]); 6741 } 6742 else if (TARGET_FLOATXX && direction == 'f') 6743 { 6744 /* Use the argument save area to move via memory. */ 6745 fprintf (asm_out_file, "\tsdc1\t%s,0($sp)\n", reg_names[fpreg]); 6746 fprintf (asm_out_file, "\tlw\t%s,0($sp)\n", reg_names[gpreg]); 6747 fprintf (asm_out_file, "\tlw\t%s,4($sp)\n", reg_names[gpreg + 1]); 6748 } 6749 else 6750 { 6751 /* Move the least-significant word. */ 6752 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, 6753 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); 6754 /* ...then the most significant word. */ 6755 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, 6756 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]); 6757 } 6758} 6759 6760/* Write out code to move floating-point arguments into or out of 6761 general registers. FP_CODE is the code describing which arguments 6762 are present (see the comment above the definition of CUMULATIVE_ARGS 6763 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */ 6764 6765static void 6766mips_output_args_xfer (int fp_code, char direction) 6767{ 6768 unsigned int gparg, fparg, f; 6769 CUMULATIVE_ARGS cum; 6770 6771 /* This code only works for o32 and o64. */ 6772 gcc_assert (TARGET_OLDABI); 6773 6774 mips_init_cumulative_args (&cum, NULL); 6775 6776 for (f = (unsigned int) fp_code; f != 0; f >>= 2) 6777 { 6778 machine_mode mode; 6779 struct mips_arg_info info; 6780 6781 if ((f & 3) == 1) 6782 mode = SFmode; 6783 else if ((f & 3) == 2) 6784 mode = DFmode; 6785 else 6786 gcc_unreachable (); 6787 6788 mips_get_arg_info (&info, &cum, mode, NULL, true); 6789 gparg = mips_arg_regno (&info, false); 6790 fparg = mips_arg_regno (&info, true); 6791 6792 if (mode == SFmode) 6793 mips_output_32bit_xfer (direction, gparg, fparg); 6794 else 6795 mips_output_64bit_xfer (direction, gparg, fparg); 6796 6797 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true); 6798 } 6799} 6800 6801/* Write a MIPS16 stub for the current function. This stub is used 6802 for functions which take arguments in the floating-point registers. 6803 It is normal-mode code that moves the floating-point arguments 6804 into the general registers and then jumps to the MIPS16 code. */ 6805 6806static void 6807mips16_build_function_stub (void) 6808{ 6809 const char *fnname, *alias_name, *separator; 6810 char *secname, *stubname; 6811 tree stubdecl; 6812 unsigned int f; 6813 rtx symbol, alias; 6814 6815 /* Create the name of the stub, and its unique section. */ 6816 symbol = XEXP (DECL_RTL (current_function_decl), 0); 6817 alias = mips16_local_alias (symbol); 6818 6819 fnname = targetm.strip_name_encoding (XSTR (symbol, 0)); 6820 alias_name = targetm.strip_name_encoding (XSTR (alias, 0)); 6821 secname = ACONCAT ((".mips16.fn.", fnname, NULL)); 6822 stubname = ACONCAT (("__fn_stub_", fnname, NULL)); 6823 6824 /* Build a decl for the stub. */ 6825 stubdecl = build_decl (BUILTINS_LOCATION, 6826 FUNCTION_DECL, get_identifier (stubname), 6827 build_function_type_list (void_type_node, NULL_TREE)); 6828 set_decl_section_name (stubdecl, secname); 6829 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, 6830 RESULT_DECL, NULL_TREE, void_type_node); 6831 6832 /* Output a comment. */ 6833 fprintf (asm_out_file, "\t# Stub function for %s (", 6834 current_function_name ()); 6835 separator = ""; 6836 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2) 6837 { 6838 fprintf (asm_out_file, "%s%s", separator, 6839 (f & 3) == 1 ? "float" : "double"); 6840 separator = ", "; 6841 } 6842 fprintf (asm_out_file, ")\n"); 6843 6844 /* Start the function definition. */ 6845 assemble_start_function (stubdecl, stubname); 6846 mips_start_function_definition (stubname, false); 6847 6848 /* If generating pic2 code, either set up the global pointer or 6849 switch to pic0. */ 6850 if (TARGET_ABICALLS_PIC2) 6851 { 6852 if (TARGET_ABSOLUTE_ABICALLS) 6853 fprintf (asm_out_file, "\t.option\tpic0\n"); 6854 else 6855 { 6856 output_asm_insn ("%(.cpload\t%^%)", NULL); 6857 /* Emit an R_MIPS_NONE relocation to tell the linker what the 6858 target function is. Use a local GOT access when loading the 6859 symbol, to cut down on the number of unnecessary GOT entries 6860 for stubs that aren't needed. */ 6861 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol); 6862 symbol = alias; 6863 } 6864 } 6865 6866 /* Load the address of the MIPS16 function into $25. Do this first so 6867 that targets with coprocessor interlocks can use an MFC1 to fill the 6868 delay slot. */ 6869 output_asm_insn ("la\t%^,%0", &symbol); 6870 6871 /* Move the arguments from floating-point registers to general registers. */ 6872 mips_output_args_xfer (crtl->args.info.fp_code, 'f'); 6873 6874 /* Jump to the MIPS16 function. */ 6875 output_asm_insn ("jr\t%^", NULL); 6876 6877 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS) 6878 fprintf (asm_out_file, "\t.option\tpic2\n"); 6879 6880 mips_end_function_definition (stubname); 6881 6882 /* If the linker needs to create a dynamic symbol for the target 6883 function, it will associate the symbol with the stub (which, 6884 unlike the target function, follows the proper calling conventions). 6885 It is therefore useful to have a local alias for the target function, 6886 so that it can still be identified as MIPS16 code. As an optimization, 6887 this symbol can also be used for indirect MIPS16 references from 6888 within this file. */ 6889 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname); 6890 6891 switch_to_section (function_section (current_function_decl)); 6892} 6893 6894/* The current function is a MIPS16 function that returns a value in an FPR. 6895 Copy the return value from its soft-float to its hard-float location. 6896 libgcc2 has special non-MIPS16 helper functions for each case. */ 6897 6898static void 6899mips16_copy_fpr_return_value (void) 6900{ 6901 rtx fn, insn, retval; 6902 tree return_type; 6903 machine_mode return_mode; 6904 const char *name; 6905 6906 return_type = DECL_RESULT (current_function_decl); 6907 return_mode = DECL_MODE (return_type); 6908 6909 name = ACONCAT (("__mips16_ret_", 6910 mips16_call_stub_mode_suffix (return_mode), 6911 NULL)); 6912 fn = mips16_stub_function (name); 6913 6914 /* The function takes arguments in $2 (and possibly $3), so calls 6915 to it cannot be lazily bound. */ 6916 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW; 6917 6918 /* Model the call as something that takes the GPR return value as 6919 argument and returns an "updated" value. */ 6920 retval = gen_rtx_REG (return_mode, GP_RETURN); 6921 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn, 6922 const0_rtx, NULL_RTX, false); 6923 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval); 6924} 6925 6926/* Consider building a stub for a MIPS16 call to function *FN_PTR. 6927 RETVAL is the location of the return value, or null if this is 6928 a "call" rather than a "call_value". ARGS_SIZE is the size of the 6929 arguments and FP_CODE is the code built by mips_function_arg; 6930 see the comment before the fp_code field in CUMULATIVE_ARGS for details. 6931 6932 There are three alternatives: 6933 6934 - If a stub was needed, emit the call and return the call insn itself. 6935 6936 - If we can avoid using a stub by redirecting the call, set *FN_PTR 6937 to the new target and return null. 6938 6939 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR 6940 unmodified. 6941 6942 A stub is needed for calls to functions that, in normal mode, 6943 receive arguments in FPRs or return values in FPRs. The stub 6944 copies the arguments from their soft-float positions to their 6945 hard-float positions, calls the real function, then copies the 6946 return value from its hard-float position to its soft-float 6947 position. 6948 6949 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub. 6950 If *FN_PTR turns out to be to a non-MIPS16 function, the linker 6951 automatically redirects the JAL to the stub, otherwise the JAL 6952 continues to call FN directly. */ 6953 6954static rtx_insn * 6955mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code) 6956{ 6957 const char *fnname; 6958 bool fp_ret_p; 6959 struct mips16_stub *l; 6960 rtx_insn *insn; 6961 rtx pattern, fn; 6962 6963 /* We don't need to do anything if we aren't in MIPS16 mode, or if 6964 we were invoked with the -msoft-float option. */ 6965 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI) 6966 return NULL; 6967 6968 /* Figure out whether the value might come back in a floating-point 6969 register. */ 6970 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval)); 6971 6972 /* We don't need to do anything if there were no floating-point 6973 arguments and the value will not be returned in a floating-point 6974 register. */ 6975 if (fp_code == 0 && !fp_ret_p) 6976 return NULL; 6977 6978 /* We don't need to do anything if this is a call to a special 6979 MIPS16 support function. */ 6980 fn = *fn_ptr; 6981 if (mips16_stub_function_p (fn)) 6982 return NULL; 6983 6984 /* If we're calling a locally-defined MIPS16 function, we know that 6985 it will return values in both the "soft-float" and "hard-float" 6986 registers. There is no need to use a stub to move the latter 6987 to the former. */ 6988 if (fp_code == 0 && mips16_local_function_p (fn)) 6989 return NULL; 6990 6991 /* This code will only work for o32 and o64 abis. The other ABI's 6992 require more sophisticated support. */ 6993 gcc_assert (TARGET_OLDABI); 6994 6995 /* If we're calling via a function pointer, use one of the magic 6996 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination. 6997 Each stub expects the function address to arrive in register $2. */ 6998 if (GET_CODE (fn) != SYMBOL_REF 6999 || !call_insn_operand (fn, VOIDmode)) 7000 { 7001 char buf[30]; 7002 rtx stub_fn, addr; 7003 rtx_insn *insn; 7004 bool lazy_p; 7005 7006 /* If this is a locally-defined and locally-binding function, 7007 avoid the stub by calling the local alias directly. */ 7008 if (mips16_local_function_p (fn)) 7009 { 7010 *fn_ptr = mips16_local_alias (fn); 7011 return NULL; 7012 } 7013 7014 /* Create a SYMBOL_REF for the libgcc.a function. */ 7015 if (fp_ret_p) 7016 sprintf (buf, "__mips16_call_stub_%s_%d", 7017 mips16_call_stub_mode_suffix (GET_MODE (retval)), 7018 fp_code); 7019 else 7020 sprintf (buf, "__mips16_call_stub_%d", fp_code); 7021 stub_fn = mips16_stub_function (buf); 7022 7023 /* The function uses $2 as an argument, so calls to it 7024 cannot be lazily bound. */ 7025 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW; 7026 7027 /* Load the target function into $2. */ 7028 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); 7029 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn); 7030 7031 /* Emit the call. */ 7032 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn, 7033 args_size, NULL_RTX, lazy_p); 7034 7035 /* Tell GCC that this call does indeed use the value of $2. */ 7036 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr); 7037 7038 /* If we are handling a floating-point return value, we need to 7039 save $18 in the function prologue. Putting a note on the 7040 call will mean that df_regs_ever_live_p ($18) will be true if the 7041 call is not eliminated, and we can check that in the prologue 7042 code. */ 7043 if (fp_ret_p) 7044 CALL_INSN_FUNCTION_USAGE (insn) = 7045 gen_rtx_EXPR_LIST (VOIDmode, 7046 gen_rtx_CLOBBER (VOIDmode, 7047 gen_rtx_REG (word_mode, 18)), 7048 CALL_INSN_FUNCTION_USAGE (insn)); 7049 7050 return insn; 7051 } 7052 7053 /* We know the function we are going to call. If we have already 7054 built a stub, we don't need to do anything further. */ 7055 fnname = targetm.strip_name_encoding (XSTR (fn, 0)); 7056 for (l = mips16_stubs; l != NULL; l = l->next) 7057 if (strcmp (l->name, fnname) == 0) 7058 break; 7059 7060 if (l == NULL) 7061 { 7062 const char *separator; 7063 char *secname, *stubname; 7064 tree stubid, stubdecl; 7065 unsigned int f; 7066 7067 /* If the function does not return in FPRs, the special stub 7068 section is named 7069 .mips16.call.FNNAME 7070 7071 If the function does return in FPRs, the stub section is named 7072 .mips16.call.fp.FNNAME 7073 7074 Build a decl for the stub. */ 7075 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "", 7076 fnname, NULL)); 7077 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "", 7078 fnname, NULL)); 7079 stubid = get_identifier (stubname); 7080 stubdecl = build_decl (BUILTINS_LOCATION, 7081 FUNCTION_DECL, stubid, 7082 build_function_type_list (void_type_node, 7083 NULL_TREE)); 7084 set_decl_section_name (stubdecl, secname); 7085 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, 7086 RESULT_DECL, NULL_TREE, 7087 void_type_node); 7088 7089 /* Output a comment. */ 7090 fprintf (asm_out_file, "\t# Stub function to call %s%s (", 7091 (fp_ret_p 7092 ? (GET_MODE (retval) == SFmode ? "float " : "double ") 7093 : ""), 7094 fnname); 7095 separator = ""; 7096 for (f = (unsigned int) fp_code; f != 0; f >>= 2) 7097 { 7098 fprintf (asm_out_file, "%s%s", separator, 7099 (f & 3) == 1 ? "float" : "double"); 7100 separator = ", "; 7101 } 7102 fprintf (asm_out_file, ")\n"); 7103 7104 /* Start the function definition. */ 7105 assemble_start_function (stubdecl, stubname); 7106 mips_start_function_definition (stubname, false); 7107 7108 if (fp_ret_p) 7109 { 7110 fprintf (asm_out_file, "\t.cfi_startproc\n"); 7111 7112 /* Create a fake CFA 4 bytes below the stack pointer. 7113 This works around unwinders (like libgcc's) that expect 7114 the CFA for non-signal frames to be unique. */ 7115 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n"); 7116 7117 /* "Save" $sp in itself so we don't use the fake CFA. 7118 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */ 7119 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n"); 7120 7121 /* Save the return address in $18. The stub's caller knows 7122 that $18 might be clobbered, even though $18 is usually 7123 a call-saved register. 7124 7125 Do it early on in case the last move to a floating-point 7126 register can be scheduled into the delay slot of the 7127 call we are about to make. */ 7128 fprintf (asm_out_file, "\tmove\t%s,%s\n", 7129 reg_names[GP_REG_FIRST + 18], 7130 reg_names[RETURN_ADDR_REGNUM]); 7131 } 7132 else 7133 { 7134 /* Load the address of the MIPS16 function into $25. Do this 7135 first so that targets with coprocessor interlocks can use 7136 an MFC1 to fill the delay slot. */ 7137 if (TARGET_EXPLICIT_RELOCS) 7138 { 7139 output_asm_insn ("lui\t%^,%%hi(%0)", &fn); 7140 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn); 7141 } 7142 else 7143 output_asm_insn ("la\t%^,%0", &fn); 7144 } 7145 7146 /* Move the arguments from general registers to floating-point 7147 registers. */ 7148 mips_output_args_xfer (fp_code, 't'); 7149 7150 if (fp_ret_p) 7151 { 7152 /* Now call the non-MIPS16 function. */ 7153 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn); 7154 fprintf (asm_out_file, "\t.cfi_register 31,18\n"); 7155 7156 /* Move the result from floating-point registers to 7157 general registers. */ 7158 switch (GET_MODE (retval)) 7159 { 7160 case SCmode: 7161 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN, 7162 TARGET_BIG_ENDIAN 7163 ? FP_REG_FIRST + 2 7164 : FP_REG_FIRST); 7165 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN, 7166 TARGET_LITTLE_ENDIAN 7167 ? FP_REG_FIRST + 2 7168 : FP_REG_FIRST); 7169 if (GET_MODE (retval) == SCmode && TARGET_64BIT) 7170 { 7171 /* On 64-bit targets, complex floats are returned in 7172 a single GPR, such that "sd" on a suitably-aligned 7173 target would store the value correctly. */ 7174 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", 7175 reg_names[GP_RETURN + TARGET_BIG_ENDIAN], 7176 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); 7177 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", 7178 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN], 7179 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]); 7180 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n", 7181 reg_names[GP_RETURN + TARGET_BIG_ENDIAN], 7182 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]); 7183 fprintf (asm_out_file, "\tor\t%s,%s,%s\n", 7184 reg_names[GP_RETURN], 7185 reg_names[GP_RETURN], 7186 reg_names[GP_RETURN + 1]); 7187 } 7188 break; 7189 7190 case SFmode: 7191 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST); 7192 break; 7193 7194 case DCmode: 7195 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD), 7196 FP_REG_FIRST + 2); 7197 /* Fall though. */ 7198 case DFmode: 7199 case V2SFmode: 7200 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT 7201 || GET_MODE (retval) != V2SFmode); 7202 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST); 7203 break; 7204 7205 default: 7206 gcc_unreachable (); 7207 } 7208 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]); 7209 fprintf (asm_out_file, "\t.cfi_endproc\n"); 7210 } 7211 else 7212 { 7213 /* Jump to the previously-loaded address. */ 7214 output_asm_insn ("jr\t%^", NULL); 7215 } 7216 7217#ifdef ASM_DECLARE_FUNCTION_SIZE 7218 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); 7219#endif 7220 7221 mips_end_function_definition (stubname); 7222 7223 /* Record this stub. */ 7224 l = XNEW (struct mips16_stub); 7225 l->name = xstrdup (fnname); 7226 l->fp_ret_p = fp_ret_p; 7227 l->next = mips16_stubs; 7228 mips16_stubs = l; 7229 } 7230 7231 /* If we expect a floating-point return value, but we've built a 7232 stub which does not expect one, then we're in trouble. We can't 7233 use the existing stub, because it won't handle the floating-point 7234 value. We can't build a new stub, because the linker won't know 7235 which stub to use for the various calls in this object file. 7236 Fortunately, this case is illegal, since it means that a function 7237 was declared in two different ways in a single compilation. */ 7238 if (fp_ret_p && !l->fp_ret_p) 7239 error ("cannot handle inconsistent calls to %qs", fnname); 7240 7241 if (retval == NULL_RTX) 7242 pattern = gen_call_internal_direct (fn, args_size); 7243 else 7244 pattern = gen_call_value_internal_direct (retval, fn, args_size); 7245 insn = mips_emit_call_insn (pattern, fn, fn, false); 7246 7247 /* If we are calling a stub which handles a floating-point return 7248 value, we need to arrange to save $18 in the prologue. We do this 7249 by marking the function call as using the register. The prologue 7250 will later see that it is used, and emit code to save it. */ 7251 if (fp_ret_p) 7252 CALL_INSN_FUNCTION_USAGE (insn) = 7253 gen_rtx_EXPR_LIST (VOIDmode, 7254 gen_rtx_CLOBBER (VOIDmode, 7255 gen_rtx_REG (word_mode, 18)), 7256 CALL_INSN_FUNCTION_USAGE (insn)); 7257 7258 return insn; 7259} 7260 7261/* Expand a call of type TYPE. RESULT is where the result will go (null 7262 for "call"s and "sibcall"s), ADDR is the address of the function, 7263 ARGS_SIZE is the size of the arguments and AUX is the value passed 7264 to us by mips_function_arg. LAZY_P is true if this call already 7265 involves a lazily-bound function address (such as when calling 7266 functions through a MIPS16 hard-float stub). 7267 7268 Return the call itself. */ 7269 7270rtx_insn * 7271mips_expand_call (enum mips_call_type type, rtx result, rtx addr, 7272 rtx args_size, rtx aux, bool lazy_p) 7273{ 7274 rtx orig_addr, pattern; 7275 rtx_insn *insn; 7276 int fp_code; 7277 7278 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux); 7279 insn = mips16_build_call_stub (result, &addr, args_size, fp_code); 7280 if (insn) 7281 { 7282 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL); 7283 return insn; 7284 } 7285 7286 orig_addr = addr; 7287 if (!call_insn_operand (addr, VOIDmode)) 7288 { 7289 if (type == MIPS_CALL_EPILOGUE) 7290 addr = MIPS_EPILOGUE_TEMP (Pmode); 7291 else 7292 addr = gen_reg_rtx (Pmode); 7293 lazy_p |= mips_load_call_address (type, addr, orig_addr); 7294 } 7295 7296 if (result == 0) 7297 { 7298 rtx (*fn) (rtx, rtx); 7299 7300 if (type == MIPS_CALL_SIBCALL) 7301 fn = gen_sibcall_internal; 7302 else 7303 fn = gen_call_internal; 7304 7305 pattern = fn (addr, args_size); 7306 } 7307 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) 7308 { 7309 /* Handle return values created by mips_return_fpr_pair. */ 7310 rtx (*fn) (rtx, rtx, rtx, rtx); 7311 rtx reg1, reg2; 7312 7313 if (type == MIPS_CALL_SIBCALL) 7314 fn = gen_sibcall_value_multiple_internal; 7315 else 7316 fn = gen_call_value_multiple_internal; 7317 7318 reg1 = XEXP (XVECEXP (result, 0, 0), 0); 7319 reg2 = XEXP (XVECEXP (result, 0, 1), 0); 7320 pattern = fn (reg1, addr, args_size, reg2); 7321 } 7322 else 7323 { 7324 rtx (*fn) (rtx, rtx, rtx); 7325 7326 if (type == MIPS_CALL_SIBCALL) 7327 fn = gen_sibcall_value_internal; 7328 else 7329 fn = gen_call_value_internal; 7330 7331 /* Handle return values created by mips_return_fpr_single. */ 7332 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) 7333 result = XEXP (XVECEXP (result, 0, 0), 0); 7334 pattern = fn (result, addr, args_size); 7335 } 7336 7337 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p); 7338} 7339 7340/* Split call instruction INSN into a $gp-clobbering call and 7341 (where necessary) an instruction to restore $gp from its save slot. 7342 CALL_PATTERN is the pattern of the new call. */ 7343 7344void 7345mips_split_call (rtx insn, rtx call_pattern) 7346{ 7347 emit_call_insn (call_pattern); 7348 if (!find_reg_note (insn, REG_NORETURN, 0)) 7349 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, 7350 POST_CALL_TMP_REG)); 7351} 7352 7353/* Return true if a call to DECL may need to use JALX. */ 7354 7355static bool 7356mips_call_may_need_jalx_p (tree decl) 7357{ 7358 /* If the current translation unit would use a different mode for DECL, 7359 assume that the call needs JALX. */ 7360 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION) 7361 return true; 7362 7363 /* mips_get_compress_mode is always accurate for locally-binding 7364 functions in the current translation unit. */ 7365 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl)) 7366 return false; 7367 7368 /* When -minterlink-compressed is in effect, assume that functions 7369 could use a different encoding mode unless an attribute explicitly 7370 tells us otherwise. */ 7371 if (TARGET_INTERLINK_COMPRESSED) 7372 { 7373 if (!TARGET_COMPRESSION 7374 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0) 7375 return true; 7376 if (TARGET_COMPRESSION 7377 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0) 7378 return true; 7379 } 7380 7381 return false; 7382} 7383 7384/* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ 7385 7386static bool 7387mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 7388{ 7389 if (!TARGET_SIBCALLS) 7390 return false; 7391 7392 /* Interrupt handlers need special epilogue code and therefore can't 7393 use sibcalls. */ 7394 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) 7395 return false; 7396 7397 /* Direct Js are only possible to functions that use the same ISA encoding. 7398 There is no JX counterpoart of JALX. */ 7399 if (decl 7400 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode) 7401 && mips_call_may_need_jalx_p (decl)) 7402 return false; 7403 7404 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs 7405 require $gp to be valid on entry, so sibcalls can only use stubs 7406 if $gp is call-clobbered. */ 7407 if (decl 7408 && TARGET_CALL_SAVED_GP 7409 && !TARGET_ABICALLS_PIC0 7410 && !targetm.binds_local_p (decl)) 7411 return false; 7412 7413 /* Otherwise OK. */ 7414 return true; 7415} 7416 7417/* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */ 7418 7419bool 7420mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, 7421 unsigned int align, 7422 enum by_pieces_operation op, 7423 bool speed_p) 7424{ 7425 if (op == STORE_BY_PIECES) 7426 return mips_store_by_pieces_p (size, align); 7427 if (op == MOVE_BY_PIECES && HAVE_movmemsi) 7428 { 7429 /* movmemsi is meant to generate code that is at least as good as 7430 move_by_pieces. However, movmemsi effectively uses a by-pieces 7431 implementation both for moves smaller than a word and for 7432 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT 7433 bytes. We should allow the tree-level optimisers to do such 7434 moves by pieces, as it often exposes other optimization 7435 opportunities. We might as well continue to use movmemsi at 7436 the rtl level though, as it produces better code when 7437 scheduling is disabled (such as at -O). */ 7438 if (currently_expanding_to_rtl) 7439 return false; 7440 if (align < BITS_PER_WORD) 7441 return size < UNITS_PER_WORD; 7442 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT; 7443 } 7444 7445 return default_use_by_pieces_infrastructure_p (size, align, op, speed_p); 7446} 7447 7448/* Implement a handler for STORE_BY_PIECES operations 7449 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */ 7450 7451bool 7452mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align) 7453{ 7454 /* Storing by pieces involves moving constants into registers 7455 of size MIN (ALIGN, BITS_PER_WORD), then storing them. 7456 We need to decide whether it is cheaper to load the address of 7457 constant data into a register and use a block move instead. */ 7458 7459 /* If the data is only byte aligned, then: 7460 7461 (a1) A block move of less than 4 bytes would involve three 3 LBs and 7462 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs 7463 instead. 7464 7465 (a2) A block move of 4 bytes from aligned source data can use an 7466 LW/SWL/SWR sequence. This is often better than the 4 LIs and 7467 4 SBs that we would generate when storing by pieces. */ 7468 if (align <= BITS_PER_UNIT) 7469 return size < 4; 7470 7471 /* If the data is 2-byte aligned, then: 7472 7473 (b1) A block move of less than 4 bytes would use a combination of LBs, 7474 LHs, SBs and SHs. We get better code by using single-instruction 7475 LIs, SBs and SHs instead. 7476 7477 (b2) A block move of 4 bytes from aligned source data would again use 7478 an LW/SWL/SWR sequence. In most cases, loading the address of 7479 the source data would require at least one extra instruction. 7480 It is often more efficient to use 2 single-instruction LIs and 7481 2 SHs instead. 7482 7483 (b3) A block move of up to 3 additional bytes would be like (b1). 7484 7485 (b4) A block move of 8 bytes from aligned source data can use two 7486 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both 7487 sequences are better than the 4 LIs and 4 SHs that we'd generate 7488 when storing by pieces. 7489 7490 The reasoning for higher alignments is similar: 7491 7492 (c1) A block move of less than 4 bytes would be the same as (b1). 7493 7494 (c2) A block move of 4 bytes would use an LW/SW sequence. Again, 7495 loading the address of the source data would typically require 7496 at least one extra instruction. It is generally better to use 7497 LUI/ORI/SW instead. 7498 7499 (c3) A block move of up to 3 additional bytes would be like (b1). 7500 7501 (c4) A block move of 8 bytes can use two LW/SW sequences or a single 7502 LD/SD sequence, and in these cases we've traditionally preferred 7503 the memory copy over the more bulky constant moves. */ 7504 return size < 8; 7505} 7506 7507/* Emit straight-line code to move LENGTH bytes from SRC to DEST. 7508 Assume that the areas do not overlap. */ 7509 7510static void 7511mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) 7512{ 7513 HOST_WIDE_INT offset, delta; 7514 unsigned HOST_WIDE_INT bits; 7515 int i; 7516 machine_mode mode; 7517 rtx *regs; 7518 7519 /* Work out how many bits to move at a time. If both operands have 7520 half-word alignment, it is usually better to move in half words. 7521 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr 7522 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr. 7523 Otherwise move word-sized chunks. */ 7524 if (MEM_ALIGN (src) == BITS_PER_WORD / 2 7525 && MEM_ALIGN (dest) == BITS_PER_WORD / 2) 7526 bits = BITS_PER_WORD / 2; 7527 else 7528 bits = BITS_PER_WORD; 7529 7530 mode = mode_for_size (bits, MODE_INT, 0); 7531 delta = bits / BITS_PER_UNIT; 7532 7533 /* Allocate a buffer for the temporary registers. */ 7534 regs = XALLOCAVEC (rtx, length / delta); 7535 7536 /* Load as many BITS-sized chunks as possible. Use a normal load if 7537 the source has enough alignment, otherwise use left/right pairs. */ 7538 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 7539 { 7540 regs[i] = gen_reg_rtx (mode); 7541 if (MEM_ALIGN (src) >= bits) 7542 mips_emit_move (regs[i], adjust_address (src, mode, offset)); 7543 else 7544 { 7545 rtx part = adjust_address (src, BLKmode, offset); 7546 set_mem_size (part, delta); 7547 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0)) 7548 gcc_unreachable (); 7549 } 7550 } 7551 7552 /* Copy the chunks to the destination. */ 7553 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 7554 if (MEM_ALIGN (dest) >= bits) 7555 mips_emit_move (adjust_address (dest, mode, offset), regs[i]); 7556 else 7557 { 7558 rtx part = adjust_address (dest, BLKmode, offset); 7559 set_mem_size (part, delta); 7560 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0)) 7561 gcc_unreachable (); 7562 } 7563 7564 /* Mop up any left-over bytes. */ 7565 if (offset < length) 7566 { 7567 src = adjust_address (src, BLKmode, offset); 7568 dest = adjust_address (dest, BLKmode, offset); 7569 move_by_pieces (dest, src, length - offset, 7570 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); 7571 } 7572} 7573 7574/* Helper function for doing a loop-based block operation on memory 7575 reference MEM. Each iteration of the loop will operate on LENGTH 7576 bytes of MEM. 7577 7578 Create a new base register for use within the loop and point it to 7579 the start of MEM. Create a new memory reference that uses this 7580 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ 7581 7582static void 7583mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, 7584 rtx *loop_reg, rtx *loop_mem) 7585{ 7586 *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); 7587 7588 /* Although the new mem does not refer to a known location, 7589 it does keep up to LENGTH bytes of alignment. */ 7590 *loop_mem = change_address (mem, BLKmode, *loop_reg); 7591 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); 7592} 7593 7594/* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER 7595 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that 7596 the memory regions do not overlap. */ 7597 7598static void 7599mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, 7600 HOST_WIDE_INT bytes_per_iter) 7601{ 7602 rtx_code_label *label; 7603 rtx src_reg, dest_reg, final_src, test; 7604 HOST_WIDE_INT leftover; 7605 7606 leftover = length % bytes_per_iter; 7607 length -= leftover; 7608 7609 /* Create registers and memory references for use within the loop. */ 7610 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); 7611 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); 7612 7613 /* Calculate the value that SRC_REG should have after the last iteration 7614 of the loop. */ 7615 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), 7616 0, 0, OPTAB_WIDEN); 7617 7618 /* Emit the start of the loop. */ 7619 label = gen_label_rtx (); 7620 emit_label (label); 7621 7622 /* Emit the loop body. */ 7623 mips_block_move_straight (dest, src, bytes_per_iter); 7624 7625 /* Move on to the next block. */ 7626 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); 7627 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); 7628 7629 /* Emit the loop condition. */ 7630 test = gen_rtx_NE (VOIDmode, src_reg, final_src); 7631 if (Pmode == DImode) 7632 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); 7633 else 7634 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); 7635 7636 /* Mop up any left-over bytes. */ 7637 if (leftover) 7638 mips_block_move_straight (dest, src, leftover); 7639} 7640 7641/* Expand a movmemsi instruction, which copies LENGTH bytes from 7642 memory reference SRC to memory reference DEST. */ 7643 7644bool 7645mips_expand_block_move (rtx dest, rtx src, rtx length) 7646{ 7647 /* Disable entirely for R6 initially. */ 7648 if (!ISA_HAS_LWL_LWR) 7649 return false; 7650 7651 if (CONST_INT_P (length)) 7652 { 7653 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT) 7654 { 7655 mips_block_move_straight (dest, src, INTVAL (length)); 7656 return true; 7657 } 7658 else if (optimize) 7659 { 7660 mips_block_move_loop (dest, src, INTVAL (length), 7661 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); 7662 return true; 7663 } 7664 } 7665 return false; 7666} 7667 7668/* Expand a loop of synci insns for the address range [BEGIN, END). */ 7669 7670void 7671mips_expand_synci_loop (rtx begin, rtx end) 7672{ 7673 rtx inc, cmp_result, mask, length; 7674 rtx_code_label *label, *end_label; 7675 7676 /* Create end_label. */ 7677 end_label = gen_label_rtx (); 7678 7679 /* Check if begin equals end. */ 7680 cmp_result = gen_rtx_EQ (VOIDmode, begin, end); 7681 emit_jump_insn (gen_condjump (cmp_result, end_label)); 7682 7683 /* Load INC with the cache line size (rdhwr INC,$1). */ 7684 inc = gen_reg_rtx (Pmode); 7685 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc))); 7686 7687 /* Check if inc is 0. */ 7688 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx); 7689 emit_jump_insn (gen_condjump (cmp_result, end_label)); 7690 7691 /* Calculate mask. */ 7692 mask = mips_force_unary (Pmode, NEG, inc); 7693 7694 /* Mask out begin by mask. */ 7695 begin = mips_force_binary (Pmode, AND, begin, mask); 7696 7697 /* Calculate length. */ 7698 length = mips_force_binary (Pmode, MINUS, end, begin); 7699 7700 /* Loop back to here. */ 7701 label = gen_label_rtx (); 7702 emit_label (label); 7703 7704 emit_insn (gen_synci (begin)); 7705 7706 /* Update length. */ 7707 mips_emit_binary (MINUS, length, length, inc); 7708 7709 /* Update begin. */ 7710 mips_emit_binary (PLUS, begin, begin, inc); 7711 7712 /* Check if length is greater than 0. */ 7713 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx); 7714 emit_jump_insn (gen_condjump (cmp_result, label)); 7715 7716 emit_label (end_label); 7717} 7718 7719/* Expand a QI or HI mode atomic memory operation. 7720 7721 GENERATOR contains a pointer to the gen_* function that generates 7722 the SI mode underlying atomic operation using masks that we 7723 calculate. 7724 7725 RESULT is the return register for the operation. Its value is NULL 7726 if unused. 7727 7728 MEM is the location of the atomic access. 7729 7730 OLDVAL is the first operand for the operation. 7731 7732 NEWVAL is the optional second operand for the operation. Its value 7733 is NULL if unused. */ 7734 7735void 7736mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator, 7737 rtx result, rtx mem, rtx oldval, rtx newval) 7738{ 7739 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask; 7740 rtx unshifted_mask_reg, mask, inverted_mask, si_op; 7741 rtx res = NULL; 7742 machine_mode mode; 7743 7744 mode = GET_MODE (mem); 7745 7746 /* Compute the address of the containing SImode value. */ 7747 orig_addr = force_reg (Pmode, XEXP (mem, 0)); 7748 memsi_addr = mips_force_binary (Pmode, AND, orig_addr, 7749 force_reg (Pmode, GEN_INT (-4))); 7750 7751 /* Create a memory reference for it. */ 7752 memsi = gen_rtx_MEM (SImode, memsi_addr); 7753 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); 7754 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); 7755 7756 /* Work out the byte offset of the QImode or HImode value, 7757 counting from the least significant byte. */ 7758 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3)); 7759 if (TARGET_BIG_ENDIAN) 7760 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2)); 7761 7762 /* Multiply by eight to convert the shift value from bytes to bits. */ 7763 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3)); 7764 7765 /* Make the final shift an SImode value, so that it can be used in 7766 SImode operations. */ 7767 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift)); 7768 7769 /* Set MASK to an inclusive mask of the QImode or HImode value. */ 7770 unshifted_mask = GEN_INT (GET_MODE_MASK (mode)); 7771 unshifted_mask_reg = force_reg (SImode, unshifted_mask); 7772 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi); 7773 7774 /* Compute the equivalent exclusive mask. */ 7775 inverted_mask = gen_reg_rtx (SImode); 7776 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask, 7777 gen_rtx_NOT (SImode, mask))); 7778 7779 /* Shift the old value into place. */ 7780 if (oldval != const0_rtx) 7781 { 7782 oldval = convert_modes (SImode, mode, oldval, true); 7783 oldval = force_reg (SImode, oldval); 7784 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi); 7785 } 7786 7787 /* Do the same for the new value. */ 7788 if (newval && newval != const0_rtx) 7789 { 7790 newval = convert_modes (SImode, mode, newval, true); 7791 newval = force_reg (SImode, newval); 7792 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi); 7793 } 7794 7795 /* Do the SImode atomic access. */ 7796 if (result) 7797 res = gen_reg_rtx (SImode); 7798 if (newval) 7799 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval); 7800 else if (result) 7801 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval); 7802 else 7803 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval); 7804 7805 emit_insn (si_op); 7806 7807 if (result) 7808 { 7809 /* Shift and convert the result. */ 7810 mips_emit_binary (AND, res, res, mask); 7811 mips_emit_binary (LSHIFTRT, res, res, shiftsi); 7812 mips_emit_move (result, gen_lowpart (GET_MODE (result), res)); 7813 } 7814} 7815 7816/* Return true if it is possible to use left/right accesses for a 7817 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP. 7818 When returning true, update *LEFT and *RIGHT as follows: 7819 7820 *LEFT is a QImode reference to the first byte if big endian or 7821 the last byte if little endian. This address can be used in the 7822 left-side instructions (LWL, SWL, LDL, SDL). 7823 7824 *RIGHT is a QImode reference to the opposite end of the field and 7825 can be used in the patterning right-side instruction. */ 7826 7827static bool 7828mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos, 7829 rtx *left, rtx *right) 7830{ 7831 rtx first, last; 7832 7833 /* Check that the size is valid. */ 7834 if (width != 32 && (!TARGET_64BIT || width != 64)) 7835 return false; 7836 7837 /* We can only access byte-aligned values. Since we are always passed 7838 a reference to the first byte of the field, it is not necessary to 7839 do anything with BITPOS after this check. */ 7840 if (bitpos % BITS_PER_UNIT != 0) 7841 return false; 7842 7843 /* Reject aligned bitfields: we want to use a normal load or store 7844 instead of a left/right pair. */ 7845 if (MEM_ALIGN (op) >= width) 7846 return false; 7847 7848 /* Get references to both ends of the field. */ 7849 first = adjust_address (op, QImode, 0); 7850 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1); 7851 7852 /* Allocate to LEFT and RIGHT according to endianness. LEFT should 7853 correspond to the MSB and RIGHT to the LSB. */ 7854 if (TARGET_BIG_ENDIAN) 7855 *left = first, *right = last; 7856 else 7857 *left = last, *right = first; 7858 7859 return true; 7860} 7861 7862/* Try to use left/right loads to expand an "extv" or "extzv" pattern. 7863 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander; 7864 the operation is the equivalent of: 7865 7866 (set DEST (*_extract SRC WIDTH BITPOS)) 7867 7868 Return true on success. */ 7869 7870bool 7871mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width, 7872 HOST_WIDE_INT bitpos, bool unsigned_p) 7873{ 7874 rtx left, right, temp; 7875 rtx dest1 = NULL_RTX; 7876 7877 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will 7878 be a DImode, create a new temp and emit a zero extend at the end. */ 7879 if (GET_MODE (dest) == DImode 7880 && REG_P (dest) 7881 && GET_MODE_BITSIZE (SImode) == width) 7882 { 7883 dest1 = dest; 7884 dest = gen_reg_rtx (SImode); 7885 } 7886 7887 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right)) 7888 return false; 7889 7890 temp = gen_reg_rtx (GET_MODE (dest)); 7891 if (GET_MODE (dest) == DImode) 7892 { 7893 emit_insn (gen_mov_ldl (temp, src, left)); 7894 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp)); 7895 } 7896 else 7897 { 7898 emit_insn (gen_mov_lwl (temp, src, left)); 7899 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); 7900 } 7901 7902 /* If we were loading 32bits and the original register was DI then 7903 sign/zero extend into the orignal dest. */ 7904 if (dest1) 7905 { 7906 if (unsigned_p) 7907 emit_insn (gen_zero_extendsidi2 (dest1, dest)); 7908 else 7909 emit_insn (gen_extendsidi2 (dest1, dest)); 7910 } 7911 return true; 7912} 7913 7914/* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH, 7915 BITPOS and SRC are the operands passed to the expander; the operation 7916 is the equivalent of: 7917 7918 (set (zero_extract DEST WIDTH BITPOS) SRC) 7919 7920 Return true on success. */ 7921 7922bool 7923mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, 7924 HOST_WIDE_INT bitpos) 7925{ 7926 rtx left, right; 7927 machine_mode mode; 7928 7929 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right)) 7930 return false; 7931 7932 mode = mode_for_size (width, MODE_INT, 0); 7933 src = gen_lowpart (mode, src); 7934 if (mode == DImode) 7935 { 7936 emit_insn (gen_mov_sdl (dest, src, left)); 7937 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); 7938 } 7939 else 7940 { 7941 emit_insn (gen_mov_swl (dest, src, left)); 7942 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); 7943 } 7944 return true; 7945} 7946 7947/* Return true if X is a MEM with the same size as MODE. */ 7948 7949bool 7950mips_mem_fits_mode_p (machine_mode mode, rtx x) 7951{ 7952 return (MEM_P (x) 7953 && MEM_SIZE_KNOWN_P (x) 7954 && MEM_SIZE (x) == GET_MODE_SIZE (mode)); 7955} 7956 7957/* Return true if (zero_extract OP WIDTH BITPOS) can be used as the 7958 source of an "ext" instruction or the destination of an "ins" 7959 instruction. OP must be a register operand and the following 7960 conditions must hold: 7961 7962 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op)) 7963 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) 7964 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) 7965 7966 Also reject lengths equal to a word as they are better handled 7967 by the move patterns. */ 7968 7969bool 7970mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) 7971{ 7972 if (!ISA_HAS_EXT_INS 7973 || !register_operand (op, VOIDmode) 7974 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) 7975 return false; 7976 7977 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1)) 7978 return false; 7979 7980 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op))) 7981 return false; 7982 7983 return true; 7984} 7985 7986/* Check if MASK and SHIFT are valid in mask-low-and-shift-left 7987 operation if MAXLEN is the maxium length of consecutive bits that 7988 can make up MASK. MODE is the mode of the operation. See 7989 mask_low_and_shift_len for the actual definition. */ 7990 7991bool 7992mask_low_and_shift_p (machine_mode mode, rtx mask, rtx shift, int maxlen) 7993{ 7994 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen); 7995} 7996 7997/* Return true iff OP1 and OP2 are valid operands together for the 7998 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider, 7999 see the table in the comment before the pattern. */ 8000 8001bool 8002and_operands_ok (machine_mode mode, rtx op1, rtx op2) 8003{ 8004 return (memory_operand (op1, mode) 8005 ? and_load_operand (op2, mode) 8006 : and_reg_operand (op2, mode)); 8007} 8008 8009/* The canonical form of a mask-low-and-shift-left operation is 8010 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits 8011 cleared. Thus we need to shift MASK to the right before checking if it 8012 is a valid mask value. MODE is the mode of the operation. If true 8013 return the length of the mask, otherwise return -1. */ 8014 8015int 8016mask_low_and_shift_len (machine_mode mode, rtx mask, rtx shift) 8017{ 8018 HOST_WIDE_INT shval; 8019 8020 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1); 8021 return exact_log2 ((UINTVAL (mask) >> shval) + 1); 8022} 8023 8024/* Return true if -msplit-addresses is selected and should be honored. 8025 8026 -msplit-addresses is a half-way house between explicit relocations 8027 and the traditional assembler macros. It can split absolute 32-bit 8028 symbolic constants into a high/lo_sum pair but uses macros for other 8029 sorts of access. 8030 8031 Like explicit relocation support for REL targets, it relies 8032 on GNU extensions in the assembler and the linker. 8033 8034 Although this code should work for -O0, it has traditionally 8035 been treated as an optimization. */ 8036 8037static bool 8038mips_split_addresses_p (void) 8039{ 8040 return (TARGET_SPLIT_ADDRESSES 8041 && optimize 8042 && !TARGET_MIPS16 8043 && !flag_pic 8044 && !ABI_HAS_64BIT_SYMBOLS); 8045} 8046 8047/* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */ 8048 8049static void 8050mips_init_relocs (void) 8051{ 8052 memset (mips_split_p, '\0', sizeof (mips_split_p)); 8053 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p)); 8054 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p)); 8055 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs)); 8056 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs)); 8057 8058 if (TARGET_MIPS16_PCREL_LOADS) 8059 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true; 8060 else 8061 { 8062 if (ABI_HAS_64BIT_SYMBOLS) 8063 { 8064 if (TARGET_EXPLICIT_RELOCS) 8065 { 8066 mips_split_p[SYMBOL_64_HIGH] = true; 8067 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest("; 8068 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher("; 8069 8070 mips_split_p[SYMBOL_64_MID] = true; 8071 mips_hi_relocs[SYMBOL_64_MID] = "%higher("; 8072 mips_lo_relocs[SYMBOL_64_MID] = "%hi("; 8073 8074 mips_split_p[SYMBOL_64_LOW] = true; 8075 mips_hi_relocs[SYMBOL_64_LOW] = "%hi("; 8076 mips_lo_relocs[SYMBOL_64_LOW] = "%lo("; 8077 8078 mips_split_p[SYMBOL_ABSOLUTE] = true; 8079 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; 8080 } 8081 } 8082 else 8083 { 8084 if (TARGET_EXPLICIT_RELOCS 8085 || mips_split_addresses_p () 8086 || TARGET_MIPS16) 8087 { 8088 mips_split_p[SYMBOL_ABSOLUTE] = true; 8089 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; 8090 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; 8091 } 8092 } 8093 } 8094 8095 if (TARGET_MIPS16) 8096 { 8097 /* The high part is provided by a pseudo copy of $gp. */ 8098 mips_split_p[SYMBOL_GP_RELATIVE] = true; 8099 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel("; 8100 } 8101 else if (TARGET_EXPLICIT_RELOCS) 8102 /* Small data constants are kept whole until after reload, 8103 then lowered by mips_rewrite_small_data. */ 8104 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel("; 8105 8106 if (TARGET_EXPLICIT_RELOCS) 8107 { 8108 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true; 8109 if (TARGET_NEWABI) 8110 { 8111 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page("; 8112 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst("; 8113 } 8114 else 8115 { 8116 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got("; 8117 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo("; 8118 } 8119 if (TARGET_MIPS16) 8120 /* Expose the use of $28 as soon as possible. */ 8121 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true; 8122 8123 if (TARGET_XGOT) 8124 { 8125 /* The HIGH and LO_SUM are matched by special .md patterns. */ 8126 mips_split_p[SYMBOL_GOT_DISP] = true; 8127 8128 mips_split_p[SYMBOL_GOTOFF_DISP] = true; 8129 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi("; 8130 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo("; 8131 8132 mips_split_p[SYMBOL_GOTOFF_CALL] = true; 8133 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi("; 8134 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo("; 8135 } 8136 else 8137 { 8138 if (TARGET_NEWABI) 8139 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp("; 8140 else 8141 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got("; 8142 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16("; 8143 if (TARGET_MIPS16) 8144 /* Expose the use of $28 as soon as possible. */ 8145 mips_split_p[SYMBOL_GOT_DISP] = true; 8146 } 8147 } 8148 8149 if (TARGET_NEWABI) 8150 { 8151 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true; 8152 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel("; 8153 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel("; 8154 } 8155 8156 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd("; 8157 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm("; 8158 8159 if (TARGET_MIPS16_PCREL_LOADS) 8160 { 8161 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true; 8162 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true; 8163 } 8164 else 8165 { 8166 mips_split_p[SYMBOL_DTPREL] = true; 8167 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi("; 8168 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo("; 8169 8170 mips_split_p[SYMBOL_TPREL] = true; 8171 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi("; 8172 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo("; 8173 } 8174 8175 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel("; 8176 mips_lo_relocs[SYMBOL_HALF] = "%half("; 8177} 8178 8179/* Print symbolic operand OP, which is part of a HIGH or LO_SUM 8180 in context CONTEXT. RELOCS is the array of relocations to use. */ 8181 8182static void 8183mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context, 8184 const char **relocs) 8185{ 8186 enum mips_symbol_type symbol_type; 8187 const char *p; 8188 8189 symbol_type = mips_classify_symbolic_expression (op, context); 8190 gcc_assert (relocs[symbol_type]); 8191 8192 fputs (relocs[symbol_type], file); 8193 output_addr_const (file, mips_strip_unspec_address (op)); 8194 for (p = relocs[symbol_type]; *p != 0; p++) 8195 if (*p == '(') 8196 fputc (')', file); 8197} 8198 8199/* Start a new block with the given asm switch enabled. If we need 8200 to print a directive, emit PREFIX before it and SUFFIX after it. */ 8201 8202static void 8203mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch, 8204 const char *prefix, const char *suffix) 8205{ 8206 if (asm_switch->nesting_level == 0) 8207 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix); 8208 asm_switch->nesting_level++; 8209} 8210 8211/* Likewise, but end a block. */ 8212 8213static void 8214mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch, 8215 const char *prefix, const char *suffix) 8216{ 8217 gcc_assert (asm_switch->nesting_level); 8218 asm_switch->nesting_level--; 8219 if (asm_switch->nesting_level == 0) 8220 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix); 8221} 8222 8223/* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1 8224 that either print a complete line or print nothing. */ 8225 8226void 8227mips_push_asm_switch (struct mips_asm_switch *asm_switch) 8228{ 8229 mips_push_asm_switch_1 (asm_switch, "\t", "\n"); 8230} 8231 8232void 8233mips_pop_asm_switch (struct mips_asm_switch *asm_switch) 8234{ 8235 mips_pop_asm_switch_1 (asm_switch, "\t", "\n"); 8236} 8237 8238/* Print the text for PRINT_OPERAND punctation character CH to FILE. 8239 The punctuation characters are: 8240 8241 '(' Start a nested ".set noreorder" block. 8242 ')' End a nested ".set noreorder" block. 8243 '[' Start a nested ".set noat" block. 8244 ']' End a nested ".set noat" block. 8245 '<' Start a nested ".set nomacro" block. 8246 '>' End a nested ".set nomacro" block. 8247 '*' Behave like %(%< if generating a delayed-branch sequence. 8248 '#' Print a nop if in a ".set noreorder" block. 8249 '/' Like '#', but do nothing within a delayed-branch sequence. 8250 '?' Print "l" if mips_branch_likely is true 8251 '~' Print a nop if mips_branch_likely is true 8252 '.' Print the name of the register with a hard-wired zero (zero or $0). 8253 '@' Print the name of the assembler temporary register (at or $1). 8254 '^' Print the name of the pic call-through register (t9 or $25). 8255 '+' Print the name of the gp register (usually gp or $28). 8256 '$' Print the name of the stack pointer register (sp or $29). 8257 ':' Print "c" to use the compact version if the delay slot is a nop. 8258 '!' Print "s" to use the short version if the delay slot contains a 8259 16-bit instruction. 8260 8261 See also mips_init_print_operand_pucnt. */ 8262 8263static void 8264mips_print_operand_punctuation (FILE *file, int ch) 8265{ 8266 switch (ch) 8267 { 8268 case '(': 8269 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t"); 8270 break; 8271 8272 case ')': 8273 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", ""); 8274 break; 8275 8276 case '[': 8277 mips_push_asm_switch_1 (&mips_noat, "", "\n\t"); 8278 break; 8279 8280 case ']': 8281 mips_pop_asm_switch_1 (&mips_noat, "\n\t", ""); 8282 break; 8283 8284 case '<': 8285 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t"); 8286 break; 8287 8288 case '>': 8289 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", ""); 8290 break; 8291 8292 case '*': 8293 if (final_sequence != 0) 8294 { 8295 mips_print_operand_punctuation (file, '('); 8296 mips_print_operand_punctuation (file, '<'); 8297 } 8298 break; 8299 8300 case '#': 8301 if (mips_noreorder.nesting_level > 0) 8302 fputs ("\n\tnop", file); 8303 break; 8304 8305 case '/': 8306 /* Print an extra newline so that the delayed insn is separated 8307 from the following ones. This looks neater and is consistent 8308 with non-nop delayed sequences. */ 8309 if (mips_noreorder.nesting_level > 0 && final_sequence == 0) 8310 fputs ("\n\tnop\n", file); 8311 break; 8312 8313 case '?': 8314 if (mips_branch_likely) 8315 putc ('l', file); 8316 break; 8317 8318 case '~': 8319 if (mips_branch_likely) 8320 fputs ("\n\tnop", file); 8321 break; 8322 8323 case '.': 8324 fputs (reg_names[GP_REG_FIRST + 0], file); 8325 break; 8326 8327 case '@': 8328 fputs (reg_names[AT_REGNUM], file); 8329 break; 8330 8331 case '^': 8332 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file); 8333 break; 8334 8335 case '+': 8336 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); 8337 break; 8338 8339 case '$': 8340 fputs (reg_names[STACK_POINTER_REGNUM], file); 8341 break; 8342 8343 case ':': 8344 /* When final_sequence is 0, the delay slot will be a nop. We can 8345 use the compact version for microMIPS. */ 8346 if (final_sequence == 0) 8347 putc ('c', file); 8348 break; 8349 8350 case '!': 8351 /* If the delay slot instruction is short, then use the 8352 compact version. */ 8353 if (final_sequence == 0 8354 || get_attr_length (final_sequence->insn (1)) == 2) 8355 putc ('s', file); 8356 break; 8357 8358 default: 8359 gcc_unreachable (); 8360 break; 8361 } 8362} 8363 8364/* Initialize mips_print_operand_punct. */ 8365 8366static void 8367mips_init_print_operand_punct (void) 8368{ 8369 const char *p; 8370 8371 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++) 8372 mips_print_operand_punct[(unsigned char) *p] = true; 8373} 8374 8375/* PRINT_OPERAND prefix LETTER refers to the integer branch instruction 8376 associated with condition CODE. Print the condition part of the 8377 opcode to FILE. */ 8378 8379static void 8380mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter) 8381{ 8382 switch (code) 8383 { 8384 case EQ: 8385 case NE: 8386 case GT: 8387 case GE: 8388 case LT: 8389 case LE: 8390 case GTU: 8391 case GEU: 8392 case LTU: 8393 case LEU: 8394 /* Conveniently, the MIPS names for these conditions are the same 8395 as their RTL equivalents. */ 8396 fputs (GET_RTX_NAME (code), file); 8397 break; 8398 8399 default: 8400 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); 8401 break; 8402 } 8403} 8404 8405/* Likewise floating-point branches. */ 8406 8407static void 8408mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter) 8409{ 8410 switch (code) 8411 { 8412 case EQ: 8413 if (ISA_HAS_CCF) 8414 fputs ("c1eqz", file); 8415 else 8416 fputs ("c1f", file); 8417 break; 8418 8419 case NE: 8420 if (ISA_HAS_CCF) 8421 fputs ("c1nez", file); 8422 else 8423 fputs ("c1t", file); 8424 break; 8425 8426 default: 8427 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); 8428 break; 8429 } 8430} 8431 8432/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 8433 8434static bool 8435mips_print_operand_punct_valid_p (unsigned char code) 8436{ 8437 return mips_print_operand_punct[code]; 8438} 8439 8440/* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are: 8441 8442 'X' Print CONST_INT OP in hexadecimal format. 8443 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format. 8444 'd' Print CONST_INT OP in decimal. 8445 'm' Print one less than CONST_INT OP in decimal. 8446 'y' Print exact log2 of CONST_INT OP in decimal. 8447 'h' Print the high-part relocation associated with OP, after stripping 8448 any outermost HIGH. 8449 'R' Print the low-part relocation associated with OP. 8450 'C' Print the integer branch condition for comparison OP. 8451 'N' Print the inverse of the integer branch condition for comparison OP. 8452 'F' Print the FPU branch condition for comparison OP. 8453 'W' Print the inverse of the FPU branch condition for comparison OP. 8454 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...), 8455 'z' for (eq:?I ...), 'n' for (ne:?I ...). 8456 't' Like 'T', but with the EQ/NE cases reversed 8457 'Y' Print mips_fp_conditions[INTVAL (OP)] 8458 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing. 8459 'q' Print a DSP accumulator register. 8460 'D' Print the second part of a double-word register or memory operand. 8461 'L' Print the low-order register in a double-word register operand. 8462 'M' Print high-order register in a double-word register operand. 8463 'z' Print $0 if OP is zero, otherwise print OP normally. 8464 'b' Print the address of a memory operand, without offset. */ 8465 8466static void 8467mips_print_operand (FILE *file, rtx op, int letter) 8468{ 8469 enum rtx_code code; 8470 8471 if (mips_print_operand_punct_valid_p (letter)) 8472 { 8473 mips_print_operand_punctuation (file, letter); 8474 return; 8475 } 8476 8477 gcc_assert (op); 8478 code = GET_CODE (op); 8479 8480 switch (letter) 8481 { 8482 case 'X': 8483 if (CONST_INT_P (op)) 8484 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); 8485 else 8486 output_operand_lossage ("invalid use of '%%%c'", letter); 8487 break; 8488 8489 case 'x': 8490 if (CONST_INT_P (op)) 8491 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff); 8492 else 8493 output_operand_lossage ("invalid use of '%%%c'", letter); 8494 break; 8495 8496 case 'd': 8497 if (CONST_INT_P (op)) 8498 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op)); 8499 else 8500 output_operand_lossage ("invalid use of '%%%c'", letter); 8501 break; 8502 8503 case 'm': 8504 if (CONST_INT_P (op)) 8505 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1); 8506 else 8507 output_operand_lossage ("invalid use of '%%%c'", letter); 8508 break; 8509 8510 case 'y': 8511 if (CONST_INT_P (op)) 8512 { 8513 int val = exact_log2 (INTVAL (op)); 8514 if (val != -1) 8515 fprintf (file, "%d", val); 8516 else 8517 output_operand_lossage ("invalid use of '%%%c'", letter); 8518 } 8519 else 8520 output_operand_lossage ("invalid use of '%%%c'", letter); 8521 break; 8522 8523 case 'h': 8524 if (code == HIGH) 8525 op = XEXP (op, 0); 8526 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs); 8527 break; 8528 8529 case 'R': 8530 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs); 8531 break; 8532 8533 case 'C': 8534 mips_print_int_branch_condition (file, code, letter); 8535 break; 8536 8537 case 'N': 8538 mips_print_int_branch_condition (file, reverse_condition (code), letter); 8539 break; 8540 8541 case 'F': 8542 mips_print_float_branch_condition (file, code, letter); 8543 break; 8544 8545 case 'W': 8546 mips_print_float_branch_condition (file, reverse_condition (code), 8547 letter); 8548 break; 8549 8550 case 'T': 8551 case 't': 8552 { 8553 int truth = (code == NE) == (letter == 'T'); 8554 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file); 8555 } 8556 break; 8557 8558 case 'Y': 8559 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions)) 8560 fputs (mips_fp_conditions[UINTVAL (op)], file); 8561 else 8562 output_operand_lossage ("'%%%c' is not a valid operand prefix", 8563 letter); 8564 break; 8565 8566 case 'Z': 8567 if (ISA_HAS_8CC || ISA_HAS_CCF) 8568 { 8569 mips_print_operand (file, op, 0); 8570 fputc (',', file); 8571 } 8572 break; 8573 8574 case 'q': 8575 if (code == REG && MD_REG_P (REGNO (op))) 8576 fprintf (file, "$ac0"); 8577 else if (code == REG && DSP_ACC_REG_P (REGNO (op))) 8578 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]); 8579 else 8580 output_operand_lossage ("invalid use of '%%%c'", letter); 8581 break; 8582 8583 default: 8584 switch (code) 8585 { 8586 case REG: 8587 { 8588 unsigned int regno = REGNO (op); 8589 if ((letter == 'M' && TARGET_LITTLE_ENDIAN) 8590 || (letter == 'L' && TARGET_BIG_ENDIAN) 8591 || letter == 'D') 8592 regno++; 8593 else if (letter && letter != 'z' && letter != 'M' && letter != 'L') 8594 output_operand_lossage ("invalid use of '%%%c'", letter); 8595 /* We need to print $0 .. $31 for COP0 registers. */ 8596 if (COP0_REG_P (regno)) 8597 fprintf (file, "$%s", ®_names[regno][4]); 8598 else 8599 fprintf (file, "%s", reg_names[regno]); 8600 } 8601 break; 8602 8603 case MEM: 8604 if (letter == 'D') 8605 output_address (plus_constant (Pmode, XEXP (op, 0), 4)); 8606 else if (letter == 'b') 8607 { 8608 gcc_assert (REG_P (XEXP (op, 0))); 8609 mips_print_operand (file, XEXP (op, 0), 0); 8610 } 8611 else if (letter && letter != 'z') 8612 output_operand_lossage ("invalid use of '%%%c'", letter); 8613 else 8614 output_address (XEXP (op, 0)); 8615 break; 8616 8617 default: 8618 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) 8619 fputs (reg_names[GP_REG_FIRST], file); 8620 else if (letter && letter != 'z') 8621 output_operand_lossage ("invalid use of '%%%c'", letter); 8622 else if (CONST_GP_P (op)) 8623 fputs (reg_names[GLOBAL_POINTER_REGNUM], file); 8624 else 8625 output_addr_const (file, mips_strip_unspec_address (op)); 8626 break; 8627 } 8628 } 8629} 8630 8631/* Implement TARGET_PRINT_OPERAND_ADDRESS. */ 8632 8633static void 8634mips_print_operand_address (FILE *file, rtx x) 8635{ 8636 struct mips_address_info addr; 8637 8638 if (mips_classify_address (&addr, x, word_mode, true)) 8639 switch (addr.type) 8640 { 8641 case ADDRESS_REG: 8642 mips_print_operand (file, addr.offset, 0); 8643 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 8644 return; 8645 8646 case ADDRESS_LO_SUM: 8647 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM, 8648 mips_lo_relocs); 8649 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 8650 return; 8651 8652 case ADDRESS_CONST_INT: 8653 output_addr_const (file, x); 8654 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); 8655 return; 8656 8657 case ADDRESS_SYMBOLIC: 8658 output_addr_const (file, mips_strip_unspec_address (x)); 8659 return; 8660 } 8661 gcc_unreachable (); 8662} 8663 8664/* Implement TARGET_ENCODE_SECTION_INFO. */ 8665 8666static void 8667mips_encode_section_info (tree decl, rtx rtl, int first) 8668{ 8669 default_encode_section_info (decl, rtl, first); 8670 8671 if (TREE_CODE (decl) == FUNCTION_DECL) 8672 { 8673 rtx symbol = XEXP (rtl, 0); 8674 tree type = TREE_TYPE (decl); 8675 8676 /* Encode whether the symbol is short or long. */ 8677 if ((TARGET_LONG_CALLS && !mips_near_type_p (type)) 8678 || mips_far_type_p (type)) 8679 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; 8680 } 8681} 8682 8683/* Implement TARGET_SELECT_RTX_SECTION. */ 8684 8685static section * 8686mips_select_rtx_section (machine_mode mode, rtx x, 8687 unsigned HOST_WIDE_INT align) 8688{ 8689 /* ??? Consider using mergeable small data sections. */ 8690 if (mips_rtx_constant_in_small_data_p (mode)) 8691 return get_named_section (NULL, ".sdata", 0); 8692 8693 return default_elf_select_rtx_section (mode, x, align); 8694} 8695 8696/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. 8697 8698 The complication here is that, with the combination TARGET_ABICALLS 8699 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use 8700 absolute addresses, and should therefore not be included in the 8701 read-only part of a DSO. Handle such cases by selecting a normal 8702 data section instead of a read-only one. The logic apes that in 8703 default_function_rodata_section. */ 8704 8705static section * 8706mips_function_rodata_section (tree decl) 8707{ 8708 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD) 8709 return default_function_rodata_section (decl); 8710 8711 if (decl && DECL_SECTION_NAME (decl)) 8712 { 8713 const char *name = DECL_SECTION_NAME (decl); 8714 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0) 8715 { 8716 char *rname = ASTRDUP (name); 8717 rname[14] = 'd'; 8718 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl); 8719 } 8720 else if (flag_function_sections 8721 && flag_data_sections 8722 && strncmp (name, ".text.", 6) == 0) 8723 { 8724 char *rname = ASTRDUP (name); 8725 memcpy (rname + 1, "data", 4); 8726 return get_section (rname, SECTION_WRITE, decl); 8727 } 8728 } 8729 return data_section; 8730} 8731 8732/* Implement TARGET_IN_SMALL_DATA_P. */ 8733 8734static bool 8735mips_in_small_data_p (const_tree decl) 8736{ 8737 unsigned HOST_WIDE_INT size; 8738 8739 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL) 8740 return false; 8741 8742 /* We don't yet generate small-data references for -mabicalls 8743 or VxWorks RTP code. See the related -G handling in 8744 mips_option_override. */ 8745 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP) 8746 return false; 8747 8748 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) 8749 { 8750 const char *name; 8751 8752 /* Reject anything that isn't in a known small-data section. */ 8753 name = DECL_SECTION_NAME (decl); 8754 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) 8755 return false; 8756 8757 /* If a symbol is defined externally, the assembler will use the 8758 usual -G rules when deciding how to implement macros. */ 8759 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl)) 8760 return true; 8761 } 8762 else if (TARGET_EMBEDDED_DATA) 8763 { 8764 /* Don't put constants into the small data section: we want them 8765 to be in ROM rather than RAM. */ 8766 if (TREE_CODE (decl) != VAR_DECL) 8767 return false; 8768 8769 if (TREE_READONLY (decl) 8770 && !TREE_SIDE_EFFECTS (decl) 8771 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl)))) 8772 return false; 8773 } 8774 8775 /* Enforce -mlocal-sdata. */ 8776 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl)) 8777 return false; 8778 8779 /* Enforce -mextern-sdata. */ 8780 if (!TARGET_EXTERN_SDATA && DECL_P (decl)) 8781 { 8782 if (DECL_EXTERNAL (decl)) 8783 return false; 8784 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL) 8785 return false; 8786 } 8787 8788 /* We have traditionally not treated zero-sized objects as small data, 8789 so this is now effectively part of the ABI. */ 8790 size = int_size_in_bytes (TREE_TYPE (decl)); 8791 return size > 0 && size <= mips_small_data_threshold; 8792} 8793 8794/* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use 8795 anchors for small data: the GP register acts as an anchor in that 8796 case. We also don't want to use them for PC-relative accesses, 8797 where the PC acts as an anchor. */ 8798 8799static bool 8800mips_use_anchors_for_symbol_p (const_rtx symbol) 8801{ 8802 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM)) 8803 { 8804 case SYMBOL_PC_RELATIVE: 8805 case SYMBOL_GP_RELATIVE: 8806 return false; 8807 8808 default: 8809 return default_use_anchors_for_symbol_p (symbol); 8810 } 8811} 8812 8813/* The MIPS debug format wants all automatic variables and arguments 8814 to be in terms of the virtual frame pointer (stack pointer before 8815 any adjustment in the function), while the MIPS 3.0 linker wants 8816 the frame pointer to be the stack pointer after the initial 8817 adjustment. So, we do the adjustment here. The arg pointer (which 8818 is eliminated) points to the virtual frame pointer, while the frame 8819 pointer (which may be eliminated) points to the stack pointer after 8820 the initial adjustments. */ 8821 8822HOST_WIDE_INT 8823mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) 8824{ 8825 rtx offset2 = const0_rtx; 8826 rtx reg = eliminate_constant_term (addr, &offset2); 8827 8828 if (offset == 0) 8829 offset = INTVAL (offset2); 8830 8831 if (reg == stack_pointer_rtx 8832 || reg == frame_pointer_rtx 8833 || reg == hard_frame_pointer_rtx) 8834 { 8835 offset -= cfun->machine->frame.total_size; 8836 if (reg == hard_frame_pointer_rtx) 8837 offset += cfun->machine->frame.hard_frame_pointer_offset; 8838 } 8839 8840 return offset; 8841} 8842 8843/* Implement ASM_OUTPUT_EXTERNAL. */ 8844 8845void 8846mips_output_external (FILE *file, tree decl, const char *name) 8847{ 8848 default_elf_asm_output_external (file, decl, name); 8849 8850 /* We output the name if and only if TREE_SYMBOL_REFERENCED is 8851 set in order to avoid putting out names that are never really 8852 used. */ 8853 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) 8854 { 8855 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl)) 8856 { 8857 /* When using assembler macros, emit .extern directives for 8858 all small-data externs so that the assembler knows how 8859 big they are. 8860 8861 In most cases it would be safe (though pointless) to emit 8862 .externs for other symbols too. One exception is when an 8863 object is within the -G limit but declared by the user to 8864 be in a section other than .sbss or .sdata. */ 8865 fputs ("\t.extern\t", file); 8866 assemble_name (file, name); 8867 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n", 8868 int_size_in_bytes (TREE_TYPE (decl))); 8869 } 8870 } 8871} 8872 8873/* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */ 8874 8875static void 8876mips_output_filename (FILE *stream, const char *name) 8877{ 8878 /* If we are emitting DWARF-2, let dwarf2out handle the ".file" 8879 directives. */ 8880 if (write_symbols == DWARF2_DEBUG) 8881 return; 8882 else if (mips_output_filename_first_time) 8883 { 8884 mips_output_filename_first_time = 0; 8885 num_source_filenames += 1; 8886 current_function_file = name; 8887 fprintf (stream, "\t.file\t%d ", num_source_filenames); 8888 output_quoted_string (stream, name); 8889 putc ('\n', stream); 8890 } 8891 /* If we are emitting stabs, let dbxout.c handle this (except for 8892 the mips_output_filename_first_time case). */ 8893 else if (write_symbols == DBX_DEBUG) 8894 return; 8895 else if (name != current_function_file 8896 && strcmp (name, current_function_file) != 0) 8897 { 8898 num_source_filenames += 1; 8899 current_function_file = name; 8900 fprintf (stream, "\t.file\t%d ", num_source_filenames); 8901 output_quoted_string (stream, name); 8902 putc ('\n', stream); 8903 } 8904} 8905 8906/* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ 8907 8908static void ATTRIBUTE_UNUSED 8909mips_output_dwarf_dtprel (FILE *file, int size, rtx x) 8910{ 8911 switch (size) 8912 { 8913 case 4: 8914 fputs ("\t.dtprelword\t", file); 8915 break; 8916 8917 case 8: 8918 fputs ("\t.dtpreldword\t", file); 8919 break; 8920 8921 default: 8922 gcc_unreachable (); 8923 } 8924 output_addr_const (file, x); 8925 fputs ("+0x8000", file); 8926} 8927 8928/* Implement TARGET_DWARF_REGISTER_SPAN. */ 8929 8930static rtx 8931mips_dwarf_register_span (rtx reg) 8932{ 8933 rtx high, low; 8934 machine_mode mode; 8935 8936 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but 8937 ensures that double-precision registers are treated as if they were 8938 64-bit physical registers. The code will run correctly with 32-bit or 8939 64-bit registers which means that dwarf information cannot be precise 8940 for all scenarios. We choose to state that the 64-bit values are stored 8941 in a single 64-bit 'piece'. This slightly unusual construct can then be 8942 interpreted as either a pair of registers if the registers are 32-bit or 8943 a single 64-bit register depending on hardware. */ 8944 mode = GET_MODE (reg); 8945 if (FP_REG_P (REGNO (reg)) 8946 && TARGET_FLOATXX 8947 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG) 8948 { 8949 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, reg)); 8950 } 8951 /* By default, GCC maps increasing register numbers to increasing 8952 memory locations, but paired FPRs are always little-endian, 8953 regardless of the prevailing endianness. */ 8954 else if (FP_REG_P (REGNO (reg)) 8955 && TARGET_BIG_ENDIAN 8956 && MAX_FPRS_PER_FMT > 1 8957 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG) 8958 { 8959 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE); 8960 high = mips_subword (reg, true); 8961 low = mips_subword (reg, false); 8962 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low)); 8963 } 8964 8965 return NULL_RTX; 8966} 8967 8968/* Implement TARGET_DWARF_FRAME_REG_MODE. */ 8969 8970static machine_mode 8971mips_dwarf_frame_reg_mode (int regno) 8972{ 8973 machine_mode mode = default_dwarf_frame_reg_mode (regno); 8974 8975 if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64) 8976 mode = SImode; 8977 8978 return mode; 8979} 8980 8981/* DSP ALU can bypass data with no delays for the following pairs. */ 8982enum insn_code dspalu_bypass_table[][2] = 8983{ 8984 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc}, 8985 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb}, 8986 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb}, 8987 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb}, 8988 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph}, 8989 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph}, 8990 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph}, 8991 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv} 8992}; 8993 8994int 8995mips_dspalu_bypass_p (rtx out_insn, rtx in_insn) 8996{ 8997 int i; 8998 int num_bypass = ARRAY_SIZE (dspalu_bypass_table); 8999 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn); 9000 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn); 9001 9002 for (i = 0; i < num_bypass; i++) 9003 { 9004 if (out_icode == dspalu_bypass_table[i][0] 9005 && in_icode == dspalu_bypass_table[i][1]) 9006 return true; 9007 } 9008 9009 return false; 9010} 9011/* Implement ASM_OUTPUT_ASCII. */ 9012 9013void 9014mips_output_ascii (FILE *stream, const char *string, size_t len) 9015{ 9016 size_t i; 9017 int cur_pos; 9018 9019 cur_pos = 17; 9020 fprintf (stream, "\t.ascii\t\""); 9021 for (i = 0; i < len; i++) 9022 { 9023 int c; 9024 9025 c = (unsigned char) string[i]; 9026 if (ISPRINT (c)) 9027 { 9028 if (c == '\\' || c == '\"') 9029 { 9030 putc ('\\', stream); 9031 cur_pos++; 9032 } 9033 putc (c, stream); 9034 cur_pos++; 9035 } 9036 else 9037 { 9038 fprintf (stream, "\\%03o", c); 9039 cur_pos += 4; 9040 } 9041 9042 if (cur_pos > 72 && i+1 < len) 9043 { 9044 cur_pos = 17; 9045 fprintf (stream, "\"\n\t.ascii\t\""); 9046 } 9047 } 9048 fprintf (stream, "\"\n"); 9049} 9050 9051/* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR. 9052 Update *ADDR with the operand that should be printed. */ 9053 9054const char * 9055mips_output_tls_reloc_directive (rtx *addr) 9056{ 9057 enum mips_symbol_type type; 9058 9059 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA); 9060 *addr = mips_strip_unspec_address (*addr); 9061 switch (type) 9062 { 9063 case SYMBOL_DTPREL: 9064 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0"; 9065 9066 case SYMBOL_TPREL: 9067 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0"; 9068 9069 default: 9070 gcc_unreachable (); 9071 } 9072} 9073 9074/* Emit either a label, .comm, or .lcomm directive. When using assembler 9075 macros, mark the symbol as written so that mips_asm_output_external 9076 won't emit an .extern for it. STREAM is the output file, NAME is the 9077 name of the symbol, INIT_STRING is the string that should be written 9078 before the symbol and FINAL_STRING is the string that should be 9079 written after it. FINAL_STRING is a printf format that consumes the 9080 remaining arguments. */ 9081 9082void 9083mips_declare_object (FILE *stream, const char *name, const char *init_string, 9084 const char *final_string, ...) 9085{ 9086 va_list ap; 9087 9088 fputs (init_string, stream); 9089 assemble_name (stream, name); 9090 va_start (ap, final_string); 9091 vfprintf (stream, final_string, ap); 9092 va_end (ap); 9093 9094 if (!TARGET_EXPLICIT_RELOCS) 9095 { 9096 tree name_tree = get_identifier (name); 9097 TREE_ASM_WRITTEN (name_tree) = 1; 9098 } 9099} 9100 9101/* Declare a common object of SIZE bytes using asm directive INIT_STRING. 9102 NAME is the name of the object and ALIGN is the required alignment 9103 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third 9104 alignment argument. */ 9105 9106void 9107mips_declare_common_object (FILE *stream, const char *name, 9108 const char *init_string, 9109 unsigned HOST_WIDE_INT size, 9110 unsigned int align, bool takes_alignment_p) 9111{ 9112 if (!takes_alignment_p) 9113 { 9114 size += (align / BITS_PER_UNIT) - 1; 9115 size -= size % (align / BITS_PER_UNIT); 9116 mips_declare_object (stream, name, init_string, 9117 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size); 9118 } 9119 else 9120 mips_declare_object (stream, name, init_string, 9121 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n", 9122 size, align / BITS_PER_UNIT); 9123} 9124 9125/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the 9126 elfos.h version, but we also need to handle -muninit-const-in-rodata. */ 9127 9128void 9129mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name, 9130 unsigned HOST_WIDE_INT size, 9131 unsigned int align) 9132{ 9133 /* If the target wants uninitialized const declarations in 9134 .rdata then don't put them in .comm. */ 9135 if (TARGET_EMBEDDED_DATA 9136 && TARGET_UNINIT_CONST_IN_RODATA 9137 && TREE_CODE (decl) == VAR_DECL 9138 && TREE_READONLY (decl) 9139 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) 9140 { 9141 if (TREE_PUBLIC (decl) && DECL_NAME (decl)) 9142 targetm.asm_out.globalize_label (stream, name); 9143 9144 switch_to_section (readonly_data_section); 9145 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); 9146 mips_declare_object (stream, name, "", 9147 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", 9148 size); 9149 } 9150 else 9151 mips_declare_common_object (stream, name, "\n\t.comm\t", 9152 size, align, true); 9153} 9154 9155#ifdef ASM_OUTPUT_SIZE_DIRECTIVE 9156extern int size_directive_output; 9157 9158/* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF 9159 definitions except that it uses mips_declare_object to emit the label. */ 9160 9161void 9162mips_declare_object_name (FILE *stream, const char *name, 9163 tree decl ATTRIBUTE_UNUSED) 9164{ 9165#ifdef ASM_OUTPUT_TYPE_DIRECTIVE 9166 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); 9167#endif 9168 9169 size_directive_output = 0; 9170 if (!flag_inhibit_size_directive && DECL_SIZE (decl)) 9171 { 9172 HOST_WIDE_INT size; 9173 9174 size_directive_output = 1; 9175 size = int_size_in_bytes (TREE_TYPE (decl)); 9176 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); 9177 } 9178 9179 mips_declare_object (stream, name, "", ":\n"); 9180} 9181 9182/* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */ 9183 9184void 9185mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end) 9186{ 9187 const char *name; 9188 9189 name = XSTR (XEXP (DECL_RTL (decl), 0), 0); 9190 if (!flag_inhibit_size_directive 9191 && DECL_SIZE (decl) != 0 9192 && !at_end 9193 && top_level 9194 && DECL_INITIAL (decl) == error_mark_node 9195 && !size_directive_output) 9196 { 9197 HOST_WIDE_INT size; 9198 9199 size_directive_output = 1; 9200 size = int_size_in_bytes (TREE_TYPE (decl)); 9201 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); 9202 } 9203} 9204#endif 9205 9206/* Return the FOO in the name of the ".mdebug.FOO" section associated 9207 with the current ABI. */ 9208 9209static const char * 9210mips_mdebug_abi_name (void) 9211{ 9212 switch (mips_abi) 9213 { 9214 case ABI_32: 9215 return "abi32"; 9216 case ABI_O64: 9217 return "abiO64"; 9218 case ABI_N32: 9219 return "abiN32"; 9220 case ABI_64: 9221 return "abi64"; 9222 case ABI_EABI: 9223 return TARGET_64BIT ? "eabi64" : "eabi32"; 9224 default: 9225 gcc_unreachable (); 9226 } 9227} 9228 9229/* Implement TARGET_ASM_FILE_START. */ 9230 9231static void 9232mips_file_start (void) 9233{ 9234 default_file_start (); 9235 9236 /* Generate a special section to describe the ABI switches used to 9237 produce the resultant binary. */ 9238 9239 /* Record the ABI itself. Modern versions of binutils encode 9240 this information in the ELF header flags, but GDB needs the 9241 information in order to correctly debug binaries produced by 9242 older binutils. See the function mips_gdbarch_init in 9243 gdb/mips-tdep.c. */ 9244 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n", 9245 mips_mdebug_abi_name ()); 9246 9247 /* There is no ELF header flag to distinguish long32 forms of the 9248 EABI from long64 forms. Emit a special section to help tools 9249 such as GDB. Do the same for o64, which is sometimes used with 9250 -mlong64. */ 9251 if (mips_abi == ABI_EABI || mips_abi == ABI_O64) 9252 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n" 9253 "\t.previous\n", TARGET_LONG64 ? 64 : 32); 9254 9255 /* Record the NaN encoding. */ 9256 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT) 9257 fprintf (asm_out_file, "\t.nan\t%s\n", 9258 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy"); 9259 9260#ifdef HAVE_AS_DOT_MODULE 9261 /* Record the FP ABI. See below for comments. */ 9262 if (TARGET_NO_FLOAT) 9263#ifdef HAVE_AS_GNU_ATTRIBUTE 9264 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file); 9265#else 9266 ; 9267#endif 9268 else if (!TARGET_HARD_FLOAT_ABI) 9269 fputs ("\t.module\tsoftfloat\n", asm_out_file); 9270 else if (!TARGET_DOUBLE_FLOAT) 9271 fputs ("\t.module\tsinglefloat\n", asm_out_file); 9272 else if (TARGET_FLOATXX) 9273 fputs ("\t.module\tfp=xx\n", asm_out_file); 9274 else if (TARGET_FLOAT64) 9275 fputs ("\t.module\tfp=64\n", asm_out_file); 9276 else 9277 fputs ("\t.module\tfp=32\n", asm_out_file); 9278 9279 if (TARGET_ODD_SPREG) 9280 fputs ("\t.module\toddspreg\n", asm_out_file); 9281 else 9282 fputs ("\t.module\tnooddspreg\n", asm_out_file); 9283 9284#else 9285#ifdef HAVE_AS_GNU_ATTRIBUTE 9286 { 9287 int attr; 9288 9289 /* No floating-point operations, -mno-float. */ 9290 if (TARGET_NO_FLOAT) 9291 attr = 0; 9292 /* Soft-float code, -msoft-float. */ 9293 else if (!TARGET_HARD_FLOAT_ABI) 9294 attr = 3; 9295 /* Single-float code, -msingle-float. */ 9296 else if (!TARGET_DOUBLE_FLOAT) 9297 attr = 2; 9298 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. 9299 Reserved attr=4. 9300 This case used 12 callee-saved double-precision registers 9301 and is deprecated. */ 9302 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */ 9303 else if (TARGET_FLOATXX) 9304 attr = 5; 9305 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */ 9306 else if (mips_abi == ABI_32 && TARGET_FLOAT64 && TARGET_ODD_SPREG) 9307 attr = 6; 9308 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */ 9309 else if (mips_abi == ABI_32 && TARGET_FLOAT64) 9310 attr = 7; 9311 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */ 9312 else 9313 attr = 1; 9314 9315 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr); 9316 } 9317#endif 9318#endif 9319 9320 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */ 9321 if (TARGET_ABICALLS) 9322 { 9323 fprintf (asm_out_file, "\t.abicalls\n"); 9324 if (TARGET_ABICALLS_PIC0) 9325 fprintf (asm_out_file, "\t.option\tpic0\n"); 9326 } 9327 9328 if (flag_verbose_asm) 9329 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", 9330 ASM_COMMENT_START, 9331 mips_small_data_threshold, mips_arch_info->name, mips_isa); 9332} 9333 9334/* Implement TARGET_ASM_CODE_END. */ 9335 9336static void 9337mips_code_end (void) 9338{ 9339 mips_finish_stub (&mips16_rdhwr_stub); 9340 mips_finish_stub (&mips16_get_fcsr_stub); 9341 mips_finish_stub (&mips16_set_fcsr_stub); 9342} 9343 9344/* Make the last instruction frame-related and note that it performs 9345 the operation described by FRAME_PATTERN. */ 9346 9347static void 9348mips_set_frame_expr (rtx frame_pattern) 9349{ 9350 rtx_insn *insn; 9351 9352 insn = get_last_insn (); 9353 RTX_FRAME_RELATED_P (insn) = 1; 9354 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 9355 frame_pattern, 9356 REG_NOTES (insn)); 9357} 9358 9359/* Return a frame-related rtx that stores REG at MEM. 9360 REG must be a single register. */ 9361 9362static rtx 9363mips_frame_set (rtx mem, rtx reg) 9364{ 9365 rtx set; 9366 9367 set = gen_rtx_SET (VOIDmode, mem, reg); 9368 RTX_FRAME_RELATED_P (set) = 1; 9369 9370 return set; 9371} 9372 9373/* Record that the epilogue has restored call-saved register REG. */ 9374 9375static void 9376mips_add_cfa_restore (rtx reg) 9377{ 9378 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, 9379 mips_epilogue.cfa_restores); 9380} 9381 9382/* If a MIPS16e SAVE or RESTORE instruction saves or restores register 9383 mips16e_s2_s8_regs[X], it must also save the registers in indexes 9384 X + 1 onwards. Likewise mips16e_a0_a3_regs. */ 9385static const unsigned char mips16e_s2_s8_regs[] = { 9386 30, 23, 22, 21, 20, 19, 18 9387}; 9388static const unsigned char mips16e_a0_a3_regs[] = { 9389 4, 5, 6, 7 9390}; 9391 9392/* A list of the registers that can be saved by the MIPS16e SAVE instruction, 9393 ordered from the uppermost in memory to the lowest in memory. */ 9394static const unsigned char mips16e_save_restore_regs[] = { 9395 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4 9396}; 9397 9398/* Return the index of the lowest X in the range [0, SIZE) for which 9399 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */ 9400 9401static unsigned int 9402mips16e_find_first_register (unsigned int mask, const unsigned char *regs, 9403 unsigned int size) 9404{ 9405 unsigned int i; 9406 9407 for (i = 0; i < size; i++) 9408 if (BITSET_P (mask, regs[i])) 9409 break; 9410 9411 return i; 9412} 9413 9414/* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR 9415 is the number of set bits. If *MASK_PTR contains REGS[X] for some X 9416 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same 9417 is true for all indexes (X, SIZE). */ 9418 9419static void 9420mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs, 9421 unsigned int size, unsigned int *num_regs_ptr) 9422{ 9423 unsigned int i; 9424 9425 i = mips16e_find_first_register (*mask_ptr, regs, size); 9426 for (i++; i < size; i++) 9427 if (!BITSET_P (*mask_ptr, regs[i])) 9428 { 9429 *num_regs_ptr += 1; 9430 *mask_ptr |= 1 << regs[i]; 9431 } 9432} 9433 9434/* Return a simplified form of X using the register values in REG_VALUES. 9435 REG_VALUES[R] is the last value assigned to hard register R, or null 9436 if R has not been modified. 9437 9438 This function is rather limited, but is good enough for our purposes. */ 9439 9440static rtx 9441mips16e_collect_propagate_value (rtx x, rtx *reg_values) 9442{ 9443 x = avoid_constant_pool_reference (x); 9444 9445 if (UNARY_P (x)) 9446 { 9447 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); 9448 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), 9449 x0, GET_MODE (XEXP (x, 0))); 9450 } 9451 9452 if (ARITHMETIC_P (x)) 9453 { 9454 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); 9455 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values); 9456 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1); 9457 } 9458 9459 if (REG_P (x) 9460 && reg_values[REGNO (x)] 9461 && !rtx_unstable_p (reg_values[REGNO (x)])) 9462 return reg_values[REGNO (x)]; 9463 9464 return x; 9465} 9466 9467/* Return true if (set DEST SRC) stores an argument register into its 9468 caller-allocated save slot, storing the number of that argument 9469 register in *REGNO_PTR if so. REG_VALUES is as for 9470 mips16e_collect_propagate_value. */ 9471 9472static bool 9473mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values, 9474 unsigned int *regno_ptr) 9475{ 9476 unsigned int argno, regno; 9477 HOST_WIDE_INT offset, required_offset; 9478 rtx addr, base; 9479 9480 /* Check that this is a word-mode store. */ 9481 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode) 9482 return false; 9483 9484 /* Check that the register being saved is an unmodified argument 9485 register. */ 9486 regno = REGNO (src); 9487 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno]) 9488 return false; 9489 argno = regno - GP_ARG_FIRST; 9490 9491 /* Check whether the address is an appropriate stack-pointer or 9492 frame-pointer access. */ 9493 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values); 9494 mips_split_plus (addr, &base, &offset); 9495 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD; 9496 if (base == hard_frame_pointer_rtx) 9497 required_offset -= cfun->machine->frame.hard_frame_pointer_offset; 9498 else if (base != stack_pointer_rtx) 9499 return false; 9500 if (offset != required_offset) 9501 return false; 9502 9503 *regno_ptr = regno; 9504 return true; 9505} 9506 9507/* A subroutine of mips_expand_prologue, called only when generating 9508 MIPS16e SAVE instructions. Search the start of the function for any 9509 instructions that save argument registers into their caller-allocated 9510 save slots. Delete such instructions and return a value N such that 9511 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted 9512 instructions redundant. */ 9513 9514static unsigned int 9515mips16e_collect_argument_saves (void) 9516{ 9517 rtx reg_values[FIRST_PSEUDO_REGISTER]; 9518 rtx_insn *insn, *next; 9519 rtx set, dest, src; 9520 unsigned int nargs, regno; 9521 9522 push_topmost_sequence (); 9523 nargs = 0; 9524 memset (reg_values, 0, sizeof (reg_values)); 9525 for (insn = get_insns (); insn; insn = next) 9526 { 9527 next = NEXT_INSN (insn); 9528 if (NOTE_P (insn) || DEBUG_INSN_P (insn)) 9529 continue; 9530 9531 if (!INSN_P (insn)) 9532 break; 9533 9534 set = PATTERN (insn); 9535 if (GET_CODE (set) != SET) 9536 break; 9537 9538 dest = SET_DEST (set); 9539 src = SET_SRC (set); 9540 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no)) 9541 { 9542 if (!BITSET_P (cfun->machine->frame.mask, regno)) 9543 { 9544 delete_insn (insn); 9545 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1); 9546 } 9547 } 9548 else if (REG_P (dest) && GET_MODE (dest) == word_mode) 9549 reg_values[REGNO (dest)] 9550 = mips16e_collect_propagate_value (src, reg_values); 9551 else 9552 break; 9553 } 9554 pop_topmost_sequence (); 9555 9556 return nargs; 9557} 9558 9559/* Return a move between register REGNO and memory location SP + OFFSET. 9560 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE. 9561 Make the move a load if RESTORE_P, otherwise make it a store. */ 9562 9563static rtx 9564mips16e_save_restore_reg (bool restore_p, bool reg_parm_p, 9565 HOST_WIDE_INT offset, unsigned int regno) 9566{ 9567 rtx reg, mem; 9568 9569 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx, 9570 offset)); 9571 reg = gen_rtx_REG (SImode, regno); 9572 if (restore_p) 9573 { 9574 mips_add_cfa_restore (reg); 9575 return gen_rtx_SET (VOIDmode, reg, mem); 9576 } 9577 if (reg_parm_p) 9578 return gen_rtx_SET (VOIDmode, mem, reg); 9579 return mips_frame_set (mem, reg); 9580} 9581 9582/* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which. 9583 The instruction must: 9584 9585 - Allocate or deallocate SIZE bytes in total; SIZE is known 9586 to be nonzero. 9587 9588 - Save or restore as many registers in *MASK_PTR as possible. 9589 The instruction saves the first registers at the top of the 9590 allocated area, with the other registers below it. 9591 9592 - Save NARGS argument registers above the allocated area. 9593 9594 (NARGS is always zero if RESTORE_P.) 9595 9596 The SAVE and RESTORE instructions cannot save and restore all general 9597 registers, so there may be some registers left over for the caller to 9598 handle. Destructively modify *MASK_PTR so that it contains the registers 9599 that still need to be saved or restored. The caller can save these 9600 registers in the memory immediately below *OFFSET_PTR, which is a 9601 byte offset from the bottom of the allocated stack area. */ 9602 9603static rtx 9604mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr, 9605 HOST_WIDE_INT *offset_ptr, unsigned int nargs, 9606 HOST_WIDE_INT size) 9607{ 9608 rtx pattern, set; 9609 HOST_WIDE_INT offset, top_offset; 9610 unsigned int i, regno; 9611 int n; 9612 9613 gcc_assert (cfun->machine->frame.num_fp == 0); 9614 9615 /* Calculate the number of elements in the PARALLEL. We need one element 9616 for the stack adjustment, one for each argument register save, and one 9617 for each additional register move. */ 9618 n = 1 + nargs; 9619 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) 9620 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i])) 9621 n++; 9622 9623 /* Create the final PARALLEL. */ 9624 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n)); 9625 n = 0; 9626 9627 /* Add the stack pointer adjustment. */ 9628 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 9629 plus_constant (Pmode, stack_pointer_rtx, 9630 restore_p ? size : -size)); 9631 RTX_FRAME_RELATED_P (set) = 1; 9632 XVECEXP (pattern, 0, n++) = set; 9633 9634 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ 9635 top_offset = restore_p ? size : 0; 9636 9637 /* Save the arguments. */ 9638 for (i = 0; i < nargs; i++) 9639 { 9640 offset = top_offset + i * UNITS_PER_WORD; 9641 set = mips16e_save_restore_reg (restore_p, true, offset, 9642 GP_ARG_FIRST + i); 9643 XVECEXP (pattern, 0, n++) = set; 9644 } 9645 9646 /* Then fill in the other register moves. */ 9647 offset = top_offset; 9648 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) 9649 { 9650 regno = mips16e_save_restore_regs[i]; 9651 if (BITSET_P (*mask_ptr, regno)) 9652 { 9653 offset -= UNITS_PER_WORD; 9654 set = mips16e_save_restore_reg (restore_p, false, offset, regno); 9655 XVECEXP (pattern, 0, n++) = set; 9656 *mask_ptr &= ~(1 << regno); 9657 } 9658 } 9659 9660 /* Tell the caller what offset it should use for the remaining registers. */ 9661 *offset_ptr = size + (offset - top_offset); 9662 9663 gcc_assert (n == XVECLEN (pattern, 0)); 9664 9665 return pattern; 9666} 9667 9668/* PATTERN is a PARALLEL whose first element adds ADJUST to the stack 9669 pointer. Return true if PATTERN matches the kind of instruction 9670 generated by mips16e_build_save_restore. If INFO is nonnull, 9671 initialize it when returning true. */ 9672 9673bool 9674mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust, 9675 struct mips16e_save_restore_info *info) 9676{ 9677 unsigned int i, nargs, mask, extra; 9678 HOST_WIDE_INT top_offset, save_offset, offset; 9679 rtx set, reg, mem, base; 9680 int n; 9681 9682 if (!GENERATE_MIPS16E_SAVE_RESTORE) 9683 return false; 9684 9685 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ 9686 top_offset = adjust > 0 ? adjust : 0; 9687 9688 /* Interpret all other members of the PARALLEL. */ 9689 save_offset = top_offset - UNITS_PER_WORD; 9690 mask = 0; 9691 nargs = 0; 9692 i = 0; 9693 for (n = 1; n < XVECLEN (pattern, 0); n++) 9694 { 9695 /* Check that we have a SET. */ 9696 set = XVECEXP (pattern, 0, n); 9697 if (GET_CODE (set) != SET) 9698 return false; 9699 9700 /* Check that the SET is a load (if restoring) or a store 9701 (if saving). */ 9702 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set); 9703 if (!MEM_P (mem)) 9704 return false; 9705 9706 /* Check that the address is the sum of the stack pointer and a 9707 possibly-zero constant offset. */ 9708 mips_split_plus (XEXP (mem, 0), &base, &offset); 9709 if (base != stack_pointer_rtx) 9710 return false; 9711 9712 /* Check that SET's other operand is a register. */ 9713 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set); 9714 if (!REG_P (reg)) 9715 return false; 9716 9717 /* Check for argument saves. */ 9718 if (offset == top_offset + nargs * UNITS_PER_WORD 9719 && REGNO (reg) == GP_ARG_FIRST + nargs) 9720 nargs++; 9721 else if (offset == save_offset) 9722 { 9723 while (mips16e_save_restore_regs[i++] != REGNO (reg)) 9724 if (i == ARRAY_SIZE (mips16e_save_restore_regs)) 9725 return false; 9726 9727 mask |= 1 << REGNO (reg); 9728 save_offset -= UNITS_PER_WORD; 9729 } 9730 else 9731 return false; 9732 } 9733 9734 /* Check that the restrictions on register ranges are met. */ 9735 extra = 0; 9736 mips16e_mask_registers (&mask, mips16e_s2_s8_regs, 9737 ARRAY_SIZE (mips16e_s2_s8_regs), &extra); 9738 mips16e_mask_registers (&mask, mips16e_a0_a3_regs, 9739 ARRAY_SIZE (mips16e_a0_a3_regs), &extra); 9740 if (extra != 0) 9741 return false; 9742 9743 /* Make sure that the topmost argument register is not saved twice. 9744 The checks above ensure that the same is then true for the other 9745 argument registers. */ 9746 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1)) 9747 return false; 9748 9749 /* Pass back information, if requested. */ 9750 if (info) 9751 { 9752 info->nargs = nargs; 9753 info->mask = mask; 9754 info->size = (adjust > 0 ? adjust : -adjust); 9755 } 9756 9757 return true; 9758} 9759 9760/* Add a MIPS16e SAVE or RESTORE register-range argument to string S 9761 for the register range [MIN_REG, MAX_REG]. Return a pointer to 9762 the null terminator. */ 9763 9764static char * 9765mips16e_add_register_range (char *s, unsigned int min_reg, 9766 unsigned int max_reg) 9767{ 9768 if (min_reg != max_reg) 9769 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]); 9770 else 9771 s += sprintf (s, ",%s", reg_names[min_reg]); 9772 return s; 9773} 9774 9775/* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction. 9776 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */ 9777 9778const char * 9779mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust) 9780{ 9781 static char buffer[300]; 9782 9783 struct mips16e_save_restore_info info; 9784 unsigned int i, end; 9785 char *s; 9786 9787 /* Parse the pattern. */ 9788 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info)) 9789 gcc_unreachable (); 9790 9791 /* Add the mnemonic. */ 9792 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t"); 9793 s += strlen (s); 9794 9795 /* Save the arguments. */ 9796 if (info.nargs > 1) 9797 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST], 9798 reg_names[GP_ARG_FIRST + info.nargs - 1]); 9799 else if (info.nargs == 1) 9800 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]); 9801 9802 /* Emit the amount of stack space to allocate or deallocate. */ 9803 s += sprintf (s, "%d", (int) info.size); 9804 9805 /* Save or restore $16. */ 9806 if (BITSET_P (info.mask, 16)) 9807 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]); 9808 9809 /* Save or restore $17. */ 9810 if (BITSET_P (info.mask, 17)) 9811 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]); 9812 9813 /* Save or restore registers in the range $s2...$s8, which 9814 mips16e_s2_s8_regs lists in decreasing order. Note that this 9815 is a software register range; the hardware registers are not 9816 numbered consecutively. */ 9817 end = ARRAY_SIZE (mips16e_s2_s8_regs); 9818 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end); 9819 if (i < end) 9820 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1], 9821 mips16e_s2_s8_regs[i]); 9822 9823 /* Save or restore registers in the range $a0...$a3. */ 9824 end = ARRAY_SIZE (mips16e_a0_a3_regs); 9825 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end); 9826 if (i < end) 9827 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i], 9828 mips16e_a0_a3_regs[end - 1]); 9829 9830 /* Save or restore $31. */ 9831 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM)) 9832 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]); 9833 9834 return buffer; 9835} 9836 9837/* Return true if the current function returns its value in a floating-point 9838 register in MIPS16 mode. */ 9839 9840static bool 9841mips16_cfun_returns_in_fpr_p (void) 9842{ 9843 tree return_type = DECL_RESULT (current_function_decl); 9844 return (TARGET_MIPS16 9845 && TARGET_HARD_FLOAT_ABI 9846 && !aggregate_value_p (return_type, current_function_decl) 9847 && mips_return_mode_in_fpr_p (DECL_MODE (return_type))); 9848} 9849 9850/* Return true if predicate PRED is true for at least one instruction. 9851 Cache the result in *CACHE, and assume that the result is true 9852 if *CACHE is already true. */ 9853 9854static bool 9855mips_find_gp_ref (bool *cache, bool (*pred) (rtx_insn *)) 9856{ 9857 rtx_insn *insn; 9858 9859 if (!*cache) 9860 { 9861 push_topmost_sequence (); 9862 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 9863 if (USEFUL_INSN_P (insn) && pred (insn)) 9864 { 9865 *cache = true; 9866 break; 9867 } 9868 pop_topmost_sequence (); 9869 } 9870 return *cache; 9871} 9872 9873/* Return true if INSN refers to the global pointer in an "inflexible" way. 9874 See mips_cfun_has_inflexible_gp_ref_p for details. */ 9875 9876static bool 9877mips_insn_has_inflexible_gp_ref_p (rtx_insn *insn) 9878{ 9879 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE 9880 indicate that the target could be a traditional MIPS 9881 lazily-binding stub. */ 9882 return find_reg_fusage (insn, USE, pic_offset_table_rtx); 9883} 9884 9885/* Return true if the current function refers to the global pointer 9886 in a way that forces $28 to be valid. This means that we can't 9887 change the choice of global pointer, even for NewABI code. 9888 9889 One example of this (and one which needs several checks) is that 9890 $28 must be valid when calling traditional MIPS lazy-binding stubs. 9891 (This restriction does not apply to PLTs.) */ 9892 9893static bool 9894mips_cfun_has_inflexible_gp_ref_p (void) 9895{ 9896 /* If the function has a nonlocal goto, $28 must hold the correct 9897 global pointer for the target function. That is, the target 9898 of the goto implicitly uses $28. */ 9899 if (crtl->has_nonlocal_goto) 9900 return true; 9901 9902 if (TARGET_ABICALLS_PIC2) 9903 { 9904 /* Symbolic accesses implicitly use the global pointer unless 9905 -mexplicit-relocs is in effect. JAL macros to symbolic addresses 9906 might go to traditional MIPS lazy-binding stubs. */ 9907 if (!TARGET_EXPLICIT_RELOCS) 9908 return true; 9909 9910 /* FUNCTION_PROFILER includes a JAL to _mcount, which again 9911 can be lazily-bound. */ 9912 if (crtl->profile) 9913 return true; 9914 9915 /* MIPS16 functions that return in FPRs need to call an 9916 external libgcc routine. This call is only made explict 9917 during mips_expand_epilogue, and it too might be lazily bound. */ 9918 if (mips16_cfun_returns_in_fpr_p ()) 9919 return true; 9920 } 9921 9922 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p, 9923 mips_insn_has_inflexible_gp_ref_p); 9924} 9925 9926/* Return true if INSN refers to the global pointer in a "flexible" way. 9927 See mips_cfun_has_flexible_gp_ref_p for details. */ 9928 9929static bool 9930mips_insn_has_flexible_gp_ref_p (rtx_insn *insn) 9931{ 9932 return (get_attr_got (insn) != GOT_UNSET 9933 || mips_small_data_pattern_p (PATTERN (insn)) 9934 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn))); 9935} 9936 9937/* Return true if the current function references the global pointer, 9938 but if those references do not inherently require the global pointer 9939 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */ 9940 9941static bool 9942mips_cfun_has_flexible_gp_ref_p (void) 9943{ 9944 /* Reload can sometimes introduce constant pool references 9945 into a function that otherwise didn't need them. For example, 9946 suppose we have an instruction like: 9947 9948 (set (reg:DF R1) (float:DF (reg:SI R2))) 9949 9950 If R2 turns out to be a constant such as 1, the instruction may 9951 have a REG_EQUAL note saying that R1 == 1.0. Reload then has 9952 the option of using this constant if R2 doesn't get allocated 9953 to a register. 9954 9955 In cases like these, reload will have added the constant to the 9956 pool but no instruction will yet refer to it. */ 9957 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool) 9958 return true; 9959 9960 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p, 9961 mips_insn_has_flexible_gp_ref_p); 9962} 9963 9964/* Return the register that should be used as the global pointer 9965 within this function. Return INVALID_REGNUM if the function 9966 doesn't need a global pointer. */ 9967 9968static unsigned int 9969mips_global_pointer (void) 9970{ 9971 unsigned int regno; 9972 9973 /* $gp is always available unless we're using a GOT. */ 9974 if (!TARGET_USE_GOT) 9975 return GLOBAL_POINTER_REGNUM; 9976 9977 /* If there are inflexible references to $gp, we must use the 9978 standard register. */ 9979 if (mips_cfun_has_inflexible_gp_ref_p ()) 9980 return GLOBAL_POINTER_REGNUM; 9981 9982 /* If there are no current references to $gp, then the only uses 9983 we can introduce later are those involved in long branches. */ 9984 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ()) 9985 return INVALID_REGNUM; 9986 9987 /* If the global pointer is call-saved, try to use a call-clobbered 9988 alternative. */ 9989 if (TARGET_CALL_SAVED_GP && crtl->is_leaf) 9990 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 9991 if (!df_regs_ever_live_p (regno) 9992 && call_really_used_regs[regno] 9993 && !fixed_regs[regno] 9994 && regno != PIC_FUNCTION_ADDR_REGNUM) 9995 return regno; 9996 9997 return GLOBAL_POINTER_REGNUM; 9998} 9999 10000/* Return true if the current function's prologue must load the global 10001 pointer value into pic_offset_table_rtx and store the same value in 10002 the function's cprestore slot (if any). 10003 10004 One problem we have to deal with is that, when emitting GOT-based 10005 position independent code, long-branch sequences will need to load 10006 the address of the branch target from the GOT. We don't know until 10007 the very end of compilation whether (and where) the function needs 10008 long branches, so we must ensure that _any_ branch can access the 10009 global pointer in some form. However, we do not want to pessimize 10010 the usual case in which all branches are short. 10011 10012 We handle this as follows: 10013 10014 (1) During reload, we set cfun->machine->global_pointer to 10015 INVALID_REGNUM if we _know_ that the current function 10016 doesn't need a global pointer. This is only valid if 10017 long branches don't need the GOT. 10018 10019 Otherwise, we assume that we might need a global pointer 10020 and pick an appropriate register. 10021 10022 (2) If cfun->machine->global_pointer != INVALID_REGNUM, 10023 we ensure that the global pointer is available at every 10024 block boundary bar entry and exit. We do this in one of two ways: 10025 10026 - If the function has a cprestore slot, we ensure that this 10027 slot is valid at every branch. However, as explained in 10028 point (6) below, there is no guarantee that pic_offset_table_rtx 10029 itself is valid if new uses of the global pointer are introduced 10030 after the first post-epilogue split. 10031 10032 We guarantee that the cprestore slot is valid by loading it 10033 into a fake register, CPRESTORE_SLOT_REGNUM. We then make 10034 this register live at every block boundary bar function entry 10035 and exit. It is then invalid to move the load (and thus the 10036 preceding store) across a block boundary. 10037 10038 - If the function has no cprestore slot, we guarantee that 10039 pic_offset_table_rtx itself is valid at every branch. 10040 10041 See mips_eh_uses for the handling of the register liveness. 10042 10043 (3) During prologue and epilogue generation, we emit "ghost" 10044 placeholder instructions to manipulate the global pointer. 10045 10046 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p 10047 and cfun->machine->must_restore_gp_when_clobbered_p if we already know 10048 that the function needs a global pointer. (There is no need to set 10049 them earlier than this, and doing it as late as possible leads to 10050 fewer false positives.) 10051 10052 (5) If cfun->machine->must_initialize_gp_p is true during a 10053 split_insns pass, we split the ghost instructions into real 10054 instructions. These split instructions can then be optimized in 10055 the usual way. Otherwise, we keep the ghost instructions intact, 10056 and optimize for the case where they aren't needed. We still 10057 have the option of splitting them later, if we need to introduce 10058 new uses of the global pointer. 10059 10060 For example, the scheduler ignores a ghost instruction that 10061 stores $28 to the stack, but it handles the split form of 10062 the ghost instruction as an ordinary store. 10063 10064 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p 10065 is true during the first post-epilogue split_insns pass, we split 10066 calls and restore_gp patterns into instructions that explicitly 10067 load pic_offset_table_rtx from the cprestore slot. Otherwise, 10068 we split these patterns into instructions that _don't_ load from 10069 the cprestore slot. 10070 10071 If cfun->machine->must_restore_gp_when_clobbered_p is true at the 10072 time of the split, then any instructions that exist at that time 10073 can make free use of pic_offset_table_rtx. However, if we want 10074 to introduce new uses of the global pointer after the split, 10075 we must explicitly load the value from the cprestore slot, since 10076 pic_offset_table_rtx itself might not be valid at a given point 10077 in the function. 10078 10079 The idea is that we want to be able to delete redundant 10080 loads from the cprestore slot in the usual case where no 10081 long branches are needed. 10082 10083 (7) If cfun->machine->must_initialize_gp_p is still false at the end 10084 of md_reorg, we decide whether the global pointer is needed for 10085 long branches. If so, we set cfun->machine->must_initialize_gp_p 10086 to true and split the ghost instructions into real instructions 10087 at that stage. 10088 10089 Note that the ghost instructions must have a zero length for three reasons: 10090 10091 - Giving the length of the underlying $gp sequence might cause 10092 us to use long branches in cases where they aren't really needed. 10093 10094 - They would perturb things like alignment calculations. 10095 10096 - More importantly, the hazard detection in md_reorg relies on 10097 empty instructions having a zero length. 10098 10099 If we find a long branch and split the ghost instructions at the 10100 end of md_reorg, the split could introduce more long branches. 10101 That isn't a problem though, because we still do the split before 10102 the final shorten_branches pass. 10103 10104 This is extremely ugly, but it seems like the best compromise between 10105 correctness and efficiency. */ 10106 10107bool 10108mips_must_initialize_gp_p (void) 10109{ 10110 return cfun->machine->must_initialize_gp_p; 10111} 10112 10113/* Return true if REGNO is a register that is ordinarily call-clobbered 10114 but must nevertheless be preserved by an interrupt handler. */ 10115 10116static bool 10117mips_interrupt_extra_call_saved_reg_p (unsigned int regno) 10118{ 10119 if ((ISA_HAS_HILO || TARGET_DSP) 10120 && MD_REG_P (regno)) 10121 return true; 10122 10123 if (TARGET_DSP && DSP_ACC_REG_P (regno)) 10124 return true; 10125 10126 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p) 10127 { 10128 /* $0 is hard-wired. */ 10129 if (regno == GP_REG_FIRST) 10130 return false; 10131 10132 /* The interrupt handler can treat kernel registers as 10133 scratch registers. */ 10134 if (KERNEL_REG_P (regno)) 10135 return false; 10136 10137 /* The function will return the stack pointer to its original value 10138 anyway. */ 10139 if (regno == STACK_POINTER_REGNUM) 10140 return false; 10141 10142 /* Otherwise, return true for registers that aren't ordinarily 10143 call-clobbered. */ 10144 return call_really_used_regs[regno]; 10145 } 10146 10147 return false; 10148} 10149 10150/* Return true if the current function should treat register REGNO 10151 as call-saved. */ 10152 10153static bool 10154mips_cfun_call_saved_reg_p (unsigned int regno) 10155{ 10156 /* If the user makes an ordinarily-call-saved register global, 10157 that register is no longer call-saved. */ 10158 if (global_regs[regno]) 10159 return false; 10160 10161 /* Interrupt handlers need to save extra registers. */ 10162 if (cfun->machine->interrupt_handler_p 10163 && mips_interrupt_extra_call_saved_reg_p (regno)) 10164 return true; 10165 10166 /* call_insns preserve $28 unless they explicitly say otherwise, 10167 so call_really_used_regs[] treats $28 as call-saved. However, 10168 we want the ABI property rather than the default call_insn 10169 property here. */ 10170 return (regno == GLOBAL_POINTER_REGNUM 10171 ? TARGET_CALL_SAVED_GP 10172 : !call_really_used_regs[regno]); 10173} 10174 10175/* Return true if the function body might clobber register REGNO. 10176 We know that REGNO is call-saved. */ 10177 10178static bool 10179mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno) 10180{ 10181 /* Some functions should be treated as clobbering all call-saved 10182 registers. */ 10183 if (crtl->saves_all_registers) 10184 return true; 10185 10186 /* DF handles cases where a register is explicitly referenced in 10187 the rtl. Incoming values are passed in call-clobbered registers, 10188 so we can assume that any live call-saved register is set within 10189 the function. */ 10190 if (df_regs_ever_live_p (regno)) 10191 return true; 10192 10193 /* Check for registers that are clobbered by FUNCTION_PROFILER. 10194 These clobbers are not explicit in the rtl. */ 10195 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno)) 10196 return true; 10197 10198 /* If we're using a call-saved global pointer, the function's 10199 prologue will need to set it up. */ 10200 if (cfun->machine->global_pointer == regno) 10201 return true; 10202 10203 /* The function's prologue will need to set the frame pointer if 10204 frame_pointer_needed. */ 10205 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 10206 return true; 10207 10208 /* If a MIPS16 function returns a value in FPRs, its epilogue 10209 will need to call an external libgcc routine. This yet-to-be 10210 generated call_insn will clobber $31. */ 10211 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ()) 10212 return true; 10213 10214 /* If REGNO is ordinarily call-clobbered, we must assume that any 10215 called function could modify it. */ 10216 if (cfun->machine->interrupt_handler_p 10217 && !crtl->is_leaf 10218 && mips_interrupt_extra_call_saved_reg_p (regno)) 10219 return true; 10220 10221 return false; 10222} 10223 10224/* Return true if the current function must save register REGNO. */ 10225 10226static bool 10227mips_save_reg_p (unsigned int regno) 10228{ 10229 if (mips_cfun_call_saved_reg_p (regno)) 10230 { 10231 if (mips_cfun_might_clobber_call_saved_reg_p (regno)) 10232 return true; 10233 10234 /* Save both registers in an FPR pair if either one is used. This is 10235 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd 10236 register to be used without the even register. */ 10237 if (FP_REG_P (regno) 10238 && MAX_FPRS_PER_FMT == 2 10239 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1)) 10240 return true; 10241 } 10242 10243 /* We need to save the incoming return address if __builtin_eh_return 10244 is being used to set a different return address. */ 10245 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) 10246 return true; 10247 10248 return false; 10249} 10250 10251/* Populate the current function's mips_frame_info structure. 10252 10253 MIPS stack frames look like: 10254 10255 +-------------------------------+ 10256 | | 10257 | incoming stack arguments | 10258 | | 10259 +-------------------------------+ 10260 | | 10261 | caller-allocated save area | 10262 A | for register arguments | 10263 | | 10264 +-------------------------------+ <-- incoming stack pointer 10265 | | 10266 | callee-allocated save area | 10267 B | for arguments that are | 10268 | split between registers and | 10269 | the stack | 10270 | | 10271 +-------------------------------+ <-- arg_pointer_rtx 10272 | | 10273 C | callee-allocated save area | 10274 | for register varargs | 10275 | | 10276 +-------------------------------+ <-- frame_pointer_rtx 10277 | | + cop0_sp_offset 10278 | COP0 reg save area | + UNITS_PER_WORD 10279 | | 10280 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset 10281 | | + UNITS_PER_WORD 10282 | accumulator save area | 10283 | | 10284 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset 10285 | | + UNITS_PER_HWFPVALUE 10286 | FPR save area | 10287 | | 10288 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset 10289 | | + UNITS_PER_WORD 10290 | GPR save area | 10291 | | 10292 +-------------------------------+ <-- frame_pointer_rtx with 10293 | | \ -fstack-protector 10294 | local variables | | var_size 10295 | | / 10296 +-------------------------------+ 10297 | | \ 10298 | $gp save area | | cprestore_size 10299 | | / 10300 P +-------------------------------+ <-- hard_frame_pointer_rtx for 10301 | | \ MIPS16 code 10302 | outgoing stack arguments | | 10303 | | | 10304 +-------------------------------+ | args_size 10305 | | | 10306 | caller-allocated save area | | 10307 | for register arguments | | 10308 | | / 10309 +-------------------------------+ <-- stack_pointer_rtx 10310 frame_pointer_rtx without 10311 -fstack-protector 10312 hard_frame_pointer_rtx for 10313 non-MIPS16 code. 10314 10315 At least two of A, B and C will be empty. 10316 10317 Dynamic stack allocations such as alloca insert data at point P. 10318 They decrease stack_pointer_rtx but leave frame_pointer_rtx and 10319 hard_frame_pointer_rtx unchanged. */ 10320 10321static void 10322mips_compute_frame_info (void) 10323{ 10324 struct mips_frame_info *frame; 10325 HOST_WIDE_INT offset, size; 10326 unsigned int regno, i; 10327 10328 /* Set this function's interrupt properties. */ 10329 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) 10330 { 10331 if (mips_isa_rev < 2) 10332 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater"); 10333 else if (TARGET_HARD_FLOAT) 10334 error ("the %<interrupt%> attribute requires %<-msoft-float%>"); 10335 else if (TARGET_MIPS16) 10336 error ("interrupt handlers cannot be MIPS16 functions"); 10337 else 10338 { 10339 cfun->machine->interrupt_handler_p = true; 10340 cfun->machine->use_shadow_register_set_p = 10341 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl)); 10342 cfun->machine->keep_interrupts_masked_p = 10343 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl)); 10344 cfun->machine->use_debug_exception_return_p = 10345 mips_use_debug_exception_return_p (TREE_TYPE 10346 (current_function_decl)); 10347 } 10348 } 10349 10350 frame = &cfun->machine->frame; 10351 memset (frame, 0, sizeof (*frame)); 10352 size = get_frame_size (); 10353 10354 cfun->machine->global_pointer = mips_global_pointer (); 10355 10356 /* The first two blocks contain the outgoing argument area and the $gp save 10357 slot. This area isn't needed in leaf functions, but if the 10358 target-independent frame size is nonzero, we have already committed to 10359 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */ 10360 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf) 10361 { 10362 /* The MIPS 3.0 linker does not like functions that dynamically 10363 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it 10364 looks like we are trying to create a second frame pointer to the 10365 function, so allocate some stack space to make it happy. */ 10366 if (cfun->calls_alloca) 10367 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl); 10368 else 10369 frame->args_size = 0; 10370 frame->cprestore_size = 0; 10371 } 10372 else 10373 { 10374 frame->args_size = crtl->outgoing_args_size; 10375 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE; 10376 } 10377 offset = frame->args_size + frame->cprestore_size; 10378 10379 /* Move above the local variables. */ 10380 frame->var_size = MIPS_STACK_ALIGN (size); 10381 offset += frame->var_size; 10382 10383 /* Find out which GPRs we need to save. */ 10384 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 10385 if (mips_save_reg_p (regno)) 10386 { 10387 frame->num_gp++; 10388 frame->mask |= 1 << (regno - GP_REG_FIRST); 10389 } 10390 10391 /* If this function calls eh_return, we must also save and restore the 10392 EH data registers. */ 10393 if (crtl->calls_eh_return) 10394 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) 10395 { 10396 frame->num_gp++; 10397 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); 10398 } 10399 10400 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers: 10401 $a3-$a0 and $s2-$s8. If we save one register in the range, we must 10402 save all later registers too. */ 10403 if (GENERATE_MIPS16E_SAVE_RESTORE) 10404 { 10405 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs, 10406 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp); 10407 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs, 10408 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp); 10409 } 10410 10411 /* Move above the GPR save area. */ 10412 if (frame->num_gp > 0) 10413 { 10414 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD); 10415 frame->gp_sp_offset = offset - UNITS_PER_WORD; 10416 } 10417 10418 /* Find out which FPRs we need to save. This loop must iterate over 10419 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */ 10420 if (TARGET_HARD_FLOAT) 10421 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT) 10422 if (mips_save_reg_p (regno)) 10423 { 10424 frame->num_fp += MAX_FPRS_PER_FMT; 10425 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST); 10426 } 10427 10428 /* Move above the FPR save area. */ 10429 if (frame->num_fp > 0) 10430 { 10431 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG); 10432 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; 10433 } 10434 10435 /* Add in space for the interrupt context information. */ 10436 if (cfun->machine->interrupt_handler_p) 10437 { 10438 /* Check HI/LO. */ 10439 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM)) 10440 { 10441 frame->num_acc++; 10442 frame->acc_mask |= (1 << 0); 10443 } 10444 10445 /* Check accumulators 1, 2, 3. */ 10446 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) 10447 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1)) 10448 { 10449 frame->num_acc++; 10450 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1); 10451 } 10452 10453 /* All interrupt context functions need space to preserve STATUS. */ 10454 frame->num_cop0_regs++; 10455 10456 /* If we don't keep interrupts masked, we need to save EPC. */ 10457 if (!cfun->machine->keep_interrupts_masked_p) 10458 frame->num_cop0_regs++; 10459 } 10460 10461 /* Move above the accumulator save area. */ 10462 if (frame->num_acc > 0) 10463 { 10464 /* Each accumulator needs 2 words. */ 10465 offset += frame->num_acc * 2 * UNITS_PER_WORD; 10466 frame->acc_sp_offset = offset - UNITS_PER_WORD; 10467 } 10468 10469 /* Move above the COP0 register save area. */ 10470 if (frame->num_cop0_regs > 0) 10471 { 10472 offset += frame->num_cop0_regs * UNITS_PER_WORD; 10473 frame->cop0_sp_offset = offset - UNITS_PER_WORD; 10474 } 10475 10476 /* Move above the callee-allocated varargs save area. */ 10477 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size); 10478 frame->arg_pointer_offset = offset; 10479 10480 /* Move above the callee-allocated area for pretend stack arguments. */ 10481 offset += crtl->args.pretend_args_size; 10482 frame->total_size = offset; 10483 10484 /* Work out the offsets of the save areas from the top of the frame. */ 10485 if (frame->gp_sp_offset > 0) 10486 frame->gp_save_offset = frame->gp_sp_offset - offset; 10487 if (frame->fp_sp_offset > 0) 10488 frame->fp_save_offset = frame->fp_sp_offset - offset; 10489 if (frame->acc_sp_offset > 0) 10490 frame->acc_save_offset = frame->acc_sp_offset - offset; 10491 if (frame->num_cop0_regs > 0) 10492 frame->cop0_save_offset = frame->cop0_sp_offset - offset; 10493 10494 /* MIPS16 code offsets the frame pointer by the size of the outgoing 10495 arguments. This tends to increase the chances of using unextended 10496 instructions for local variables and incoming arguments. */ 10497 if (TARGET_MIPS16) 10498 frame->hard_frame_pointer_offset = frame->args_size; 10499} 10500 10501/* Return the style of GP load sequence that is being used for the 10502 current function. */ 10503 10504enum mips_loadgp_style 10505mips_current_loadgp_style (void) 10506{ 10507 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM) 10508 return LOADGP_NONE; 10509 10510 if (TARGET_RTP_PIC) 10511 return LOADGP_RTP; 10512 10513 if (TARGET_ABSOLUTE_ABICALLS) 10514 return LOADGP_ABSOLUTE; 10515 10516 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; 10517} 10518 10519/* Implement TARGET_FRAME_POINTER_REQUIRED. */ 10520 10521static bool 10522mips_frame_pointer_required (void) 10523{ 10524 /* If the function contains dynamic stack allocations, we need to 10525 use the frame pointer to access the static parts of the frame. */ 10526 if (cfun->calls_alloca) 10527 return true; 10528 10529 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise, 10530 reload may be unable to compute the address of a local variable, 10531 since there is no way to add a large constant to the stack pointer 10532 without using a second temporary register. */ 10533 if (TARGET_MIPS16) 10534 { 10535 mips_compute_frame_info (); 10536 if (!SMALL_OPERAND (cfun->machine->frame.total_size)) 10537 return true; 10538 } 10539 10540 return false; 10541} 10542 10543/* Make sure that we're not trying to eliminate to the wrong hard frame 10544 pointer. */ 10545 10546static bool 10547mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 10548{ 10549 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); 10550} 10551 10552/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer 10553 or argument pointer. TO is either the stack pointer or hard frame 10554 pointer. */ 10555 10556HOST_WIDE_INT 10557mips_initial_elimination_offset (int from, int to) 10558{ 10559 HOST_WIDE_INT offset; 10560 10561 mips_compute_frame_info (); 10562 10563 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */ 10564 switch (from) 10565 { 10566 case FRAME_POINTER_REGNUM: 10567 if (FRAME_GROWS_DOWNWARD) 10568 offset = (cfun->machine->frame.args_size 10569 + cfun->machine->frame.cprestore_size 10570 + cfun->machine->frame.var_size); 10571 else 10572 offset = 0; 10573 break; 10574 10575 case ARG_POINTER_REGNUM: 10576 offset = cfun->machine->frame.arg_pointer_offset; 10577 break; 10578 10579 default: 10580 gcc_unreachable (); 10581 } 10582 10583 if (to == HARD_FRAME_POINTER_REGNUM) 10584 offset -= cfun->machine->frame.hard_frame_pointer_offset; 10585 10586 return offset; 10587} 10588 10589/* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */ 10590 10591static void 10592mips_extra_live_on_entry (bitmap regs) 10593{ 10594 if (TARGET_USE_GOT) 10595 { 10596 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up 10597 the global pointer. */ 10598 if (!TARGET_ABSOLUTE_ABICALLS) 10599 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM); 10600 10601 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of 10602 the global pointer. */ 10603 if (TARGET_MIPS16) 10604 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM); 10605 10606 /* See the comment above load_call<mode> for details. */ 10607 bitmap_set_bit (regs, GOT_VERSION_REGNUM); 10608 } 10609} 10610 10611/* Implement RETURN_ADDR_RTX. We do not support moving back to a 10612 previous frame. */ 10613 10614rtx 10615mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 10616{ 10617 if (count != 0) 10618 return const0_rtx; 10619 10620 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); 10621} 10622 10623/* Emit code to change the current function's return address to 10624 ADDRESS. SCRATCH is available as a scratch register, if needed. 10625 ADDRESS and SCRATCH are both word-mode GPRs. */ 10626 10627void 10628mips_set_return_address (rtx address, rtx scratch) 10629{ 10630 rtx slot_address; 10631 10632 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); 10633 slot_address = mips_add_offset (scratch, stack_pointer_rtx, 10634 cfun->machine->frame.gp_sp_offset); 10635 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); 10636} 10637 10638/* Return true if the current function has a cprestore slot. */ 10639 10640bool 10641mips_cfun_has_cprestore_slot_p (void) 10642{ 10643 return (cfun->machine->global_pointer != INVALID_REGNUM 10644 && cfun->machine->frame.cprestore_size > 0); 10645} 10646 10647/* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the 10648 cprestore slot. LOAD_P is true if the caller wants to load from 10649 the cprestore slot; it is false if the caller wants to store to 10650 the slot. */ 10651 10652static void 10653mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset, 10654 bool load_p) 10655{ 10656 const struct mips_frame_info *frame; 10657 10658 frame = &cfun->machine->frame; 10659 /* .cprestore always uses the stack pointer instead of the frame pointer. 10660 We have a free choice for direct stores for non-MIPS16 functions, 10661 and for MIPS16 functions whose cprestore slot is in range of the 10662 stack pointer. Using the stack pointer would sometimes give more 10663 (early) scheduling freedom, but using the frame pointer would 10664 sometimes give more (late) scheduling freedom. It's hard to 10665 predict which applies to a given function, so let's keep things 10666 simple. 10667 10668 Loads must always use the frame pointer in functions that call 10669 alloca, and there's little benefit to using the stack pointer 10670 otherwise. */ 10671 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p)) 10672 { 10673 *base = hard_frame_pointer_rtx; 10674 *offset = frame->args_size - frame->hard_frame_pointer_offset; 10675 } 10676 else 10677 { 10678 *base = stack_pointer_rtx; 10679 *offset = frame->args_size; 10680 } 10681} 10682 10683/* Return true if X is the load or store address of the cprestore slot; 10684 LOAD_P says which. */ 10685 10686bool 10687mips_cprestore_address_p (rtx x, bool load_p) 10688{ 10689 rtx given_base, required_base; 10690 HOST_WIDE_INT given_offset, required_offset; 10691 10692 mips_split_plus (x, &given_base, &given_offset); 10693 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p); 10694 return given_base == required_base && given_offset == required_offset; 10695} 10696 10697/* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are 10698 going to load from it, false if we are going to store to it. 10699 Use TEMP as a temporary register if need be. */ 10700 10701static rtx 10702mips_cprestore_slot (rtx temp, bool load_p) 10703{ 10704 rtx base; 10705 HOST_WIDE_INT offset; 10706 10707 mips_get_cprestore_base_and_offset (&base, &offset, load_p); 10708 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset)); 10709} 10710 10711/* Emit instructions to save global pointer value GP into cprestore 10712 slot MEM. OFFSET is the offset that MEM applies to the base register. 10713 10714 MEM may not be a legitimate address. If it isn't, TEMP is a 10715 temporary register that can be used, otherwise it is a SCRATCH. */ 10716 10717void 10718mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp) 10719{ 10720 if (TARGET_CPRESTORE_DIRECTIVE) 10721 { 10722 gcc_assert (gp == pic_offset_table_rtx); 10723 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset))); 10724 } 10725 else 10726 mips_emit_move (mips_cprestore_slot (temp, false), gp); 10727} 10728 10729/* Restore $gp from its save slot, using TEMP as a temporary base register 10730 if need be. This function is for o32 and o64 abicalls only. 10731 10732 See mips_must_initialize_gp_p for details about how we manage the 10733 global pointer. */ 10734 10735void 10736mips_restore_gp_from_cprestore_slot (rtx temp) 10737{ 10738 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed); 10739 10740 if (!cfun->machine->must_restore_gp_when_clobbered_p) 10741 { 10742 emit_note (NOTE_INSN_DELETED); 10743 return; 10744 } 10745 10746 if (TARGET_MIPS16) 10747 { 10748 mips_emit_move (temp, mips_cprestore_slot (temp, true)); 10749 mips_emit_move (pic_offset_table_rtx, temp); 10750 } 10751 else 10752 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true)); 10753 if (!TARGET_EXPLICIT_RELOCS) 10754 emit_insn (gen_blockage ()); 10755} 10756 10757/* A function to save or store a register. The first argument is the 10758 register and the second is the stack slot. */ 10759typedef void (*mips_save_restore_fn) (rtx, rtx); 10760 10761/* Use FN to save or restore register REGNO. MODE is the register's 10762 mode and OFFSET is the offset of its save slot from the current 10763 stack pointer. */ 10764 10765static void 10766mips_save_restore_reg (machine_mode mode, int regno, 10767 HOST_WIDE_INT offset, mips_save_restore_fn fn) 10768{ 10769 rtx mem; 10770 10771 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, 10772 offset)); 10773 fn (gen_rtx_REG (mode, regno), mem); 10774} 10775 10776/* Call FN for each accumlator that is saved by the current function. 10777 SP_OFFSET is the offset of the current stack pointer from the start 10778 of the frame. */ 10779 10780static void 10781mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn) 10782{ 10783 HOST_WIDE_INT offset; 10784 int regno; 10785 10786 offset = cfun->machine->frame.acc_sp_offset - sp_offset; 10787 if (BITSET_P (cfun->machine->frame.acc_mask, 0)) 10788 { 10789 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn); 10790 offset -= UNITS_PER_WORD; 10791 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn); 10792 offset -= UNITS_PER_WORD; 10793 } 10794 10795 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) 10796 if (BITSET_P (cfun->machine->frame.acc_mask, 10797 ((regno - DSP_ACC_REG_FIRST) / 2) + 1)) 10798 { 10799 mips_save_restore_reg (word_mode, regno, offset, fn); 10800 offset -= UNITS_PER_WORD; 10801 } 10802} 10803 10804/* Save register REG to MEM. Make the instruction frame-related. */ 10805 10806static void 10807mips_save_reg (rtx reg, rtx mem) 10808{ 10809 if (GET_MODE (reg) == DFmode 10810 && (!TARGET_FLOAT64 10811 || mips_abi == ABI_32)) 10812 { 10813 rtx x1, x2; 10814 10815 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY); 10816 10817 x1 = mips_frame_set (mips_subword (mem, false), 10818 mips_subword (reg, false)); 10819 x2 = mips_frame_set (mips_subword (mem, true), 10820 mips_subword (reg, true)); 10821 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2))); 10822 } 10823 else 10824 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg))); 10825} 10826 10827/* Capture the register combinations that are allowed in a SWM or LWM 10828 instruction. The entries are ordered by number of registers set in 10829 the mask. We also ignore the single register encodings because a 10830 normal SW/LW is preferred. */ 10831 10832static const unsigned int umips_swm_mask[17] = { 10833 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000, 10834 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000, 10835 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000, 10836 0x000f0000, 0x80030000, 0x00070000, 0x80010000, 10837 0x00030000 10838}; 10839 10840static const unsigned int umips_swm_encoding[17] = { 10841 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2 10842}; 10843 10844/* Try to use a microMIPS LWM or SWM instruction to save or restore 10845 as many GPRs in *MASK as possible. *OFFSET is the offset from the 10846 stack pointer of the topmost save slot. 10847 10848 Remove from *MASK all registers that were handled using LWM and SWM. 10849 Update *OFFSET so that it points to the first unused save slot. */ 10850 10851static bool 10852umips_build_save_restore (mips_save_restore_fn fn, 10853 unsigned *mask, HOST_WIDE_INT *offset) 10854{ 10855 int nregs; 10856 unsigned int i, j; 10857 rtx pattern, set, reg, mem; 10858 HOST_WIDE_INT this_offset; 10859 rtx this_base; 10860 10861 /* Try matching $16 to $31 (s0 to ra). */ 10862 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++) 10863 if ((*mask & 0xffff0000) == umips_swm_mask[i]) 10864 break; 10865 10866 if (i == ARRAY_SIZE (umips_swm_mask)) 10867 return false; 10868 10869 /* Get the offset of the lowest save slot. */ 10870 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4); 10871 this_offset = *offset - UNITS_PER_WORD * (nregs - 1); 10872 10873 /* LWM/SWM can only support offsets from -2048 to 2047. */ 10874 if (!UMIPS_12BIT_OFFSET_P (this_offset)) 10875 return false; 10876 10877 /* Create the final PARALLEL. */ 10878 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); 10879 this_base = stack_pointer_rtx; 10880 10881 /* For registers $16-$23 and $30. */ 10882 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++) 10883 { 10884 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD; 10885 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset)); 10886 unsigned int regno = (j != 8) ? 16 + j : 30; 10887 *mask &= ~(1 << regno); 10888 reg = gen_rtx_REG (SImode, regno); 10889 if (fn == mips_save_reg) 10890 set = mips_frame_set (mem, reg); 10891 else 10892 { 10893 set = gen_rtx_SET (VOIDmode, reg, mem); 10894 mips_add_cfa_restore (reg); 10895 } 10896 XVECEXP (pattern, 0, j) = set; 10897 } 10898 10899 /* For register $31. */ 10900 if (umips_swm_encoding[i] >> 4) 10901 { 10902 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD; 10903 *mask &= ~(1 << 31); 10904 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset)); 10905 reg = gen_rtx_REG (SImode, 31); 10906 if (fn == mips_save_reg) 10907 set = mips_frame_set (mem, reg); 10908 else 10909 { 10910 set = gen_rtx_SET (VOIDmode, reg, mem); 10911 mips_add_cfa_restore (reg); 10912 } 10913 XVECEXP (pattern, 0, j) = set; 10914 } 10915 10916 pattern = emit_insn (pattern); 10917 if (fn == mips_save_reg) 10918 RTX_FRAME_RELATED_P (pattern) = 1; 10919 10920 /* Adjust the last offset. */ 10921 *offset -= UNITS_PER_WORD * nregs; 10922 10923 return true; 10924} 10925 10926/* Call FN for each register that is saved by the current function. 10927 SP_OFFSET is the offset of the current stack pointer from the start 10928 of the frame. */ 10929 10930static void 10931mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, 10932 mips_save_restore_fn fn) 10933{ 10934 machine_mode fpr_mode; 10935 int regno; 10936 const struct mips_frame_info *frame = &cfun->machine->frame; 10937 HOST_WIDE_INT offset; 10938 unsigned int mask; 10939 10940 /* Save registers starting from high to low. The debuggers prefer at least 10941 the return register be stored at func+4, and also it allows us not to 10942 need a nop in the epilogue if at least one register is reloaded in 10943 addition to return address. */ 10944 offset = frame->gp_sp_offset - sp_offset; 10945 mask = frame->mask; 10946 10947 if (TARGET_MICROMIPS) 10948 umips_build_save_restore (fn, &mask, &offset); 10949 10950 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) 10951 if (BITSET_P (mask, regno - GP_REG_FIRST)) 10952 { 10953 /* Record the ra offset for use by mips_function_profiler. */ 10954 if (regno == RETURN_ADDR_REGNUM) 10955 cfun->machine->frame.ra_fp_offset = offset + sp_offset; 10956 mips_save_restore_reg (word_mode, regno, offset, fn); 10957 offset -= UNITS_PER_WORD; 10958 } 10959 10960 /* This loop must iterate over the same space as its companion in 10961 mips_compute_frame_info. */ 10962 offset = cfun->machine->frame.fp_sp_offset - sp_offset; 10963 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); 10964 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; 10965 regno >= FP_REG_FIRST; 10966 regno -= MAX_FPRS_PER_FMT) 10967 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) 10968 { 10969 if (!TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT 10970 && (fixed_regs[regno] || fixed_regs[regno + 1])) 10971 { 10972 if (fixed_regs[regno]) 10973 mips_save_restore_reg (SFmode, regno + 1, offset, fn); 10974 else 10975 mips_save_restore_reg (SFmode, regno, offset, fn); 10976 } 10977 else 10978 mips_save_restore_reg (fpr_mode, regno, offset, fn); 10979 offset -= GET_MODE_SIZE (fpr_mode); 10980 } 10981} 10982 10983/* Return true if a move between register REGNO and its save slot (MEM) 10984 can be done in a single move. LOAD_P is true if we are loading 10985 from the slot, false if we are storing to it. */ 10986 10987static bool 10988mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p) 10989{ 10990 /* There is a specific MIPS16 instruction for saving $31 to the stack. */ 10991 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM) 10992 return false; 10993 10994 return mips_secondary_reload_class (REGNO_REG_CLASS (regno), 10995 GET_MODE (mem), mem, load_p) == NO_REGS; 10996} 10997 10998/* Emit a move from SRC to DEST, given that one of them is a register 10999 save slot and that the other is a register. TEMP is a temporary 11000 GPR of the same mode that is available if need be. */ 11001 11002void 11003mips_emit_save_slot_move (rtx dest, rtx src, rtx temp) 11004{ 11005 unsigned int regno; 11006 rtx mem; 11007 11008 if (REG_P (src)) 11009 { 11010 regno = REGNO (src); 11011 mem = dest; 11012 } 11013 else 11014 { 11015 regno = REGNO (dest); 11016 mem = src; 11017 } 11018 11019 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ()) 11020 { 11021 /* We don't yet know whether we'll need this instruction or not. 11022 Postpone the decision by emitting a ghost move. This move 11023 is specifically not frame-related; only the split version is. */ 11024 if (TARGET_64BIT) 11025 emit_insn (gen_move_gpdi (dest, src)); 11026 else 11027 emit_insn (gen_move_gpsi (dest, src)); 11028 return; 11029 } 11030 11031 if (regno == HI_REGNUM) 11032 { 11033 if (REG_P (dest)) 11034 { 11035 mips_emit_move (temp, src); 11036 if (TARGET_64BIT) 11037 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST), 11038 temp, gen_rtx_REG (DImode, LO_REGNUM))); 11039 else 11040 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST), 11041 temp, gen_rtx_REG (SImode, LO_REGNUM))); 11042 } 11043 else 11044 { 11045 if (TARGET_64BIT) 11046 emit_insn (gen_mfhidi_ti (temp, 11047 gen_rtx_REG (TImode, MD_REG_FIRST))); 11048 else 11049 emit_insn (gen_mfhisi_di (temp, 11050 gen_rtx_REG (DImode, MD_REG_FIRST))); 11051 mips_emit_move (dest, temp); 11052 } 11053 } 11054 else if (mips_direct_save_slot_move_p (regno, mem, mem == src)) 11055 mips_emit_move (dest, src); 11056 else 11057 { 11058 gcc_assert (!reg_overlap_mentioned_p (dest, temp)); 11059 mips_emit_move (temp, src); 11060 mips_emit_move (dest, temp); 11061 } 11062 if (MEM_P (dest)) 11063 mips_set_frame_expr (mips_frame_set (dest, src)); 11064} 11065 11066/* If we're generating n32 or n64 abicalls, and the current function 11067 does not use $28 as its global pointer, emit a cplocal directive. 11068 Use pic_offset_table_rtx as the argument to the directive. */ 11069 11070static void 11071mips_output_cplocal (void) 11072{ 11073 if (!TARGET_EXPLICIT_RELOCS 11074 && mips_must_initialize_gp_p () 11075 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM) 11076 output_asm_insn (".cplocal %+", 0); 11077} 11078 11079/* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */ 11080 11081static void 11082mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 11083{ 11084 const char *fnname; 11085 11086 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle 11087 floating-point arguments. */ 11088 if (TARGET_MIPS16 11089 && TARGET_HARD_FLOAT_ABI 11090 && crtl->args.info.fp_code != 0) 11091 mips16_build_function_stub (); 11092 11093 /* Get the function name the same way that toplev.c does before calling 11094 assemble_start_function. This is needed so that the name used here 11095 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ 11096 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 11097 mips_start_function_definition (fnname, TARGET_MIPS16); 11098 11099 /* Output MIPS-specific frame information. */ 11100 if (!flag_inhibit_size_directive) 11101 { 11102 const struct mips_frame_info *frame; 11103 11104 frame = &cfun->machine->frame; 11105 11106 /* .frame FRAMEREG, FRAMESIZE, RETREG. */ 11107 fprintf (file, 11108 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t" 11109 "# vars= " HOST_WIDE_INT_PRINT_DEC 11110 ", regs= %d/%d" 11111 ", args= " HOST_WIDE_INT_PRINT_DEC 11112 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", 11113 reg_names[frame_pointer_needed 11114 ? HARD_FRAME_POINTER_REGNUM 11115 : STACK_POINTER_REGNUM], 11116 (frame_pointer_needed 11117 ? frame->total_size - frame->hard_frame_pointer_offset 11118 : frame->total_size), 11119 reg_names[RETURN_ADDR_REGNUM], 11120 frame->var_size, 11121 frame->num_gp, frame->num_fp, 11122 frame->args_size, 11123 frame->cprestore_size); 11124 11125 /* .mask MASK, OFFSET. */ 11126 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", 11127 frame->mask, frame->gp_save_offset); 11128 11129 /* .fmask MASK, OFFSET. */ 11130 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", 11131 frame->fmask, frame->fp_save_offset); 11132 } 11133 11134 /* Handle the initialization of $gp for SVR4 PIC, if applicable. 11135 Also emit the ".set noreorder; .set nomacro" sequence for functions 11136 that need it. */ 11137 if (mips_must_initialize_gp_p () 11138 && mips_current_loadgp_style () == LOADGP_OLDABI) 11139 { 11140 if (TARGET_MIPS16) 11141 { 11142 /* This is a fixed-form sequence. The position of the 11143 first two instructions is important because of the 11144 way _gp_disp is defined. */ 11145 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); 11146 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); 11147 output_asm_insn ("sll\t$2,16", 0); 11148 output_asm_insn ("addu\t$2,$3", 0); 11149 } 11150 else 11151 { 11152 /* .cpload must be in a .set noreorder but not a 11153 .set nomacro block. */ 11154 mips_push_asm_switch (&mips_noreorder); 11155 output_asm_insn (".cpload\t%^", 0); 11156 if (!cfun->machine->all_noreorder_p) 11157 mips_pop_asm_switch (&mips_noreorder); 11158 else 11159 mips_push_asm_switch (&mips_nomacro); 11160 } 11161 } 11162 else if (cfun->machine->all_noreorder_p) 11163 { 11164 mips_push_asm_switch (&mips_noreorder); 11165 mips_push_asm_switch (&mips_nomacro); 11166 } 11167 11168 /* Tell the assembler which register we're using as the global 11169 pointer. This is needed for thunks, since they can use either 11170 explicit relocs or assembler macros. */ 11171 mips_output_cplocal (); 11172} 11173 11174/* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */ 11175 11176static void 11177mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, 11178 HOST_WIDE_INT size ATTRIBUTE_UNUSED) 11179{ 11180 const char *fnname; 11181 11182 /* Reinstate the normal $gp. */ 11183 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM); 11184 mips_output_cplocal (); 11185 11186 if (cfun->machine->all_noreorder_p) 11187 { 11188 mips_pop_asm_switch (&mips_nomacro); 11189 mips_pop_asm_switch (&mips_noreorder); 11190 } 11191 11192 /* Get the function name the same way that toplev.c does before calling 11193 assemble_start_function. This is needed so that the name used here 11194 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ 11195 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 11196 mips_end_function_definition (fnname); 11197} 11198 11199/* Emit an optimisation barrier for accesses to the current frame. */ 11200 11201static void 11202mips_frame_barrier (void) 11203{ 11204 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx)); 11205} 11206 11207 11208/* The __gnu_local_gp symbol. */ 11209 11210static GTY(()) rtx mips_gnu_local_gp; 11211 11212/* If we're generating n32 or n64 abicalls, emit instructions 11213 to set up the global pointer. */ 11214 11215static void 11216mips_emit_loadgp (void) 11217{ 11218 rtx addr, offset, incoming_address, base, index, pic_reg; 11219 11220 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; 11221 switch (mips_current_loadgp_style ()) 11222 { 11223 case LOADGP_ABSOLUTE: 11224 if (mips_gnu_local_gp == NULL) 11225 { 11226 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); 11227 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; 11228 } 11229 emit_insn (PMODE_INSN (gen_loadgp_absolute, 11230 (pic_reg, mips_gnu_local_gp))); 11231 break; 11232 11233 case LOADGP_OLDABI: 11234 /* Added by mips_output_function_prologue. */ 11235 break; 11236 11237 case LOADGP_NEWABI: 11238 addr = XEXP (DECL_RTL (current_function_decl), 0); 11239 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP); 11240 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 11241 emit_insn (PMODE_INSN (gen_loadgp_newabi, 11242 (pic_reg, offset, incoming_address))); 11243 break; 11244 11245 case LOADGP_RTP: 11246 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE)); 11247 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX)); 11248 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index))); 11249 break; 11250 11251 default: 11252 return; 11253 } 11254 11255 if (TARGET_MIPS16) 11256 emit_insn (PMODE_INSN (gen_copygp_mips16, 11257 (pic_offset_table_rtx, pic_reg))); 11258 11259 /* Emit a blockage if there are implicit uses of the GP register. 11260 This includes profiled functions, because FUNCTION_PROFILE uses 11261 a jal macro. */ 11262 if (!TARGET_EXPLICIT_RELOCS || crtl->profile) 11263 emit_insn (gen_loadgp_blockage ()); 11264} 11265 11266#define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) 11267 11268#if PROBE_INTERVAL > 32768 11269#error Cannot use indexed addressing mode for stack probing 11270#endif 11271 11272/* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, 11273 inclusive. These are offsets from the current stack pointer. */ 11274 11275static void 11276mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) 11277{ 11278 if (TARGET_MIPS16) 11279 sorry ("-fstack-check=specific not implemented for MIPS16"); 11280 11281 /* See if we have a constant small number of probes to generate. If so, 11282 that's the easy case. */ 11283 if (first + size <= 32768) 11284 { 11285 HOST_WIDE_INT i; 11286 11287 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until 11288 it exceeds SIZE. If only one probe is needed, this will not 11289 generate any code. Then probe at FIRST + SIZE. */ 11290 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) 11291 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, 11292 -(first + i))); 11293 11294 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, 11295 -(first + size))); 11296 } 11297 11298 /* Otherwise, do the same as above, but in a loop. Note that we must be 11299 extra careful with variables wrapping around because we might be at 11300 the very top (or the very bottom) of the address space and we have 11301 to be able to handle this case properly; in particular, we use an 11302 equality test for the loop condition. */ 11303 else 11304 { 11305 HOST_WIDE_INT rounded_size; 11306 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode); 11307 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode); 11308 11309 /* Sanity check for the addressing mode we're going to use. */ 11310 gcc_assert (first <= 32768); 11311 11312 11313 /* Step 1: round SIZE to the previous multiple of the interval. */ 11314 11315 rounded_size = size & -PROBE_INTERVAL; 11316 11317 11318 /* Step 2: compute initial and final value of the loop counter. */ 11319 11320 /* TEST_ADDR = SP + FIRST. */ 11321 emit_insn (gen_rtx_SET (VOIDmode, r3, 11322 plus_constant (Pmode, stack_pointer_rtx, 11323 -first))); 11324 11325 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ 11326 if (rounded_size > 32768) 11327 { 11328 emit_move_insn (r12, GEN_INT (rounded_size)); 11329 emit_insn (gen_rtx_SET (VOIDmode, r12, 11330 gen_rtx_MINUS (Pmode, r3, r12))); 11331 } 11332 else 11333 emit_insn (gen_rtx_SET (VOIDmode, r12, 11334 plus_constant (Pmode, r3, -rounded_size))); 11335 11336 11337 /* Step 3: the loop 11338 11339 while (TEST_ADDR != LAST_ADDR) 11340 { 11341 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL 11342 probe at TEST_ADDR 11343 } 11344 11345 probes at FIRST + N * PROBE_INTERVAL for values of N from 1 11346 until it is equal to ROUNDED_SIZE. */ 11347 11348 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12))); 11349 11350 11351 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time 11352 that SIZE is equal to ROUNDED_SIZE. */ 11353 11354 if (size != rounded_size) 11355 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size)); 11356 } 11357 11358 /* Make sure nothing is scheduled before we are done. */ 11359 emit_insn (gen_blockage ()); 11360} 11361 11362/* Probe a range of stack addresses from REG1 to REG2 inclusive. These are 11363 absolute addresses. */ 11364 11365const char * 11366mips_output_probe_stack_range (rtx reg1, rtx reg2) 11367{ 11368 static int labelno = 0; 11369 char loop_lab[32], end_lab[32], tmp[64]; 11370 rtx xops[2]; 11371 11372 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno); 11373 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++); 11374 11375 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); 11376 11377 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */ 11378 xops[0] = reg1; 11379 xops[1] = reg2; 11380 strcpy (tmp, "%(%<beq\t%0,%1,"); 11381 output_asm_insn (strcat (tmp, &end_lab[1]), xops); 11382 11383 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ 11384 xops[1] = GEN_INT (-PROBE_INTERVAL); 11385 if (TARGET_64BIT && TARGET_LONG64) 11386 output_asm_insn ("daddiu\t%0,%0,%1", xops); 11387 else 11388 output_asm_insn ("addiu\t%0,%0,%1", xops); 11389 11390 /* Probe at TEST_ADDR and branch. */ 11391 fprintf (asm_out_file, "\tb\t"); 11392 assemble_name_raw (asm_out_file, loop_lab); 11393 fputc ('\n', asm_out_file); 11394 if (TARGET_64BIT) 11395 output_asm_insn ("sd\t$0,0(%0)%)", xops); 11396 else 11397 output_asm_insn ("sw\t$0,0(%0)%)", xops); 11398 11399 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab); 11400 11401 return ""; 11402} 11403 11404/* Return true if X contains a kernel register. */ 11405 11406static bool 11407mips_refers_to_kernel_reg_p (const_rtx x) 11408{ 11409 subrtx_iterator::array_type array; 11410 FOR_EACH_SUBRTX (iter, array, x, NONCONST) 11411 if (REG_P (*iter) && KERNEL_REG_P (REGNO (*iter))) 11412 return true; 11413 return false; 11414} 11415 11416/* Expand the "prologue" pattern. */ 11417 11418void 11419mips_expand_prologue (void) 11420{ 11421 const struct mips_frame_info *frame; 11422 HOST_WIDE_INT size; 11423 unsigned int nargs; 11424 11425 if (cfun->machine->global_pointer != INVALID_REGNUM) 11426 { 11427 /* Check whether an insn uses pic_offset_table_rtx, either explicitly 11428 or implicitly. If so, we can commit to using a global pointer 11429 straight away, otherwise we need to defer the decision. */ 11430 if (mips_cfun_has_inflexible_gp_ref_p () 11431 || mips_cfun_has_flexible_gp_ref_p ()) 11432 { 11433 cfun->machine->must_initialize_gp_p = true; 11434 cfun->machine->must_restore_gp_when_clobbered_p = true; 11435 } 11436 11437 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); 11438 } 11439 11440 frame = &cfun->machine->frame; 11441 size = frame->total_size; 11442 11443 if (flag_stack_usage_info) 11444 current_function_static_stack_size = size; 11445 11446 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) 11447 { 11448 if (crtl->is_leaf && !cfun->calls_alloca) 11449 { 11450 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) 11451 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, 11452 size - STACK_CHECK_PROTECT); 11453 } 11454 else if (size > 0) 11455 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size); 11456 } 11457 11458 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP 11459 bytes beforehand; this is enough to cover the register save area 11460 without going out of range. */ 11461 if (((frame->mask | frame->fmask | frame->acc_mask) != 0) 11462 || frame->num_cop0_regs > 0) 11463 { 11464 HOST_WIDE_INT step1; 11465 11466 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); 11467 if (GENERATE_MIPS16E_SAVE_RESTORE) 11468 { 11469 HOST_WIDE_INT offset; 11470 unsigned int mask, regno; 11471 11472 /* Try to merge argument stores into the save instruction. */ 11473 nargs = mips16e_collect_argument_saves (); 11474 11475 /* Build the save instruction. */ 11476 mask = frame->mask; 11477 rtx insn = mips16e_build_save_restore (false, &mask, &offset, 11478 nargs, step1); 11479 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 11480 mips_frame_barrier (); 11481 size -= step1; 11482 11483 /* Check if we need to save other registers. */ 11484 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) 11485 if (BITSET_P (mask, regno - GP_REG_FIRST)) 11486 { 11487 offset -= UNITS_PER_WORD; 11488 mips_save_restore_reg (word_mode, regno, 11489 offset, mips_save_reg); 11490 } 11491 } 11492 else 11493 { 11494 if (cfun->machine->interrupt_handler_p) 11495 { 11496 HOST_WIDE_INT offset; 11497 rtx mem; 11498 11499 /* If this interrupt is using a shadow register set, we need to 11500 get the stack pointer from the previous register set. */ 11501 if (cfun->machine->use_shadow_register_set_p) 11502 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx, 11503 stack_pointer_rtx)); 11504 11505 if (!cfun->machine->keep_interrupts_masked_p) 11506 { 11507 /* Move from COP0 Cause to K0. */ 11508 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM), 11509 gen_rtx_REG (SImode, 11510 COP0_CAUSE_REG_NUM))); 11511 /* Move from COP0 EPC to K1. */ 11512 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), 11513 gen_rtx_REG (SImode, 11514 COP0_EPC_REG_NUM))); 11515 } 11516 11517 /* Allocate the first part of the frame. */ 11518 rtx insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 11519 GEN_INT (-step1)); 11520 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 11521 mips_frame_barrier (); 11522 size -= step1; 11523 11524 /* Start at the uppermost location for saving. */ 11525 offset = frame->cop0_sp_offset - size; 11526 if (!cfun->machine->keep_interrupts_masked_p) 11527 { 11528 /* Push EPC into its stack slot. */ 11529 mem = gen_frame_mem (word_mode, 11530 plus_constant (Pmode, stack_pointer_rtx, 11531 offset)); 11532 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); 11533 offset -= UNITS_PER_WORD; 11534 } 11535 11536 /* Move from COP0 Status to K1. */ 11537 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), 11538 gen_rtx_REG (SImode, 11539 COP0_STATUS_REG_NUM))); 11540 11541 /* Right justify the RIPL in k0. */ 11542 if (!cfun->machine->keep_interrupts_masked_p) 11543 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), 11544 gen_rtx_REG (SImode, K0_REG_NUM), 11545 GEN_INT (CAUSE_IPL))); 11546 11547 /* Push Status into its stack slot. */ 11548 mem = gen_frame_mem (word_mode, 11549 plus_constant (Pmode, stack_pointer_rtx, 11550 offset)); 11551 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); 11552 offset -= UNITS_PER_WORD; 11553 11554 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ 11555 if (!cfun->machine->keep_interrupts_masked_p) 11556 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), 11557 GEN_INT (6), 11558 GEN_INT (SR_IPL), 11559 gen_rtx_REG (SImode, K0_REG_NUM))); 11560 11561 if (!cfun->machine->keep_interrupts_masked_p) 11562 /* Enable interrupts by clearing the KSU ERL and EXL bits. 11563 IE is already the correct value, so we don't have to do 11564 anything explicit. */ 11565 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), 11566 GEN_INT (4), 11567 GEN_INT (SR_EXL), 11568 gen_rtx_REG (SImode, GP_REG_FIRST))); 11569 else 11570 /* Disable interrupts by clearing the KSU, ERL, EXL, 11571 and IE bits. */ 11572 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), 11573 GEN_INT (5), 11574 GEN_INT (SR_IE), 11575 gen_rtx_REG (SImode, GP_REG_FIRST))); 11576 } 11577 else 11578 { 11579 rtx insn = gen_add3_insn (stack_pointer_rtx, 11580 stack_pointer_rtx, 11581 GEN_INT (-step1)); 11582 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 11583 mips_frame_barrier (); 11584 size -= step1; 11585 } 11586 mips_for_each_saved_acc (size, mips_save_reg); 11587 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg); 11588 } 11589 } 11590 11591 /* Allocate the rest of the frame. */ 11592 if (size > 0) 11593 { 11594 if (SMALL_OPERAND (-size)) 11595 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, 11596 stack_pointer_rtx, 11597 GEN_INT (-size)))) = 1; 11598 else 11599 { 11600 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size)); 11601 if (TARGET_MIPS16) 11602 { 11603 /* There are no instructions to add or subtract registers 11604 from the stack pointer, so use the frame pointer as a 11605 temporary. We should always be using a frame pointer 11606 in this case anyway. */ 11607 gcc_assert (frame_pointer_needed); 11608 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); 11609 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx, 11610 hard_frame_pointer_rtx, 11611 MIPS_PROLOGUE_TEMP (Pmode))); 11612 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx); 11613 } 11614 else 11615 emit_insn (gen_sub3_insn (stack_pointer_rtx, 11616 stack_pointer_rtx, 11617 MIPS_PROLOGUE_TEMP (Pmode))); 11618 11619 /* Describe the combined effect of the previous instructions. */ 11620 mips_set_frame_expr 11621 (gen_rtx_SET (VOIDmode, stack_pointer_rtx, 11622 plus_constant (Pmode, stack_pointer_rtx, -size))); 11623 } 11624 mips_frame_barrier (); 11625 } 11626 11627 /* Set up the frame pointer, if we're using one. */ 11628 if (frame_pointer_needed) 11629 { 11630 HOST_WIDE_INT offset; 11631 11632 offset = frame->hard_frame_pointer_offset; 11633 if (offset == 0) 11634 { 11635 rtx insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); 11636 RTX_FRAME_RELATED_P (insn) = 1; 11637 } 11638 else if (SMALL_OPERAND (offset)) 11639 { 11640 rtx insn = gen_add3_insn (hard_frame_pointer_rtx, 11641 stack_pointer_rtx, GEN_INT (offset)); 11642 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 11643 } 11644 else 11645 { 11646 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset)); 11647 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); 11648 emit_insn (gen_add3_insn (hard_frame_pointer_rtx, 11649 hard_frame_pointer_rtx, 11650 MIPS_PROLOGUE_TEMP (Pmode))); 11651 mips_set_frame_expr 11652 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, 11653 plus_constant (Pmode, stack_pointer_rtx, offset))); 11654 } 11655 } 11656 11657 mips_emit_loadgp (); 11658 11659 /* Initialize the $gp save slot. */ 11660 if (mips_cfun_has_cprestore_slot_p ()) 11661 { 11662 rtx base, mem, gp, temp; 11663 HOST_WIDE_INT offset; 11664 11665 mips_get_cprestore_base_and_offset (&base, &offset, false); 11666 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset)); 11667 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; 11668 temp = (SMALL_OPERAND (offset) 11669 ? gen_rtx_SCRATCH (Pmode) 11670 : MIPS_PROLOGUE_TEMP (Pmode)); 11671 emit_insn (PMODE_INSN (gen_potential_cprestore, 11672 (mem, GEN_INT (offset), gp, temp))); 11673 11674 mips_get_cprestore_base_and_offset (&base, &offset, true); 11675 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset)); 11676 emit_insn (PMODE_INSN (gen_use_cprestore, (mem))); 11677 } 11678 11679 /* We need to search back to the last use of K0 or K1. */ 11680 if (cfun->machine->interrupt_handler_p) 11681 { 11682 rtx_insn *insn; 11683 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn)) 11684 if (INSN_P (insn) 11685 && mips_refers_to_kernel_reg_p (PATTERN (insn))) 11686 break; 11687 /* Emit a move from K1 to COP0 Status after insn. */ 11688 gcc_assert (insn != NULL_RTX); 11689 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), 11690 gen_rtx_REG (SImode, K1_REG_NUM)), 11691 insn); 11692 } 11693 11694 /* If we are profiling, make sure no instructions are scheduled before 11695 the call to mcount. */ 11696 if (crtl->profile) 11697 emit_insn (gen_blockage ()); 11698} 11699 11700/* Attach all pending register saves to the previous instruction. 11701 Return that instruction. */ 11702 11703static rtx_insn * 11704mips_epilogue_emit_cfa_restores (void) 11705{ 11706 rtx_insn *insn; 11707 11708 insn = get_last_insn (); 11709 gcc_assert (insn && !REG_NOTES (insn)); 11710 if (mips_epilogue.cfa_restores) 11711 { 11712 RTX_FRAME_RELATED_P (insn) = 1; 11713 REG_NOTES (insn) = mips_epilogue.cfa_restores; 11714 mips_epilogue.cfa_restores = 0; 11715 } 11716 return insn; 11717} 11718 11719/* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is 11720 now at REG + OFFSET. */ 11721 11722static void 11723mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset) 11724{ 11725 rtx_insn *insn; 11726 11727 insn = mips_epilogue_emit_cfa_restores (); 11728 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset) 11729 { 11730 RTX_FRAME_RELATED_P (insn) = 1; 11731 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, 11732 plus_constant (Pmode, reg, offset), 11733 REG_NOTES (insn)); 11734 mips_epilogue.cfa_reg = reg; 11735 mips_epilogue.cfa_offset = offset; 11736 } 11737} 11738 11739/* Emit instructions to restore register REG from slot MEM. Also update 11740 the cfa_restores list. */ 11741 11742static void 11743mips_restore_reg (rtx reg, rtx mem) 11744{ 11745 /* There's no MIPS16 instruction to load $31 directly. Load into 11746 $7 instead and adjust the return insn appropriately. */ 11747 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM) 11748 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7); 11749 else if (GET_MODE (reg) == DFmode 11750 && (!TARGET_FLOAT64 11751 || mips_abi == ABI_32)) 11752 { 11753 mips_add_cfa_restore (mips_subword (reg, true)); 11754 mips_add_cfa_restore (mips_subword (reg, false)); 11755 } 11756 else 11757 mips_add_cfa_restore (reg); 11758 11759 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg))); 11760 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg)) 11761 /* The CFA is currently defined in terms of the register whose 11762 value we have just restored. Redefine the CFA in terms of 11763 the stack pointer. */ 11764 mips_epilogue_set_cfa (stack_pointer_rtx, 11765 mips_epilogue.cfa_restore_sp_offset); 11766} 11767 11768/* Emit code to set the stack pointer to BASE + OFFSET, given that 11769 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame. 11770 BASE, if not the stack pointer, is available as a temporary. */ 11771 11772static void 11773mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size) 11774{ 11775 if (base == stack_pointer_rtx && offset == const0_rtx) 11776 return; 11777 11778 mips_frame_barrier (); 11779 if (offset == const0_rtx) 11780 { 11781 emit_move_insn (stack_pointer_rtx, base); 11782 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size); 11783 } 11784 else if (TARGET_MIPS16 && base != stack_pointer_rtx) 11785 { 11786 emit_insn (gen_add3_insn (base, base, offset)); 11787 mips_epilogue_set_cfa (base, new_frame_size); 11788 emit_move_insn (stack_pointer_rtx, base); 11789 } 11790 else 11791 { 11792 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset)); 11793 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size); 11794 } 11795} 11796 11797/* Emit any instructions needed before a return. */ 11798 11799void 11800mips_expand_before_return (void) 11801{ 11802 /* When using a call-clobbered gp, we start out with unified call 11803 insns that include instructions to restore the gp. We then split 11804 these unified calls after reload. These split calls explicitly 11805 clobber gp, so there is no need to define 11806 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED. 11807 11808 For consistency, we should also insert an explicit clobber of $28 11809 before return insns, so that the post-reload optimizers know that 11810 the register is not live on exit. */ 11811 if (TARGET_CALL_CLOBBERED_GP) 11812 emit_clobber (pic_offset_table_rtx); 11813} 11814 11815/* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P 11816 says which. */ 11817 11818void 11819mips_expand_epilogue (bool sibcall_p) 11820{ 11821 const struct mips_frame_info *frame; 11822 HOST_WIDE_INT step1, step2; 11823 rtx base, adjust; 11824 rtx_insn *insn; 11825 bool use_jraddiusp_p = false; 11826 11827 if (!sibcall_p && mips_can_use_return_insn ()) 11828 { 11829 emit_jump_insn (gen_return ()); 11830 return; 11831 } 11832 11833 /* In MIPS16 mode, if the return value should go into a floating-point 11834 register, we need to call a helper routine to copy it over. */ 11835 if (mips16_cfun_returns_in_fpr_p ()) 11836 mips16_copy_fpr_return_value (); 11837 11838 /* Split the frame into two. STEP1 is the amount of stack we should 11839 deallocate before restoring the registers. STEP2 is the amount we 11840 should deallocate afterwards. 11841 11842 Start off by assuming that no registers need to be restored. */ 11843 frame = &cfun->machine->frame; 11844 step1 = frame->total_size; 11845 step2 = 0; 11846 11847 /* Work out which register holds the frame address. */ 11848 if (!frame_pointer_needed) 11849 base = stack_pointer_rtx; 11850 else 11851 { 11852 base = hard_frame_pointer_rtx; 11853 step1 -= frame->hard_frame_pointer_offset; 11854 } 11855 mips_epilogue.cfa_reg = base; 11856 mips_epilogue.cfa_offset = step1; 11857 mips_epilogue.cfa_restores = NULL_RTX; 11858 11859 /* If we need to restore registers, deallocate as much stack as 11860 possible in the second step without going out of range. */ 11861 if ((frame->mask | frame->fmask | frame->acc_mask) != 0 11862 || frame->num_cop0_regs > 0) 11863 { 11864 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP); 11865 step1 -= step2; 11866 } 11867 11868 /* Get an rtx for STEP1 that we can add to BASE. */ 11869 adjust = GEN_INT (step1); 11870 if (!SMALL_OPERAND (step1)) 11871 { 11872 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust); 11873 adjust = MIPS_EPILOGUE_TEMP (Pmode); 11874 } 11875 mips_deallocate_stack (base, adjust, step2); 11876 11877 /* If we're using addressing macros, $gp is implicitly used by all 11878 SYMBOL_REFs. We must emit a blockage insn before restoring $gp 11879 from the stack. */ 11880 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS) 11881 emit_insn (gen_blockage ()); 11882 11883 mips_epilogue.cfa_restore_sp_offset = step2; 11884 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0) 11885 { 11886 unsigned int regno, mask; 11887 HOST_WIDE_INT offset; 11888 rtx restore; 11889 11890 /* Generate the restore instruction. */ 11891 mask = frame->mask; 11892 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2); 11893 11894 /* Restore any other registers manually. */ 11895 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) 11896 if (BITSET_P (mask, regno - GP_REG_FIRST)) 11897 { 11898 offset -= UNITS_PER_WORD; 11899 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg); 11900 } 11901 11902 /* Restore the remaining registers and deallocate the final bit 11903 of the frame. */ 11904 mips_frame_barrier (); 11905 emit_insn (restore); 11906 mips_epilogue_set_cfa (stack_pointer_rtx, 0); 11907 } 11908 else 11909 { 11910 /* Restore the registers. */ 11911 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg); 11912 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2, 11913 mips_restore_reg); 11914 11915 if (cfun->machine->interrupt_handler_p) 11916 { 11917 HOST_WIDE_INT offset; 11918 rtx mem; 11919 11920 offset = frame->cop0_sp_offset - (frame->total_size - step2); 11921 if (!cfun->machine->keep_interrupts_masked_p) 11922 { 11923 /* Restore the original EPC. */ 11924 mem = gen_frame_mem (word_mode, 11925 plus_constant (Pmode, stack_pointer_rtx, 11926 offset)); 11927 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); 11928 offset -= UNITS_PER_WORD; 11929 11930 /* Move to COP0 EPC. */ 11931 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM), 11932 gen_rtx_REG (SImode, K0_REG_NUM))); 11933 } 11934 11935 /* Restore the original Status. */ 11936 mem = gen_frame_mem (word_mode, 11937 plus_constant (Pmode, stack_pointer_rtx, 11938 offset)); 11939 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); 11940 offset -= UNITS_PER_WORD; 11941 11942 /* If we don't use shadow register set, we need to update SP. */ 11943 if (!cfun->machine->use_shadow_register_set_p) 11944 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0); 11945 else 11946 /* The choice of position is somewhat arbitrary in this case. */ 11947 mips_epilogue_emit_cfa_restores (); 11948 11949 /* Move to COP0 Status. */ 11950 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), 11951 gen_rtx_REG (SImode, K0_REG_NUM))); 11952 } 11953 else if (TARGET_MICROMIPS 11954 && !crtl->calls_eh_return 11955 && !sibcall_p 11956 && step2 > 0 11957 && mips_unsigned_immediate_p (step2, 5, 2)) 11958 use_jraddiusp_p = true; 11959 else 11960 /* Deallocate the final bit of the frame. */ 11961 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0); 11962 } 11963 11964 if (!use_jraddiusp_p) 11965 gcc_assert (!mips_epilogue.cfa_restores); 11966 11967 /* Add in the __builtin_eh_return stack adjustment. We need to 11968 use a temporary in MIPS16 code. */ 11969 if (crtl->calls_eh_return) 11970 { 11971 if (TARGET_MIPS16) 11972 { 11973 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx); 11974 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode), 11975 MIPS_EPILOGUE_TEMP (Pmode), 11976 EH_RETURN_STACKADJ_RTX)); 11977 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode)); 11978 } 11979 else 11980 emit_insn (gen_add3_insn (stack_pointer_rtx, 11981 stack_pointer_rtx, 11982 EH_RETURN_STACKADJ_RTX)); 11983 } 11984 11985 if (!sibcall_p) 11986 { 11987 mips_expand_before_return (); 11988 if (cfun->machine->interrupt_handler_p) 11989 { 11990 /* Interrupt handlers generate eret or deret. */ 11991 if (cfun->machine->use_debug_exception_return_p) 11992 emit_jump_insn (gen_mips_deret ()); 11993 else 11994 emit_jump_insn (gen_mips_eret ()); 11995 } 11996 else 11997 { 11998 rtx pat; 11999 12000 /* When generating MIPS16 code, the normal 12001 mips_for_each_saved_gpr_and_fpr path will restore the return 12002 address into $7 rather than $31. */ 12003 if (TARGET_MIPS16 12004 && !GENERATE_MIPS16E_SAVE_RESTORE 12005 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM)) 12006 { 12007 /* simple_returns cannot rely on values that are only available 12008 on paths through the epilogue (because return paths that do 12009 not pass through the epilogue may nevertheless reuse a 12010 simple_return that occurs at the end of the epilogue). 12011 Use a normal return here instead. */ 12012 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7); 12013 pat = gen_return_internal (reg); 12014 } 12015 else if (use_jraddiusp_p) 12016 pat = gen_jraddiusp (GEN_INT (step2)); 12017 else 12018 { 12019 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 12020 pat = gen_simple_return_internal (reg); 12021 } 12022 emit_jump_insn (pat); 12023 if (use_jraddiusp_p) 12024 mips_epilogue_set_cfa (stack_pointer_rtx, step2); 12025 } 12026 } 12027 12028 /* Search from the beginning to the first use of K0 or K1. */ 12029 if (cfun->machine->interrupt_handler_p 12030 && !cfun->machine->keep_interrupts_masked_p) 12031 { 12032 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) 12033 if (INSN_P (insn) 12034 && mips_refers_to_kernel_reg_p (PATTERN (insn))) 12035 break; 12036 gcc_assert (insn != NULL_RTX); 12037 /* Insert disable interrupts before the first use of K0 or K1. */ 12038 emit_insn_before (gen_mips_di (), insn); 12039 emit_insn_before (gen_mips_ehb (), insn); 12040 } 12041} 12042 12043/* Return nonzero if this function is known to have a null epilogue. 12044 This allows the optimizer to omit jumps to jumps if no stack 12045 was created. */ 12046 12047bool 12048mips_can_use_return_insn (void) 12049{ 12050 /* Interrupt handlers need to go through the epilogue. */ 12051 if (cfun->machine->interrupt_handler_p) 12052 return false; 12053 12054 if (!reload_completed) 12055 return false; 12056 12057 if (crtl->profile) 12058 return false; 12059 12060 /* In MIPS16 mode, a function that returns a floating-point value 12061 needs to arrange to copy the return value into the floating-point 12062 registers. */ 12063 if (mips16_cfun_returns_in_fpr_p ()) 12064 return false; 12065 12066 return cfun->machine->frame.total_size == 0; 12067} 12068 12069/* Return true if register REGNO can store a value of mode MODE. 12070 The result of this function is cached in mips_hard_regno_mode_ok. */ 12071 12072static bool 12073mips_hard_regno_mode_ok_p (unsigned int regno, machine_mode mode) 12074{ 12075 unsigned int size; 12076 enum mode_class mclass; 12077 12078 if (mode == CCV2mode) 12079 return (ISA_HAS_8CC 12080 && ST_REG_P (regno) 12081 && (regno - ST_REG_FIRST) % 2 == 0); 12082 12083 if (mode == CCV4mode) 12084 return (ISA_HAS_8CC 12085 && ST_REG_P (regno) 12086 && (regno - ST_REG_FIRST) % 4 == 0); 12087 12088 if (mode == CCmode) 12089 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM; 12090 12091 size = GET_MODE_SIZE (mode); 12092 mclass = GET_MODE_CLASS (mode); 12093 12094 if (GP_REG_P (regno) && mode != CCFmode) 12095 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; 12096 12097 if (FP_REG_P (regno) 12098 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0 12099 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG))) 12100 { 12101 /* Deny use of odd-numbered registers for 32-bit data for 12102 the o32 FP64A ABI. */ 12103 if (TARGET_O32_FP64A_ABI && size <= 4 && (regno & 1) != 0) 12104 return false; 12105 12106 /* The FPXX ABI requires double-precision values to be placed in 12107 even-numbered registers. Disallow odd-numbered registers with 12108 CCFmode because CCFmode double-precision compares will write a 12109 64-bit value to a register. */ 12110 if (mode == CCFmode) 12111 return !(TARGET_FLOATXX && (regno & 1) != 0); 12112 12113 /* Allow 64-bit vector modes for Loongson-2E/2F. */ 12114 if (TARGET_LOONGSON_VECTORS 12115 && (mode == V2SImode 12116 || mode == V4HImode 12117 || mode == V8QImode 12118 || mode == DImode)) 12119 return true; 12120 12121 if (mclass == MODE_FLOAT 12122 || mclass == MODE_COMPLEX_FLOAT 12123 || mclass == MODE_VECTOR_FLOAT) 12124 return size <= UNITS_PER_FPVALUE; 12125 12126 /* Allow integer modes that fit into a single register. We need 12127 to put integers into FPRs when using instructions like CVT 12128 and TRUNC. There's no point allowing sizes smaller than a word, 12129 because the FPU has no appropriate load/store instructions. */ 12130 if (mclass == MODE_INT) 12131 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG; 12132 } 12133 12134 /* Don't allow vector modes in accumulators. */ 12135 if (ACC_REG_P (regno) 12136 && !VECTOR_MODE_P (mode) 12137 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) 12138 { 12139 if (MD_REG_P (regno)) 12140 { 12141 /* After a multiplication or division, clobbering HI makes 12142 the value of LO unpredictable, and vice versa. This means 12143 that, for all interesting cases, HI and LO are effectively 12144 a single register. 12145 12146 We model this by requiring that any value that uses HI 12147 also uses LO. */ 12148 if (size <= UNITS_PER_WORD * 2) 12149 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); 12150 } 12151 else 12152 { 12153 /* DSP accumulators do not have the same restrictions as 12154 HI and LO, so we can treat them as normal doubleword 12155 registers. */ 12156 if (size <= UNITS_PER_WORD) 12157 return true; 12158 12159 if (size <= UNITS_PER_WORD * 2 12160 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) 12161 return true; 12162 } 12163 } 12164 12165 if (ALL_COP_REG_P (regno)) 12166 return mclass == MODE_INT && size <= UNITS_PER_WORD; 12167 12168 if (regno == GOT_VERSION_REGNUM) 12169 return mode == SImode; 12170 12171 return false; 12172} 12173 12174/* Implement HARD_REGNO_NREGS. */ 12175 12176unsigned int 12177mips_hard_regno_nregs (int regno, machine_mode mode) 12178{ 12179 if (ST_REG_P (regno)) 12180 /* The size of FP status registers is always 4, because they only hold 12181 CCmode values, and CCmode is always considered to be 4 bytes wide. */ 12182 return (GET_MODE_SIZE (mode) + 3) / 4; 12183 12184 if (FP_REG_P (regno)) 12185 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; 12186 12187 /* All other registers are word-sized. */ 12188 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 12189} 12190 12191/* Implement CLASS_MAX_NREGS, taking the maximum of the cases 12192 in mips_hard_regno_nregs. */ 12193 12194int 12195mips_class_max_nregs (enum reg_class rclass, machine_mode mode) 12196{ 12197 int size; 12198 HARD_REG_SET left; 12199 12200 size = 0x8000; 12201 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); 12202 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) 12203 { 12204 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode)) 12205 size = MIN (size, 4); 12206 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); 12207 } 12208 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) 12209 { 12210 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode)) 12211 size = MIN (size, UNITS_PER_FPREG); 12212 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); 12213 } 12214 if (!hard_reg_set_empty_p (left)) 12215 size = MIN (size, UNITS_PER_WORD); 12216 return (GET_MODE_SIZE (mode) + size - 1) / size; 12217} 12218 12219/* Implement CANNOT_CHANGE_MODE_CLASS. */ 12220 12221bool 12222mips_cannot_change_mode_class (machine_mode from, 12223 machine_mode to, 12224 enum reg_class rclass) 12225{ 12226 /* Allow conversions between different Loongson integer vectors, 12227 and between those vectors and DImode. */ 12228 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8 12229 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to)) 12230 return false; 12231 12232 /* Otherwise, there are several problems with changing the modes of 12233 values in floating-point registers: 12234 12235 - When a multi-word value is stored in paired floating-point 12236 registers, the first register always holds the low word. We 12237 therefore can't allow FPRs to change between single-word and 12238 multi-word modes on big-endian targets. 12239 12240 - GCC assumes that each word of a multiword register can be 12241 accessed individually using SUBREGs. This is not true for 12242 floating-point registers if they are bigger than a word. 12243 12244 - Loading a 32-bit value into a 64-bit floating-point register 12245 will not sign-extend the value, despite what LOAD_EXTEND_OP 12246 says. We can't allow FPRs to change from SImode to a wider 12247 mode on 64-bit targets. 12248 12249 - If the FPU has already interpreted a value in one format, we 12250 must not ask it to treat the value as having a different 12251 format. 12252 12253 We therefore disallow all mode changes involving FPRs. */ 12254 12255 return reg_classes_intersect_p (FP_REGS, rclass); 12256} 12257 12258/* Implement target hook small_register_classes_for_mode_p. */ 12259 12260static bool 12261mips_small_register_classes_for_mode_p (machine_mode mode 12262 ATTRIBUTE_UNUSED) 12263{ 12264 return TARGET_MIPS16; 12265} 12266 12267/* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */ 12268 12269static bool 12270mips_mode_ok_for_mov_fmt_p (machine_mode mode) 12271{ 12272 switch (mode) 12273 { 12274 case CCFmode: 12275 case SFmode: 12276 return TARGET_HARD_FLOAT; 12277 12278 case DFmode: 12279 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT; 12280 12281 case V2SFmode: 12282 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT; 12283 12284 default: 12285 return false; 12286 } 12287} 12288 12289/* Implement MODES_TIEABLE_P. */ 12290 12291bool 12292mips_modes_tieable_p (machine_mode mode1, machine_mode mode2) 12293{ 12294 /* FPRs allow no mode punning, so it's not worth tying modes if we'd 12295 prefer to put one of them in FPRs. */ 12296 return (mode1 == mode2 12297 || (!mips_mode_ok_for_mov_fmt_p (mode1) 12298 && !mips_mode_ok_for_mov_fmt_p (mode2))); 12299} 12300 12301/* Implement TARGET_PREFERRED_RELOAD_CLASS. */ 12302 12303static reg_class_t 12304mips_preferred_reload_class (rtx x, reg_class_t rclass) 12305{ 12306 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass)) 12307 return LEA_REGS; 12308 12309 if (reg_class_subset_p (FP_REGS, rclass) 12310 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x))) 12311 return FP_REGS; 12312 12313 if (reg_class_subset_p (GR_REGS, rclass)) 12314 rclass = GR_REGS; 12315 12316 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass)) 12317 rclass = M16_REGS; 12318 12319 return rclass; 12320} 12321 12322/* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. 12323 Return a "canonical" class to represent it in later calculations. */ 12324 12325static reg_class_t 12326mips_canonicalize_move_class (reg_class_t rclass) 12327{ 12328 /* All moves involving accumulator registers have the same cost. */ 12329 if (reg_class_subset_p (rclass, ACC_REGS)) 12330 rclass = ACC_REGS; 12331 12332 /* Likewise promote subclasses of general registers to the most 12333 interesting containing class. */ 12334 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS)) 12335 rclass = M16_REGS; 12336 else if (reg_class_subset_p (rclass, GENERAL_REGS)) 12337 rclass = GENERAL_REGS; 12338 12339 return rclass; 12340} 12341 12342/* Return the cost of moving a value from a register of class FROM to a GPR. 12343 Return 0 for classes that are unions of other classes handled by this 12344 function. */ 12345 12346static int 12347mips_move_to_gpr_cost (reg_class_t from) 12348{ 12349 switch (from) 12350 { 12351 case M16_REGS: 12352 case GENERAL_REGS: 12353 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ 12354 return 2; 12355 12356 case ACC_REGS: 12357 /* MFLO and MFHI. */ 12358 return 6; 12359 12360 case FP_REGS: 12361 /* MFC1, etc. */ 12362 return 4; 12363 12364 case COP0_REGS: 12365 case COP2_REGS: 12366 case COP3_REGS: 12367 /* This choice of value is historical. */ 12368 return 5; 12369 12370 default: 12371 return 0; 12372 } 12373} 12374 12375/* Return the cost of moving a value from a GPR to a register of class TO. 12376 Return 0 for classes that are unions of other classes handled by this 12377 function. */ 12378 12379static int 12380mips_move_from_gpr_cost (reg_class_t to) 12381{ 12382 switch (to) 12383 { 12384 case M16_REGS: 12385 case GENERAL_REGS: 12386 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ 12387 return 2; 12388 12389 case ACC_REGS: 12390 /* MTLO and MTHI. */ 12391 return 6; 12392 12393 case FP_REGS: 12394 /* MTC1, etc. */ 12395 return 4; 12396 12397 case COP0_REGS: 12398 case COP2_REGS: 12399 case COP3_REGS: 12400 /* This choice of value is historical. */ 12401 return 5; 12402 12403 default: 12404 return 0; 12405 } 12406} 12407 12408/* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the 12409 maximum of the move costs for subclasses; regclass will work out 12410 the maximum for us. */ 12411 12412static int 12413mips_register_move_cost (machine_mode mode, 12414 reg_class_t from, reg_class_t to) 12415{ 12416 reg_class_t dregs; 12417 int cost1, cost2; 12418 12419 from = mips_canonicalize_move_class (from); 12420 to = mips_canonicalize_move_class (to); 12421 12422 /* Handle moves that can be done without using general-purpose registers. */ 12423 if (from == FP_REGS) 12424 { 12425 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode)) 12426 /* MOV.FMT. */ 12427 return 4; 12428 } 12429 12430 /* Handle cases in which only one class deviates from the ideal. */ 12431 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS; 12432 if (from == dregs) 12433 return mips_move_from_gpr_cost (to); 12434 if (to == dregs) 12435 return mips_move_to_gpr_cost (from); 12436 12437 /* Handles cases that require a GPR temporary. */ 12438 cost1 = mips_move_to_gpr_cost (from); 12439 if (cost1 != 0) 12440 { 12441 cost2 = mips_move_from_gpr_cost (to); 12442 if (cost2 != 0) 12443 return cost1 + cost2; 12444 } 12445 12446 return 0; 12447} 12448 12449/* Implement TARGET_REGISTER_PRIORITY. */ 12450 12451static int 12452mips_register_priority (int hard_regno) 12453{ 12454 /* Treat MIPS16 registers with higher priority than other regs. */ 12455 if (TARGET_MIPS16 12456 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno)) 12457 return 1; 12458 return 0; 12459} 12460 12461/* Implement TARGET_MEMORY_MOVE_COST. */ 12462 12463static int 12464mips_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) 12465{ 12466 return (mips_cost->memory_latency 12467 + memory_move_secondary_cost (mode, rclass, in)); 12468} 12469 12470/* Implement SECONDARY_MEMORY_NEEDED. */ 12471 12472bool 12473mips_secondary_memory_needed (enum reg_class class1, enum reg_class class2, 12474 machine_mode mode) 12475{ 12476 /* Ignore spilled pseudos. */ 12477 if (lra_in_progress && (class1 == NO_REGS || class2 == NO_REGS)) 12478 return false; 12479 12480 if (((class1 == FP_REGS) != (class2 == FP_REGS)) 12481 && ((TARGET_FLOATXX && !ISA_HAS_MXHC1) 12482 || TARGET_O32_FP64A_ABI) 12483 && GET_MODE_SIZE (mode) >= 8) 12484 return true; 12485 12486 return false; 12487} 12488 12489/* Return the register class required for a secondary register when 12490 copying between one of the registers in RCLASS and value X, which 12491 has mode MODE. X is the source of the move if IN_P, otherwise it 12492 is the destination. Return NO_REGS if no secondary register is 12493 needed. */ 12494 12495enum reg_class 12496mips_secondary_reload_class (enum reg_class rclass, 12497 machine_mode mode, rtx x, bool) 12498{ 12499 int regno; 12500 12501 /* If X is a constant that cannot be loaded into $25, it must be loaded 12502 into some other GPR. No other register class allows a direct move. */ 12503 if (mips_dangerous_for_la25_p (x)) 12504 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS; 12505 12506 regno = true_regnum (x); 12507 if (TARGET_MIPS16) 12508 { 12509 /* In MIPS16 mode, every move must involve a member of M16_REGS. */ 12510 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno)) 12511 return M16_REGS; 12512 12513 return NO_REGS; 12514 } 12515 12516 /* Copying from accumulator registers to anywhere other than a general 12517 register requires a temporary general register. */ 12518 if (reg_class_subset_p (rclass, ACC_REGS)) 12519 return GP_REG_P (regno) ? NO_REGS : GR_REGS; 12520 if (ACC_REG_P (regno)) 12521 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; 12522 12523 if (reg_class_subset_p (rclass, FP_REGS)) 12524 { 12525 if (regno < 0 12526 || (MEM_P (x) 12527 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))) 12528 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use 12529 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */ 12530 return NO_REGS; 12531 12532 if (GP_REG_P (regno) || x == CONST0_RTX (mode)) 12533 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */ 12534 return NO_REGS; 12535 12536 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x)) 12537 /* We can force the constant to memory and use lwc1 12538 and ldc1. As above, we will use pairs of lwc1s if 12539 ldc1 is not supported. */ 12540 return NO_REGS; 12541 12542 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode)) 12543 /* In this case we can use mov.fmt. */ 12544 return NO_REGS; 12545 12546 /* Otherwise, we need to reload through an integer register. */ 12547 return GR_REGS; 12548 } 12549 if (FP_REG_P (regno)) 12550 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; 12551 12552 return NO_REGS; 12553} 12554 12555/* Implement TARGET_MODE_REP_EXTENDED. */ 12556 12557static int 12558mips_mode_rep_extended (machine_mode mode, machine_mode mode_rep) 12559{ 12560 /* On 64-bit targets, SImode register values are sign-extended to DImode. */ 12561 if (TARGET_64BIT && mode == SImode && mode_rep == DImode) 12562 return SIGN_EXTEND; 12563 12564 return UNKNOWN; 12565} 12566 12567/* Implement TARGET_VALID_POINTER_MODE. */ 12568 12569static bool 12570mips_valid_pointer_mode (machine_mode mode) 12571{ 12572 return mode == SImode || (TARGET_64BIT && mode == DImode); 12573} 12574 12575/* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */ 12576 12577static bool 12578mips_vector_mode_supported_p (machine_mode mode) 12579{ 12580 switch (mode) 12581 { 12582 case V2SFmode: 12583 return TARGET_PAIRED_SINGLE_FLOAT; 12584 12585 case V2HImode: 12586 case V4QImode: 12587 case V2HQmode: 12588 case V2UHQmode: 12589 case V2HAmode: 12590 case V2UHAmode: 12591 case V4QQmode: 12592 case V4UQQmode: 12593 return TARGET_DSP; 12594 12595 case V2SImode: 12596 case V4HImode: 12597 case V8QImode: 12598 return TARGET_LOONGSON_VECTORS; 12599 12600 default: 12601 return false; 12602 } 12603} 12604 12605/* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ 12606 12607static bool 12608mips_scalar_mode_supported_p (machine_mode mode) 12609{ 12610 if (ALL_FIXED_POINT_MODE_P (mode) 12611 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) 12612 return true; 12613 12614 return default_scalar_mode_supported_p (mode); 12615} 12616 12617/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ 12618 12619static machine_mode 12620mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED) 12621{ 12622 if (TARGET_PAIRED_SINGLE_FLOAT 12623 && mode == SFmode) 12624 return V2SFmode; 12625 return word_mode; 12626} 12627 12628/* Implement TARGET_INIT_LIBFUNCS. */ 12629 12630static void 12631mips_init_libfuncs (void) 12632{ 12633 if (TARGET_FIX_VR4120) 12634 { 12635 /* Register the special divsi3 and modsi3 functions needed to work 12636 around VR4120 division errata. */ 12637 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); 12638 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); 12639 } 12640 12641 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI) 12642 { 12643 /* Register the MIPS16 -mhard-float stubs. */ 12644 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3"); 12645 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3"); 12646 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3"); 12647 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3"); 12648 12649 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2"); 12650 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2"); 12651 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2"); 12652 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2"); 12653 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2"); 12654 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2"); 12655 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2"); 12656 12657 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi"); 12658 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf"); 12659 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf"); 12660 12661 if (TARGET_DOUBLE_FLOAT) 12662 { 12663 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3"); 12664 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3"); 12665 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3"); 12666 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3"); 12667 12668 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2"); 12669 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2"); 12670 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2"); 12671 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2"); 12672 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2"); 12673 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2"); 12674 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2"); 12675 12676 set_conv_libfunc (sext_optab, DFmode, SFmode, 12677 "__mips16_extendsfdf2"); 12678 set_conv_libfunc (trunc_optab, SFmode, DFmode, 12679 "__mips16_truncdfsf2"); 12680 set_conv_libfunc (sfix_optab, SImode, DFmode, 12681 "__mips16_fix_truncdfsi"); 12682 set_conv_libfunc (sfloat_optab, DFmode, SImode, 12683 "__mips16_floatsidf"); 12684 set_conv_libfunc (ufloat_optab, DFmode, SImode, 12685 "__mips16_floatunsidf"); 12686 } 12687 } 12688 12689 /* The MIPS16 ISA does not have an encoding for "sync", so we rely 12690 on an external non-MIPS16 routine to implement __sync_synchronize. 12691 Similarly for the rest of the ll/sc libfuncs. */ 12692 if (TARGET_MIPS16) 12693 { 12694 synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); 12695 init_sync_libfuncs (UNITS_PER_WORD); 12696 } 12697} 12698 12699/* Build up a multi-insn sequence that loads label TARGET into $AT. */ 12700 12701static void 12702mips_process_load_label (rtx target) 12703{ 12704 rtx base, gp, intop; 12705 HOST_WIDE_INT offset; 12706 12707 mips_multi_start (); 12708 switch (mips_abi) 12709 { 12710 case ABI_N32: 12711 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0); 12712 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0); 12713 break; 12714 12715 case ABI_64: 12716 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0); 12717 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0); 12718 break; 12719 12720 default: 12721 gp = pic_offset_table_rtx; 12722 if (mips_cfun_has_cprestore_slot_p ()) 12723 { 12724 gp = gen_rtx_REG (Pmode, AT_REGNUM); 12725 mips_get_cprestore_base_and_offset (&base, &offset, true); 12726 if (!SMALL_OPERAND (offset)) 12727 { 12728 intop = GEN_INT (CONST_HIGH_PART (offset)); 12729 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0); 12730 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0); 12731 12732 base = gp; 12733 offset = CONST_LOW_PART (offset); 12734 } 12735 intop = GEN_INT (offset); 12736 if (ISA_HAS_LOAD_DELAY) 12737 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0); 12738 else 12739 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0); 12740 } 12741 if (ISA_HAS_LOAD_DELAY) 12742 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0); 12743 else 12744 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0); 12745 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0); 12746 break; 12747 } 12748} 12749 12750/* Return the number of instructions needed to load a label into $AT. */ 12751 12752static unsigned int 12753mips_load_label_num_insns (void) 12754{ 12755 if (cfun->machine->load_label_num_insns == 0) 12756 { 12757 mips_process_load_label (pc_rtx); 12758 cfun->machine->load_label_num_insns = mips_multi_num_insns; 12759 } 12760 return cfun->machine->load_label_num_insns; 12761} 12762 12763/* Emit an asm sequence to start a noat block and load the address 12764 of a label into $1. */ 12765 12766void 12767mips_output_load_label (rtx target) 12768{ 12769 mips_push_asm_switch (&mips_noat); 12770 if (TARGET_EXPLICIT_RELOCS) 12771 { 12772 mips_process_load_label (target); 12773 mips_multi_write (); 12774 } 12775 else 12776 { 12777 if (Pmode == DImode) 12778 output_asm_insn ("dla\t%@,%0", &target); 12779 else 12780 output_asm_insn ("la\t%@,%0", &target); 12781 } 12782} 12783 12784/* Return the length of INSN. LENGTH is the initial length computed by 12785 attributes in the machine-description file. */ 12786 12787int 12788mips_adjust_insn_length (rtx_insn *insn, int length) 12789{ 12790 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length 12791 of a PIC long-branch sequence. Substitute the correct value. */ 12792 if (length == MAX_PIC_BRANCH_LENGTH 12793 && JUMP_P (insn) 12794 && INSN_CODE (insn) >= 0 12795 && get_attr_type (insn) == TYPE_BRANCH) 12796 { 12797 /* Add the branch-over instruction and its delay slot, if this 12798 is a conditional branch. */ 12799 length = simplejump_p (insn) ? 0 : 8; 12800 12801 /* Add the size of a load into $AT. */ 12802 length += BASE_INSN_LENGTH * mips_load_label_num_insns (); 12803 12804 /* Add the length of an indirect jump, ignoring the delay slot. */ 12805 length += TARGET_COMPRESSION ? 2 : 4; 12806 } 12807 12808 /* A unconditional jump has an unfilled delay slot if it is not part 12809 of a sequence. A conditional jump normally has a delay slot, but 12810 does not on MIPS16. */ 12811 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn))) 12812 length += TARGET_MIPS16 ? 2 : 4; 12813 12814 /* See how many nops might be needed to avoid hardware hazards. */ 12815 if (!cfun->machine->ignore_hazard_length_p 12816 && INSN_P (insn) 12817 && INSN_CODE (insn) >= 0) 12818 switch (get_attr_hazard (insn)) 12819 { 12820 case HAZARD_NONE: 12821 break; 12822 12823 case HAZARD_DELAY: 12824 length += NOP_INSN_LENGTH; 12825 break; 12826 12827 case HAZARD_HILO: 12828 length += NOP_INSN_LENGTH * 2; 12829 break; 12830 } 12831 12832 return length; 12833} 12834 12835/* Return the assembly code for INSN, which has the operands given by 12836 OPERANDS, and which branches to OPERANDS[0] if some condition is true. 12837 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0] 12838 is in range of a direct branch. BRANCH_IF_FALSE is an inverted 12839 version of BRANCH_IF_TRUE. */ 12840 12841const char * 12842mips_output_conditional_branch (rtx_insn *insn, rtx *operands, 12843 const char *branch_if_true, 12844 const char *branch_if_false) 12845{ 12846 unsigned int length; 12847 rtx taken; 12848 12849 gcc_assert (LABEL_P (operands[0])); 12850 12851 length = get_attr_length (insn); 12852 if (length <= 8) 12853 { 12854 /* Just a simple conditional branch. */ 12855 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); 12856 return branch_if_true; 12857 } 12858 12859 /* Generate a reversed branch around a direct jump. This fallback does 12860 not use branch-likely instructions. */ 12861 mips_branch_likely = false; 12862 rtx_code_label *not_taken = gen_label_rtx (); 12863 taken = operands[0]; 12864 12865 /* Generate the reversed branch to NOT_TAKEN. */ 12866 operands[0] = not_taken; 12867 output_asm_insn (branch_if_false, operands); 12868 12869 /* If INSN has a delay slot, we must provide delay slots for both the 12870 branch to NOT_TAKEN and the conditional jump. We must also ensure 12871 that INSN's delay slot is executed in the appropriate cases. */ 12872 if (final_sequence) 12873 { 12874 /* This first delay slot will always be executed, so use INSN's 12875 delay slot if is not annulled. */ 12876 if (!INSN_ANNULLED_BRANCH_P (insn)) 12877 { 12878 final_scan_insn (final_sequence->insn (1), 12879 asm_out_file, optimize, 1, NULL); 12880 final_sequence->insn (1)->set_deleted (); 12881 } 12882 else 12883 output_asm_insn ("nop", 0); 12884 fprintf (asm_out_file, "\n"); 12885 } 12886 12887 /* Output the unconditional branch to TAKEN. */ 12888 if (TARGET_ABSOLUTE_JUMPS) 12889 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken); 12890 else 12891 { 12892 mips_output_load_label (taken); 12893 output_asm_insn ("jr\t%@%]%/", 0); 12894 } 12895 12896 /* Now deal with its delay slot; see above. */ 12897 if (final_sequence) 12898 { 12899 /* This delay slot will only be executed if the branch is taken. 12900 Use INSN's delay slot if is annulled. */ 12901 if (INSN_ANNULLED_BRANCH_P (insn)) 12902 { 12903 final_scan_insn (final_sequence->insn (1), 12904 asm_out_file, optimize, 1, NULL); 12905 final_sequence->insn (1)->set_deleted (); 12906 } 12907 else 12908 output_asm_insn ("nop", 0); 12909 fprintf (asm_out_file, "\n"); 12910 } 12911 12912 /* Output NOT_TAKEN. */ 12913 targetm.asm_out.internal_label (asm_out_file, "L", 12914 CODE_LABEL_NUMBER (not_taken)); 12915 return ""; 12916} 12917 12918/* Return the assembly code for INSN, which branches to OPERANDS[0] 12919 if some ordering condition is true. The condition is given by 12920 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of 12921 OPERANDS[1]. OPERANDS[2] is the comparison's first operand; 12922 its second is always zero. */ 12923 12924const char * 12925mips_output_order_conditional_branch (rtx_insn *insn, rtx *operands, bool inverted_p) 12926{ 12927 const char *branch[2]; 12928 12929 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true. 12930 Make BRANCH[0] branch on the inverse condition. */ 12931 switch (GET_CODE (operands[1])) 12932 { 12933 /* These cases are equivalent to comparisons against zero. */ 12934 case LEU: 12935 inverted_p = !inverted_p; 12936 /* Fall through. */ 12937 case GTU: 12938 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0"); 12939 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0"); 12940 break; 12941 12942 /* These cases are always true or always false. */ 12943 case LTU: 12944 inverted_p = !inverted_p; 12945 /* Fall through. */ 12946 case GEU: 12947 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0"); 12948 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0"); 12949 break; 12950 12951 default: 12952 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0"); 12953 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0"); 12954 break; 12955 } 12956 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); 12957} 12958 12959/* Start a block of code that needs access to the LL, SC and SYNC 12960 instructions. */ 12961 12962static void 12963mips_start_ll_sc_sync_block (void) 12964{ 12965 if (!ISA_HAS_LL_SC) 12966 { 12967 output_asm_insn (".set\tpush", 0); 12968 if (TARGET_64BIT) 12969 output_asm_insn (".set\tmips3", 0); 12970 else 12971 output_asm_insn (".set\tmips2", 0); 12972 } 12973} 12974 12975/* End a block started by mips_start_ll_sc_sync_block. */ 12976 12977static void 12978mips_end_ll_sc_sync_block (void) 12979{ 12980 if (!ISA_HAS_LL_SC) 12981 output_asm_insn (".set\tpop", 0); 12982} 12983 12984/* Output and/or return the asm template for a sync instruction. */ 12985 12986const char * 12987mips_output_sync (void) 12988{ 12989 mips_start_ll_sc_sync_block (); 12990 output_asm_insn ("sync", 0); 12991 mips_end_ll_sc_sync_block (); 12992 return ""; 12993} 12994 12995/* Return the asm template associated with sync_insn1 value TYPE. 12996 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */ 12997 12998static const char * 12999mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p) 13000{ 13001 switch (type) 13002 { 13003 case SYNC_INSN1_MOVE: 13004 return "move\t%0,%z2"; 13005 case SYNC_INSN1_LI: 13006 return "li\t%0,%2"; 13007 case SYNC_INSN1_ADDU: 13008 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2"; 13009 case SYNC_INSN1_ADDIU: 13010 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2"; 13011 case SYNC_INSN1_SUBU: 13012 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2"; 13013 case SYNC_INSN1_AND: 13014 return "and\t%0,%1,%z2"; 13015 case SYNC_INSN1_ANDI: 13016 return "andi\t%0,%1,%2"; 13017 case SYNC_INSN1_OR: 13018 return "or\t%0,%1,%z2"; 13019 case SYNC_INSN1_ORI: 13020 return "ori\t%0,%1,%2"; 13021 case SYNC_INSN1_XOR: 13022 return "xor\t%0,%1,%z2"; 13023 case SYNC_INSN1_XORI: 13024 return "xori\t%0,%1,%2"; 13025 } 13026 gcc_unreachable (); 13027} 13028 13029/* Return the asm template associated with sync_insn2 value TYPE. */ 13030 13031static const char * 13032mips_sync_insn2_template (enum attr_sync_insn2 type) 13033{ 13034 switch (type) 13035 { 13036 case SYNC_INSN2_NOP: 13037 gcc_unreachable (); 13038 case SYNC_INSN2_AND: 13039 return "and\t%0,%1,%z2"; 13040 case SYNC_INSN2_XOR: 13041 return "xor\t%0,%1,%z2"; 13042 case SYNC_INSN2_NOT: 13043 return "nor\t%0,%1,%."; 13044 } 13045 gcc_unreachable (); 13046} 13047 13048/* OPERANDS are the operands to a sync loop instruction and INDEX is 13049 the value of the one of the sync_* attributes. Return the operand 13050 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't 13051 have the associated attribute. */ 13052 13053static rtx 13054mips_get_sync_operand (rtx *operands, int index, rtx default_value) 13055{ 13056 if (index > 0) 13057 default_value = operands[index - 1]; 13058 return default_value; 13059} 13060 13061/* INSN is a sync loop with operands OPERANDS. Build up a multi-insn 13062 sequence for it. */ 13063 13064static void 13065mips_process_sync_loop (rtx_insn *insn, rtx *operands) 13066{ 13067 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask; 13068 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp; 13069 unsigned int tmp3_insn; 13070 enum attr_sync_insn1 insn1; 13071 enum attr_sync_insn2 insn2; 13072 bool is_64bit_p; 13073 int memmodel_attr; 13074 enum memmodel model; 13075 13076 /* Read an operand from the sync_WHAT attribute and store it in 13077 variable WHAT. DEFAULT is the default value if no attribute 13078 is specified. */ 13079#define READ_OPERAND(WHAT, DEFAULT) \ 13080 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \ 13081 DEFAULT) 13082 13083 /* Read the memory. */ 13084 READ_OPERAND (mem, 0); 13085 gcc_assert (mem); 13086 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64); 13087 13088 /* Read the other attributes. */ 13089 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM); 13090 READ_OPERAND (oldval, at); 13091 READ_OPERAND (cmp, 0); 13092 READ_OPERAND (newval, at); 13093 READ_OPERAND (inclusive_mask, 0); 13094 READ_OPERAND (exclusive_mask, 0); 13095 READ_OPERAND (required_oldval, 0); 13096 READ_OPERAND (insn1_op2, 0); 13097 insn1 = get_attr_sync_insn1 (insn); 13098 insn2 = get_attr_sync_insn2 (insn); 13099 13100 /* Don't bother setting CMP result that is never used. */ 13101 if (cmp && find_reg_note (insn, REG_UNUSED, cmp)) 13102 cmp = 0; 13103 13104 memmodel_attr = get_attr_sync_memmodel (insn); 13105 switch (memmodel_attr) 13106 { 13107 case 10: 13108 model = MEMMODEL_ACQ_REL; 13109 break; 13110 case 11: 13111 model = MEMMODEL_ACQUIRE; 13112 break; 13113 default: 13114 model = memmodel_from_int (INTVAL (operands[memmodel_attr])); 13115 } 13116 13117 mips_multi_start (); 13118 13119 /* Output the release side of the memory barrier. */ 13120 if (need_atomic_barrier_p (model, true)) 13121 { 13122 if (required_oldval == 0 && TARGET_OCTEON) 13123 { 13124 /* Octeon doesn't reorder reads, so a full barrier can be 13125 created by using SYNCW to order writes combined with the 13126 write from the following SC. When the SC successfully 13127 completes, we know that all preceding writes are also 13128 committed to the coherent memory system. It is possible 13129 for a single SYNCW to fail, but a pair of them will never 13130 fail, so we use two. */ 13131 mips_multi_add_insn ("syncw", NULL); 13132 mips_multi_add_insn ("syncw", NULL); 13133 } 13134 else 13135 mips_multi_add_insn ("sync", NULL); 13136 } 13137 13138 /* Output the branch-back label. */ 13139 mips_multi_add_label ("1:"); 13140 13141 /* OLDVAL = *MEM. */ 13142 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1", 13143 oldval, mem, NULL); 13144 13145 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */ 13146 if (required_oldval) 13147 { 13148 if (inclusive_mask == 0) 13149 tmp1 = oldval; 13150 else 13151 { 13152 gcc_assert (oldval != at); 13153 mips_multi_add_insn ("and\t%0,%1,%2", 13154 at, oldval, inclusive_mask, NULL); 13155 tmp1 = at; 13156 } 13157 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL); 13158 13159 /* CMP = 0 [delay slot]. */ 13160 if (cmp) 13161 mips_multi_add_insn ("li\t%0,0", cmp, NULL); 13162 } 13163 13164 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */ 13165 if (exclusive_mask == 0) 13166 tmp1 = const0_rtx; 13167 else 13168 { 13169 gcc_assert (oldval != at); 13170 mips_multi_add_insn ("and\t%0,%1,%z2", 13171 at, oldval, exclusive_mask, NULL); 13172 tmp1 = at; 13173 } 13174 13175 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2). 13176 13177 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit 13178 at least one instruction in that case. */ 13179 if (insn1 == SYNC_INSN1_MOVE 13180 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP)) 13181 tmp2 = insn1_op2; 13182 else 13183 { 13184 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p), 13185 newval, oldval, insn1_op2, NULL); 13186 tmp2 = newval; 13187 } 13188 13189 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */ 13190 if (insn2 == SYNC_INSN2_NOP) 13191 tmp3 = tmp2; 13192 else 13193 { 13194 mips_multi_add_insn (mips_sync_insn2_template (insn2), 13195 newval, tmp2, inclusive_mask, NULL); 13196 tmp3 = newval; 13197 } 13198 tmp3_insn = mips_multi_last_index (); 13199 13200 /* $AT = $TMP1 | $TMP3. */ 13201 if (tmp1 == const0_rtx || tmp3 == const0_rtx) 13202 { 13203 mips_multi_set_operand (tmp3_insn, 0, at); 13204 tmp3 = at; 13205 } 13206 else 13207 { 13208 gcc_assert (tmp1 != tmp3); 13209 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL); 13210 } 13211 13212 /* if (!commit (*MEM = $AT)) goto 1. 13213 13214 This will sometimes be a delayed branch; see the write code below 13215 for details. */ 13216 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); 13217 13218 /* When using branch likely (-mfix-r10000), the delay slot instruction 13219 will be annulled on false. The normal delay slot instructions 13220 calculate the overall result of the atomic operation and must not 13221 be annulled. To ensure this behaviour unconditionally use a NOP 13222 in the delay slot for the branch likely case. */ 13223 13224 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at, NULL); 13225 13226 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ 13227 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) 13228 { 13229 mips_multi_copy_insn (tmp3_insn); 13230 mips_multi_set_operand (mips_multi_last_index (), 0, newval); 13231 } 13232 else if (!(required_oldval && cmp) && !mips_branch_likely) 13233 mips_multi_add_insn ("nop", NULL); 13234 13235 /* CMP = 1 -- either standalone or in a delay slot. */ 13236 if (required_oldval && cmp) 13237 mips_multi_add_insn ("li\t%0,1", cmp, NULL); 13238 13239 /* Output the acquire side of the memory barrier. */ 13240 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false)) 13241 mips_multi_add_insn ("sync", NULL); 13242 13243 /* Output the exit label, if needed. */ 13244 if (required_oldval) 13245 mips_multi_add_label ("2:"); 13246 13247#undef READ_OPERAND 13248} 13249 13250/* Output and/or return the asm template for sync loop INSN, which has 13251 the operands given by OPERANDS. */ 13252 13253const char * 13254mips_output_sync_loop (rtx_insn *insn, rtx *operands) 13255{ 13256 /* Use branch-likely instructions to work around the LL/SC R10000 13257 errata. */ 13258 mips_branch_likely = TARGET_FIX_R10000; 13259 13260 mips_process_sync_loop (insn, operands); 13261 13262 mips_push_asm_switch (&mips_noreorder); 13263 mips_push_asm_switch (&mips_nomacro); 13264 mips_push_asm_switch (&mips_noat); 13265 mips_start_ll_sc_sync_block (); 13266 13267 mips_multi_write (); 13268 13269 mips_end_ll_sc_sync_block (); 13270 mips_pop_asm_switch (&mips_noat); 13271 mips_pop_asm_switch (&mips_nomacro); 13272 mips_pop_asm_switch (&mips_noreorder); 13273 13274 return ""; 13275} 13276 13277/* Return the number of individual instructions in sync loop INSN, 13278 which has the operands given by OPERANDS. */ 13279 13280unsigned int 13281mips_sync_loop_insns (rtx_insn *insn, rtx *operands) 13282{ 13283 /* Use branch-likely instructions to work around the LL/SC R10000 13284 errata. */ 13285 mips_branch_likely = TARGET_FIX_R10000; 13286 mips_process_sync_loop (insn, operands); 13287 return mips_multi_num_insns; 13288} 13289 13290/* Return the assembly code for DIV or DDIV instruction DIVISION, which has 13291 the operands given by OPERANDS. Add in a divide-by-zero check if needed. 13292 13293 When working around R4000 and R4400 errata, we need to make sure that 13294 the division is not immediately followed by a shift[1][2]. We also 13295 need to stop the division from being put into a branch delay slot[3]. 13296 The easiest way to avoid both problems is to add a nop after the 13297 division. When a divide-by-zero check is needed, this nop can be 13298 used to fill the branch delay slot. 13299 13300 [1] If a double-word or a variable shift executes immediately 13301 after starting an integer division, the shift may give an 13302 incorrect result. See quotations of errata #16 and #28 from 13303 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 13304 in mips.md for details. 13305 13306 [2] A similar bug to [1] exists for all revisions of the 13307 R4000 and the R4400 when run in an MC configuration. 13308 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0": 13309 13310 "19. In this following sequence: 13311 13312 ddiv (or ddivu or div or divu) 13313 dsll32 (or dsrl32, dsra32) 13314 13315 if an MPT stall occurs, while the divide is slipping the cpu 13316 pipeline, then the following double shift would end up with an 13317 incorrect result. 13318 13319 Workaround: The compiler needs to avoid generating any 13320 sequence with divide followed by extended double shift." 13321 13322 This erratum is also present in "MIPS R4400MC Errata, Processor 13323 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0 13324 & 3.0" as errata #10 and #4, respectively. 13325 13326 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 13327 (also valid for MIPS R4000MC processors): 13328 13329 "52. R4000SC: This bug does not apply for the R4000PC. 13330 13331 There are two flavors of this bug: 13332 13333 1) If the instruction just after divide takes an RF exception 13334 (tlb-refill, tlb-invalid) and gets an instruction cache 13335 miss (both primary and secondary) and the line which is 13336 currently in secondary cache at this index had the first 13337 data word, where the bits 5..2 are set, then R4000 would 13338 get a wrong result for the div. 13339 13340 ##1 13341 nop 13342 div r8, r9 13343 ------------------- # end-of page. -tlb-refill 13344 nop 13345 ##2 13346 nop 13347 div r8, r9 13348 ------------------- # end-of page. -tlb-invalid 13349 nop 13350 13351 2) If the divide is in the taken branch delay slot, where the 13352 target takes RF exception and gets an I-cache miss for the 13353 exception vector or where I-cache miss occurs for the 13354 target address, under the above mentioned scenarios, the 13355 div would get wrong results. 13356 13357 ##1 13358 j r2 # to next page mapped or unmapped 13359 div r8,r9 # this bug would be there as long 13360 # as there is an ICache miss and 13361 nop # the "data pattern" is present 13362 13363 ##2 13364 beq r0, r0, NextPage # to Next page 13365 div r8,r9 13366 nop 13367 13368 This bug is present for div, divu, ddiv, and ddivu 13369 instructions. 13370 13371 Workaround: For item 1), OS could make sure that the next page 13372 after the divide instruction is also mapped. For item 2), the 13373 compiler could make sure that the divide instruction is not in 13374 the branch delay slot." 13375 13376 These processors have PRId values of 0x00004220 and 0x00004300 for 13377 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */ 13378 13379const char * 13380mips_output_division (const char *division, rtx *operands) 13381{ 13382 const char *s; 13383 13384 s = division; 13385 if (TARGET_FIX_R4000 || TARGET_FIX_R4400) 13386 { 13387 output_asm_insn (s, operands); 13388 s = "nop"; 13389 } 13390 if (TARGET_CHECK_ZERO_DIV) 13391 { 13392 if (TARGET_MIPS16) 13393 { 13394 output_asm_insn (s, operands); 13395 s = "bnez\t%2,1f\n\tbreak\t7\n1:"; 13396 } 13397 else if (GENERATE_DIVIDE_TRAPS) 13398 { 13399 /* Avoid long replay penalty on load miss by putting the trap before 13400 the divide. */ 13401 if (TUNE_74K) 13402 output_asm_insn ("teq\t%2,%.,7", operands); 13403 else 13404 { 13405 output_asm_insn (s, operands); 13406 s = "teq\t%2,%.,7"; 13407 } 13408 } 13409 else 13410 { 13411 output_asm_insn ("%(bne\t%2,%.,1f", operands); 13412 output_asm_insn (s, operands); 13413 s = "break\t7%)\n1:"; 13414 } 13415 } 13416 return s; 13417} 13418 13419/* Return true if destination of IN_INSN is used as add source in 13420 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example: 13421 madd.s dst, x, y, z 13422 madd.s a, dst, b, c */ 13423 13424bool 13425mips_fmadd_bypass (rtx_insn *out_insn, rtx_insn *in_insn) 13426{ 13427 int dst_reg, src_reg; 13428 13429 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD); 13430 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD); 13431 13432 extract_insn (in_insn); 13433 dst_reg = REG_P (recog_data.operand[0]); 13434 13435 extract_insn (out_insn); 13436 src_reg = REG_P (recog_data.operand[1]); 13437 13438 if (dst_reg == src_reg) 13439 return true; 13440 13441 return false; 13442} 13443 13444/* Return true if IN_INSN is a multiply-add or multiply-subtract 13445 instruction and if OUT_INSN assigns to the accumulator operand. */ 13446 13447bool 13448mips_linked_madd_p (rtx_insn *out_insn, rtx_insn *in_insn) 13449{ 13450 enum attr_accum_in accum_in; 13451 int accum_in_opnum; 13452 rtx accum_in_op; 13453 13454 if (recog_memoized (in_insn) < 0) 13455 return false; 13456 13457 accum_in = get_attr_accum_in (in_insn); 13458 if (accum_in == ACCUM_IN_NONE) 13459 return false; 13460 13461 accum_in_opnum = accum_in - ACCUM_IN_0; 13462 13463 extract_insn (in_insn); 13464 gcc_assert (accum_in_opnum < recog_data.n_operands); 13465 accum_in_op = recog_data.operand[accum_in_opnum]; 13466 13467 return reg_set_p (accum_in_op, out_insn); 13468} 13469 13470/* True if the dependency between OUT_INSN and IN_INSN is on the store 13471 data rather than the address. We need this because the cprestore 13472 pattern is type "store", but is defined using an UNSPEC_VOLATILE, 13473 which causes the default routine to abort. We just return false 13474 for that case. */ 13475 13476bool 13477mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) 13478{ 13479 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) 13480 return false; 13481 13482 return !store_data_bypass_p (out_insn, in_insn); 13483} 13484 13485 13486/* Variables and flags used in scheduler hooks when tuning for 13487 Loongson 2E/2F. */ 13488static struct 13489{ 13490 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch 13491 strategy. */ 13492 13493 /* If true, then next ALU1/2 instruction will go to ALU1. */ 13494 bool alu1_turn_p; 13495 13496 /* If true, then next FALU1/2 unstruction will go to FALU1. */ 13497 bool falu1_turn_p; 13498 13499 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */ 13500 int alu1_core_unit_code; 13501 int alu2_core_unit_code; 13502 int falu1_core_unit_code; 13503 int falu2_core_unit_code; 13504 13505 /* True if current cycle has a multi instruction. 13506 This flag is used in mips_ls2_dfa_post_advance_cycle. */ 13507 bool cycle_has_multi_p; 13508 13509 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units. 13510 These are used in mips_ls2_dfa_post_advance_cycle to initialize 13511 DFA state. 13512 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2 13513 instruction to go ALU1. */ 13514 rtx_insn *alu1_turn_enabled_insn; 13515 rtx_insn *alu2_turn_enabled_insn; 13516 rtx_insn *falu1_turn_enabled_insn; 13517 rtx_insn *falu2_turn_enabled_insn; 13518} mips_ls2; 13519 13520/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output 13521 dependencies have no cost, except on the 20Kc where output-dependence 13522 is treated like input-dependence. */ 13523 13524static int 13525mips_adjust_cost (rtx_insn *insn ATTRIBUTE_UNUSED, rtx link, 13526 rtx_insn *dep ATTRIBUTE_UNUSED, int cost) 13527{ 13528 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT 13529 && TUNE_20KC) 13530 return cost; 13531 if (REG_NOTE_KIND (link) != 0) 13532 return 0; 13533 return cost; 13534} 13535 13536/* Return the number of instructions that can be issued per cycle. */ 13537 13538static int 13539mips_issue_rate (void) 13540{ 13541 switch (mips_tune) 13542 { 13543 case PROCESSOR_74KC: 13544 case PROCESSOR_74KF2_1: 13545 case PROCESSOR_74KF1_1: 13546 case PROCESSOR_74KF3_2: 13547 /* The 74k is not strictly quad-issue cpu, but can be seen as one 13548 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns, 13549 but in reality only a maximum of 3 insns can be issued as 13550 floating-point loads and stores also require a slot in the 13551 AGEN pipe. */ 13552 case PROCESSOR_R10000: 13553 /* All R10K Processors are quad-issue (being the first MIPS 13554 processors to support this feature). */ 13555 return 4; 13556 13557 case PROCESSOR_20KC: 13558 case PROCESSOR_R4130: 13559 case PROCESSOR_R5400: 13560 case PROCESSOR_R5500: 13561 case PROCESSOR_R5900: 13562 case PROCESSOR_R7000: 13563 case PROCESSOR_R9000: 13564 case PROCESSOR_OCTEON: 13565 case PROCESSOR_OCTEON2: 13566 case PROCESSOR_OCTEON3: 13567 return 2; 13568 13569 case PROCESSOR_SB1: 13570 case PROCESSOR_SB1A: 13571 /* This is actually 4, but we get better performance if we claim 3. 13572 This is partly because of unwanted speculative code motion with the 13573 larger number, and partly because in most common cases we can't 13574 reach the theoretical max of 4. */ 13575 return 3; 13576 13577 case PROCESSOR_LOONGSON_2E: 13578 case PROCESSOR_LOONGSON_2F: 13579 case PROCESSOR_LOONGSON_3A: 13580 case PROCESSOR_P5600: 13581 return 4; 13582 13583 case PROCESSOR_XLP: 13584 return (reload_completed ? 4 : 3); 13585 13586 default: 13587 return 1; 13588 } 13589} 13590 13591/* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */ 13592 13593static void 13594mips_ls2_init_dfa_post_cycle_insn (void) 13595{ 13596 start_sequence (); 13597 emit_insn (gen_ls2_alu1_turn_enabled_insn ()); 13598 mips_ls2.alu1_turn_enabled_insn = get_insns (); 13599 end_sequence (); 13600 13601 start_sequence (); 13602 emit_insn (gen_ls2_alu2_turn_enabled_insn ()); 13603 mips_ls2.alu2_turn_enabled_insn = get_insns (); 13604 end_sequence (); 13605 13606 start_sequence (); 13607 emit_insn (gen_ls2_falu1_turn_enabled_insn ()); 13608 mips_ls2.falu1_turn_enabled_insn = get_insns (); 13609 end_sequence (); 13610 13611 start_sequence (); 13612 emit_insn (gen_ls2_falu2_turn_enabled_insn ()); 13613 mips_ls2.falu2_turn_enabled_insn = get_insns (); 13614 end_sequence (); 13615 13616 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core"); 13617 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core"); 13618 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core"); 13619 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core"); 13620} 13621 13622/* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook. 13623 Init data used in mips_dfa_post_advance_cycle. */ 13624 13625static void 13626mips_init_dfa_post_cycle_insn (void) 13627{ 13628 if (TUNE_LOONGSON_2EF) 13629 mips_ls2_init_dfa_post_cycle_insn (); 13630} 13631 13632/* Initialize STATE when scheduling for Loongson 2E/2F. 13633 Support round-robin dispatch scheme by enabling only one of 13634 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions 13635 respectively. */ 13636 13637static void 13638mips_ls2_dfa_post_advance_cycle (state_t state) 13639{ 13640 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code)) 13641 { 13642 /* Though there are no non-pipelined ALU1 insns, 13643 we can get an instruction of type 'multi' before reload. */ 13644 gcc_assert (mips_ls2.cycle_has_multi_p); 13645 mips_ls2.alu1_turn_p = false; 13646 } 13647 13648 mips_ls2.cycle_has_multi_p = false; 13649 13650 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code)) 13651 /* We have a non-pipelined alu instruction in the core, 13652 adjust round-robin counter. */ 13653 mips_ls2.alu1_turn_p = true; 13654 13655 if (mips_ls2.alu1_turn_p) 13656 { 13657 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0) 13658 gcc_unreachable (); 13659 } 13660 else 13661 { 13662 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0) 13663 gcc_unreachable (); 13664 } 13665 13666 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code)) 13667 { 13668 /* There are no non-pipelined FALU1 insns. */ 13669 gcc_unreachable (); 13670 mips_ls2.falu1_turn_p = false; 13671 } 13672 13673 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code)) 13674 /* We have a non-pipelined falu instruction in the core, 13675 adjust round-robin counter. */ 13676 mips_ls2.falu1_turn_p = true; 13677 13678 if (mips_ls2.falu1_turn_p) 13679 { 13680 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0) 13681 gcc_unreachable (); 13682 } 13683 else 13684 { 13685 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0) 13686 gcc_unreachable (); 13687 } 13688} 13689 13690/* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE. 13691 This hook is being called at the start of each cycle. */ 13692 13693static void 13694mips_dfa_post_advance_cycle (void) 13695{ 13696 if (TUNE_LOONGSON_2EF) 13697 mips_ls2_dfa_post_advance_cycle (curr_state); 13698} 13699 13700/* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should 13701 be as wide as the scheduling freedom in the DFA. */ 13702 13703static int 13704mips_multipass_dfa_lookahead (void) 13705{ 13706 /* Can schedule up to 4 of the 6 function units in any one cycle. */ 13707 if (TUNE_SB1) 13708 return 4; 13709 13710 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) 13711 return 4; 13712 13713 if (TUNE_OCTEON) 13714 return 2; 13715 13716 if (TUNE_P5600) 13717 return 4; 13718 13719 return 0; 13720} 13721 13722/* Remove the instruction at index LOWER from ready queue READY and 13723 reinsert it in front of the instruction at index HIGHER. LOWER must 13724 be <= HIGHER. */ 13725 13726static void 13727mips_promote_ready (rtx_insn **ready, int lower, int higher) 13728{ 13729 rtx_insn *new_head; 13730 int i; 13731 13732 new_head = ready[lower]; 13733 for (i = lower; i < higher; i++) 13734 ready[i] = ready[i + 1]; 13735 ready[i] = new_head; 13736} 13737 13738/* If the priority of the instruction at POS2 in the ready queue READY 13739 is within LIMIT units of that of the instruction at POS1, swap the 13740 instructions if POS2 is not already less than POS1. */ 13741 13742static void 13743mips_maybe_swap_ready (rtx_insn **ready, int pos1, int pos2, int limit) 13744{ 13745 if (pos1 < pos2 13746 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2])) 13747 { 13748 rtx_insn *temp; 13749 13750 temp = ready[pos1]; 13751 ready[pos1] = ready[pos2]; 13752 ready[pos2] = temp; 13753 } 13754} 13755 13756/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction 13757 that may clobber hi or lo. */ 13758static rtx_insn *mips_macc_chains_last_hilo; 13759 13760/* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has 13761 been scheduled, updating mips_macc_chains_last_hilo appropriately. */ 13762 13763static void 13764mips_macc_chains_record (rtx_insn *insn) 13765{ 13766 if (get_attr_may_clobber_hilo (insn)) 13767 mips_macc_chains_last_hilo = insn; 13768} 13769 13770/* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which 13771 has NREADY elements, looking for a multiply-add or multiply-subtract 13772 instruction that is cumulative with mips_macc_chains_last_hilo. 13773 If there is one, promote it ahead of anything else that might 13774 clobber hi or lo. */ 13775 13776static void 13777mips_macc_chains_reorder (rtx_insn **ready, int nready) 13778{ 13779 int i, j; 13780 13781 if (mips_macc_chains_last_hilo != 0) 13782 for (i = nready - 1; i >= 0; i--) 13783 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i])) 13784 { 13785 for (j = nready - 1; j > i; j--) 13786 if (recog_memoized (ready[j]) >= 0 13787 && get_attr_may_clobber_hilo (ready[j])) 13788 { 13789 mips_promote_ready (ready, i, j); 13790 break; 13791 } 13792 break; 13793 } 13794} 13795 13796/* The last instruction to be scheduled. */ 13797static rtx_insn *vr4130_last_insn; 13798 13799/* A note_stores callback used by vr4130_true_reg_dependence_p. DATA 13800 points to an rtx that is initially an instruction. Nullify the rtx 13801 if the instruction uses the value of register X. */ 13802 13803static void 13804vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, 13805 void *data) 13806{ 13807 rtx *insn_ptr; 13808 13809 insn_ptr = (rtx *) data; 13810 if (REG_P (x) 13811 && *insn_ptr != 0 13812 && reg_referenced_p (x, PATTERN (*insn_ptr))) 13813 *insn_ptr = 0; 13814} 13815 13816/* Return true if there is true register dependence between vr4130_last_insn 13817 and INSN. */ 13818 13819static bool 13820vr4130_true_reg_dependence_p (rtx insn) 13821{ 13822 note_stores (PATTERN (vr4130_last_insn), 13823 vr4130_true_reg_dependence_p_1, &insn); 13824 return insn == 0; 13825} 13826 13827/* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of 13828 the ready queue and that INSN2 is the instruction after it, return 13829 true if it is worth promoting INSN2 ahead of INSN1. Look for cases 13830 in which INSN1 and INSN2 can probably issue in parallel, but for 13831 which (INSN2, INSN1) should be less sensitive to instruction 13832 alignment than (INSN1, INSN2). See 4130.md for more details. */ 13833 13834static bool 13835vr4130_swap_insns_p (rtx_insn *insn1, rtx_insn *insn2) 13836{ 13837 sd_iterator_def sd_it; 13838 dep_t dep; 13839 13840 /* Check for the following case: 13841 13842 1) there is some other instruction X with an anti dependence on INSN1; 13843 2) X has a higher priority than INSN2; and 13844 3) X is an arithmetic instruction (and thus has no unit restrictions). 13845 13846 If INSN1 is the last instruction blocking X, it would better to 13847 choose (INSN1, X) over (INSN2, INSN1). */ 13848 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep) 13849 if (DEP_TYPE (dep) == REG_DEP_ANTI 13850 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2) 13851 && recog_memoized (DEP_CON (dep)) >= 0 13852 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU) 13853 return false; 13854 13855 if (vr4130_last_insn != 0 13856 && recog_memoized (insn1) >= 0 13857 && recog_memoized (insn2) >= 0) 13858 { 13859 /* See whether INSN1 and INSN2 use different execution units, 13860 or if they are both ALU-type instructions. If so, they can 13861 probably execute in parallel. */ 13862 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1); 13863 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2); 13864 if (class1 != class2 || class1 == VR4130_CLASS_ALU) 13865 { 13866 /* If only one of the instructions has a dependence on 13867 vr4130_last_insn, prefer to schedule the other one first. */ 13868 bool dep1_p = vr4130_true_reg_dependence_p (insn1); 13869 bool dep2_p = vr4130_true_reg_dependence_p (insn2); 13870 if (dep1_p != dep2_p) 13871 return dep1_p; 13872 13873 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn 13874 is not an ALU-type instruction and if INSN1 uses the same 13875 execution unit. (Note that if this condition holds, we already 13876 know that INSN2 uses a different execution unit.) */ 13877 if (class1 != VR4130_CLASS_ALU 13878 && recog_memoized (vr4130_last_insn) >= 0 13879 && class1 == get_attr_vr4130_class (vr4130_last_insn)) 13880 return true; 13881 } 13882 } 13883 return false; 13884} 13885 13886/* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready 13887 queue with at least two instructions. Swap the first two if 13888 vr4130_swap_insns_p says that it could be worthwhile. */ 13889 13890static void 13891vr4130_reorder (rtx_insn **ready, int nready) 13892{ 13893 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2])) 13894 mips_promote_ready (ready, nready - 2, nready - 1); 13895} 13896 13897/* Record whether last 74k AGEN instruction was a load or store. */ 13898static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN; 13899 13900/* Initialize mips_last_74k_agen_insn from INSN. A null argument 13901 resets to TYPE_UNKNOWN state. */ 13902 13903static void 13904mips_74k_agen_init (rtx_insn *insn) 13905{ 13906 if (!insn || CALL_P (insn) || JUMP_P (insn)) 13907 mips_last_74k_agen_insn = TYPE_UNKNOWN; 13908 else 13909 { 13910 enum attr_type type = get_attr_type (insn); 13911 if (type == TYPE_LOAD || type == TYPE_STORE) 13912 mips_last_74k_agen_insn = type; 13913 } 13914} 13915 13916/* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple 13917 loads to be grouped together, and multiple stores to be grouped 13918 together. Swap things around in the ready queue to make this happen. */ 13919 13920static void 13921mips_74k_agen_reorder (rtx_insn **ready, int nready) 13922{ 13923 int i; 13924 int store_pos, load_pos; 13925 13926 store_pos = -1; 13927 load_pos = -1; 13928 13929 for (i = nready - 1; i >= 0; i--) 13930 { 13931 rtx_insn *insn = ready[i]; 13932 if (USEFUL_INSN_P (insn)) 13933 switch (get_attr_type (insn)) 13934 { 13935 case TYPE_STORE: 13936 if (store_pos == -1) 13937 store_pos = i; 13938 break; 13939 13940 case TYPE_LOAD: 13941 if (load_pos == -1) 13942 load_pos = i; 13943 break; 13944 13945 default: 13946 break; 13947 } 13948 } 13949 13950 if (load_pos == -1 || store_pos == -1) 13951 return; 13952 13953 switch (mips_last_74k_agen_insn) 13954 { 13955 case TYPE_UNKNOWN: 13956 /* Prefer to schedule loads since they have a higher latency. */ 13957 case TYPE_LOAD: 13958 /* Swap loads to the front of the queue. */ 13959 mips_maybe_swap_ready (ready, load_pos, store_pos, 4); 13960 break; 13961 case TYPE_STORE: 13962 /* Swap stores to the front of the queue. */ 13963 mips_maybe_swap_ready (ready, store_pos, load_pos, 4); 13964 break; 13965 default: 13966 break; 13967 } 13968} 13969 13970/* Implement TARGET_SCHED_INIT. */ 13971 13972static void 13973mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 13974 int max_ready ATTRIBUTE_UNUSED) 13975{ 13976 mips_macc_chains_last_hilo = 0; 13977 vr4130_last_insn = 0; 13978 mips_74k_agen_init (NULL); 13979 13980 /* When scheduling for Loongson2, branch instructions go to ALU1, 13981 therefore basic block is most likely to start with round-robin counter 13982 pointed to ALU2. */ 13983 mips_ls2.alu1_turn_p = false; 13984 mips_ls2.falu1_turn_p = true; 13985} 13986 13987/* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */ 13988 13989static void 13990mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 13991 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) 13992{ 13993 if (!reload_completed 13994 && TUNE_MACC_CHAINS 13995 && *nreadyp > 0) 13996 mips_macc_chains_reorder (ready, *nreadyp); 13997 13998 if (reload_completed 13999 && TUNE_MIPS4130 14000 && !TARGET_VR4130_ALIGN 14001 && *nreadyp > 1) 14002 vr4130_reorder (ready, *nreadyp); 14003 14004 if (TUNE_74K) 14005 mips_74k_agen_reorder (ready, *nreadyp); 14006} 14007 14008/* Implement TARGET_SCHED_REORDER. */ 14009 14010static int 14011mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 14012 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) 14013{ 14014 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); 14015 return mips_issue_rate (); 14016} 14017 14018/* Implement TARGET_SCHED_REORDER2. */ 14019 14020static int 14021mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 14022 rtx_insn **ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) 14023{ 14024 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle); 14025 return cached_can_issue_more; 14026} 14027 14028/* Update round-robin counters for ALU1/2 and FALU1/2. */ 14029 14030static void 14031mips_ls2_variable_issue (rtx_insn *insn) 14032{ 14033 if (mips_ls2.alu1_turn_p) 14034 { 14035 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code)) 14036 mips_ls2.alu1_turn_p = false; 14037 } 14038 else 14039 { 14040 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code)) 14041 mips_ls2.alu1_turn_p = true; 14042 } 14043 14044 if (mips_ls2.falu1_turn_p) 14045 { 14046 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code)) 14047 mips_ls2.falu1_turn_p = false; 14048 } 14049 else 14050 { 14051 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code)) 14052 mips_ls2.falu1_turn_p = true; 14053 } 14054 14055 if (recog_memoized (insn) >= 0) 14056 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI); 14057} 14058 14059/* Implement TARGET_SCHED_VARIABLE_ISSUE. */ 14060 14061static int 14062mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 14063 rtx_insn *insn, int more) 14064{ 14065 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */ 14066 if (USEFUL_INSN_P (insn)) 14067 { 14068 if (get_attr_type (insn) != TYPE_GHOST) 14069 more--; 14070 if (!reload_completed && TUNE_MACC_CHAINS) 14071 mips_macc_chains_record (insn); 14072 vr4130_last_insn = insn; 14073 if (TUNE_74K) 14074 mips_74k_agen_init (insn); 14075 else if (TUNE_LOONGSON_2EF) 14076 mips_ls2_variable_issue (insn); 14077 } 14078 14079 /* Instructions of type 'multi' should all be split before 14080 the second scheduling pass. */ 14081 gcc_assert (!reload_completed 14082 || recog_memoized (insn) < 0 14083 || get_attr_type (insn) != TYPE_MULTI); 14084 14085 cached_can_issue_more = more; 14086 return more; 14087} 14088 14089/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY), 14090 return the first operand of the associated PREF or PREFX insn. */ 14091 14092rtx 14093mips_prefetch_cookie (rtx write, rtx locality) 14094{ 14095 /* store_streamed / load_streamed. */ 14096 if (INTVAL (locality) <= 0) 14097 return GEN_INT (INTVAL (write) + 4); 14098 14099 /* store / load. */ 14100 if (INTVAL (locality) <= 2) 14101 return write; 14102 14103 /* store_retained / load_retained. */ 14104 return GEN_INT (INTVAL (write) + 6); 14105} 14106 14107/* Flags that indicate when a built-in function is available. 14108 14109 BUILTIN_AVAIL_NON_MIPS16 14110 The function is available on the current target if !TARGET_MIPS16. 14111 14112 BUILTIN_AVAIL_MIPS16 14113 The function is available on the current target if TARGET_MIPS16. */ 14114#define BUILTIN_AVAIL_NON_MIPS16 1 14115#define BUILTIN_AVAIL_MIPS16 2 14116 14117/* Declare an availability predicate for built-in functions that 14118 require non-MIPS16 mode and also require COND to be true. 14119 NAME is the main part of the predicate's name. */ 14120#define AVAIL_NON_MIPS16(NAME, COND) \ 14121 static unsigned int \ 14122 mips_builtin_avail_##NAME (void) \ 14123 { \ 14124 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ 14125 } 14126 14127/* Declare an availability predicate for built-in functions that 14128 support both MIPS16 and non-MIPS16 code and also require COND 14129 to be true. NAME is the main part of the predicate's name. */ 14130#define AVAIL_ALL(NAME, COND) \ 14131 static unsigned int \ 14132 mips_builtin_avail_##NAME (void) \ 14133 { \ 14134 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \ 14135 } 14136 14137/* This structure describes a single built-in function. */ 14138struct mips_builtin_description { 14139 /* The code of the main .md file instruction. See mips_builtin_type 14140 for more information. */ 14141 enum insn_code icode; 14142 14143 /* The floating-point comparison code to use with ICODE, if any. */ 14144 enum mips_fp_condition cond; 14145 14146 /* The name of the built-in function. */ 14147 const char *name; 14148 14149 /* Specifies how the function should be expanded. */ 14150 enum mips_builtin_type builtin_type; 14151 14152 /* The function's prototype. */ 14153 enum mips_function_type function_type; 14154 14155 /* Whether the function is available. */ 14156 unsigned int (*avail) (void); 14157}; 14158 14159AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI) 14160AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT) 14161AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT) 14162AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D) 14163AVAIL_NON_MIPS16 (dsp, TARGET_DSP) 14164AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) 14165AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) 14166AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) 14167AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) 14168AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) 14169AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) 14170 14171/* Construct a mips_builtin_description from the given arguments. 14172 14173 INSN is the name of the associated instruction pattern, without the 14174 leading CODE_FOR_mips_. 14175 14176 CODE is the floating-point condition code associated with the 14177 function. It can be 'f' if the field is not applicable. 14178 14179 NAME is the name of the function itself, without the leading 14180 "__builtin_mips_". 14181 14182 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. 14183 14184 AVAIL is the name of the availability predicate, without the leading 14185 mips_builtin_avail_. */ 14186#define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \ 14187 FUNCTION_TYPE, AVAIL) \ 14188 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \ 14189 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \ 14190 mips_builtin_avail_ ## AVAIL } 14191 14192/* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function 14193 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL 14194 are as for MIPS_BUILTIN. */ 14195#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ 14196 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) 14197 14198/* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which 14199 are subject to mips_builtin_avail_<AVAIL>. */ 14200#define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \ 14201 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \ 14202 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \ 14203 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \ 14204 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL) 14205 14206/* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. 14207 The lower and upper forms are subject to mips_builtin_avail_<AVAIL> 14208 while the any and all forms are subject to mips_builtin_avail_mips3d. */ 14209#define CMP_PS_BUILTINS(INSN, COND, AVAIL) \ 14210 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \ 14211 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \ 14212 mips3d), \ 14213 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \ 14214 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \ 14215 mips3d), \ 14216 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \ 14217 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \ 14218 AVAIL), \ 14219 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \ 14220 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \ 14221 AVAIL) 14222 14223/* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions 14224 are subject to mips_builtin_avail_mips3d. */ 14225#define CMP_4S_BUILTINS(INSN, COND) \ 14226 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \ 14227 MIPS_BUILTIN_CMP_ANY, \ 14228 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \ 14229 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \ 14230 MIPS_BUILTIN_CMP_ALL, \ 14231 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d) 14232 14233/* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison 14234 instruction requires mips_builtin_avail_<AVAIL>. */ 14235#define MOVTF_BUILTINS(INSN, COND, AVAIL) \ 14236 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \ 14237 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 14238 AVAIL), \ 14239 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \ 14240 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 14241 AVAIL) 14242 14243/* Define all the built-in functions related to C.cond.fmt condition COND. */ 14244#define CMP_BUILTINS(COND) \ 14245 MOVTF_BUILTINS (c, COND, paired_single), \ 14246 MOVTF_BUILTINS (cabs, COND, mips3d), \ 14247 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \ 14248 CMP_PS_BUILTINS (c, COND, paired_single), \ 14249 CMP_PS_BUILTINS (cabs, COND, mips3d), \ 14250 CMP_4S_BUILTINS (c, COND), \ 14251 CMP_4S_BUILTINS (cabs, COND) 14252 14253/* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET 14254 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE 14255 and AVAIL are as for MIPS_BUILTIN. */ 14256#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ 14257 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ 14258 FUNCTION_TYPE, AVAIL) 14259 14260/* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP 14261 branch instruction. AVAIL is as for MIPS_BUILTIN. */ 14262#define BPOSGE_BUILTIN(VALUE, AVAIL) \ 14263 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ 14264 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) 14265 14266/* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> 14267 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a 14268 builtin_description field. */ 14269#define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \ 14270 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \ 14271 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \ 14272 FUNCTION_TYPE, mips_builtin_avail_loongson } 14273 14274/* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN> 14275 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a 14276 builtin_description field. */ 14277#define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \ 14278 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE) 14279 14280/* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name. 14281 We use functions of this form when the same insn can be usefully applied 14282 to more than one datatype. */ 14283#define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \ 14284 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE) 14285 14286#define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 14287#define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 14288#define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 14289#define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 14290#define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3 14291#define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3 14292#define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit 14293#define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit 14294 14295#define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si 14296#define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi 14297#define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi 14298#define CODE_FOR_loongson_paddw CODE_FOR_addv2si3 14299#define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3 14300#define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3 14301#define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3 14302#define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3 14303#define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3 14304#define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3 14305#define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3 14306#define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3 14307#define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3 14308#define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3 14309#define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart 14310#define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart 14311#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3 14312#define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3 14313#define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3 14314#define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3 14315#define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3 14316#define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3 14317#define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3 14318#define CODE_FOR_loongson_psubw CODE_FOR_subv2si3 14319#define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3 14320#define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3 14321#define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3 14322#define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3 14323#define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3 14324#define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3 14325 14326static const struct mips_builtin_description mips_builtins[] = { 14327#define MIPS_GET_FCSR 0 14328 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float), 14329#define MIPS_SET_FCSR 1 14330 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float), 14331 14332 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 14333 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 14334 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 14335 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 14336 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single), 14337 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single), 14338 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single), 14339 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single), 14340 14341 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single), 14342 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 14343 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 14344 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), 14345 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d), 14346 14347 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d), 14348 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d), 14349 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), 14350 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d), 14351 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d), 14352 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 14353 14354 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d), 14355 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d), 14356 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), 14357 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d), 14358 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d), 14359 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 14360 14361 MIPS_FP_CONDITIONS (CMP_BUILTINS), 14362 14363 /* Built-in functions for the SB-1 processor. */ 14364 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single), 14365 14366 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */ 14367 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14368 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14369 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), 14370 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 14371 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 14372 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14373 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14374 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), 14375 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 14376 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 14377 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp), 14378 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp), 14379 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp), 14380 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp), 14381 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp), 14382 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp), 14383 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), 14384 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), 14385 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), 14386 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), 14387 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp), 14388 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp), 14389 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), 14390 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), 14391 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), 14392 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), 14393 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), 14394 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), 14395 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), 14396 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), 14397 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), 14398 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 14399 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 14400 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp), 14401 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), 14402 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 14403 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 14404 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp), 14405 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), 14406 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), 14407 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14408 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp), 14409 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp), 14410 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp), 14411 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp), 14412 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp), 14413 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp), 14414 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), 14415 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), 14416 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), 14417 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), 14418 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), 14419 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), 14420 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), 14421 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), 14422 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), 14423 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 14424 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14425 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 14426 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp), 14427 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp), 14428 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp), 14429 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp), 14430 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp), 14431 BPOSGE_BUILTIN (32, dsp), 14432 14433 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */ 14434 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2), 14435 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14436 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14437 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 14438 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 14439 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2), 14440 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2), 14441 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), 14442 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), 14443 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), 14444 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14445 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14446 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2), 14447 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14448 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2), 14449 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2), 14450 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), 14451 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), 14452 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2), 14453 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), 14454 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), 14455 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2), 14456 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14457 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14458 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 14459 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 14460 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14461 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14462 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), 14463 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), 14464 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14465 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 14466 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), 14467 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), 14468 14469 /* Built-in functions for the DSP ASE (32-bit only). */ 14470 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 14471 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 14472 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 14473 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 14474 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14475 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14476 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14477 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 14478 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 14479 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14480 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14481 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14482 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 14483 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32), 14484 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32), 14485 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32), 14486 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32), 14487 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32), 14488 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32), 14489 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32), 14490 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32), 14491 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 14492 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), 14493 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 14494 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), 14495 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32), 14496 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32), 14497 14498 /* Built-in functions for the DSP ASE (64-bit only). */ 14499 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64), 14500 14501 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */ 14502 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14503 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14504 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14505 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14506 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14507 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14508 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14509 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14510 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 14511 14512 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ 14513 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), 14514 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), 14515 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI), 14516 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14517 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14518 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14519 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), 14520 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14521 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), 14522 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI), 14523 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI), 14524 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14525 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI), 14526 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14527 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14528 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI), 14529 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14530 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14531 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14532 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI), 14533 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI), 14534 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14535 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI), 14536 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14537 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14538 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14539 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14540 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14541 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), 14542 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14543 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), 14544 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14545 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14546 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14547 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), 14548 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14549 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), 14550 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI), 14551 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI), 14552 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14553 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14554 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14555 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14556 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14557 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14558 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14559 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14560 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI), 14561 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14562 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14563 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14564 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14565 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI), 14566 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI), 14567 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14568 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14569 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14570 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI), 14571 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14572 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI), 14573 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI), 14574 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), 14575 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI), 14576 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), 14577 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI), 14578 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), 14579 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI), 14580 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), 14581 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI), 14582 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), 14583 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI), 14584 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), 14585 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI), 14586 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), 14587 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI), 14588 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14589 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14590 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14591 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), 14592 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14593 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), 14594 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI), 14595 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI), 14596 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI), 14597 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI), 14598 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14599 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14600 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14601 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14602 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14603 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), 14604 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14605 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), 14606 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), 14607 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), 14608 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), 14609 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), 14610 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), 14611 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), 14612 14613 /* Sundry other built-in functions. */ 14614 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache) 14615}; 14616 14617/* Index I is the function declaration for mips_builtins[I], or null if the 14618 function isn't defined on this target. */ 14619static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)]; 14620 14621/* MODE is a vector mode whose elements have type TYPE. Return the type 14622 of the vector itself. */ 14623 14624static tree 14625mips_builtin_vector_type (tree type, machine_mode mode) 14626{ 14627 static tree types[2 * (int) MAX_MACHINE_MODE]; 14628 int mode_index; 14629 14630 mode_index = (int) mode; 14631 14632 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type)) 14633 mode_index += MAX_MACHINE_MODE; 14634 14635 if (types[mode_index] == NULL_TREE) 14636 types[mode_index] = build_vector_type_for_mode (type, mode); 14637 return types[mode_index]; 14638} 14639 14640/* Return a type for 'const volatile void *'. */ 14641 14642static tree 14643mips_build_cvpointer_type (void) 14644{ 14645 static tree cache; 14646 14647 if (cache == NULL_TREE) 14648 cache = build_pointer_type (build_qualified_type 14649 (void_type_node, 14650 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)); 14651 return cache; 14652} 14653 14654/* Source-level argument types. */ 14655#define MIPS_ATYPE_VOID void_type_node 14656#define MIPS_ATYPE_INT integer_type_node 14657#define MIPS_ATYPE_POINTER ptr_type_node 14658#define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type () 14659 14660/* Standard mode-based argument types. */ 14661#define MIPS_ATYPE_UQI unsigned_intQI_type_node 14662#define MIPS_ATYPE_SI intSI_type_node 14663#define MIPS_ATYPE_USI unsigned_intSI_type_node 14664#define MIPS_ATYPE_DI intDI_type_node 14665#define MIPS_ATYPE_UDI unsigned_intDI_type_node 14666#define MIPS_ATYPE_SF float_type_node 14667#define MIPS_ATYPE_DF double_type_node 14668 14669/* Vector argument types. */ 14670#define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode) 14671#define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode) 14672#define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode) 14673#define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode) 14674#define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode) 14675#define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode) 14676#define MIPS_ATYPE_UV2SI \ 14677 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode) 14678#define MIPS_ATYPE_UV4HI \ 14679 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode) 14680#define MIPS_ATYPE_UV8QI \ 14681 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode) 14682 14683/* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists 14684 their associated MIPS_ATYPEs. */ 14685#define MIPS_FTYPE_ATYPES1(A, B) \ 14686 MIPS_ATYPE_##A, MIPS_ATYPE_##B 14687 14688#define MIPS_FTYPE_ATYPES2(A, B, C) \ 14689 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C 14690 14691#define MIPS_FTYPE_ATYPES3(A, B, C, D) \ 14692 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D 14693 14694#define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \ 14695 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \ 14696 MIPS_ATYPE_##E 14697 14698/* Return the function type associated with function prototype TYPE. */ 14699 14700static tree 14701mips_build_function_type (enum mips_function_type type) 14702{ 14703 static tree types[(int) MIPS_MAX_FTYPE_MAX]; 14704 14705 if (types[(int) type] == NULL_TREE) 14706 switch (type) 14707 { 14708#define DEF_MIPS_FTYPE(NUM, ARGS) \ 14709 case MIPS_FTYPE_NAME##NUM ARGS: \ 14710 types[(int) type] \ 14711 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \ 14712 NULL_TREE); \ 14713 break; 14714#include "config/mips/mips-ftypes.def" 14715#undef DEF_MIPS_FTYPE 14716 default: 14717 gcc_unreachable (); 14718 } 14719 14720 return types[(int) type]; 14721} 14722 14723/* Implement TARGET_INIT_BUILTINS. */ 14724 14725static void 14726mips_init_builtins (void) 14727{ 14728 const struct mips_builtin_description *d; 14729 unsigned int i; 14730 14731 /* Iterate through all of the bdesc arrays, initializing all of the 14732 builtin functions. */ 14733 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++) 14734 { 14735 d = &mips_builtins[i]; 14736 if (d->avail ()) 14737 mips_builtin_decls[i] 14738 = add_builtin_function (d->name, 14739 mips_build_function_type (d->function_type), 14740 i, BUILT_IN_MD, NULL, NULL); 14741 } 14742} 14743 14744/* Implement TARGET_BUILTIN_DECL. */ 14745 14746static tree 14747mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED) 14748{ 14749 if (code >= ARRAY_SIZE (mips_builtins)) 14750 return error_mark_node; 14751 return mips_builtin_decls[code]; 14752} 14753 14754/* Take argument ARGNO from EXP's argument list and convert it into 14755 an expand operand. Store the operand in *OP. */ 14756 14757static void 14758mips_prepare_builtin_arg (struct expand_operand *op, tree exp, 14759 unsigned int argno) 14760{ 14761 tree arg; 14762 rtx value; 14763 14764 arg = CALL_EXPR_ARG (exp, argno); 14765 value = expand_normal (arg); 14766 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg))); 14767} 14768 14769/* Expand instruction ICODE as part of a built-in function sequence. 14770 Use the first NOPS elements of OPS as the instruction's operands. 14771 HAS_TARGET_P is true if operand 0 is a target; it is false if the 14772 instruction has no target. 14773 14774 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */ 14775 14776static rtx 14777mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, 14778 struct expand_operand *ops, bool has_target_p) 14779{ 14780 if (!maybe_expand_insn (icode, nops, ops)) 14781 { 14782 error ("invalid argument to built-in function"); 14783 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx; 14784 } 14785 return has_target_p ? ops[0].value : const0_rtx; 14786} 14787 14788/* Expand a floating-point comparison for built-in function call EXP. 14789 The first NARGS arguments are the values to be compared. ICODE is 14790 the .md pattern that does the comparison and COND is the condition 14791 that is being tested. Return an rtx for the result. */ 14792 14793static rtx 14794mips_expand_builtin_compare_1 (enum insn_code icode, 14795 enum mips_fp_condition cond, 14796 tree exp, int nargs) 14797{ 14798 struct expand_operand ops[MAX_RECOG_OPERANDS]; 14799 rtx output; 14800 int opno, argno; 14801 14802 /* The instruction should have a target operand, an operand for each 14803 argument, and an operand for COND. */ 14804 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args); 14805 14806 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode); 14807 opno = 0; 14808 create_fixed_operand (&ops[opno++], output); 14809 for (argno = 0; argno < nargs; argno++) 14810 mips_prepare_builtin_arg (&ops[opno++], exp, argno); 14811 create_integer_operand (&ops[opno++], (int) cond); 14812 return mips_expand_builtin_insn (icode, opno, ops, true); 14813} 14814 14815/* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function; 14816 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function 14817 and ICODE is the code of the associated .md pattern. TARGET, if nonnull, 14818 suggests a good place to put the result. */ 14819 14820static rtx 14821mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, 14822 bool has_target_p) 14823{ 14824 struct expand_operand ops[MAX_RECOG_OPERANDS]; 14825 int opno, argno; 14826 14827 /* Map any target to operand 0. */ 14828 opno = 0; 14829 if (has_target_p) 14830 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp))); 14831 14832 /* Map the arguments to the other operands. */ 14833 gcc_assert (opno + call_expr_nargs (exp) 14834 == insn_data[icode].n_generator_args); 14835 for (argno = 0; argno < call_expr_nargs (exp); argno++) 14836 mips_prepare_builtin_arg (&ops[opno++], exp, argno); 14837 14838 return mips_expand_builtin_insn (icode, opno, ops, has_target_p); 14839} 14840 14841/* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps 14842 function; TYPE says which. EXP is the CALL_EXPR that calls the 14843 function, ICODE is the instruction that should be used to compare 14844 the first two arguments, and COND is the condition it should test. 14845 TARGET, if nonnull, suggests a good place to put the result. */ 14846 14847static rtx 14848mips_expand_builtin_movtf (enum mips_builtin_type type, 14849 enum insn_code icode, enum mips_fp_condition cond, 14850 rtx target, tree exp) 14851{ 14852 struct expand_operand ops[4]; 14853 rtx cmp_result; 14854 14855 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2); 14856 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp))); 14857 if (type == MIPS_BUILTIN_MOVT) 14858 { 14859 mips_prepare_builtin_arg (&ops[2], exp, 2); 14860 mips_prepare_builtin_arg (&ops[1], exp, 3); 14861 } 14862 else 14863 { 14864 mips_prepare_builtin_arg (&ops[1], exp, 2); 14865 mips_prepare_builtin_arg (&ops[2], exp, 3); 14866 } 14867 create_fixed_operand (&ops[3], cmp_result); 14868 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps, 14869 4, ops, true); 14870} 14871 14872/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE 14873 into TARGET otherwise. Return TARGET. */ 14874 14875static rtx 14876mips_builtin_branch_and_move (rtx condition, rtx target, 14877 rtx value_if_true, rtx value_if_false) 14878{ 14879 rtx_code_label *true_label, *done_label; 14880 14881 true_label = gen_label_rtx (); 14882 done_label = gen_label_rtx (); 14883 14884 /* First assume that CONDITION is false. */ 14885 mips_emit_move (target, value_if_false); 14886 14887 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */ 14888 emit_jump_insn (gen_condjump (condition, true_label)); 14889 emit_jump_insn (gen_jump (done_label)); 14890 emit_barrier (); 14891 14892 /* Fix TARGET if CONDITION is true. */ 14893 emit_label (true_label); 14894 mips_emit_move (target, value_if_true); 14895 14896 emit_label (done_label); 14897 return target; 14898} 14899 14900/* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is 14901 the CALL_EXPR that calls the function, ICODE is the code of the 14902 comparison instruction, and COND is the condition it should test. 14903 TARGET, if nonnull, suggests a good place to put the boolean result. */ 14904 14905static rtx 14906mips_expand_builtin_compare (enum mips_builtin_type builtin_type, 14907 enum insn_code icode, enum mips_fp_condition cond, 14908 rtx target, tree exp) 14909{ 14910 rtx offset, condition, cmp_result; 14911 14912 if (target == 0 || GET_MODE (target) != SImode) 14913 target = gen_reg_rtx (SImode); 14914 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 14915 call_expr_nargs (exp)); 14916 14917 /* If the comparison sets more than one register, we define the result 14918 to be 0 if all registers are false and -1 if all registers are true. 14919 The value of the complete result is indeterminate otherwise. */ 14920 switch (builtin_type) 14921 { 14922 case MIPS_BUILTIN_CMP_ALL: 14923 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx); 14924 return mips_builtin_branch_and_move (condition, target, 14925 const0_rtx, const1_rtx); 14926 14927 case MIPS_BUILTIN_CMP_UPPER: 14928 case MIPS_BUILTIN_CMP_LOWER: 14929 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER); 14930 condition = gen_single_cc (cmp_result, offset); 14931 return mips_builtin_branch_and_move (condition, target, 14932 const1_rtx, const0_rtx); 14933 14934 default: 14935 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx); 14936 return mips_builtin_branch_and_move (condition, target, 14937 const1_rtx, const0_rtx); 14938 } 14939} 14940 14941/* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET, 14942 if nonnull, suggests a good place to put the boolean result. */ 14943 14944static rtx 14945mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) 14946{ 14947 rtx condition, cmp_result; 14948 int cmp_value; 14949 14950 if (target == 0 || GET_MODE (target) != SImode) 14951 target = gen_reg_rtx (SImode); 14952 14953 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM); 14954 14955 if (builtin_type == MIPS_BUILTIN_BPOSGE32) 14956 cmp_value = 32; 14957 else 14958 gcc_assert (0); 14959 14960 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value)); 14961 return mips_builtin_branch_and_move (condition, target, 14962 const1_rtx, const0_rtx); 14963} 14964 14965/* Implement TARGET_EXPAND_BUILTIN. */ 14966 14967static rtx 14968mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, 14969 machine_mode mode, int ignore) 14970{ 14971 tree fndecl; 14972 unsigned int fcode, avail; 14973 const struct mips_builtin_description *d; 14974 14975 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 14976 fcode = DECL_FUNCTION_CODE (fndecl); 14977 gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); 14978 d = &mips_builtins[fcode]; 14979 avail = d->avail (); 14980 gcc_assert (avail != 0); 14981 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)) 14982 { 14983 error ("built-in function %qE not supported for MIPS16", 14984 DECL_NAME (fndecl)); 14985 return ignore ? const0_rtx : CONST0_RTX (mode); 14986 } 14987 switch (d->builtin_type) 14988 { 14989 case MIPS_BUILTIN_DIRECT: 14990 return mips_expand_builtin_direct (d->icode, target, exp, true); 14991 14992 case MIPS_BUILTIN_DIRECT_NO_TARGET: 14993 return mips_expand_builtin_direct (d->icode, target, exp, false); 14994 14995 case MIPS_BUILTIN_MOVT: 14996 case MIPS_BUILTIN_MOVF: 14997 return mips_expand_builtin_movtf (d->builtin_type, d->icode, 14998 d->cond, target, exp); 14999 15000 case MIPS_BUILTIN_CMP_ANY: 15001 case MIPS_BUILTIN_CMP_ALL: 15002 case MIPS_BUILTIN_CMP_UPPER: 15003 case MIPS_BUILTIN_CMP_LOWER: 15004 case MIPS_BUILTIN_CMP_SINGLE: 15005 return mips_expand_builtin_compare (d->builtin_type, d->icode, 15006 d->cond, target, exp); 15007 15008 case MIPS_BUILTIN_BPOSGE32: 15009 return mips_expand_builtin_bposge (d->builtin_type, target); 15010 } 15011 gcc_unreachable (); 15012} 15013 15014/* An entry in the MIPS16 constant pool. VALUE is the pool constant, 15015 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */ 15016struct mips16_constant { 15017 struct mips16_constant *next; 15018 rtx value; 15019 rtx_code_label *label; 15020 machine_mode mode; 15021}; 15022 15023/* Information about an incomplete MIPS16 constant pool. FIRST is the 15024 first constant, HIGHEST_ADDRESS is the highest address that the first 15025 byte of the pool can have, and INSN_ADDRESS is the current instruction 15026 address. */ 15027struct mips16_constant_pool { 15028 struct mips16_constant *first; 15029 int highest_address; 15030 int insn_address; 15031}; 15032 15033/* Add constant VALUE to POOL and return its label. MODE is the 15034 value's mode (used for CONST_INTs, etc.). */ 15035 15036static rtx_code_label * 15037mips16_add_constant (struct mips16_constant_pool *pool, 15038 rtx value, machine_mode mode) 15039{ 15040 struct mips16_constant **p, *c; 15041 bool first_of_size_p; 15042 15043 /* See whether the constant is already in the pool. If so, return the 15044 existing label, otherwise leave P pointing to the place where the 15045 constant should be added. 15046 15047 Keep the pool sorted in increasing order of mode size so that we can 15048 reduce the number of alignments needed. */ 15049 first_of_size_p = true; 15050 for (p = &pool->first; *p != 0; p = &(*p)->next) 15051 { 15052 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value)) 15053 return (*p)->label; 15054 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode)) 15055 break; 15056 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode)) 15057 first_of_size_p = false; 15058 } 15059 15060 /* In the worst case, the constant needed by the earliest instruction 15061 will end up at the end of the pool. The entire pool must then be 15062 accessible from that instruction. 15063 15064 When adding the first constant, set the pool's highest address to 15065 the address of the first out-of-range byte. Adjust this address 15066 downwards each time a new constant is added. */ 15067 if (pool->first == 0) 15068 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address 15069 of the instruction with the lowest two bits clear. The base PC 15070 value for LDPC has the lowest three bits clear. Assume the worst 15071 case here; namely that the PC-relative instruction occupies the 15072 last 2 bytes in an aligned word. */ 15073 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000; 15074 pool->highest_address -= GET_MODE_SIZE (mode); 15075 if (first_of_size_p) 15076 /* Take into account the worst possible padding due to alignment. */ 15077 pool->highest_address -= GET_MODE_SIZE (mode) - 1; 15078 15079 /* Create a new entry. */ 15080 c = XNEW (struct mips16_constant); 15081 c->value = value; 15082 c->mode = mode; 15083 c->label = gen_label_rtx (); 15084 c->next = *p; 15085 *p = c; 15086 15087 return c->label; 15088} 15089 15090/* Output constant VALUE after instruction INSN and return the last 15091 instruction emitted. MODE is the mode of the constant. */ 15092 15093static rtx_insn * 15094mips16_emit_constants_1 (machine_mode mode, rtx value, rtx_insn *insn) 15095{ 15096 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode)) 15097 { 15098 rtx size = GEN_INT (GET_MODE_SIZE (mode)); 15099 return emit_insn_after (gen_consttable_int (value, size), insn); 15100 } 15101 15102 if (SCALAR_FLOAT_MODE_P (mode)) 15103 return emit_insn_after (gen_consttable_float (value), insn); 15104 15105 if (VECTOR_MODE_P (mode)) 15106 { 15107 int i; 15108 15109 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++) 15110 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode), 15111 CONST_VECTOR_ELT (value, i), insn); 15112 return insn; 15113 } 15114 15115 gcc_unreachable (); 15116} 15117 15118/* Dump out the constants in CONSTANTS after INSN. */ 15119 15120static void 15121mips16_emit_constants (struct mips16_constant *constants, rtx_insn *insn) 15122{ 15123 struct mips16_constant *c, *next; 15124 int align; 15125 15126 align = 0; 15127 for (c = constants; c != NULL; c = next) 15128 { 15129 /* If necessary, increase the alignment of PC. */ 15130 if (align < GET_MODE_SIZE (c->mode)) 15131 { 15132 int align_log = floor_log2 (GET_MODE_SIZE (c->mode)); 15133 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn); 15134 } 15135 align = GET_MODE_SIZE (c->mode); 15136 15137 insn = emit_label_after (c->label, insn); 15138 insn = mips16_emit_constants_1 (c->mode, c->value, insn); 15139 15140 next = c->next; 15141 free (c); 15142 } 15143 15144 emit_barrier_after (insn); 15145} 15146 15147/* Return the length of instruction INSN. */ 15148 15149static int 15150mips16_insn_length (rtx_insn *insn) 15151{ 15152 if (JUMP_TABLE_DATA_P (insn)) 15153 { 15154 rtx body = PATTERN (insn); 15155 if (GET_CODE (body) == ADDR_VEC) 15156 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0); 15157 else if (GET_CODE (body) == ADDR_DIFF_VEC) 15158 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1); 15159 else 15160 gcc_unreachable (); 15161 } 15162 return get_attr_length (insn); 15163} 15164 15165/* If *X is a symbolic constant that refers to the constant pool, add 15166 the constant to POOL and rewrite *X to use the constant's label. */ 15167 15168static void 15169mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x) 15170{ 15171 rtx base, offset; 15172 rtx_code_label *label; 15173 15174 split_const (*x, &base, &offset); 15175 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base)) 15176 { 15177 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)), 15178 get_pool_mode (base)); 15179 base = gen_rtx_LABEL_REF (Pmode, label); 15180 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE); 15181 } 15182} 15183 15184/* Rewrite INSN so that constant pool references refer to the constant's 15185 label instead. */ 15186 15187static void 15188mips16_rewrite_pool_refs (rtx_insn *insn, struct mips16_constant_pool *pool) 15189{ 15190 subrtx_ptr_iterator::array_type array; 15191 FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), ALL) 15192 { 15193 rtx *loc = *iter; 15194 15195 if (force_to_mem_operand (*loc, Pmode)) 15196 { 15197 rtx mem = force_const_mem (GET_MODE (*loc), *loc); 15198 validate_change (insn, loc, mem, false); 15199 } 15200 15201 if (MEM_P (*loc)) 15202 { 15203 mips16_rewrite_pool_constant (pool, &XEXP (*loc, 0)); 15204 iter.skip_subrtxes (); 15205 } 15206 else 15207 { 15208 if (TARGET_MIPS16_TEXT_LOADS) 15209 mips16_rewrite_pool_constant (pool, loc); 15210 if (GET_CODE (*loc) == CONST 15211 /* Don't rewrite the __mips16_rdwr symbol. */ 15212 || (GET_CODE (*loc) == UNSPEC 15213 && XINT (*loc, 1) == UNSPEC_TLS_GET_TP)) 15214 iter.skip_subrtxes (); 15215 } 15216 } 15217} 15218 15219/* Return whether CFG is used in mips_reorg. */ 15220 15221static bool 15222mips_cfg_in_reorg (void) 15223{ 15224 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE 15225 || TARGET_RELAX_PIC_CALLS); 15226} 15227 15228/* Build MIPS16 constant pools. Split the instructions if SPLIT_P, 15229 otherwise assume that they are already split. */ 15230 15231static void 15232mips16_lay_out_constants (bool split_p) 15233{ 15234 struct mips16_constant_pool pool; 15235 rtx_insn *insn, *barrier; 15236 15237 if (!TARGET_MIPS16_PCREL_LOADS) 15238 return; 15239 15240 if (split_p) 15241 { 15242 if (mips_cfg_in_reorg ()) 15243 split_all_insns (); 15244 else 15245 split_all_insns_noflow (); 15246 } 15247 barrier = 0; 15248 memset (&pool, 0, sizeof (pool)); 15249 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 15250 { 15251 /* Rewrite constant pool references in INSN. */ 15252 if (USEFUL_INSN_P (insn)) 15253 mips16_rewrite_pool_refs (insn, &pool); 15254 15255 pool.insn_address += mips16_insn_length (insn); 15256 15257 if (pool.first != NULL) 15258 { 15259 /* If there are no natural barriers between the first user of 15260 the pool and the highest acceptable address, we'll need to 15261 create a new instruction to jump around the constant pool. 15262 In the worst case, this instruction will be 4 bytes long. 15263 15264 If it's too late to do this transformation after INSN, 15265 do it immediately before INSN. */ 15266 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address) 15267 { 15268 rtx_code_label *label; 15269 rtx_insn *jump; 15270 15271 label = gen_label_rtx (); 15272 15273 jump = emit_jump_insn_before (gen_jump (label), insn); 15274 JUMP_LABEL (jump) = label; 15275 LABEL_NUSES (label) = 1; 15276 barrier = emit_barrier_after (jump); 15277 15278 emit_label_after (label, barrier); 15279 pool.insn_address += 4; 15280 } 15281 15282 /* See whether the constant pool is now out of range of the first 15283 user. If so, output the constants after the previous barrier. 15284 Note that any instructions between BARRIER and INSN (inclusive) 15285 will use negative offsets to refer to the pool. */ 15286 if (pool.insn_address > pool.highest_address) 15287 { 15288 mips16_emit_constants (pool.first, barrier); 15289 pool.first = NULL; 15290 barrier = 0; 15291 } 15292 else if (BARRIER_P (insn)) 15293 barrier = insn; 15294 } 15295 } 15296 mips16_emit_constants (pool.first, get_last_insn ()); 15297} 15298 15299/* Return true if it is worth r10k_simplify_address's while replacing 15300 an address with X. We are looking for constants, and for addresses 15301 at a known offset from the incoming stack pointer. */ 15302 15303static bool 15304r10k_simplified_address_p (rtx x) 15305{ 15306 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) 15307 x = XEXP (x, 0); 15308 return x == virtual_incoming_args_rtx || CONSTANT_P (x); 15309} 15310 15311/* X is an expression that appears in INSN. Try to use the UD chains 15312 to simplify it, returning the simplified form on success and the 15313 original form otherwise. Replace the incoming value of $sp with 15314 virtual_incoming_args_rtx (which should never occur in X otherwise). */ 15315 15316static rtx 15317r10k_simplify_address (rtx x, rtx_insn *insn) 15318{ 15319 rtx newx, op0, op1, set, note; 15320 rtx_insn *def_insn; 15321 df_ref use, def; 15322 struct df_link *defs; 15323 15324 newx = NULL_RTX; 15325 if (UNARY_P (x)) 15326 { 15327 op0 = r10k_simplify_address (XEXP (x, 0), insn); 15328 if (op0 != XEXP (x, 0)) 15329 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x), 15330 op0, GET_MODE (XEXP (x, 0))); 15331 } 15332 else if (BINARY_P (x)) 15333 { 15334 op0 = r10k_simplify_address (XEXP (x, 0), insn); 15335 op1 = r10k_simplify_address (XEXP (x, 1), insn); 15336 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) 15337 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); 15338 } 15339 else if (GET_CODE (x) == LO_SUM) 15340 { 15341 /* LO_SUMs can be offset from HIGHs, if we know they won't 15342 overflow. See mips_classify_address for the rationale behind 15343 the lax check. */ 15344 op0 = r10k_simplify_address (XEXP (x, 0), insn); 15345 if (GET_CODE (op0) == HIGH) 15346 newx = XEXP (x, 1); 15347 } 15348 else if (REG_P (x)) 15349 { 15350 /* Uses are recorded by regno_reg_rtx, not X itself. */ 15351 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]); 15352 gcc_assert (use); 15353 defs = DF_REF_CHAIN (use); 15354 15355 /* Require a single definition. */ 15356 if (defs && defs->next == NULL) 15357 { 15358 def = defs->ref; 15359 if (DF_REF_IS_ARTIFICIAL (def)) 15360 { 15361 /* Replace the incoming value of $sp with 15362 virtual_incoming_args_rtx. */ 15363 if (x == stack_pointer_rtx 15364 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) 15365 newx = virtual_incoming_args_rtx; 15366 } 15367 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use), 15368 DF_REF_BB (def))) 15369 { 15370 /* Make sure that DEF_INSN is a single set of REG. */ 15371 def_insn = DF_REF_INSN (def); 15372 if (NONJUMP_INSN_P (def_insn)) 15373 { 15374 set = single_set (def_insn); 15375 if (set && rtx_equal_p (SET_DEST (set), x)) 15376 { 15377 /* Prefer to use notes, since the def-use chains 15378 are often shorter. */ 15379 note = find_reg_equal_equiv_note (def_insn); 15380 if (note) 15381 newx = XEXP (note, 0); 15382 else 15383 newx = SET_SRC (set); 15384 newx = r10k_simplify_address (newx, def_insn); 15385 } 15386 } 15387 } 15388 } 15389 } 15390 if (newx && r10k_simplified_address_p (newx)) 15391 return newx; 15392 return x; 15393} 15394 15395/* Return true if ADDRESS is known to be an uncached address 15396 on R10K systems. */ 15397 15398static bool 15399r10k_uncached_address_p (unsigned HOST_WIDE_INT address) 15400{ 15401 unsigned HOST_WIDE_INT upper; 15402 15403 /* Check for KSEG1. */ 15404 if (address + 0x60000000 < 0x20000000) 15405 return true; 15406 15407 /* Check for uncached XKPHYS addresses. */ 15408 if (Pmode == DImode) 15409 { 15410 upper = (address >> 40) & 0xf9ffff; 15411 if (upper == 0x900000 || upper == 0xb80000) 15412 return true; 15413 } 15414 return false; 15415} 15416 15417/* Return true if we can prove that an access to address X in instruction 15418 INSN would be safe from R10K speculation. This X is a general 15419 expression; it might not be a legitimate address. */ 15420 15421static bool 15422r10k_safe_address_p (rtx x, rtx_insn *insn) 15423{ 15424 rtx base, offset; 15425 HOST_WIDE_INT offset_val; 15426 15427 x = r10k_simplify_address (x, insn); 15428 15429 /* Check for references to the stack frame. It doesn't really matter 15430 how much of the frame has been allocated at INSN; -mr10k-cache-barrier 15431 allows us to assume that accesses to any part of the eventual frame 15432 is safe from speculation at any point in the function. */ 15433 mips_split_plus (x, &base, &offset_val); 15434 if (base == virtual_incoming_args_rtx 15435 && offset_val >= -cfun->machine->frame.total_size 15436 && offset_val < cfun->machine->frame.args_size) 15437 return true; 15438 15439 /* Check for uncached addresses. */ 15440 if (CONST_INT_P (x)) 15441 return r10k_uncached_address_p (INTVAL (x)); 15442 15443 /* Check for accesses to a static object. */ 15444 split_const (x, &base, &offset); 15445 return offset_within_block_p (base, INTVAL (offset)); 15446} 15447 15448/* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is 15449 an in-range access to an automatic variable, or to an object with 15450 a link-time-constant address. */ 15451 15452static bool 15453r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset) 15454{ 15455 HOST_WIDE_INT bitoffset, bitsize; 15456 tree inner, var_offset; 15457 machine_mode mode; 15458 int unsigned_p, volatile_p; 15459 15460 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode, 15461 &unsigned_p, &volatile_p, false); 15462 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset) 15463 return false; 15464 15465 offset += bitoffset / BITS_PER_UNIT; 15466 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner)); 15467} 15468 15469/* Return true if X contains a MEM that is not safe from R10K speculation. 15470 INSN is the instruction that contains X. */ 15471 15472static bool 15473r10k_needs_protection_p_1 (rtx x, rtx_insn *insn) 15474{ 15475 subrtx_var_iterator::array_type array; 15476 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) 15477 { 15478 rtx mem = *iter; 15479 if (MEM_P (mem)) 15480 { 15481 if ((MEM_EXPR (mem) 15482 && MEM_OFFSET_KNOWN_P (mem) 15483 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem))) 15484 || r10k_safe_address_p (XEXP (mem, 0), insn)) 15485 iter.skip_subrtxes (); 15486 else 15487 return true; 15488 } 15489 } 15490 return false; 15491} 15492 15493/* A note_stores callback for which DATA points to an instruction pointer. 15494 If *DATA is nonnull, make it null if it X contains a MEM that is not 15495 safe from R10K speculation. */ 15496 15497static void 15498r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED, 15499 void *data) 15500{ 15501 rtx_insn **insn_ptr; 15502 15503 insn_ptr = (rtx_insn **) data; 15504 if (*insn_ptr && r10k_needs_protection_p_1 (x, *insn_ptr)) 15505 *insn_ptr = NULL; 15506} 15507 15508/* X is the pattern of a call instruction. Return true if the call is 15509 not to a declared function. */ 15510 15511static bool 15512r10k_needs_protection_p_call (const_rtx x) 15513{ 15514 subrtx_iterator::array_type array; 15515 FOR_EACH_SUBRTX (iter, array, x, NONCONST) 15516 { 15517 const_rtx mem = *iter; 15518 if (MEM_P (mem)) 15519 { 15520 const_rtx addr = XEXP (mem, 0); 15521 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DECL (addr)) 15522 iter.skip_subrtxes (); 15523 else 15524 return true; 15525 } 15526 } 15527 return false; 15528} 15529 15530/* Return true if instruction INSN needs to be protected by an R10K 15531 cache barrier. */ 15532 15533static bool 15534r10k_needs_protection_p (rtx_insn *insn) 15535{ 15536 if (CALL_P (insn)) 15537 return r10k_needs_protection_p_call (PATTERN (insn)); 15538 15539 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE) 15540 { 15541 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn); 15542 return insn == NULL_RTX; 15543 } 15544 15545 return r10k_needs_protection_p_1 (PATTERN (insn), insn); 15546} 15547 15548/* Return true if BB is only reached by blocks in PROTECTED_BBS and if every 15549 edge is unconditional. */ 15550 15551static bool 15552r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs) 15553{ 15554 edge_iterator ei; 15555 edge e; 15556 15557 FOR_EACH_EDGE (e, ei, bb->preds) 15558 if (!single_succ_p (e->src) 15559 || !bitmap_bit_p (protected_bbs, e->src->index) 15560 || (e->flags & EDGE_COMPLEX) != 0) 15561 return false; 15562 return true; 15563} 15564 15565/* Implement -mr10k-cache-barrier= for the current function. */ 15566 15567static void 15568r10k_insert_cache_barriers (void) 15569{ 15570 int *rev_post_order; 15571 unsigned int i, n; 15572 basic_block bb; 15573 sbitmap protected_bbs; 15574 rtx_insn *insn, *end; 15575 rtx unprotected_region; 15576 15577 if (TARGET_MIPS16) 15578 { 15579 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier"); 15580 return; 15581 } 15582 15583 /* Calculate dominators. */ 15584 calculate_dominance_info (CDI_DOMINATORS); 15585 15586 /* Bit X of PROTECTED_BBS is set if the last operation in basic block 15587 X is protected by a cache barrier. */ 15588 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun)); 15589 bitmap_clear (protected_bbs); 15590 15591 /* Iterate over the basic blocks in reverse post-order. */ 15592 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun)); 15593 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false); 15594 for (i = 0; i < n; i++) 15595 { 15596 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]); 15597 15598 /* If this block is only reached by unconditional edges, and if the 15599 source of every edge is protected, the beginning of the block is 15600 also protected. */ 15601 if (r10k_protected_bb_p (bb, protected_bbs)) 15602 unprotected_region = NULL_RTX; 15603 else 15604 unprotected_region = pc_rtx; 15605 end = NEXT_INSN (BB_END (bb)); 15606 15607 /* UNPROTECTED_REGION is: 15608 15609 - null if we are processing a protected region, 15610 - pc_rtx if we are processing an unprotected region but have 15611 not yet found the first instruction in it 15612 - the first instruction in an unprotected region otherwise. */ 15613 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn)) 15614 { 15615 if (unprotected_region && USEFUL_INSN_P (insn)) 15616 { 15617 if (recog_memoized (insn) == CODE_FOR_mips_cache) 15618 /* This CACHE instruction protects the following code. */ 15619 unprotected_region = NULL_RTX; 15620 else 15621 { 15622 /* See if INSN is the first instruction in this 15623 unprotected region. */ 15624 if (unprotected_region == pc_rtx) 15625 unprotected_region = insn; 15626 15627 /* See if INSN needs to be protected. If so, 15628 we must insert a cache barrier somewhere between 15629 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't 15630 clear which position is better performance-wise, 15631 but as a tie-breaker, we assume that it is better 15632 to allow delay slots to be back-filled where 15633 possible, and that it is better not to insert 15634 barriers in the middle of already-scheduled code. 15635 We therefore insert the barrier at the beginning 15636 of the region. */ 15637 if (r10k_needs_protection_p (insn)) 15638 { 15639 emit_insn_before (gen_r10k_cache_barrier (), 15640 unprotected_region); 15641 unprotected_region = NULL_RTX; 15642 } 15643 } 15644 } 15645 15646 if (CALL_P (insn)) 15647 /* The called function is not required to protect the exit path. 15648 The code that follows a call is therefore unprotected. */ 15649 unprotected_region = pc_rtx; 15650 } 15651 15652 /* Record whether the end of this block is protected. */ 15653 if (unprotected_region == NULL_RTX) 15654 bitmap_set_bit (protected_bbs, bb->index); 15655 } 15656 XDELETEVEC (rev_post_order); 15657 15658 sbitmap_free (protected_bbs); 15659 15660 free_dominance_info (CDI_DOMINATORS); 15661} 15662 15663/* If INSN is a call, return the underlying CALL expr. Return NULL_RTX 15664 otherwise. If INSN has two call rtx, then store the second one in 15665 SECOND_CALL. */ 15666 15667static rtx 15668mips_call_expr_from_insn (rtx_insn *insn, rtx *second_call) 15669{ 15670 rtx x; 15671 rtx x2; 15672 15673 if (!CALL_P (insn)) 15674 return NULL_RTX; 15675 15676 x = PATTERN (insn); 15677 if (GET_CODE (x) == PARALLEL) 15678 { 15679 /* Calls returning complex values have two CALL rtx. Look for the second 15680 one here, and return it via the SECOND_CALL arg. */ 15681 x2 = XVECEXP (x, 0, 1); 15682 if (GET_CODE (x2) == SET) 15683 x2 = XEXP (x2, 1); 15684 if (GET_CODE (x2) == CALL) 15685 *second_call = x2; 15686 15687 x = XVECEXP (x, 0, 0); 15688 } 15689 if (GET_CODE (x) == SET) 15690 x = XEXP (x, 1); 15691 gcc_assert (GET_CODE (x) == CALL); 15692 15693 return x; 15694} 15695 15696/* REG is set in DEF. See if the definition is one of the ways we load a 15697 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. 15698 If it is, return the symbol reference of the function, otherwise return 15699 NULL_RTX. 15700 15701 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret 15702 the values of source registers, otherwise treat such registers as 15703 having an unknown value. */ 15704 15705static rtx 15706mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p) 15707{ 15708 rtx_insn *def_insn; 15709 rtx set; 15710 15711 if (DF_REF_IS_ARTIFICIAL (def)) 15712 return NULL_RTX; 15713 15714 def_insn = DF_REF_INSN (def); 15715 set = single_set (def_insn); 15716 if (set && rtx_equal_p (SET_DEST (set), reg)) 15717 { 15718 rtx note, src, symbol; 15719 15720 /* First see whether the source is a plain symbol. This is used 15721 when calling symbols that are not lazily bound. */ 15722 src = SET_SRC (set); 15723 if (GET_CODE (src) == SYMBOL_REF) 15724 return src; 15725 15726 /* Handle %call16 references. */ 15727 symbol = mips_strip_unspec_call (src); 15728 if (symbol) 15729 { 15730 gcc_assert (GET_CODE (symbol) == SYMBOL_REF); 15731 return symbol; 15732 } 15733 15734 /* If we have something more complicated, look for a 15735 REG_EQUAL or REG_EQUIV note. */ 15736 note = find_reg_equal_equiv_note (def_insn); 15737 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) 15738 return XEXP (note, 0); 15739 15740 /* Follow at most one simple register copy. Such copies are 15741 interesting in cases like: 15742 15743 for (...) 15744 { 15745 locally_binding_fn (...); 15746 } 15747 15748 and: 15749 15750 locally_binding_fn (...); 15751 ... 15752 locally_binding_fn (...); 15753 15754 where the load of locally_binding_fn can legitimately be 15755 hoisted or shared. However, we do not expect to see complex 15756 chains of copies, so a full worklist solution to the problem 15757 would probably be overkill. */ 15758 if (recurse_p && REG_P (src)) 15759 return mips_find_pic_call_symbol (def_insn, src, false); 15760 } 15761 15762 return NULL_RTX; 15763} 15764 15765/* Find the definition of the use of REG in INSN. See if the definition 15766 is one of the ways we load a register with a symbol address for a 15767 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference 15768 of the function, otherwise return NULL_RTX. RECURSE_P is as for 15769 mips_pic_call_symbol_from_set. */ 15770 15771static rtx 15772mips_find_pic_call_symbol (rtx_insn *insn, rtx reg, bool recurse_p) 15773{ 15774 df_ref use; 15775 struct df_link *defs; 15776 rtx symbol; 15777 15778 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]); 15779 if (!use) 15780 return NULL_RTX; 15781 defs = DF_REF_CHAIN (use); 15782 if (!defs) 15783 return NULL_RTX; 15784 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); 15785 if (!symbol) 15786 return NULL_RTX; 15787 15788 /* If we have more than one definition, they need to be identical. */ 15789 for (defs = defs->next; defs; defs = defs->next) 15790 { 15791 rtx other; 15792 15793 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p); 15794 if (!rtx_equal_p (symbol, other)) 15795 return NULL_RTX; 15796 } 15797 15798 return symbol; 15799} 15800 15801/* Replace the args_size operand of the call expression CALL with the 15802 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */ 15803 15804static void 15805mips_annotate_pic_call_expr (rtx call, rtx symbol) 15806{ 15807 rtx args_size; 15808 15809 args_size = XEXP (call, 1); 15810 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size), 15811 gen_rtvec (2, args_size, symbol), 15812 UNSPEC_CALL_ATTR); 15813} 15814 15815/* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See 15816 if instead of the arg_size argument it contains the call attributes. If 15817 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function 15818 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is 15819 -1. */ 15820 15821bool 15822mips_get_pic_call_symbol (rtx *operands, int args_size_opno) 15823{ 15824 rtx args_size, symbol; 15825 15826 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1) 15827 return false; 15828 15829 args_size = operands[args_size_opno]; 15830 if (GET_CODE (args_size) != UNSPEC) 15831 return false; 15832 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR); 15833 15834 symbol = XVECEXP (args_size, 0, 1); 15835 gcc_assert (GET_CODE (symbol) == SYMBOL_REF); 15836 15837 operands[args_size_opno] = symbol; 15838 return true; 15839} 15840 15841/* Use DF to annotate PIC indirect calls with the function symbol they 15842 dispatch to. */ 15843 15844static void 15845mips_annotate_pic_calls (void) 15846{ 15847 basic_block bb; 15848 rtx_insn *insn; 15849 15850 FOR_EACH_BB_FN (bb, cfun) 15851 FOR_BB_INSNS (bb, insn) 15852 { 15853 rtx call, reg, symbol, second_call; 15854 15855 second_call = 0; 15856 call = mips_call_expr_from_insn (insn, &second_call); 15857 if (!call) 15858 continue; 15859 gcc_assert (MEM_P (XEXP (call, 0))); 15860 reg = XEXP (XEXP (call, 0), 0); 15861 if (!REG_P (reg)) 15862 continue; 15863 15864 symbol = mips_find_pic_call_symbol (insn, reg, true); 15865 if (symbol) 15866 { 15867 mips_annotate_pic_call_expr (call, symbol); 15868 if (second_call) 15869 mips_annotate_pic_call_expr (second_call, symbol); 15870 } 15871 } 15872} 15873 15874/* A temporary variable used by note_uses callbacks, etc. */ 15875static rtx_insn *mips_sim_insn; 15876 15877/* A structure representing the state of the processor pipeline. 15878 Used by the mips_sim_* family of functions. */ 15879struct mips_sim { 15880 /* The maximum number of instructions that can be issued in a cycle. 15881 (Caches mips_issue_rate.) */ 15882 unsigned int issue_rate; 15883 15884 /* The current simulation time. */ 15885 unsigned int time; 15886 15887 /* How many more instructions can be issued in the current cycle. */ 15888 unsigned int insns_left; 15889 15890 /* LAST_SET[X].INSN is the last instruction to set register X. 15891 LAST_SET[X].TIME is the time at which that instruction was issued. 15892 INSN is null if no instruction has yet set register X. */ 15893 struct { 15894 rtx_insn *insn; 15895 unsigned int time; 15896 } last_set[FIRST_PSEUDO_REGISTER]; 15897 15898 /* The pipeline's current DFA state. */ 15899 state_t dfa_state; 15900}; 15901 15902/* Reset STATE to the initial simulation state. */ 15903 15904static void 15905mips_sim_reset (struct mips_sim *state) 15906{ 15907 curr_state = state->dfa_state; 15908 15909 state->time = 0; 15910 state->insns_left = state->issue_rate; 15911 memset (&state->last_set, 0, sizeof (state->last_set)); 15912 state_reset (curr_state); 15913 15914 targetm.sched.init (0, false, 0); 15915 advance_state (curr_state); 15916} 15917 15918/* Initialize STATE before its first use. DFA_STATE points to an 15919 allocated but uninitialized DFA state. */ 15920 15921static void 15922mips_sim_init (struct mips_sim *state, state_t dfa_state) 15923{ 15924 if (targetm.sched.init_dfa_pre_cycle_insn) 15925 targetm.sched.init_dfa_pre_cycle_insn (); 15926 15927 if (targetm.sched.init_dfa_post_cycle_insn) 15928 targetm.sched.init_dfa_post_cycle_insn (); 15929 15930 state->issue_rate = mips_issue_rate (); 15931 state->dfa_state = dfa_state; 15932 mips_sim_reset (state); 15933} 15934 15935/* Advance STATE by one clock cycle. */ 15936 15937static void 15938mips_sim_next_cycle (struct mips_sim *state) 15939{ 15940 curr_state = state->dfa_state; 15941 15942 state->time++; 15943 state->insns_left = state->issue_rate; 15944 advance_state (curr_state); 15945} 15946 15947/* Advance simulation state STATE until instruction INSN can read 15948 register REG. */ 15949 15950static void 15951mips_sim_wait_reg (struct mips_sim *state, rtx_insn *insn, rtx reg) 15952{ 15953 unsigned int regno, end_regno; 15954 15955 end_regno = END_REGNO (reg); 15956 for (regno = REGNO (reg); regno < end_regno; regno++) 15957 if (state->last_set[regno].insn != 0) 15958 { 15959 unsigned int t; 15960 15961 t = (state->last_set[regno].time 15962 + insn_latency (state->last_set[regno].insn, insn)); 15963 while (state->time < t) 15964 mips_sim_next_cycle (state); 15965 } 15966} 15967 15968/* A note_uses callback. For each register in *X, advance simulation 15969 state DATA until mips_sim_insn can read the register's value. */ 15970 15971static void 15972mips_sim_wait_regs_1 (rtx *x, void *data) 15973{ 15974 subrtx_var_iterator::array_type array; 15975 FOR_EACH_SUBRTX_VAR (iter, array, *x, NONCONST) 15976 if (REG_P (*iter)) 15977 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *iter); 15978} 15979 15980/* Advance simulation state STATE until all of INSN's register 15981 dependencies are satisfied. */ 15982 15983static void 15984mips_sim_wait_regs (struct mips_sim *state, rtx_insn *insn) 15985{ 15986 mips_sim_insn = insn; 15987 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state); 15988} 15989 15990/* Advance simulation state STATE until the units required by 15991 instruction INSN are available. */ 15992 15993static void 15994mips_sim_wait_units (struct mips_sim *state, rtx_insn *insn) 15995{ 15996 state_t tmp_state; 15997 15998 tmp_state = alloca (state_size ()); 15999 while (state->insns_left == 0 16000 || (memcpy (tmp_state, state->dfa_state, state_size ()), 16001 state_transition (tmp_state, insn) >= 0)) 16002 mips_sim_next_cycle (state); 16003} 16004 16005/* Advance simulation state STATE until INSN is ready to issue. */ 16006 16007static void 16008mips_sim_wait_insn (struct mips_sim *state, rtx_insn *insn) 16009{ 16010 mips_sim_wait_regs (state, insn); 16011 mips_sim_wait_units (state, insn); 16012} 16013 16014/* mips_sim_insn has just set X. Update the LAST_SET array 16015 in simulation state DATA. */ 16016 16017static void 16018mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 16019{ 16020 struct mips_sim *state; 16021 16022 state = (struct mips_sim *) data; 16023 if (REG_P (x)) 16024 { 16025 unsigned int regno, end_regno; 16026 16027 end_regno = END_REGNO (x); 16028 for (regno = REGNO (x); regno < end_regno; regno++) 16029 { 16030 state->last_set[regno].insn = mips_sim_insn; 16031 state->last_set[regno].time = state->time; 16032 } 16033 } 16034} 16035 16036/* Issue instruction INSN in scheduler state STATE. Assume that INSN 16037 can issue immediately (i.e., that mips_sim_wait_insn has already 16038 been called). */ 16039 16040static void 16041mips_sim_issue_insn (struct mips_sim *state, rtx_insn *insn) 16042{ 16043 curr_state = state->dfa_state; 16044 16045 state_transition (curr_state, insn); 16046 state->insns_left = targetm.sched.variable_issue (0, false, insn, 16047 state->insns_left); 16048 16049 mips_sim_insn = insn; 16050 note_stores (PATTERN (insn), mips_sim_record_set, state); 16051} 16052 16053/* Simulate issuing a NOP in state STATE. */ 16054 16055static void 16056mips_sim_issue_nop (struct mips_sim *state) 16057{ 16058 if (state->insns_left == 0) 16059 mips_sim_next_cycle (state); 16060 state->insns_left--; 16061} 16062 16063/* Update simulation state STATE so that it's ready to accept the instruction 16064 after INSN. INSN should be part of the main rtl chain, not a member of a 16065 SEQUENCE. */ 16066 16067static void 16068mips_sim_finish_insn (struct mips_sim *state, rtx_insn *insn) 16069{ 16070 /* If INSN is a jump with an implicit delay slot, simulate a nop. */ 16071 if (JUMP_P (insn)) 16072 mips_sim_issue_nop (state); 16073 16074 switch (GET_CODE (SEQ_BEGIN (insn))) 16075 { 16076 case CODE_LABEL: 16077 case CALL_INSN: 16078 /* We can't predict the processor state after a call or label. */ 16079 mips_sim_reset (state); 16080 break; 16081 16082 case JUMP_INSN: 16083 /* The delay slots of branch likely instructions are only executed 16084 when the branch is taken. Therefore, if the caller has simulated 16085 the delay slot instruction, STATE does not really reflect the state 16086 of the pipeline for the instruction after the delay slot. Also, 16087 branch likely instructions tend to incur a penalty when not taken, 16088 so there will probably be an extra delay between the branch and 16089 the instruction after the delay slot. */ 16090 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn))) 16091 mips_sim_reset (state); 16092 break; 16093 16094 default: 16095 break; 16096 } 16097} 16098 16099/* Use simulator state STATE to calculate the execution time of 16100 instruction sequence SEQ. */ 16101 16102static unsigned int 16103mips_seq_time (struct mips_sim *state, rtx_insn *seq) 16104{ 16105 mips_sim_reset (state); 16106 for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn)) 16107 { 16108 mips_sim_wait_insn (state, insn); 16109 mips_sim_issue_insn (state, insn); 16110 } 16111 return state->time; 16112} 16113 16114/* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p 16115 setting SETTING, using STATE to simulate instruction sequences. */ 16116 16117static unsigned int 16118mips_mult_zero_zero_cost (struct mips_sim *state, bool setting) 16119{ 16120 mips_tuning_info.fast_mult_zero_zero_p = setting; 16121 start_sequence (); 16122 16123 machine_mode dword_mode = TARGET_64BIT ? TImode : DImode; 16124 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST); 16125 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED); 16126 16127 /* If the target provides mulsidi3_32bit then that's the most likely 16128 consumer of the result. Test for bypasses. */ 16129 if (dword_mode == DImode && HAVE_maddsidi4) 16130 { 16131 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4); 16132 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo)); 16133 } 16134 16135 unsigned int time = mips_seq_time (state, get_insns ()); 16136 end_sequence (); 16137 return time; 16138} 16139 16140/* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0" 16141 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly. 16142 Prefer MULT -- which is shorter -- in the event of a tie. */ 16143 16144static void 16145mips_set_fast_mult_zero_zero_p (struct mips_sim *state) 16146{ 16147 if (TARGET_MIPS16 || !ISA_HAS_HILO) 16148 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO 16149 registers then there is no reason to zero them, arbitrarily choose to 16150 say that "MULT $0,$0" would be faster. */ 16151 mips_tuning_info.fast_mult_zero_zero_p = true; 16152 else 16153 { 16154 unsigned int true_time = mips_mult_zero_zero_cost (state, true); 16155 unsigned int false_time = mips_mult_zero_zero_cost (state, false); 16156 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time); 16157 } 16158} 16159 16160/* Set up costs based on the current architecture and tuning settings. */ 16161 16162static void 16163mips_set_tuning_info (void) 16164{ 16165 if (mips_tuning_info.initialized_p 16166 && mips_tuning_info.arch == mips_arch 16167 && mips_tuning_info.tune == mips_tune 16168 && mips_tuning_info.mips16_p == TARGET_MIPS16) 16169 return; 16170 16171 mips_tuning_info.arch = mips_arch; 16172 mips_tuning_info.tune = mips_tune; 16173 mips_tuning_info.mips16_p = TARGET_MIPS16; 16174 mips_tuning_info.initialized_p = true; 16175 16176 dfa_start (); 16177 16178 struct mips_sim state; 16179 mips_sim_init (&state, alloca (state_size ())); 16180 16181 mips_set_fast_mult_zero_zero_p (&state); 16182 16183 dfa_finish (); 16184} 16185 16186/* Implement TARGET_EXPAND_TO_RTL_HOOK. */ 16187 16188static void 16189mips_expand_to_rtl_hook (void) 16190{ 16191 /* We need to call this at a point where we can safely create sequences 16192 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also 16193 need to call it at a point where the DFA infrastructure is not 16194 already in use, so we can't just call it lazily on demand. 16195 16196 At present, mips_tuning_info is only needed during post-expand 16197 RTL passes such as split_insns, so this hook should be early enough. 16198 We may need to move the call elsewhere if mips_tuning_info starts 16199 to be used for other things (such as rtx_costs, or expanders that 16200 could be called during gimple optimization). */ 16201 mips_set_tuning_info (); 16202} 16203 16204/* The VR4130 pipeline issues aligned pairs of instructions together, 16205 but it stalls the second instruction if it depends on the first. 16206 In order to cut down the amount of logic required, this dependence 16207 check is not based on a full instruction decode. Instead, any non-SPECIAL 16208 instruction is assumed to modify the register specified by bits 20-16 16209 (which is usually the "rt" field). 16210 16211 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an 16212 input, so we can end up with a false dependence between the branch 16213 and its delay slot. If this situation occurs in instruction INSN, 16214 try to avoid it by swapping rs and rt. */ 16215 16216static void 16217vr4130_avoid_branch_rt_conflict (rtx_insn *insn) 16218{ 16219 rtx_insn *first, *second; 16220 16221 first = SEQ_BEGIN (insn); 16222 second = SEQ_END (insn); 16223 if (JUMP_P (first) 16224 && NONJUMP_INSN_P (second) 16225 && GET_CODE (PATTERN (first)) == SET 16226 && GET_CODE (SET_DEST (PATTERN (first))) == PC 16227 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE) 16228 { 16229 /* Check for the right kind of condition. */ 16230 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0); 16231 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) 16232 && REG_P (XEXP (cond, 0)) 16233 && REG_P (XEXP (cond, 1)) 16234 && reg_referenced_p (XEXP (cond, 1), PATTERN (second)) 16235 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second))) 16236 { 16237 /* SECOND mentions the rt register but not the rs register. */ 16238 rtx tmp = XEXP (cond, 0); 16239 XEXP (cond, 0) = XEXP (cond, 1); 16240 XEXP (cond, 1) = tmp; 16241 } 16242 } 16243} 16244 16245/* Implement -mvr4130-align. Go through each basic block and simulate the 16246 processor pipeline. If we find that a pair of instructions could execute 16247 in parallel, and the first of those instructions is not 8-byte aligned, 16248 insert a nop to make it aligned. */ 16249 16250static void 16251vr4130_align_insns (void) 16252{ 16253 struct mips_sim state; 16254 rtx_insn *insn, *subinsn, *last, *last2, *next; 16255 bool aligned_p; 16256 16257 dfa_start (); 16258 16259 /* LAST is the last instruction before INSN to have a nonzero length. 16260 LAST2 is the last such instruction before LAST. */ 16261 last = 0; 16262 last2 = 0; 16263 16264 /* ALIGNED_P is true if INSN is known to be at an aligned address. */ 16265 aligned_p = true; 16266 16267 mips_sim_init (&state, alloca (state_size ())); 16268 for (insn = get_insns (); insn != 0; insn = next) 16269 { 16270 unsigned int length; 16271 16272 next = NEXT_INSN (insn); 16273 16274 /* See the comment above vr4130_avoid_branch_rt_conflict for details. 16275 This isn't really related to the alignment pass, but we do it on 16276 the fly to avoid a separate instruction walk. */ 16277 vr4130_avoid_branch_rt_conflict (insn); 16278 16279 length = get_attr_length (insn); 16280 if (length > 0 && USEFUL_INSN_P (insn)) 16281 FOR_EACH_SUBINSN (subinsn, insn) 16282 { 16283 mips_sim_wait_insn (&state, subinsn); 16284 16285 /* If we want this instruction to issue in parallel with the 16286 previous one, make sure that the previous instruction is 16287 aligned. There are several reasons why this isn't worthwhile 16288 when the second instruction is a call: 16289 16290 - Calls are less likely to be performance critical, 16291 - There's a good chance that the delay slot can execute 16292 in parallel with the call. 16293 - The return address would then be unaligned. 16294 16295 In general, if we're going to insert a nop between instructions 16296 X and Y, it's better to insert it immediately after X. That 16297 way, if the nop makes Y aligned, it will also align any labels 16298 between X and Y. */ 16299 if (state.insns_left != state.issue_rate 16300 && !CALL_P (subinsn)) 16301 { 16302 if (subinsn == SEQ_BEGIN (insn) && aligned_p) 16303 { 16304 /* SUBINSN is the first instruction in INSN and INSN is 16305 aligned. We want to align the previous instruction 16306 instead, so insert a nop between LAST2 and LAST. 16307 16308 Note that LAST could be either a single instruction 16309 or a branch with a delay slot. In the latter case, 16310 LAST, like INSN, is already aligned, but the delay 16311 slot must have some extra delay that stops it from 16312 issuing at the same time as the branch. We therefore 16313 insert a nop before the branch in order to align its 16314 delay slot. */ 16315 gcc_assert (last2); 16316 emit_insn_after (gen_nop (), last2); 16317 aligned_p = false; 16318 } 16319 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p) 16320 { 16321 /* SUBINSN is the delay slot of INSN, but INSN is 16322 currently unaligned. Insert a nop between 16323 LAST and INSN to align it. */ 16324 gcc_assert (last); 16325 emit_insn_after (gen_nop (), last); 16326 aligned_p = true; 16327 } 16328 } 16329 mips_sim_issue_insn (&state, subinsn); 16330 } 16331 mips_sim_finish_insn (&state, insn); 16332 16333 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ 16334 length = get_attr_length (insn); 16335 if (length > 0) 16336 { 16337 /* If the instruction is an asm statement or multi-instruction 16338 mips.md patern, the length is only an estimate. Insert an 16339 8 byte alignment after it so that the following instructions 16340 can be handled correctly. */ 16341 if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) 16342 && (recog_memoized (insn) < 0 || length >= 8)) 16343 { 16344 next = emit_insn_after (gen_align (GEN_INT (3)), insn); 16345 next = NEXT_INSN (next); 16346 mips_sim_next_cycle (&state); 16347 aligned_p = true; 16348 } 16349 else if (length & 4) 16350 aligned_p = !aligned_p; 16351 last2 = last; 16352 last = insn; 16353 } 16354 16355 /* See whether INSN is an aligned label. */ 16356 if (LABEL_P (insn) && label_to_alignment (insn) >= 3) 16357 aligned_p = true; 16358 } 16359 dfa_finish (); 16360} 16361 16362/* This structure records that the current function has a LO_SUM 16363 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is 16364 the largest offset applied to BASE by all such LO_SUMs. */ 16365struct mips_lo_sum_offset { 16366 rtx base; 16367 HOST_WIDE_INT offset; 16368}; 16369 16370/* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ 16371 16372static hashval_t 16373mips_hash_base (rtx base) 16374{ 16375 int do_not_record_p; 16376 16377 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); 16378} 16379 16380/* Hashtable helpers. */ 16381 16382struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset> 16383{ 16384 typedef mips_lo_sum_offset value_type; 16385 typedef rtx_def compare_type; 16386 static inline hashval_t hash (const value_type *); 16387 static inline bool equal (const value_type *, const compare_type *); 16388}; 16389 16390/* Hash-table callbacks for mips_lo_sum_offsets. */ 16391 16392inline hashval_t 16393mips_lo_sum_offset_hasher::hash (const value_type *entry) 16394{ 16395 return mips_hash_base (entry->base); 16396} 16397 16398inline bool 16399mips_lo_sum_offset_hasher::equal (const value_type *entry, 16400 const compare_type *value) 16401{ 16402 return rtx_equal_p (entry->base, value); 16403} 16404 16405typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table; 16406 16407/* Look up symbolic constant X in HTAB, which is a hash table of 16408 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be 16409 paired with a recorded LO_SUM, otherwise record X in the table. */ 16410 16411static bool 16412mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x, 16413 enum insert_option option) 16414{ 16415 rtx base, offset; 16416 mips_lo_sum_offset **slot; 16417 struct mips_lo_sum_offset *entry; 16418 16419 /* Split X into a base and offset. */ 16420 split_const (x, &base, &offset); 16421 if (UNSPEC_ADDRESS_P (base)) 16422 base = UNSPEC_ADDRESS (base); 16423 16424 /* Look up the base in the hash table. */ 16425 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option); 16426 if (slot == NULL) 16427 return false; 16428 16429 entry = (struct mips_lo_sum_offset *) *slot; 16430 if (option == INSERT) 16431 { 16432 if (entry == NULL) 16433 { 16434 entry = XNEW (struct mips_lo_sum_offset); 16435 entry->base = base; 16436 entry->offset = INTVAL (offset); 16437 *slot = entry; 16438 } 16439 else 16440 { 16441 if (INTVAL (offset) > entry->offset) 16442 entry->offset = INTVAL (offset); 16443 } 16444 } 16445 return INTVAL (offset) <= entry->offset; 16446} 16447 16448/* Search X for LO_SUMs and record them in HTAB. */ 16449 16450static void 16451mips_record_lo_sums (const_rtx x, mips_offset_table *htab) 16452{ 16453 subrtx_iterator::array_type array; 16454 FOR_EACH_SUBRTX (iter, array, x, NONCONST) 16455 if (GET_CODE (*iter) == LO_SUM) 16456 mips_lo_sum_offset_lookup (htab, XEXP (*iter, 1), INSERT); 16457} 16458 16459/* Return true if INSN is a SET of an orphaned high-part relocation. 16460 HTAB is a hash table of mips_lo_sum_offsets that describes all the 16461 LO_SUMs in the current function. */ 16462 16463static bool 16464mips_orphaned_high_part_p (mips_offset_table *htab, rtx_insn *insn) 16465{ 16466 enum mips_symbol_type type; 16467 rtx x, set; 16468 16469 set = single_set (insn); 16470 if (set) 16471 { 16472 /* Check for %his. */ 16473 x = SET_SRC (set); 16474 if (GET_CODE (x) == HIGH 16475 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) 16476 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); 16477 16478 /* Check for local %gots (and %got_pages, which is redundant but OK). */ 16479 if (GET_CODE (x) == UNSPEC 16480 && XINT (x, 1) == UNSPEC_LOAD_GOT 16481 && mips_symbolic_constant_p (XVECEXP (x, 0, 1), 16482 SYMBOL_CONTEXT_LEA, &type) 16483 && type == SYMBOL_GOTOFF_PAGE) 16484 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT); 16485 } 16486 return false; 16487} 16488 16489/* Subroutine of mips_reorg_process_insns. If there is a hazard between 16490 INSN and a previous instruction, avoid it by inserting nops after 16491 instruction AFTER. 16492 16493 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at 16494 this point. If *DELAYED_REG is non-null, INSN must wait a cycle 16495 before using the value of that register. *HILO_DELAY counts the 16496 number of instructions since the last hilo hazard (that is, 16497 the number of instructions since the last MFLO or MFHI). 16498 16499 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY 16500 for the next instruction. 16501 16502 LO_REG is an rtx for the LO register, used in dependence checking. */ 16503 16504static void 16505mips_avoid_hazard (rtx_insn *after, rtx_insn *insn, int *hilo_delay, 16506 rtx *delayed_reg, rtx lo_reg) 16507{ 16508 rtx pattern, set; 16509 int nops, ninsns; 16510 16511 pattern = PATTERN (insn); 16512 16513 /* Do not put the whole function in .set noreorder if it contains 16514 an asm statement. We don't know whether there will be hazards 16515 between the asm statement and the gcc-generated code. */ 16516 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0) 16517 cfun->machine->all_noreorder_p = false; 16518 16519 /* Ignore zero-length instructions (barriers and the like). */ 16520 ninsns = get_attr_length (insn) / 4; 16521 if (ninsns == 0) 16522 return; 16523 16524 /* Work out how many nops are needed. Note that we only care about 16525 registers that are explicitly mentioned in the instruction's pattern. 16526 It doesn't matter that calls use the argument registers or that they 16527 clobber hi and lo. */ 16528 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) 16529 nops = 2 - *hilo_delay; 16530 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) 16531 nops = 1; 16532 else 16533 nops = 0; 16534 16535 /* Insert the nops between this instruction and the previous one. 16536 Each new nop takes us further from the last hilo hazard. */ 16537 *hilo_delay += nops; 16538 while (nops-- > 0) 16539 emit_insn_after (gen_hazard_nop (), after); 16540 16541 /* Set up the state for the next instruction. */ 16542 *hilo_delay += ninsns; 16543 *delayed_reg = 0; 16544 if (INSN_CODE (insn) >= 0) 16545 switch (get_attr_hazard (insn)) 16546 { 16547 case HAZARD_NONE: 16548 break; 16549 16550 case HAZARD_HILO: 16551 *hilo_delay = 0; 16552 break; 16553 16554 case HAZARD_DELAY: 16555 set = single_set (insn); 16556 gcc_assert (set); 16557 *delayed_reg = SET_DEST (set); 16558 break; 16559 } 16560} 16561 16562/* Go through the instruction stream and insert nops where necessary. 16563 Also delete any high-part relocations whose partnering low parts 16564 are now all dead. See if the whole function can then be put into 16565 .set noreorder and .set nomacro. */ 16566 16567static void 16568mips_reorg_process_insns (void) 16569{ 16570 rtx_insn *insn, *last_insn, *subinsn, *next_insn; 16571 rtx lo_reg, delayed_reg; 16572 int hilo_delay; 16573 16574 /* Force all instructions to be split into their final form. */ 16575 split_all_insns_noflow (); 16576 16577 /* Recalculate instruction lengths without taking nops into account. */ 16578 cfun->machine->ignore_hazard_length_p = true; 16579 shorten_branches (get_insns ()); 16580 16581 cfun->machine->all_noreorder_p = true; 16582 16583 /* We don't track MIPS16 PC-relative offsets closely enough to make 16584 a good job of "set .noreorder" code in MIPS16 mode. */ 16585 if (TARGET_MIPS16) 16586 cfun->machine->all_noreorder_p = false; 16587 16588 /* Code that doesn't use explicit relocs can't be ".set nomacro". */ 16589 if (!TARGET_EXPLICIT_RELOCS) 16590 cfun->machine->all_noreorder_p = false; 16591 16592 /* Profiled functions can't be all noreorder because the profiler 16593 support uses assembler macros. */ 16594 if (crtl->profile) 16595 cfun->machine->all_noreorder_p = false; 16596 16597 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be 16598 all noreorder because we rely on the assembler to work around some 16599 errata. The R5900 too has several bugs. */ 16600 if (TARGET_FIX_VR4120 16601 || TARGET_FIX_RM7000 16602 || TARGET_FIX_24K 16603 || TARGET_MIPS5900) 16604 cfun->machine->all_noreorder_p = false; 16605 16606 /* The same is true for -mfix-vr4130 if we might generate MFLO or 16607 MFHI instructions. Note that we avoid using MFLO and MFHI if 16608 the VR4130 MACC and DMACC instructions are available instead; 16609 see the *mfhilo_{si,di}_macc patterns. */ 16610 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI) 16611 cfun->machine->all_noreorder_p = false; 16612 16613 mips_offset_table htab (37); 16614 16615 /* Make a first pass over the instructions, recording all the LO_SUMs. */ 16616 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) 16617 FOR_EACH_SUBINSN (subinsn, insn) 16618 if (USEFUL_INSN_P (subinsn)) 16619 { 16620 rtx body = PATTERN (insn); 16621 int noperands = asm_noperands (body); 16622 if (noperands >= 0) 16623 { 16624 rtx *ops = XALLOCAVEC (rtx, noperands); 16625 bool *used = XALLOCAVEC (bool, noperands); 16626 const char *string = decode_asm_operands (body, ops, NULL, NULL, 16627 NULL, NULL); 16628 get_referenced_operands (string, used, noperands); 16629 for (int i = 0; i < noperands; ++i) 16630 if (used[i]) 16631 mips_record_lo_sums (ops[i], &htab); 16632 } 16633 else 16634 mips_record_lo_sums (PATTERN (subinsn), &htab); 16635 } 16636 16637 last_insn = 0; 16638 hilo_delay = 2; 16639 delayed_reg = 0; 16640 lo_reg = gen_rtx_REG (SImode, LO_REGNUM); 16641 16642 /* Make a second pass over the instructions. Delete orphaned 16643 high-part relocations or turn them into NOPs. Avoid hazards 16644 by inserting NOPs. */ 16645 for (insn = get_insns (); insn != 0; insn = next_insn) 16646 { 16647 next_insn = NEXT_INSN (insn); 16648 if (USEFUL_INSN_P (insn)) 16649 { 16650 if (GET_CODE (PATTERN (insn)) == SEQUENCE) 16651 { 16652 /* If we find an orphaned high-part relocation in a delay 16653 slot, it's easier to turn that instruction into a NOP than 16654 to delete it. The delay slot will be a NOP either way. */ 16655 FOR_EACH_SUBINSN (subinsn, insn) 16656 if (INSN_P (subinsn)) 16657 { 16658 if (mips_orphaned_high_part_p (&htab, subinsn)) 16659 { 16660 PATTERN (subinsn) = gen_nop (); 16661 INSN_CODE (subinsn) = CODE_FOR_nop; 16662 } 16663 mips_avoid_hazard (last_insn, subinsn, &hilo_delay, 16664 &delayed_reg, lo_reg); 16665 } 16666 last_insn = insn; 16667 } 16668 else 16669 { 16670 /* INSN is a single instruction. Delete it if it's an 16671 orphaned high-part relocation. */ 16672 if (mips_orphaned_high_part_p (&htab, insn)) 16673 delete_insn (insn); 16674 /* Also delete cache barriers if the last instruction 16675 was an annulled branch. INSN will not be speculatively 16676 executed. */ 16677 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier 16678 && last_insn 16679 && JUMP_P (SEQ_BEGIN (last_insn)) 16680 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn))) 16681 delete_insn (insn); 16682 else 16683 { 16684 mips_avoid_hazard (last_insn, insn, &hilo_delay, 16685 &delayed_reg, lo_reg); 16686 last_insn = insn; 16687 } 16688 } 16689 } 16690 } 16691} 16692 16693/* Return true if the function has a long branch instruction. */ 16694 16695static bool 16696mips_has_long_branch_p (void) 16697{ 16698 rtx_insn *insn, *subinsn; 16699 int normal_length; 16700 16701 /* We need up-to-date instruction lengths. */ 16702 shorten_branches (get_insns ()); 16703 16704 /* Look for a branch that is longer than normal. The normal length for 16705 non-MIPS16 branches is 8, because the length includes the delay slot. 16706 It is 4 for MIPS16, because MIPS16 branches are extended instructions, 16707 but they have no delay slot. */ 16708 normal_length = (TARGET_MIPS16 ? 4 : 8); 16709 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 16710 FOR_EACH_SUBINSN (subinsn, insn) 16711 if (JUMP_P (subinsn) 16712 && get_attr_length (subinsn) > normal_length 16713 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn))) 16714 return true; 16715 16716 return false; 16717} 16718 16719/* If we are using a GOT, but have not decided to use a global pointer yet, 16720 see whether we need one to implement long branches. Convert the ghost 16721 global-pointer instructions into real ones if so. */ 16722 16723static bool 16724mips_expand_ghost_gp_insns (void) 16725{ 16726 /* Quick exit if we already know that we will or won't need a 16727 global pointer. */ 16728 if (!TARGET_USE_GOT 16729 || cfun->machine->global_pointer == INVALID_REGNUM 16730 || mips_must_initialize_gp_p ()) 16731 return false; 16732 16733 /* Run a full check for long branches. */ 16734 if (!mips_has_long_branch_p ()) 16735 return false; 16736 16737 /* We've now established that we need $gp. */ 16738 cfun->machine->must_initialize_gp_p = true; 16739 split_all_insns_noflow (); 16740 16741 return true; 16742} 16743 16744/* Subroutine of mips_reorg to manage passes that require DF. */ 16745 16746static void 16747mips_df_reorg (void) 16748{ 16749 /* Create def-use chains. */ 16750 df_set_flags (DF_EQ_NOTES); 16751 df_chain_add_problem (DF_UD_CHAIN); 16752 df_analyze (); 16753 16754 if (TARGET_RELAX_PIC_CALLS) 16755 mips_annotate_pic_calls (); 16756 16757 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE) 16758 r10k_insert_cache_barriers (); 16759 16760 df_finish_pass (false); 16761} 16762 16763/* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is 16764 called very late in mips_reorg, but the caller is required to run 16765 mips16_lay_out_constants on the result. */ 16766 16767static void 16768mips16_load_branch_target (rtx dest, rtx src) 16769{ 16770 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 16771 { 16772 rtx page, low; 16773 16774 if (mips_cfun_has_cprestore_slot_p ()) 16775 mips_emit_move (dest, mips_cprestore_slot (dest, true)); 16776 else 16777 mips_emit_move (dest, pic_offset_table_rtx); 16778 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE); 16779 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST); 16780 emit_insn (gen_rtx_SET (VOIDmode, dest, 16781 PMODE_INSN (gen_unspec_got, (dest, page)))); 16782 emit_insn (gen_rtx_SET (VOIDmode, dest, 16783 gen_rtx_LO_SUM (Pmode, dest, low))); 16784 } 16785 else 16786 { 16787 src = mips_unspec_address (src, SYMBOL_ABSOLUTE); 16788 mips_emit_move (dest, src); 16789 } 16790} 16791 16792/* If we're compiling a MIPS16 function, look for and split any long branches. 16793 This must be called after all other instruction modifications in 16794 mips_reorg. */ 16795 16796static void 16797mips16_split_long_branches (void) 16798{ 16799 bool something_changed; 16800 16801 if (!TARGET_MIPS16) 16802 return; 16803 16804 /* Loop until the alignments for all targets are sufficient. */ 16805 do 16806 { 16807 rtx_insn *insn; 16808 16809 shorten_branches (get_insns ()); 16810 something_changed = false; 16811 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 16812 if (JUMP_P (insn) 16813 && get_attr_length (insn) > 4 16814 && (any_condjump_p (insn) || any_uncondjump_p (insn))) 16815 { 16816 rtx old_label, temp, saved_temp; 16817 rtx_code_label *new_label; 16818 rtx target; 16819 rtx_insn *jump, *jump_sequence; 16820 16821 start_sequence (); 16822 16823 /* Free up a MIPS16 register by saving it in $1. */ 16824 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM); 16825 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); 16826 emit_move_insn (saved_temp, temp); 16827 16828 /* Load the branch target into TEMP. */ 16829 old_label = JUMP_LABEL (insn); 16830 target = gen_rtx_LABEL_REF (Pmode, old_label); 16831 mips16_load_branch_target (temp, target); 16832 16833 /* Jump to the target and restore the register's 16834 original value. */ 16835 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore, 16836 (temp, temp, saved_temp))); 16837 JUMP_LABEL (jump) = old_label; 16838 LABEL_NUSES (old_label)++; 16839 16840 /* Rewrite any symbolic references that are supposed to use 16841 a PC-relative constant pool. */ 16842 mips16_lay_out_constants (false); 16843 16844 if (simplejump_p (insn)) 16845 /* We're going to replace INSN with a longer form. */ 16846 new_label = NULL; 16847 else 16848 { 16849 /* Create a branch-around label for the original 16850 instruction. */ 16851 new_label = gen_label_rtx (); 16852 emit_label (new_label); 16853 } 16854 16855 jump_sequence = get_insns (); 16856 end_sequence (); 16857 16858 emit_insn_after (jump_sequence, insn); 16859 if (new_label) 16860 invert_jump (insn, new_label, false); 16861 else 16862 delete_insn (insn); 16863 something_changed = true; 16864 } 16865 } 16866 while (something_changed); 16867} 16868 16869/* Implement TARGET_MACHINE_DEPENDENT_REORG. */ 16870 16871static void 16872mips_reorg (void) 16873{ 16874 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during 16875 insn splitting in mips16_lay_out_constants, DF insn info is only kept up 16876 to date if the CFG is available. */ 16877 if (mips_cfg_in_reorg ()) 16878 compute_bb_for_insn (); 16879 mips16_lay_out_constants (true); 16880 if (mips_cfg_in_reorg ()) 16881 { 16882 mips_df_reorg (); 16883 free_bb_for_insn (); 16884 } 16885} 16886 16887/* We use a machine specific pass to do a second machine dependent reorg 16888 pass after delay branch scheduling. */ 16889 16890static unsigned int 16891mips_machine_reorg2 (void) 16892{ 16893 mips_reorg_process_insns (); 16894 if (!TARGET_MIPS16 16895 && TARGET_EXPLICIT_RELOCS 16896 && TUNE_MIPS4130 16897 && TARGET_VR4130_ALIGN) 16898 vr4130_align_insns (); 16899 if (mips_expand_ghost_gp_insns ()) 16900 /* The expansion could invalidate some of the VR4130 alignment 16901 optimizations, but this should be an extremely rare case anyhow. */ 16902 mips_reorg_process_insns (); 16903 mips16_split_long_branches (); 16904 return 0; 16905} 16906 16907namespace { 16908 16909const pass_data pass_data_mips_machine_reorg2 = 16910{ 16911 RTL_PASS, /* type */ 16912 "mach2", /* name */ 16913 OPTGROUP_NONE, /* optinfo_flags */ 16914 TV_MACH_DEP, /* tv_id */ 16915 0, /* properties_required */ 16916 0, /* properties_provided */ 16917 0, /* properties_destroyed */ 16918 0, /* todo_flags_start */ 16919 0, /* todo_flags_finish */ 16920}; 16921 16922class pass_mips_machine_reorg2 : public rtl_opt_pass 16923{ 16924public: 16925 pass_mips_machine_reorg2(gcc::context *ctxt) 16926 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt) 16927 {} 16928 16929 /* opt_pass methods: */ 16930 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); } 16931 16932}; // class pass_mips_machine_reorg2 16933 16934} // anon namespace 16935 16936rtl_opt_pass * 16937make_pass_mips_machine_reorg2 (gcc::context *ctxt) 16938{ 16939 return new pass_mips_machine_reorg2 (ctxt); 16940} 16941 16942 16943/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 16944 in order to avoid duplicating too much logic from elsewhere. */ 16945 16946static void 16947mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 16948 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 16949 tree function) 16950{ 16951 rtx this_rtx, temp1, temp2, fnaddr; 16952 rtx_insn *insn; 16953 bool use_sibcall_p; 16954 16955 /* Pretend to be a post-reload pass while generating rtl. */ 16956 reload_completed = 1; 16957 16958 /* Mark the end of the (empty) prologue. */ 16959 emit_note (NOTE_INSN_PROLOGUE_END); 16960 16961 /* Determine if we can use a sibcall to call FUNCTION directly. */ 16962 fnaddr = XEXP (DECL_RTL (function), 0); 16963 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL) 16964 && const_call_insn_operand (fnaddr, Pmode)); 16965 16966 /* Determine if we need to load FNADDR from the GOT. */ 16967 if (!use_sibcall_p 16968 && (mips_got_symbol_type_p 16969 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA)))) 16970 { 16971 /* Pick a global pointer. Use a call-clobbered register if 16972 TARGET_CALL_SAVED_GP. */ 16973 cfun->machine->global_pointer 16974 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM; 16975 cfun->machine->must_initialize_gp_p = true; 16976 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); 16977 16978 /* Set up the global pointer for n32 or n64 abicalls. */ 16979 mips_emit_loadgp (); 16980 } 16981 16982 /* We need two temporary registers in some cases. */ 16983 temp1 = gen_rtx_REG (Pmode, 2); 16984 temp2 = gen_rtx_REG (Pmode, 3); 16985 16986 /* Find out which register contains the "this" pointer. */ 16987 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 16988 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); 16989 else 16990 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); 16991 16992 /* Add DELTA to THIS_RTX. */ 16993 if (delta != 0) 16994 { 16995 rtx offset = GEN_INT (delta); 16996 if (!SMALL_OPERAND (delta)) 16997 { 16998 mips_emit_move (temp1, offset); 16999 offset = temp1; 17000 } 17001 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); 17002 } 17003 17004 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ 17005 if (vcall_offset != 0) 17006 { 17007 rtx addr; 17008 17009 /* Set TEMP1 to *THIS_RTX. */ 17010 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); 17011 17012 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ 17013 addr = mips_add_offset (temp2, temp1, vcall_offset); 17014 17015 /* Load the offset and add it to THIS_RTX. */ 17016 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); 17017 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); 17018 } 17019 17020 /* Jump to the target function. Use a sibcall if direct jumps are 17021 allowed, otherwise load the address into a register first. */ 17022 if (use_sibcall_p) 17023 { 17024 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); 17025 SIBLING_CALL_P (insn) = 1; 17026 } 17027 else 17028 { 17029 /* This is messy. GAS treats "la $25,foo" as part of a call 17030 sequence and may allow a global "foo" to be lazily bound. 17031 The general move patterns therefore reject this combination. 17032 17033 In this context, lazy binding would actually be OK 17034 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for 17035 TARGET_CALL_SAVED_GP; see mips_load_call_address. 17036 We must therefore load the address via a temporary 17037 register if mips_dangerous_for_la25_p. 17038 17039 If we jump to the temporary register rather than $25, 17040 the assembler can use the move insn to fill the jump's 17041 delay slot. 17042 17043 We can use the same technique for MIPS16 code, where $25 17044 is not a valid JR register. */ 17045 if (TARGET_USE_PIC_FN_ADDR_REG 17046 && !TARGET_MIPS16 17047 && !mips_dangerous_for_la25_p (fnaddr)) 17048 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 17049 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr); 17050 17051 if (TARGET_USE_PIC_FN_ADDR_REG 17052 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM) 17053 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1); 17054 emit_jump_insn (gen_indirect_jump (temp1)); 17055 } 17056 17057 /* Run just enough of rest_of_compilation. This sequence was 17058 "borrowed" from alpha.c. */ 17059 insn = get_insns (); 17060 split_all_insns_noflow (); 17061 mips16_lay_out_constants (true); 17062 shorten_branches (insn); 17063 final_start_function (insn, file, 1); 17064 final (insn, file, 1); 17065 final_end_function (); 17066 17067 /* Clean up the vars set above. Note that final_end_function resets 17068 the global pointer for us. */ 17069 reload_completed = 0; 17070} 17071 17072 17073/* The last argument passed to mips_set_compression_mode, 17074 or negative if the function hasn't been called yet. */ 17075static unsigned int old_compression_mode = -1; 17076 17077/* Set up the target-dependent global state for ISA mode COMPRESSION_MODE, 17078 which is either MASK_MIPS16 or MASK_MICROMIPS. */ 17079 17080static void 17081mips_set_compression_mode (unsigned int compression_mode) 17082{ 17083 17084 if (compression_mode == old_compression_mode) 17085 return; 17086 17087 /* Restore base settings of various flags. */ 17088 target_flags = mips_base_target_flags; 17089 flag_schedule_insns = mips_base_schedule_insns; 17090 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition; 17091 flag_move_loop_invariants = mips_base_move_loop_invariants; 17092 align_loops = mips_base_align_loops; 17093 align_jumps = mips_base_align_jumps; 17094 align_functions = mips_base_align_functions; 17095 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS); 17096 target_flags |= compression_mode; 17097 17098 if (compression_mode & MASK_MIPS16) 17099 { 17100 /* Switch to MIPS16 mode. */ 17101 target_flags |= MASK_MIPS16; 17102 17103 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */ 17104 target_flags &= ~MASK_SYNCI; 17105 17106 /* Don't run the scheduler before reload, since it tends to 17107 increase register pressure. */ 17108 flag_schedule_insns = 0; 17109 17110 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects 17111 the whole function to be in a single section. */ 17112 flag_reorder_blocks_and_partition = 0; 17113 17114 /* Don't move loop invariants, because it tends to increase 17115 register pressure. It also introduces an extra move in cases 17116 where the constant is the first operand in a two-operand binary 17117 instruction, or when it forms a register argument to a functon 17118 call. */ 17119 flag_move_loop_invariants = 0; 17120 17121 target_flags |= MASK_EXPLICIT_RELOCS; 17122 17123 /* Experiments suggest we get the best overall section-anchor 17124 results from using the range of an unextended LW or SW. Code 17125 that makes heavy use of byte or short accesses can do better 17126 with ranges of 0...31 and 0...63 respectively, but most code is 17127 sensitive to the range of LW and SW instead. */ 17128 targetm.min_anchor_offset = 0; 17129 targetm.max_anchor_offset = 127; 17130 17131 targetm.const_anchor = 0; 17132 17133 /* MIPS16 has no BAL instruction. */ 17134 target_flags &= ~MASK_RELAX_PIC_CALLS; 17135 17136 /* The R4000 errata don't apply to any known MIPS16 cores. 17137 It's simpler to make the R4000 fixes and MIPS16 mode 17138 mutually exclusive. */ 17139 target_flags &= ~MASK_FIX_R4000; 17140 17141 if (flag_pic && !TARGET_OLDABI) 17142 sorry ("MIPS16 PIC for ABIs other than o32 and o64"); 17143 17144 if (TARGET_XGOT) 17145 sorry ("MIPS16 -mxgot code"); 17146 17147 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI) 17148 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64"); 17149 } 17150 else 17151 { 17152 /* Switch to microMIPS or the standard encoding. */ 17153 17154 if (TARGET_MICROMIPS) 17155 /* Avoid branch likely. */ 17156 target_flags &= ~MASK_BRANCHLIKELY; 17157 17158 /* Provide default values for align_* for 64-bit targets. */ 17159 if (TARGET_64BIT) 17160 { 17161 if (align_loops == 0) 17162 align_loops = 8; 17163 if (align_jumps == 0) 17164 align_jumps = 8; 17165 if (align_functions == 0) 17166 align_functions = 8; 17167 } 17168 17169 targetm.min_anchor_offset = -32768; 17170 targetm.max_anchor_offset = 32767; 17171 17172 targetm.const_anchor = 0x8000; 17173 } 17174 17175 /* (Re)initialize MIPS target internals for new ISA. */ 17176 mips_init_relocs (); 17177 17178 if (compression_mode & MASK_MIPS16) 17179 { 17180 if (!mips16_globals) 17181 mips16_globals = save_target_globals_default_opts (); 17182 else 17183 restore_target_globals (mips16_globals); 17184 } 17185 else 17186 restore_target_globals (&default_target_globals); 17187 17188 old_compression_mode = compression_mode; 17189} 17190 17191/* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current 17192 function should use the MIPS16 or microMIPS ISA and switch modes 17193 accordingly. */ 17194 17195static void 17196mips_set_current_function (tree fndecl) 17197{ 17198 mips_set_compression_mode (mips_get_compress_mode (fndecl)); 17199} 17200 17201/* Allocate a chunk of memory for per-function machine-dependent data. */ 17202 17203static struct machine_function * 17204mips_init_machine_status (void) 17205{ 17206 return ggc_cleared_alloc<machine_function> (); 17207} 17208 17209/* Return the processor associated with the given ISA level, or null 17210 if the ISA isn't valid. */ 17211 17212static const struct mips_cpu_info * 17213mips_cpu_info_from_isa (int isa) 17214{ 17215 unsigned int i; 17216 17217 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) 17218 if (mips_cpu_info_table[i].isa == isa) 17219 return mips_cpu_info_table + i; 17220 17221 return NULL; 17222} 17223 17224/* Return a mips_cpu_info entry determined by an option valued 17225 OPT. */ 17226 17227static const struct mips_cpu_info * 17228mips_cpu_info_from_opt (int opt) 17229{ 17230 switch (opt) 17231 { 17232 case MIPS_ARCH_OPTION_FROM_ABI: 17233 /* 'from-abi' selects the most compatible architecture for the 17234 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit 17235 ABIs. For the EABIs, we have to decide whether we're using 17236 the 32-bit or 64-bit version. */ 17237 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1 17238 : ABI_NEEDS_64BIT_REGS ? 3 17239 : (TARGET_64BIT ? 3 : 1)); 17240 17241 case MIPS_ARCH_OPTION_NATIVE: 17242 gcc_unreachable (); 17243 17244 default: 17245 return &mips_cpu_info_table[opt]; 17246 } 17247} 17248 17249/* Return a default mips_cpu_info entry, given that no -march= option 17250 was explicitly specified. */ 17251 17252static const struct mips_cpu_info * 17253mips_default_arch (void) 17254{ 17255#if defined (MIPS_CPU_STRING_DEFAULT) 17256 unsigned int i; 17257 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) 17258 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0) 17259 return mips_cpu_info_table + i; 17260 gcc_unreachable (); 17261#elif defined (MIPS_ISA_DEFAULT) 17262 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT); 17263#else 17264 /* 'from-abi' makes a good default: you get whatever the ABI 17265 requires. */ 17266 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI); 17267#endif 17268} 17269 17270/* Set up globals to generate code for the ISA or processor 17271 described by INFO. */ 17272 17273static void 17274mips_set_architecture (const struct mips_cpu_info *info) 17275{ 17276 if (info != 0) 17277 { 17278 mips_arch_info = info; 17279 mips_arch = info->cpu; 17280 mips_isa = info->isa; 17281 if (mips_isa < 32) 17282 mips_isa_rev = 0; 17283 else 17284 mips_isa_rev = (mips_isa & 31) + 1; 17285 } 17286} 17287 17288/* Likewise for tuning. */ 17289 17290static void 17291mips_set_tune (const struct mips_cpu_info *info) 17292{ 17293 if (info != 0) 17294 { 17295 mips_tune_info = info; 17296 mips_tune = info->cpu; 17297 } 17298} 17299 17300/* Implement TARGET_OPTION_OVERRIDE. */ 17301 17302static void 17303mips_option_override (void) 17304{ 17305 int i, start, regno, mode; 17306 17307 if (global_options_set.x_mips_isa_option) 17308 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option]; 17309 17310#ifdef SUBTARGET_OVERRIDE_OPTIONS 17311 SUBTARGET_OVERRIDE_OPTIONS; 17312#endif 17313 17314 /* MIPS16 and microMIPS cannot coexist. */ 17315 if (TARGET_MICROMIPS && TARGET_MIPS16) 17316 error ("unsupported combination: %s", "-mips16 -mmicromips"); 17317 17318 /* Save the base compression state and process flags as though we 17319 were generating uncompressed code. */ 17320 mips_base_compression_flags = TARGET_COMPRESSION; 17321 target_flags &= ~TARGET_COMPRESSION; 17322 17323 /* -mno-float overrides -mhard-float and -msoft-float. */ 17324 if (TARGET_NO_FLOAT) 17325 { 17326 target_flags |= MASK_SOFT_FLOAT_ABI; 17327 target_flags_explicit |= MASK_SOFT_FLOAT_ABI; 17328 } 17329 17330 if (TARGET_FLIP_MIPS16) 17331 TARGET_INTERLINK_COMPRESSED = 1; 17332 17333 /* Set the small data limit. */ 17334 mips_small_data_threshold = (global_options_set.x_g_switch_value 17335 ? g_switch_value 17336 : MIPS_DEFAULT_GVALUE); 17337 17338 /* The following code determines the architecture and register size. 17339 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()). 17340 The GAS and GCC code should be kept in sync as much as possible. */ 17341 17342 if (global_options_set.x_mips_arch_option) 17343 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option)); 17344 17345 if (mips_isa_option_info != 0) 17346 { 17347 if (mips_arch_info == 0) 17348 mips_set_architecture (mips_isa_option_info); 17349 else if (mips_arch_info->isa != mips_isa_option_info->isa) 17350 error ("%<-%s%> conflicts with the other architecture options, " 17351 "which specify a %s processor", 17352 mips_isa_option_info->name, 17353 mips_cpu_info_from_isa (mips_arch_info->isa)->name); 17354 } 17355 17356 if (mips_arch_info == 0) 17357 mips_set_architecture (mips_default_arch ()); 17358 17359 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS) 17360 error ("%<-march=%s%> is not compatible with the selected ABI", 17361 mips_arch_info->name); 17362 17363 /* Optimize for mips_arch, unless -mtune selects a different processor. */ 17364 if (global_options_set.x_mips_tune_option) 17365 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option)); 17366 17367 if (mips_tune_info == 0) 17368 mips_set_tune (mips_arch_info); 17369 17370 if ((target_flags_explicit & MASK_64BIT) != 0) 17371 { 17372 /* The user specified the size of the integer registers. Make sure 17373 it agrees with the ABI and ISA. */ 17374 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS) 17375 error ("%<-mgp64%> used with a 32-bit processor"); 17376 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS) 17377 error ("%<-mgp32%> used with a 64-bit ABI"); 17378 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS) 17379 error ("%<-mgp64%> used with a 32-bit ABI"); 17380 } 17381 else 17382 { 17383 /* Infer the integer register size from the ABI and processor. 17384 Restrict ourselves to 32-bit registers if that's all the 17385 processor has, or if the ABI cannot handle 64-bit registers. */ 17386 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS) 17387 target_flags &= ~MASK_64BIT; 17388 else 17389 target_flags |= MASK_64BIT; 17390 } 17391 17392 if ((target_flags_explicit & MASK_FLOAT64) != 0) 17393 { 17394 if (mips_isa_rev >= 6 && !TARGET_FLOAT64) 17395 error ("the %qs architecture does not support %<-mfp32%>", 17396 mips_arch_info->name); 17397 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64) 17398 error ("unsupported combination: %s", "-mfp64 -msingle-float"); 17399 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64) 17400 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float"); 17401 else if (!TARGET_64BIT && TARGET_FLOAT64) 17402 { 17403 if (!ISA_HAS_MXHC1) 17404 error ("%<-mgp32%> and %<-mfp64%> can only be combined if" 17405 " the target supports the mfhc1 and mthc1 instructions"); 17406 else if (mips_abi != ABI_32) 17407 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using" 17408 " the o32 ABI"); 17409 } 17410 } 17411 else 17412 { 17413 /* -msingle-float selects 32-bit float registers. On r6 and later, 17414 -mdouble-float selects 64-bit float registers, since the old paired 17415 register model is not supported. In other cases the float registers 17416 should be the same size as the integer ones. */ 17417 if (mips_isa_rev >= 6 && TARGET_DOUBLE_FLOAT && !TARGET_FLOATXX) 17418 target_flags |= MASK_FLOAT64; 17419 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT) 17420 target_flags |= MASK_FLOAT64; 17421 else 17422 target_flags &= ~MASK_FLOAT64; 17423 } 17424 17425 if (mips_abi != ABI_32 && TARGET_FLOATXX) 17426 error ("%<-mfpxx%> can only be used with the o32 ABI"); 17427 else if (TARGET_FLOAT64 && TARGET_FLOATXX) 17428 error ("unsupported combination: %s", "-mfp64 -mfpxx"); 17429 else if (ISA_MIPS1 && !TARGET_FLOAT32) 17430 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info->name); 17431 else if (TARGET_FLOATXX && !mips_lra_flag) 17432 error ("%<-mfpxx%> requires %<-mlra%>"); 17433 17434 /* End of code shared with GAS. */ 17435 17436 /* The R5900 FPU only supports single precision. */ 17437 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT) 17438 error ("unsupported combination: %s", 17439 "-march=r5900 -mhard-float -mdouble-float"); 17440 17441 /* If a -mlong* option was given, check that it matches the ABI, 17442 otherwise infer the -mlong* setting from the other options. */ 17443 if ((target_flags_explicit & MASK_LONG64) != 0) 17444 { 17445 if (TARGET_LONG64) 17446 { 17447 if (mips_abi == ABI_N32) 17448 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64"); 17449 else if (mips_abi == ABI_32) 17450 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64"); 17451 else if (mips_abi == ABI_O64 && TARGET_ABICALLS) 17452 /* We have traditionally allowed non-abicalls code to use 17453 an LP64 form of o64. However, it would take a bit more 17454 effort to support the combination of 32-bit GOT entries 17455 and 64-bit pointers, so we treat the abicalls case as 17456 an error. */ 17457 error ("the combination of %qs and %qs is incompatible with %qs", 17458 "-mabi=o64", "-mabicalls", "-mlong64"); 17459 } 17460 else 17461 { 17462 if (mips_abi == ABI_64) 17463 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32"); 17464 } 17465 } 17466 else 17467 { 17468 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64) 17469 target_flags |= MASK_LONG64; 17470 else 17471 target_flags &= ~MASK_LONG64; 17472 } 17473 17474 if (!TARGET_OLDABI) 17475 flag_pcc_struct_return = 0; 17476 17477 /* Decide which rtx_costs structure to use. */ 17478 if (optimize_size) 17479 mips_cost = &mips_rtx_cost_optimize_size; 17480 else 17481 mips_cost = &mips_rtx_cost_data[mips_tune]; 17482 17483 /* If the user hasn't specified a branch cost, use the processor's 17484 default. */ 17485 if (mips_branch_cost == 0) 17486 mips_branch_cost = mips_cost->branch_cost; 17487 17488 /* If neither -mbranch-likely nor -mno-branch-likely was given 17489 on the command line, set MASK_BRANCHLIKELY based on the target 17490 architecture and tuning flags. Annulled delay slots are a 17491 size win, so we only consider the processor-specific tuning 17492 for !optimize_size. */ 17493 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0) 17494 { 17495 if (ISA_HAS_BRANCHLIKELY 17496 && (optimize_size 17497 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0)) 17498 target_flags |= MASK_BRANCHLIKELY; 17499 else 17500 target_flags &= ~MASK_BRANCHLIKELY; 17501 } 17502 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) 17503 warning (0, "the %qs architecture does not support branch-likely" 17504 " instructions", mips_arch_info->name); 17505 17506 /* If the user hasn't specified -mimadd or -mno-imadd set 17507 MASK_IMADD based on the target architecture and tuning 17508 flags. */ 17509 if ((target_flags_explicit & MASK_IMADD) == 0) 17510 { 17511 if (ISA_HAS_MADD_MSUB && 17512 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0) 17513 target_flags |= MASK_IMADD; 17514 else 17515 target_flags &= ~MASK_IMADD; 17516 } 17517 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB) 17518 warning (0, "the %qs architecture does not support madd or msub" 17519 " instructions", mips_arch_info->name); 17520 17521 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command 17522 line, set MASK_ODD_SPREG based on the ISA and ABI. */ 17523 if ((target_flags_explicit & MASK_ODD_SPREG) == 0) 17524 { 17525 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */ 17526 if (!ISA_HAS_ODD_SPREG || TARGET_FLOATXX) 17527 target_flags &= ~MASK_ODD_SPREG; 17528 else 17529 target_flags |= MASK_ODD_SPREG; 17530 } 17531 else if (TARGET_ODD_SPREG && !ISA_HAS_ODD_SPREG) 17532 warning (0, "the %qs architecture does not support odd single-precision" 17533 " registers", mips_arch_info->name); 17534 17535 if (!TARGET_ODD_SPREG && TARGET_64BIT) 17536 { 17537 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg"); 17538 /* Allow compilation to continue further even though invalid output 17539 will be produced. */ 17540 target_flags |= MASK_ODD_SPREG; 17541 } 17542 17543 /* The effect of -mabicalls isn't defined for the EABI. */ 17544 if (mips_abi == ABI_EABI && TARGET_ABICALLS) 17545 { 17546 error ("unsupported combination: %s", "-mabicalls -mabi=eabi"); 17547 target_flags &= ~MASK_ABICALLS; 17548 } 17549 17550 /* PIC requires -mabicalls. */ 17551 if (flag_pic) 17552 { 17553 if (mips_abi == ABI_EABI) 17554 error ("cannot generate position-independent code for %qs", 17555 "-mabi=eabi"); 17556 else if (!TARGET_ABICALLS) 17557 error ("position-independent code requires %qs", "-mabicalls"); 17558 } 17559 17560 if (TARGET_ABICALLS_PIC2) 17561 /* We need to set flag_pic for executables as well as DSOs 17562 because we may reference symbols that are not defined in 17563 the final executable. (MIPS does not use things like 17564 copy relocs, for example.) 17565 17566 There is a body of code that uses __PIC__ to distinguish 17567 between -mabicalls and -mno-abicalls code. The non-__PIC__ 17568 variant is usually appropriate for TARGET_ABICALLS_PIC0, as 17569 long as any indirect jumps use $25. */ 17570 flag_pic = 1; 17571 17572 /* -mvr4130-align is a "speed over size" optimization: it usually produces 17573 faster code, but at the expense of more nops. Enable it at -O3 and 17574 above. */ 17575 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) 17576 target_flags |= MASK_VR4130_ALIGN; 17577 17578 /* Prefer a call to memcpy over inline code when optimizing for size, 17579 though see MOVE_RATIO in mips.h. */ 17580 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) 17581 target_flags |= MASK_MEMCPY; 17582 17583 /* If we have a nonzero small-data limit, check that the -mgpopt 17584 setting is consistent with the other target flags. */ 17585 if (mips_small_data_threshold > 0) 17586 { 17587 if (!TARGET_GPOPT) 17588 { 17589 if (!TARGET_EXPLICIT_RELOCS) 17590 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>"); 17591 17592 TARGET_LOCAL_SDATA = false; 17593 TARGET_EXTERN_SDATA = false; 17594 } 17595 else 17596 { 17597 if (TARGET_VXWORKS_RTP) 17598 warning (0, "cannot use small-data accesses for %qs", "-mrtp"); 17599 17600 if (TARGET_ABICALLS) 17601 warning (0, "cannot use small-data accesses for %qs", 17602 "-mabicalls"); 17603 } 17604 } 17605 17606 /* Set NaN and ABS defaults. */ 17607 if (mips_nan == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY) 17608 mips_nan = MIPS_IEEE_754_2008; 17609 if (mips_abs == MIPS_IEEE_754_DEFAULT && !ISA_HAS_IEEE_754_LEGACY) 17610 mips_abs = MIPS_IEEE_754_2008; 17611 17612 /* Check for IEEE 754 legacy/2008 support. */ 17613 if ((mips_nan == MIPS_IEEE_754_LEGACY 17614 || mips_abs == MIPS_IEEE_754_LEGACY) 17615 && !ISA_HAS_IEEE_754_LEGACY) 17616 warning (0, "the %qs architecture does not support %<-m%s=legacy%>", 17617 mips_arch_info->name, 17618 mips_nan == MIPS_IEEE_754_LEGACY ? "nan" : "abs"); 17619 17620 if ((mips_nan == MIPS_IEEE_754_2008 17621 || mips_abs == MIPS_IEEE_754_2008) 17622 && !ISA_HAS_IEEE_754_2008) 17623 warning (0, "the %qs architecture does not support %<-m%s=2008%>", 17624 mips_arch_info->name, 17625 mips_nan == MIPS_IEEE_754_2008 ? "nan" : "abs"); 17626 17627 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format 17628 for all its floating point. */ 17629 if (mips_nan != MIPS_IEEE_754_2008) 17630 { 17631 REAL_MODE_FORMAT (SFmode) = &mips_single_format; 17632 REAL_MODE_FORMAT (DFmode) = &mips_double_format; 17633 REAL_MODE_FORMAT (TFmode) = &mips_quad_format; 17634 } 17635 17636 /* Make sure that the user didn't turn off paired single support when 17637 MIPS-3D support is requested. */ 17638 if (TARGET_MIPS3D 17639 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT) 17640 && !TARGET_PAIRED_SINGLE_FLOAT) 17641 error ("%<-mips3d%> requires %<-mpaired-single%>"); 17642 17643 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */ 17644 if (TARGET_MIPS3D) 17645 target_flags |= MASK_PAIRED_SINGLE_FLOAT; 17646 17647 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 17648 and TARGET_HARD_FLOAT_ABI are both true. */ 17649 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) 17650 { 17651 error ("%qs must be used with %qs", 17652 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single", 17653 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float"); 17654 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT; 17655 TARGET_MIPS3D = 0; 17656 } 17657 17658 /* Make sure that -mpaired-single is only used on ISAs that support it. 17659 We must disable it otherwise since it relies on other ISA properties 17660 like ISA_HAS_8CC having their normal values. */ 17661 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE) 17662 { 17663 error ("the %qs architecture does not support paired-single" 17664 " instructions", mips_arch_info->name); 17665 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT; 17666 TARGET_MIPS3D = 0; 17667 } 17668 17669 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE 17670 && !TARGET_CACHE_BUILTIN) 17671 { 17672 error ("%qs requires a target that provides the %qs instruction", 17673 "-mr10k-cache-barrier", "cache"); 17674 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; 17675 } 17676 17677 /* If TARGET_DSPR2, enable TARGET_DSP. */ 17678 if (TARGET_DSPR2) 17679 TARGET_DSP = true; 17680 17681 if (TARGET_DSP && mips_isa_rev >= 6) 17682 { 17683 error ("the %qs architecture does not support DSP instructions", 17684 mips_arch_info->name); 17685 TARGET_DSP = false; 17686 TARGET_DSPR2 = false; 17687 } 17688 17689 /* .eh_frame addresses should be the same width as a C pointer. 17690 Most MIPS ABIs support only one pointer size, so the assembler 17691 will usually know exactly how big an .eh_frame address is. 17692 17693 Unfortunately, this is not true of the 64-bit EABI. The ABI was 17694 originally defined to use 64-bit pointers (i.e. it is LP64), and 17695 this is still the default mode. However, we also support an n32-like 17696 ILP32 mode, which is selected by -mlong32. The problem is that the 17697 assembler has traditionally not had an -mlong option, so it has 17698 traditionally not known whether we're using the ILP32 or LP64 form. 17699 17700 As it happens, gas versions up to and including 2.19 use _32-bit_ 17701 addresses for EABI64 .cfi_* directives. This is wrong for the 17702 default LP64 mode, so we can't use the directives by default. 17703 Moreover, since gas's current behavior is at odds with gcc's 17704 default behavior, it seems unwise to rely on future versions 17705 of gas behaving the same way. We therefore avoid using .cfi 17706 directives for -mlong32 as well. */ 17707 if (mips_abi == ABI_EABI && TARGET_64BIT) 17708 flag_dwarf2_cfi_asm = 0; 17709 17710 /* .cfi_* directives generate a read-only section, so fall back on 17711 manual .eh_frame creation if we need the section to be writable. */ 17712 if (TARGET_WRITABLE_EH_FRAME) 17713 flag_dwarf2_cfi_asm = 0; 17714 17715 mips_init_print_operand_punct (); 17716 17717 /* Set up array to map GCC register number to debug register number. 17718 Ignore the special purpose register numbers. */ 17719 17720 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 17721 { 17722 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM; 17723 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i)) 17724 mips_dwarf_regno[i] = i; 17725 else 17726 mips_dwarf_regno[i] = INVALID_REGNUM; 17727 } 17728 17729 start = GP_DBX_FIRST - GP_REG_FIRST; 17730 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) 17731 mips_dbx_regno[i] = i + start; 17732 17733 start = FP_DBX_FIRST - FP_REG_FIRST; 17734 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) 17735 mips_dbx_regno[i] = i + start; 17736 17737 /* Accumulator debug registers use big-endian ordering. */ 17738 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0; 17739 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1; 17740 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0; 17741 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1; 17742 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) 17743 { 17744 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i; 17745 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1; 17746 } 17747 17748 /* Set up mips_hard_regno_mode_ok. */ 17749 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 17750 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 17751 mips_hard_regno_mode_ok[mode][regno] 17752 = mips_hard_regno_mode_ok_p (regno, (machine_mode) mode); 17753 17754 /* Function to allocate machine-dependent function status. */ 17755 init_machine_status = &mips_init_machine_status; 17756 17757 /* Default to working around R4000 errata only if the processor 17758 was selected explicitly. */ 17759 if ((target_flags_explicit & MASK_FIX_R4000) == 0 17760 && strcmp (mips_arch_info->name, "r4000") == 0) 17761 target_flags |= MASK_FIX_R4000; 17762 17763 /* Default to working around R4400 errata only if the processor 17764 was selected explicitly. */ 17765 if ((target_flags_explicit & MASK_FIX_R4400) == 0 17766 && strcmp (mips_arch_info->name, "r4400") == 0) 17767 target_flags |= MASK_FIX_R4400; 17768 17769 /* Default to working around R10000 errata only if the processor 17770 was selected explicitly. */ 17771 if ((target_flags_explicit & MASK_FIX_R10000) == 0 17772 && strcmp (mips_arch_info->name, "r10000") == 0) 17773 target_flags |= MASK_FIX_R10000; 17774 17775 /* Make sure that branch-likely instructions available when using 17776 -mfix-r10000. The instructions are not available if either: 17777 17778 1. -mno-branch-likely was passed. 17779 2. The selected ISA does not support branch-likely and 17780 the command line does not include -mbranch-likely. */ 17781 if (TARGET_FIX_R10000 17782 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0 17783 ? !ISA_HAS_BRANCHLIKELY 17784 : !TARGET_BRANCHLIKELY)) 17785 sorry ("%qs requires branch-likely instructions", "-mfix-r10000"); 17786 17787 if (TARGET_SYNCI && !ISA_HAS_SYNCI) 17788 { 17789 warning (0, "the %qs architecture does not support the synci " 17790 "instruction", mips_arch_info->name); 17791 target_flags &= ~MASK_SYNCI; 17792 } 17793 17794 /* Only optimize PIC indirect calls if they are actually required. */ 17795 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS) 17796 target_flags &= ~MASK_RELAX_PIC_CALLS; 17797 17798 /* Save base state of options. */ 17799 mips_base_target_flags = target_flags; 17800 mips_base_schedule_insns = flag_schedule_insns; 17801 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition; 17802 mips_base_move_loop_invariants = flag_move_loop_invariants; 17803 mips_base_align_loops = align_loops; 17804 mips_base_align_jumps = align_jumps; 17805 mips_base_align_functions = align_functions; 17806 17807 /* Now select the ISA mode. 17808 17809 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes 17810 later if required. */ 17811 mips_set_compression_mode (0); 17812 17813 /* We register a second machine specific reorg pass after delay slot 17814 filling. Registering the pass must be done at start up. It's 17815 convenient to do it here. */ 17816 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g); 17817 struct register_pass_info insert_pass_mips_machine_reorg2 = 17818 { 17819 new_pass, /* pass */ 17820 "dbr", /* reference_pass_name */ 17821 1, /* ref_pass_instance_number */ 17822 PASS_POS_INSERT_AFTER /* po_op */ 17823 }; 17824 register_pass (&insert_pass_mips_machine_reorg2); 17825 17826 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900) 17827 REAL_MODE_FORMAT (SFmode) = &spu_single_format; 17828} 17829 17830/* Swap the register information for registers I and I + 1, which 17831 currently have the wrong endianness. Note that the registers' 17832 fixedness and call-clobberedness might have been set on the 17833 command line. */ 17834 17835static void 17836mips_swap_registers (unsigned int i) 17837{ 17838 int tmpi; 17839 const char *tmps; 17840 17841#define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi) 17842#define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps) 17843 17844 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]); 17845 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]); 17846 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]); 17847 SWAP_STRING (reg_names[i], reg_names[i + 1]); 17848 17849#undef SWAP_STRING 17850#undef SWAP_INT 17851} 17852 17853/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ 17854 17855static void 17856mips_conditional_register_usage (void) 17857{ 17858 17859 if (ISA_HAS_DSP) 17860 { 17861 /* These DSP control register fields are global. */ 17862 global_regs[CCDSP_PO_REGNUM] = 1; 17863 global_regs[CCDSP_SC_REGNUM] = 1; 17864 } 17865 else 17866 AND_COMPL_HARD_REG_SET (accessible_reg_set, 17867 reg_class_contents[(int) DSP_ACC_REGS]); 17868 17869 if (!ISA_HAS_HILO) 17870 AND_COMPL_HARD_REG_SET (accessible_reg_set, 17871 reg_class_contents[(int) MD_REGS]); 17872 17873 if (!TARGET_HARD_FLOAT) 17874 { 17875 AND_COMPL_HARD_REG_SET (accessible_reg_set, 17876 reg_class_contents[(int) FP_REGS]); 17877 AND_COMPL_HARD_REG_SET (accessible_reg_set, 17878 reg_class_contents[(int) ST_REGS]); 17879 } 17880 else if (!ISA_HAS_8CC) 17881 { 17882 /* We only have a single condition-code register. We implement 17883 this by fixing all the condition-code registers and generating 17884 RTL that refers directly to ST_REG_FIRST. */ 17885 AND_COMPL_HARD_REG_SET (accessible_reg_set, 17886 reg_class_contents[(int) ST_REGS]); 17887 if (!ISA_HAS_CCF) 17888 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM); 17889 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1; 17890 } 17891 if (TARGET_MIPS16) 17892 { 17893 /* In MIPS16 mode, we prohibit the unused $s registers, since they 17894 are call-saved, and saving them via a MIPS16 register would 17895 probably waste more time than just reloading the value. 17896 17897 We permit the $t temporary registers when optimizing for speed 17898 but not when optimizing for space because using them results in 17899 code that is larger (but faster) then not using them. We do 17900 allow $24 (t8) because it is used in CMP and CMPI instructions 17901 and $25 (t9) because it is used as the function call address in 17902 SVR4 PIC code. */ 17903 17904 fixed_regs[18] = call_used_regs[18] = 1; 17905 fixed_regs[19] = call_used_regs[19] = 1; 17906 fixed_regs[20] = call_used_regs[20] = 1; 17907 fixed_regs[21] = call_used_regs[21] = 1; 17908 fixed_regs[22] = call_used_regs[22] = 1; 17909 fixed_regs[23] = call_used_regs[23] = 1; 17910 fixed_regs[26] = call_used_regs[26] = 1; 17911 fixed_regs[27] = call_used_regs[27] = 1; 17912 fixed_regs[30] = call_used_regs[30] = 1; 17913 if (optimize_size) 17914 { 17915 fixed_regs[8] = call_used_regs[8] = 1; 17916 fixed_regs[9] = call_used_regs[9] = 1; 17917 fixed_regs[10] = call_used_regs[10] = 1; 17918 fixed_regs[11] = call_used_regs[11] = 1; 17919 fixed_regs[12] = call_used_regs[12] = 1; 17920 fixed_regs[13] = call_used_regs[13] = 1; 17921 fixed_regs[14] = call_used_regs[14] = 1; 17922 fixed_regs[15] = call_used_regs[15] = 1; 17923 } 17924 17925 /* Do not allow HI and LO to be treated as register operands. 17926 There are no MTHI or MTLO instructions (or any real need 17927 for them) and one-way registers cannot easily be reloaded. */ 17928 AND_COMPL_HARD_REG_SET (operand_reg_set, 17929 reg_class_contents[(int) MD_REGS]); 17930 } 17931 /* $f20-$f23 are call-clobbered for n64. */ 17932 if (mips_abi == ABI_64) 17933 { 17934 int regno; 17935 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) 17936 call_really_used_regs[regno] = call_used_regs[regno] = 1; 17937 } 17938 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered 17939 for n32 and o32 FP64. */ 17940 if (mips_abi == ABI_N32 17941 || (mips_abi == ABI_32 17942 && TARGET_FLOAT64)) 17943 { 17944 int regno; 17945 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) 17946 call_really_used_regs[regno] = call_used_regs[regno] = 1; 17947 } 17948 /* Make sure that double-register accumulator values are correctly 17949 ordered for the current endianness. */ 17950 if (TARGET_LITTLE_ENDIAN) 17951 { 17952 unsigned int regno; 17953 17954 mips_swap_registers (MD_REG_FIRST); 17955 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2) 17956 mips_swap_registers (regno); 17957 } 17958} 17959 17960/* Implement EH_USES. */ 17961 17962bool 17963mips_eh_uses (unsigned int regno) 17964{ 17965 if (reload_completed && !TARGET_ABSOLUTE_JUMPS) 17966 { 17967 /* We need to force certain registers to be live in order to handle 17968 PIC long branches correctly. See mips_must_initialize_gp_p for 17969 details. */ 17970 if (mips_cfun_has_cprestore_slot_p ()) 17971 { 17972 if (regno == CPRESTORE_SLOT_REGNUM) 17973 return true; 17974 } 17975 else 17976 { 17977 if (cfun->machine->global_pointer == regno) 17978 return true; 17979 } 17980 } 17981 17982 return false; 17983} 17984 17985/* Implement EPILOGUE_USES. */ 17986 17987bool 17988mips_epilogue_uses (unsigned int regno) 17989{ 17990 /* Say that the epilogue uses the return address register. Note that 17991 in the case of sibcalls, the values "used by the epilogue" are 17992 considered live at the start of the called function. */ 17993 if (regno == RETURN_ADDR_REGNUM) 17994 return true; 17995 17996 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM. 17997 See the comment above load_call<mode> for details. */ 17998 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM) 17999 return true; 18000 18001 /* An interrupt handler must preserve some registers that are 18002 ordinarily call-clobbered. */ 18003 if (cfun->machine->interrupt_handler_p 18004 && mips_interrupt_extra_call_saved_reg_p (regno)) 18005 return true; 18006 18007 return false; 18008} 18009 18010/* Return true if INSN needs to be wrapped in ".set noat". 18011 INSN has NOPERANDS operands, stored in OPVEC. */ 18012 18013static bool 18014mips_need_noat_wrapper_p (rtx_insn *insn, rtx *opvec, int noperands) 18015{ 18016 if (recog_memoized (insn) >= 0) 18017 { 18018 subrtx_iterator::array_type array; 18019 for (int i = 0; i < noperands; i++) 18020 FOR_EACH_SUBRTX (iter, array, opvec[i], NONCONST) 18021 if (REG_P (*iter) && REGNO (*iter) == AT_REGNUM) 18022 return true; 18023 } 18024 return false; 18025} 18026 18027/* Implement FINAL_PRESCAN_INSN. */ 18028 18029void 18030mips_final_prescan_insn (rtx_insn *insn, rtx *opvec, int noperands) 18031{ 18032 if (mips_need_noat_wrapper_p (insn, opvec, noperands)) 18033 mips_push_asm_switch (&mips_noat); 18034} 18035 18036/* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */ 18037 18038static void 18039mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx_insn *insn, 18040 rtx *opvec, int noperands) 18041{ 18042 if (mips_need_noat_wrapper_p (insn, opvec, noperands)) 18043 mips_pop_asm_switch (&mips_noat); 18044} 18045 18046/* Return the function that is used to expand the <u>mulsidi3 pattern. 18047 EXT_CODE is the code of the extension used. Return NULL if widening 18048 multiplication shouldn't be used. */ 18049 18050mulsidi3_gen_fn 18051mips_mulsidi3_gen_fn (enum rtx_code ext_code) 18052{ 18053 bool signed_p; 18054 18055 signed_p = ext_code == SIGN_EXTEND; 18056 if (TARGET_64BIT) 18057 { 18058 /* Don't use widening multiplication with MULT when we have DMUL. Even 18059 with the extension of its input operands DMUL is faster. Note that 18060 the extension is not needed for signed multiplication. In order to 18061 ensure that we always remove the redundant sign-extension in this 18062 case we still expand mulsidi3 for DMUL. */ 18063 if (ISA_HAS_R6DMUL) 18064 return signed_p ? gen_mulsidi3_64bit_r6dmul : NULL; 18065 if (ISA_HAS_DMUL3) 18066 return signed_p ? gen_mulsidi3_64bit_dmul : NULL; 18067 if (TARGET_MIPS16) 18068 return (signed_p 18069 ? gen_mulsidi3_64bit_mips16 18070 : gen_umulsidi3_64bit_mips16); 18071 if (TARGET_FIX_R4000) 18072 return NULL; 18073 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit; 18074 } 18075 else 18076 { 18077 if (ISA_HAS_R6MUL) 18078 return (signed_p ? gen_mulsidi3_32bit_r6 : gen_umulsidi3_32bit_r6); 18079 if (TARGET_MIPS16) 18080 return (signed_p 18081 ? gen_mulsidi3_32bit_mips16 18082 : gen_umulsidi3_32bit_mips16); 18083 if (TARGET_FIX_R4000 && !ISA_HAS_DSP) 18084 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000; 18085 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit; 18086 } 18087} 18088 18089/* Return true if PATTERN matches the kind of instruction generated by 18090 umips_build_save_restore. SAVE_P is true for store. */ 18091 18092bool 18093umips_save_restore_pattern_p (bool save_p, rtx pattern) 18094{ 18095 int n; 18096 unsigned int i; 18097 HOST_WIDE_INT first_offset = 0; 18098 rtx first_base = 0; 18099 unsigned int regmask = 0; 18100 18101 for (n = 0; n < XVECLEN (pattern, 0); n++) 18102 { 18103 rtx set, reg, mem, this_base; 18104 HOST_WIDE_INT this_offset; 18105 18106 /* Check that we have a SET. */ 18107 set = XVECEXP (pattern, 0, n); 18108 if (GET_CODE (set) != SET) 18109 return false; 18110 18111 /* Check that the SET is a load (if restoring) or a store 18112 (if saving). */ 18113 mem = save_p ? SET_DEST (set) : SET_SRC (set); 18114 if (!MEM_P (mem) || MEM_VOLATILE_P (mem)) 18115 return false; 18116 18117 /* Check that the address is the sum of base and a possibly-zero 18118 constant offset. Determine if the offset is in range. */ 18119 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset); 18120 if (!REG_P (this_base)) 18121 return false; 18122 18123 if (n == 0) 18124 { 18125 if (!UMIPS_12BIT_OFFSET_P (this_offset)) 18126 return false; 18127 first_base = this_base; 18128 first_offset = this_offset; 18129 } 18130 else 18131 { 18132 /* Check that the save slots are consecutive. */ 18133 if (REGNO (this_base) != REGNO (first_base) 18134 || this_offset != first_offset + UNITS_PER_WORD * n) 18135 return false; 18136 } 18137 18138 /* Check that SET's other operand is a register. */ 18139 reg = save_p ? SET_SRC (set) : SET_DEST (set); 18140 if (!REG_P (reg)) 18141 return false; 18142 18143 regmask |= 1 << REGNO (reg); 18144 } 18145 18146 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++) 18147 if (regmask == umips_swm_mask[i]) 18148 return true; 18149 18150 return false; 18151} 18152 18153/* Return the assembly instruction for microMIPS LWM or SWM. 18154 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */ 18155 18156const char * 18157umips_output_save_restore (bool save_p, rtx pattern) 18158{ 18159 static char buffer[300]; 18160 char *s; 18161 int n; 18162 HOST_WIDE_INT offset; 18163 rtx base, mem, set, last_set, last_reg; 18164 18165 /* Parse the pattern. */ 18166 gcc_assert (umips_save_restore_pattern_p (save_p, pattern)); 18167 18168 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t"); 18169 s += strlen (s); 18170 n = XVECLEN (pattern, 0); 18171 18172 set = XVECEXP (pattern, 0, 0); 18173 mem = save_p ? SET_DEST (set) : SET_SRC (set); 18174 mips_split_plus (XEXP (mem, 0), &base, &offset); 18175 18176 last_set = XVECEXP (pattern, 0, n - 1); 18177 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set); 18178 18179 if (REGNO (last_reg) == 31) 18180 n--; 18181 18182 gcc_assert (n <= 9); 18183 if (n == 0) 18184 ; 18185 else if (n == 1) 18186 s += sprintf (s, "%s,", reg_names[16]); 18187 else if (n < 9) 18188 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]); 18189 else if (n == 9) 18190 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23], 18191 reg_names[30]); 18192 18193 if (REGNO (last_reg) == 31) 18194 s += sprintf (s, "%s,", reg_names[31]); 18195 18196 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]); 18197 return buffer; 18198} 18199 18200/* Return true if MEM1 and MEM2 use the same base register, and the 18201 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the 18202 register into (from) which the contents of MEM1 will be loaded 18203 (stored), depending on the value of LOAD_P. 18204 SWAP_P is true when the 1st and 2nd instructions are swapped. */ 18205 18206static bool 18207umips_load_store_pair_p_1 (bool load_p, bool swap_p, 18208 rtx first_reg, rtx mem1, rtx mem2) 18209{ 18210 rtx base1, base2; 18211 HOST_WIDE_INT offset1, offset2; 18212 18213 if (!MEM_P (mem1) || !MEM_P (mem2)) 18214 return false; 18215 18216 mips_split_plus (XEXP (mem1, 0), &base1, &offset1); 18217 mips_split_plus (XEXP (mem2, 0), &base2, &offset2); 18218 18219 if (!REG_P (base1) || !rtx_equal_p (base1, base2)) 18220 return false; 18221 18222 /* Avoid invalid load pair instructions. */ 18223 if (load_p && REGNO (first_reg) == REGNO (base1)) 18224 return false; 18225 18226 /* We must avoid this case for anti-dependence. 18227 Ex: lw $3, 4($3) 18228 lw $2, 0($3) 18229 first_reg is $2, but the base is $3. */ 18230 if (load_p 18231 && swap_p 18232 && REGNO (first_reg) + 1 == REGNO (base1)) 18233 return false; 18234 18235 if (offset2 != offset1 + 4) 18236 return false; 18237 18238 if (!UMIPS_12BIT_OFFSET_P (offset1)) 18239 return false; 18240 18241 return true; 18242} 18243 18244/* OPERANDS describes the operands to a pair of SETs, in the order 18245 dest1, src1, dest2, src2. Return true if the operands can be used 18246 in an LWP or SWP instruction; LOAD_P says which. */ 18247 18248bool 18249umips_load_store_pair_p (bool load_p, rtx *operands) 18250{ 18251 rtx reg1, reg2, mem1, mem2; 18252 18253 if (load_p) 18254 { 18255 reg1 = operands[0]; 18256 reg2 = operands[2]; 18257 mem1 = operands[1]; 18258 mem2 = operands[3]; 18259 } 18260 else 18261 { 18262 reg1 = operands[1]; 18263 reg2 = operands[3]; 18264 mem1 = operands[0]; 18265 mem2 = operands[2]; 18266 } 18267 18268 if (REGNO (reg2) == REGNO (reg1) + 1) 18269 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2); 18270 18271 if (REGNO (reg1) == REGNO (reg2) + 1) 18272 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1); 18273 18274 return false; 18275} 18276 18277/* Return the assembly instruction for a microMIPS LWP or SWP in which 18278 the first register is REG and the first memory slot is MEM. 18279 LOAD_P is true for LWP. */ 18280 18281static void 18282umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem) 18283{ 18284 rtx ops[] = {reg, mem}; 18285 18286 if (load_p) 18287 output_asm_insn ("lwp\t%0,%1", ops); 18288 else 18289 output_asm_insn ("swp\t%0,%1", ops); 18290} 18291 18292/* Output the assembly instruction for a microMIPS LWP or SWP instruction. 18293 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */ 18294 18295void 18296umips_output_load_store_pair (bool load_p, rtx *operands) 18297{ 18298 rtx reg1, reg2, mem1, mem2; 18299 if (load_p) 18300 { 18301 reg1 = operands[0]; 18302 reg2 = operands[2]; 18303 mem1 = operands[1]; 18304 mem2 = operands[3]; 18305 } 18306 else 18307 { 18308 reg1 = operands[1]; 18309 reg2 = operands[3]; 18310 mem1 = operands[0]; 18311 mem2 = operands[2]; 18312 } 18313 18314 if (REGNO (reg2) == REGNO (reg1) + 1) 18315 { 18316 umips_output_load_store_pair_1 (load_p, reg1, mem1); 18317 return; 18318 } 18319 18320 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1); 18321 umips_output_load_store_pair_1 (load_p, reg2, mem2); 18322} 18323 18324/* Return true if REG1 and REG2 match the criteria for a movep insn. */ 18325 18326bool 18327umips_movep_target_p (rtx reg1, rtx reg2) 18328{ 18329 int regno1, regno2, pair; 18330 unsigned int i; 18331 static const int match[8] = { 18332 0x00000060, /* 5, 6 */ 18333 0x000000a0, /* 5, 7 */ 18334 0x000000c0, /* 6, 7 */ 18335 0x00200010, /* 4, 21 */ 18336 0x00400010, /* 4, 22 */ 18337 0x00000030, /* 4, 5 */ 18338 0x00000050, /* 4, 6 */ 18339 0x00000090 /* 4, 7 */ 18340 }; 18341 18342 if (!REG_P (reg1) || !REG_P (reg2)) 18343 return false; 18344 18345 regno1 = REGNO (reg1); 18346 regno2 = REGNO (reg2); 18347 18348 if (!GP_REG_P (regno1) || !GP_REG_P (regno2)) 18349 return false; 18350 18351 pair = (1 << regno1) | (1 << regno2); 18352 18353 for (i = 0; i < ARRAY_SIZE (match); i++) 18354 if (pair == match[i]) 18355 return true; 18356 18357 return false; 18358} 18359 18360/* Return the size in bytes of the trampoline code, padded to 18361 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target 18362 function address immediately follow. */ 18363 18364int 18365mips_trampoline_code_size (void) 18366{ 18367 if (TARGET_USE_PIC_FN_ADDR_REG) 18368 return 4 * 4; 18369 else if (ptr_mode == DImode) 18370 return 8 * 4; 18371 else if (ISA_HAS_LOAD_DELAY) 18372 return 6 * 4; 18373 else 18374 return 4 * 4; 18375} 18376 18377/* Implement TARGET_TRAMPOLINE_INIT. */ 18378 18379static void 18380mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 18381{ 18382 rtx addr, end_addr, high, low, opcode, mem; 18383 rtx trampoline[8]; 18384 unsigned int i, j; 18385 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset; 18386 18387 /* Work out the offsets of the pointers from the start of the 18388 trampoline code. */ 18389 end_addr_offset = mips_trampoline_code_size (); 18390 static_chain_offset = end_addr_offset; 18391 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); 18392 18393 /* Get pointers to the beginning and end of the code block. */ 18394 addr = force_reg (Pmode, XEXP (m_tramp, 0)); 18395 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset)); 18396 18397#define OP(X) gen_int_mode (X, SImode) 18398 18399 /* Build up the code in TRAMPOLINE. */ 18400 i = 0; 18401 if (TARGET_USE_PIC_FN_ADDR_REG) 18402 { 18403 /* $25 contains the address of the trampoline. Emit code of the form: 18404 18405 l[wd] $1, target_function_offset($25) 18406 l[wd] $static_chain, static_chain_offset($25) 18407 jr $1 18408 move $25,$1. */ 18409 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM, 18410 target_function_offset, 18411 PIC_FUNCTION_ADDR_REGNUM)); 18412 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, 18413 static_chain_offset, 18414 PIC_FUNCTION_ADDR_REGNUM)); 18415 trampoline[i++] = OP (MIPS_JR (AT_REGNUM)); 18416 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM)); 18417 } 18418 else if (ptr_mode == DImode) 18419 { 18420 /* It's too cumbersome to create the full 64-bit address, so let's 18421 instead use: 18422 18423 move $1, $31 18424 bal 1f 18425 nop 18426 1: l[wd] $25, target_function_offset - 12($31) 18427 l[wd] $static_chain, static_chain_offset - 12($31) 18428 jr $25 18429 move $31, $1 18430 18431 where 12 is the offset of "1:" from the start of the code block. */ 18432 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM)); 18433 trampoline[i++] = OP (MIPS_BAL (1)); 18434 trampoline[i++] = OP (MIPS_NOP); 18435 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, 18436 target_function_offset - 12, 18437 RETURN_ADDR_REGNUM)); 18438 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, 18439 static_chain_offset - 12, 18440 RETURN_ADDR_REGNUM)); 18441 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); 18442 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM)); 18443 } 18444 else 18445 { 18446 /* If the target has load delays, emit: 18447 18448 lui $1, %hi(end_addr) 18449 lw $25, %lo(end_addr + ...)($1) 18450 lw $static_chain, %lo(end_addr + ...)($1) 18451 jr $25 18452 nop 18453 18454 Otherwise emit: 18455 18456 lui $1, %hi(end_addr) 18457 lw $25, %lo(end_addr + ...)($1) 18458 jr $25 18459 lw $static_chain, %lo(end_addr + ...)($1). */ 18460 18461 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned 18462 to 64 bits, so the %lo value will have the bottom 3 bits clear. */ 18463 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000), 18464 NULL, false, OPTAB_WIDEN); 18465 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16), 18466 NULL, false, OPTAB_WIDEN); 18467 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true); 18468 18469 /* Emit the LUI. */ 18470 opcode = OP (MIPS_LUI (AT_REGNUM, 0)); 18471 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high, 18472 NULL, false, OPTAB_WIDEN); 18473 18474 /* Emit the load of the target function. */ 18475 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, 18476 target_function_offset - end_addr_offset, 18477 AT_REGNUM)); 18478 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, 18479 NULL, false, OPTAB_WIDEN); 18480 18481 /* Emit the JR here, if we can. */ 18482 if (!ISA_HAS_LOAD_DELAY) 18483 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); 18484 18485 /* Emit the load of the static chain register. */ 18486 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, 18487 static_chain_offset - end_addr_offset, 18488 AT_REGNUM)); 18489 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, 18490 NULL, false, OPTAB_WIDEN); 18491 18492 /* Emit the JR, if we couldn't above. */ 18493 if (ISA_HAS_LOAD_DELAY) 18494 { 18495 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); 18496 trampoline[i++] = OP (MIPS_NOP); 18497 } 18498 } 18499 18500#undef OP 18501 18502 /* Copy the trampoline code. Leave any padding uninitialized. */ 18503 for (j = 0; j < i; j++) 18504 { 18505 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode)); 18506 mips_emit_move (mem, trampoline[j]); 18507 } 18508 18509 /* Set up the static chain pointer field. */ 18510 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); 18511 mips_emit_move (mem, chain_value); 18512 18513 /* Set up the target function field. */ 18514 mem = adjust_address (m_tramp, ptr_mode, target_function_offset); 18515 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); 18516 18517 /* Flush the code part of the trampoline. */ 18518 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); 18519 emit_insn (gen_clear_cache (addr, end_addr)); 18520} 18521 18522/* Implement FUNCTION_PROFILER. */ 18523 18524void mips_function_profiler (FILE *file) 18525{ 18526 if (TARGET_MIPS16) 18527 sorry ("mips16 function profiling"); 18528 if (TARGET_LONG_CALLS) 18529 { 18530 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ 18531 if (Pmode == DImode) 18532 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]); 18533 else 18534 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]); 18535 } 18536 mips_push_asm_switch (&mips_noat); 18537 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n", 18538 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]); 18539 /* _mcount treats $2 as the static chain register. */ 18540 if (cfun->static_chain_decl != NULL) 18541 fprintf (file, "\tmove\t%s,%s\n", reg_names[2], 18542 reg_names[STATIC_CHAIN_REGNUM]); 18543 if (TARGET_MCOUNT_RA_ADDRESS) 18544 { 18545 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the 18546 ra save location. */ 18547 if (cfun->machine->frame.ra_fp_offset == 0) 18548 /* ra not saved, pass zero. */ 18549 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]); 18550 else 18551 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n", 18552 Pmode == DImode ? "dla" : "la", reg_names[12], 18553 cfun->machine->frame.ra_fp_offset, 18554 reg_names[STACK_POINTER_REGNUM]); 18555 } 18556 if (!TARGET_NEWABI) 18557 fprintf (file, 18558 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", 18559 TARGET_64BIT ? "dsubu" : "subu", 18560 reg_names[STACK_POINTER_REGNUM], 18561 reg_names[STACK_POINTER_REGNUM], 18562 Pmode == DImode ? 16 : 8); 18563 18564 if (TARGET_LONG_CALLS) 18565 fprintf (file, "\tjalr\t%s\n", reg_names[3]); 18566 else 18567 fprintf (file, "\tjal\t_mcount\n"); 18568 mips_pop_asm_switch (&mips_noat); 18569 /* _mcount treats $2 as the static chain register. */ 18570 if (cfun->static_chain_decl != NULL) 18571 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], 18572 reg_names[2]); 18573} 18574 18575/* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default 18576 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even 18577 when TARGET_LOONGSON_VECTORS is true. */ 18578 18579static unsigned HOST_WIDE_INT 18580mips_shift_truncation_mask (machine_mode mode) 18581{ 18582 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) 18583 return 0; 18584 18585 return GET_MODE_BITSIZE (mode) - 1; 18586} 18587 18588/* Implement TARGET_PREPARE_PCH_SAVE. */ 18589 18590static void 18591mips_prepare_pch_save (void) 18592{ 18593 /* We are called in a context where the current MIPS16 vs. non-MIPS16 18594 setting should be irrelevant. The question then is: which setting 18595 makes most sense at load time? 18596 18597 The PCH is loaded before the first token is read. We should never 18598 have switched into MIPS16 mode by that point, and thus should not 18599 have populated mips16_globals. Nor can we load the entire contents 18600 of mips16_globals from the PCH file, because mips16_globals contains 18601 a combination of GGC and non-GGC data. 18602 18603 There is therefore no point in trying save the GGC part of 18604 mips16_globals to the PCH file, or to preserve MIPS16ness across 18605 the PCH save and load. The loading compiler would not have access 18606 to the non-GGC parts of mips16_globals (either from the PCH file, 18607 or from a copy that the loading compiler generated itself) and would 18608 have to call target_reinit anyway. 18609 18610 It therefore seems best to switch back to non-MIPS16 mode at 18611 save time, and to ensure that mips16_globals remains null after 18612 a PCH load. */ 18613 mips_set_compression_mode (0); 18614 mips16_globals = 0; 18615} 18616 18617/* Generate or test for an insn that supports a constant permutation. */ 18618 18619#define MAX_VECT_LEN 8 18620 18621struct expand_vec_perm_d 18622{ 18623 rtx target, op0, op1; 18624 unsigned char perm[MAX_VECT_LEN]; 18625 machine_mode vmode; 18626 unsigned char nelt; 18627 bool one_vector_p; 18628 bool testing_p; 18629}; 18630 18631/* Construct (set target (vec_select op0 (parallel perm))) and 18632 return true if that's a valid instruction in the active ISA. */ 18633 18634static bool 18635mips_expand_vselect (rtx target, rtx op0, 18636 const unsigned char *perm, unsigned nelt) 18637{ 18638 rtx rperm[MAX_VECT_LEN], x; 18639 rtx_insn *insn; 18640 unsigned i; 18641 18642 for (i = 0; i < nelt; ++i) 18643 rperm[i] = GEN_INT (perm[i]); 18644 18645 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); 18646 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); 18647 x = gen_rtx_SET (VOIDmode, target, x); 18648 18649 insn = emit_insn (x); 18650 if (recog_memoized (insn) < 0) 18651 { 18652 remove_insn (insn); 18653 return false; 18654 } 18655 return true; 18656} 18657 18658/* Similar, but generate a vec_concat from op0 and op1 as well. */ 18659 18660static bool 18661mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1, 18662 const unsigned char *perm, unsigned nelt) 18663{ 18664 machine_mode v2mode; 18665 rtx x; 18666 18667 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0)); 18668 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); 18669 return mips_expand_vselect (target, x, perm, nelt); 18670} 18671 18672/* Recognize patterns for even-odd extraction. */ 18673 18674static bool 18675mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d) 18676{ 18677 unsigned i, odd, nelt = d->nelt; 18678 rtx t0, t1, t2, t3; 18679 18680 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) 18681 return false; 18682 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */ 18683 if (nelt < 4) 18684 return false; 18685 18686 odd = d->perm[0]; 18687 if (odd > 1) 18688 return false; 18689 for (i = 1; i < nelt; ++i) 18690 if (d->perm[i] != i * 2 + odd) 18691 return false; 18692 18693 if (d->testing_p) 18694 return true; 18695 18696 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */ 18697 t0 = gen_reg_rtx (d->vmode); 18698 t1 = gen_reg_rtx (d->vmode); 18699 switch (d->vmode) 18700 { 18701 case V4HImode: 18702 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1)); 18703 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1)); 18704 if (odd) 18705 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0)); 18706 else 18707 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0)); 18708 break; 18709 18710 case V8QImode: 18711 t2 = gen_reg_rtx (d->vmode); 18712 t3 = gen_reg_rtx (d->vmode); 18713 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1)); 18714 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1)); 18715 emit_insn (gen_loongson_punpckhbh (t2, t1, t0)); 18716 emit_insn (gen_loongson_punpcklbh (t3, t1, t0)); 18717 if (odd) 18718 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2)); 18719 else 18720 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2)); 18721 break; 18722 18723 default: 18724 gcc_unreachable (); 18725 } 18726 return true; 18727} 18728 18729/* Recognize patterns for the Loongson PSHUFH instruction. */ 18730 18731static bool 18732mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d) 18733{ 18734 unsigned i, mask; 18735 rtx rmask; 18736 18737 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) 18738 return false; 18739 if (d->vmode != V4HImode) 18740 return false; 18741 if (d->testing_p) 18742 return true; 18743 18744 /* Convert the selector into the packed 8-bit form for pshufh. */ 18745 /* Recall that loongson is little-endian only. No big-endian 18746 adjustment required. */ 18747 for (i = mask = 0; i < 4; i++) 18748 mask |= (d->perm[i] & 3) << (i * 2); 18749 rmask = force_reg (SImode, GEN_INT (mask)); 18750 18751 if (d->one_vector_p) 18752 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask)); 18753 else 18754 { 18755 rtx t0, t1, x, merge, rmerge[4]; 18756 18757 t0 = gen_reg_rtx (V4HImode); 18758 t1 = gen_reg_rtx (V4HImode); 18759 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask)); 18760 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask)); 18761 18762 for (i = 0; i < 4; ++i) 18763 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx); 18764 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge)); 18765 merge = force_reg (V4HImode, merge); 18766 18767 x = gen_rtx_AND (V4HImode, merge, t1); 18768 emit_insn (gen_rtx_SET (VOIDmode, t1, x)); 18769 18770 x = gen_rtx_NOT (V4HImode, merge); 18771 x = gen_rtx_AND (V4HImode, x, t0); 18772 emit_insn (gen_rtx_SET (VOIDmode, t0, x)); 18773 18774 x = gen_rtx_IOR (V4HImode, t0, t1); 18775 emit_insn (gen_rtx_SET (VOIDmode, d->target, x)); 18776 } 18777 18778 return true; 18779} 18780 18781/* Recognize broadcast patterns for the Loongson. */ 18782 18783static bool 18784mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d) 18785{ 18786 unsigned i, elt; 18787 rtx t0, t1; 18788 18789 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) 18790 return false; 18791 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */ 18792 if (d->vmode != V8QImode) 18793 return false; 18794 if (!d->one_vector_p) 18795 return false; 18796 18797 elt = d->perm[0]; 18798 for (i = 1; i < 8; ++i) 18799 if (d->perm[i] != elt) 18800 return false; 18801 18802 if (d->testing_p) 18803 return true; 18804 18805 /* With one interleave we put two of the desired element adjacent. */ 18806 t0 = gen_reg_rtx (V8QImode); 18807 if (elt < 4) 18808 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0)); 18809 else 18810 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0)); 18811 18812 /* Shuffle that one HImode element into all locations. */ 18813 elt &= 3; 18814 elt *= 0x55; 18815 t1 = gen_reg_rtx (V4HImode); 18816 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0), 18817 force_reg (SImode, GEN_INT (elt)))); 18818 18819 emit_move_insn (d->target, gen_lowpart (V8QImode, t1)); 18820 return true; 18821} 18822 18823static bool 18824mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) 18825{ 18826 unsigned int i, nelt = d->nelt; 18827 unsigned char perm2[MAX_VECT_LEN]; 18828 18829 if (d->one_vector_p) 18830 { 18831 /* Try interleave with alternating operands. */ 18832 memcpy (perm2, d->perm, sizeof(perm2)); 18833 for (i = 1; i < nelt; i += 2) 18834 perm2[i] += nelt; 18835 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt)) 18836 return true; 18837 } 18838 else 18839 { 18840 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, 18841 d->perm, nelt)) 18842 return true; 18843 18844 /* Try again with swapped operands. */ 18845 for (i = 0; i < nelt; ++i) 18846 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1); 18847 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) 18848 return true; 18849 } 18850 18851 if (mips_expand_vpc_loongson_even_odd (d)) 18852 return true; 18853 if (mips_expand_vpc_loongson_pshufh (d)) 18854 return true; 18855 if (mips_expand_vpc_loongson_bcast (d)) 18856 return true; 18857 return false; 18858} 18859 18860/* Expand a vec_perm_const pattern. */ 18861 18862bool 18863mips_expand_vec_perm_const (rtx operands[4]) 18864{ 18865 struct expand_vec_perm_d d; 18866 int i, nelt, which; 18867 unsigned char orig_perm[MAX_VECT_LEN]; 18868 rtx sel; 18869 bool ok; 18870 18871 d.target = operands[0]; 18872 d.op0 = operands[1]; 18873 d.op1 = operands[2]; 18874 sel = operands[3]; 18875 18876 d.vmode = GET_MODE (d.target); 18877 gcc_assert (VECTOR_MODE_P (d.vmode)); 18878 d.nelt = nelt = GET_MODE_NUNITS (d.vmode); 18879 d.testing_p = false; 18880 18881 for (i = which = 0; i < nelt; ++i) 18882 { 18883 rtx e = XVECEXP (sel, 0, i); 18884 int ei = INTVAL (e) & (2 * nelt - 1); 18885 which |= (ei < nelt ? 1 : 2); 18886 orig_perm[i] = ei; 18887 } 18888 memcpy (d.perm, orig_perm, MAX_VECT_LEN); 18889 18890 switch (which) 18891 { 18892 default: 18893 gcc_unreachable(); 18894 18895 case 3: 18896 d.one_vector_p = false; 18897 if (!rtx_equal_p (d.op0, d.op1)) 18898 break; 18899 /* FALLTHRU */ 18900 18901 case 2: 18902 for (i = 0; i < nelt; ++i) 18903 d.perm[i] &= nelt - 1; 18904 d.op0 = d.op1; 18905 d.one_vector_p = true; 18906 break; 18907 18908 case 1: 18909 d.op1 = d.op0; 18910 d.one_vector_p = true; 18911 break; 18912 } 18913 18914 ok = mips_expand_vec_perm_const_1 (&d); 18915 18916 /* If we were given a two-vector permutation which just happened to 18917 have both input vectors equal, we folded this into a one-vector 18918 permutation. There are several loongson patterns that are matched 18919 via direct vec_select+vec_concat expansion, but we do not have 18920 support in mips_expand_vec_perm_const_1 to guess the adjustment 18921 that should be made for a single operand. Just try again with 18922 the original permutation. */ 18923 if (!ok && which == 3) 18924 { 18925 d.op0 = operands[1]; 18926 d.op1 = operands[2]; 18927 d.one_vector_p = false; 18928 memcpy (d.perm, orig_perm, MAX_VECT_LEN); 18929 ok = mips_expand_vec_perm_const_1 (&d); 18930 } 18931 18932 return ok; 18933} 18934 18935/* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ 18936 18937static bool 18938mips_vectorize_vec_perm_const_ok (machine_mode vmode, 18939 const unsigned char *sel) 18940{ 18941 struct expand_vec_perm_d d; 18942 unsigned int i, nelt, which; 18943 bool ret; 18944 18945 d.vmode = vmode; 18946 d.nelt = nelt = GET_MODE_NUNITS (d.vmode); 18947 d.testing_p = true; 18948 memcpy (d.perm, sel, nelt); 18949 18950 /* Categorize the set of elements in the selector. */ 18951 for (i = which = 0; i < nelt; ++i) 18952 { 18953 unsigned char e = d.perm[i]; 18954 gcc_assert (e < 2 * nelt); 18955 which |= (e < nelt ? 1 : 2); 18956 } 18957 18958 /* For all elements from second vector, fold the elements to first. */ 18959 if (which == 2) 18960 for (i = 0; i < nelt; ++i) 18961 d.perm[i] -= nelt; 18962 18963 /* Check whether the mask can be applied to the vector type. */ 18964 d.one_vector_p = (which != 3); 18965 18966 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); 18967 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); 18968 if (!d.one_vector_p) 18969 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); 18970 18971 start_sequence (); 18972 ret = mips_expand_vec_perm_const_1 (&d); 18973 end_sequence (); 18974 18975 return ret; 18976} 18977 18978/* Expand an integral vector unpack operation. */ 18979 18980void 18981mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) 18982{ 18983 machine_mode imode = GET_MODE (operands[1]); 18984 rtx (*unpack) (rtx, rtx, rtx); 18985 rtx (*cmpgt) (rtx, rtx, rtx); 18986 rtx tmp, dest, zero; 18987 18988 switch (imode) 18989 { 18990 case V8QImode: 18991 if (high_p) 18992 unpack = gen_loongson_punpckhbh; 18993 else 18994 unpack = gen_loongson_punpcklbh; 18995 cmpgt = gen_loongson_pcmpgtb; 18996 break; 18997 case V4HImode: 18998 if (high_p) 18999 unpack = gen_loongson_punpckhhw; 19000 else 19001 unpack = gen_loongson_punpcklhw; 19002 cmpgt = gen_loongson_pcmpgth; 19003 break; 19004 default: 19005 gcc_unreachable (); 19006 } 19007 19008 zero = force_reg (imode, CONST0_RTX (imode)); 19009 if (unsigned_p) 19010 tmp = zero; 19011 else 19012 { 19013 tmp = gen_reg_rtx (imode); 19014 emit_insn (cmpgt (tmp, zero, operands[1])); 19015 } 19016 19017 dest = gen_reg_rtx (imode); 19018 emit_insn (unpack (dest, operands[1], tmp)); 19019 19020 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest)); 19021} 19022 19023/* A subroutine of mips_expand_vec_init, match constant vector elements. */ 19024 19025static inline bool 19026mips_constant_elt_p (rtx x) 19027{ 19028 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE; 19029} 19030 19031/* A subroutine of mips_expand_vec_init, expand via broadcast. */ 19032 19033static void 19034mips_expand_vi_broadcast (machine_mode vmode, rtx target, rtx elt) 19035{ 19036 struct expand_vec_perm_d d; 19037 rtx t1; 19038 bool ok; 19039 19040 if (elt != const0_rtx) 19041 elt = force_reg (GET_MODE_INNER (vmode), elt); 19042 if (REG_P (elt)) 19043 elt = gen_lowpart (DImode, elt); 19044 19045 t1 = gen_reg_rtx (vmode); 19046 switch (vmode) 19047 { 19048 case V8QImode: 19049 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt)); 19050 break; 19051 case V4HImode: 19052 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt)); 19053 break; 19054 default: 19055 gcc_unreachable (); 19056 } 19057 19058 memset (&d, 0, sizeof (d)); 19059 d.target = target; 19060 d.op0 = t1; 19061 d.op1 = t1; 19062 d.vmode = vmode; 19063 d.nelt = GET_MODE_NUNITS (vmode); 19064 d.one_vector_p = true; 19065 19066 ok = mips_expand_vec_perm_const_1 (&d); 19067 gcc_assert (ok); 19068} 19069 19070/* A subroutine of mips_expand_vec_init, replacing all of the non-constant 19071 elements of VALS with zeros, copy the constant vector to TARGET. */ 19072 19073static void 19074mips_expand_vi_constant (machine_mode vmode, unsigned nelt, 19075 rtx target, rtx vals) 19076{ 19077 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0)); 19078 unsigned i; 19079 19080 for (i = 0; i < nelt; ++i) 19081 { 19082 if (!mips_constant_elt_p (RTVEC_ELT (vec, i))) 19083 RTVEC_ELT (vec, i) = const0_rtx; 19084 } 19085 19086 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec)); 19087} 19088 19089 19090/* A subroutine of mips_expand_vec_init, expand via pinsrh. */ 19091 19092static void 19093mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var) 19094{ 19095 mips_expand_vi_constant (V4HImode, 4, target, vals); 19096 19097 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var), 19098 GEN_INT (one_var))); 19099} 19100 19101/* A subroutine of mips_expand_vec_init, expand anything via memory. */ 19102 19103static void 19104mips_expand_vi_general (machine_mode vmode, machine_mode imode, 19105 unsigned nelt, unsigned nvar, rtx target, rtx vals) 19106{ 19107 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode)); 19108 unsigned int i, isize = GET_MODE_SIZE (imode); 19109 19110 if (nvar < nelt) 19111 mips_expand_vi_constant (vmode, nelt, mem, vals); 19112 19113 for (i = 0; i < nelt; ++i) 19114 { 19115 rtx x = XVECEXP (vals, 0, i); 19116 if (!mips_constant_elt_p (x)) 19117 emit_move_insn (adjust_address (mem, imode, i * isize), x); 19118 } 19119 19120 emit_move_insn (target, mem); 19121} 19122 19123/* Expand a vector initialization. */ 19124 19125void 19126mips_expand_vector_init (rtx target, rtx vals) 19127{ 19128 machine_mode vmode = GET_MODE (target); 19129 machine_mode imode = GET_MODE_INNER (vmode); 19130 unsigned i, nelt = GET_MODE_NUNITS (vmode); 19131 unsigned nvar = 0, one_var = -1u; 19132 bool all_same = true; 19133 rtx x; 19134 19135 for (i = 0; i < nelt; ++i) 19136 { 19137 x = XVECEXP (vals, 0, i); 19138 if (!mips_constant_elt_p (x)) 19139 nvar++, one_var = i; 19140 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) 19141 all_same = false; 19142 } 19143 19144 /* Load constants from the pool, or whatever's handy. */ 19145 if (nvar == 0) 19146 { 19147 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0))); 19148 return; 19149 } 19150 19151 /* For two-part initialization, always use CONCAT. */ 19152 if (nelt == 2) 19153 { 19154 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0)); 19155 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1)); 19156 x = gen_rtx_VEC_CONCAT (vmode, op0, op1); 19157 emit_insn (gen_rtx_SET (VOIDmode, target, x)); 19158 return; 19159 } 19160 19161 /* Loongson is the only cpu with vectors with more elements. */ 19162 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS); 19163 19164 /* If all values are identical, broadcast the value. */ 19165 if (all_same) 19166 { 19167 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0)); 19168 return; 19169 } 19170 19171 /* If we've only got one non-variable V4HImode, use PINSRH. */ 19172 if (nvar == 1 && vmode == V4HImode) 19173 { 19174 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var); 19175 return; 19176 } 19177 19178 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals); 19179} 19180 19181/* Expand a vector reduction. */ 19182 19183void 19184mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx)) 19185{ 19186 machine_mode vmode = GET_MODE (in); 19187 unsigned char perm2[2]; 19188 rtx last, next, fold, x; 19189 bool ok; 19190 19191 last = in; 19192 fold = gen_reg_rtx (vmode); 19193 switch (vmode) 19194 { 19195 case V2SFmode: 19196 /* Use PUL/PLU to produce { L, H } op { H, L }. 19197 By reversing the pair order, rather than a pure interleave high, 19198 we avoid erroneous exceptional conditions that we might otherwise 19199 produce from the computation of H op H. */ 19200 perm2[0] = 1; 19201 perm2[1] = 2; 19202 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2); 19203 gcc_assert (ok); 19204 break; 19205 19206 case V2SImode: 19207 /* Use interleave to produce { H, L } op { H, H }. */ 19208 emit_insn (gen_loongson_punpckhwd (fold, last, last)); 19209 break; 19210 19211 case V4HImode: 19212 /* Perform the first reduction with interleave, 19213 and subsequent reductions with shifts. */ 19214 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last)); 19215 19216 next = gen_reg_rtx (vmode); 19217 emit_insn (gen (next, last, fold)); 19218 last = next; 19219 19220 fold = gen_reg_rtx (vmode); 19221 x = force_reg (SImode, GEN_INT (16)); 19222 emit_insn (gen_vec_shr_v4hi (fold, last, x)); 19223 break; 19224 19225 case V8QImode: 19226 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last)); 19227 19228 next = gen_reg_rtx (vmode); 19229 emit_insn (gen (next, last, fold)); 19230 last = next; 19231 19232 fold = gen_reg_rtx (vmode); 19233 x = force_reg (SImode, GEN_INT (16)); 19234 emit_insn (gen_vec_shr_v8qi (fold, last, x)); 19235 19236 next = gen_reg_rtx (vmode); 19237 emit_insn (gen (next, last, fold)); 19238 last = next; 19239 19240 fold = gen_reg_rtx (vmode); 19241 x = force_reg (SImode, GEN_INT (8)); 19242 emit_insn (gen_vec_shr_v8qi (fold, last, x)); 19243 break; 19244 19245 default: 19246 gcc_unreachable (); 19247 } 19248 19249 emit_insn (gen (target, last, fold)); 19250} 19251 19252/* Expand a vector minimum/maximum. */ 19253 19254void 19255mips_expand_vec_minmax (rtx target, rtx op0, rtx op1, 19256 rtx (*cmp) (rtx, rtx, rtx), bool min_p) 19257{ 19258 machine_mode vmode = GET_MODE (target); 19259 rtx tc, t0, t1, x; 19260 19261 tc = gen_reg_rtx (vmode); 19262 t0 = gen_reg_rtx (vmode); 19263 t1 = gen_reg_rtx (vmode); 19264 19265 /* op0 > op1 */ 19266 emit_insn (cmp (tc, op0, op1)); 19267 19268 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0)); 19269 emit_insn (gen_rtx_SET (VOIDmode, t0, x)); 19270 19271 x = gen_rtx_NOT (vmode, tc); 19272 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1)); 19273 emit_insn (gen_rtx_SET (VOIDmode, t1, x)); 19274 19275 x = gen_rtx_IOR (vmode, t0, t1); 19276 emit_insn (gen_rtx_SET (VOIDmode, target, x)); 19277} 19278 19279/* Implement HARD_REGNO_CALLER_SAVE_MODE. */ 19280 19281machine_mode 19282mips_hard_regno_caller_save_mode (unsigned int regno, 19283 unsigned int nregs, 19284 machine_mode mode) 19285{ 19286 /* For performance, avoid saving/restoring upper parts of a register 19287 by returning MODE as save mode when the mode is known. */ 19288 if (mode == VOIDmode) 19289 return choose_hard_reg_mode (regno, nregs, false); 19290 else 19291 return mode; 19292} 19293 19294/* Implement TARGET_CASE_VALUES_THRESHOLD. */ 19295 19296unsigned int 19297mips_case_values_threshold (void) 19298{ 19299 /* In MIPS16 mode using a larger case threshold generates smaller code. */ 19300 if (TARGET_MIPS16 && optimize_size) 19301 return 10; 19302 else 19303 return default_case_values_threshold (); 19304} 19305 19306/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */ 19307 19308static void 19309mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) 19310{ 19311 if (!TARGET_HARD_FLOAT_ABI) 19312 return; 19313 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI); 19314 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI); 19315 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI); 19316 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR]; 19317 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR]; 19318 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0); 19319 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI, 19320 fcsr_orig_var, get_fcsr_hold_call); 19321 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var, 19322 build_int_cst (MIPS_ATYPE_USI, 0xfffff003)); 19323 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI, 19324 fcsr_mod_var, hold_mod_val); 19325 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var); 19326 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI, 19327 hold_assign_orig, hold_assign_mod); 19328 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all, 19329 set_fcsr_hold_call); 19330 19331 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var); 19332 19333 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0); 19334 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI, 19335 exceptions_var, get_fcsr_update_call); 19336 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var); 19337 *update = build2 (COMPOUND_EXPR, void_type_node, *update, 19338 set_fcsr_update_call); 19339 tree atomic_feraiseexcept 19340 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); 19341 tree int_exceptions_var = fold_convert (integer_type_node, 19342 exceptions_var); 19343 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept, 19344 1, int_exceptions_var); 19345 *update = build2 (COMPOUND_EXPR, void_type_node, *update, 19346 atomic_feraiseexcept_call); 19347} 19348 19349/* Implement TARGET_SPILL_CLASS. */ 19350 19351static reg_class_t 19352mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED, 19353 machine_mode mode ATTRIBUTE_UNUSED) 19354{ 19355 if (TARGET_MIPS16) 19356 return SPILL_REGS; 19357 return NO_REGS; 19358} 19359 19360/* Implement TARGET_LRA_P. */ 19361 19362static bool 19363mips_lra_p (void) 19364{ 19365 return mips_lra_flag; 19366} 19367 19368/* Initialize the GCC target structure. */ 19369#undef TARGET_ASM_ALIGNED_HI_OP 19370#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 19371#undef TARGET_ASM_ALIGNED_SI_OP 19372#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 19373#undef TARGET_ASM_ALIGNED_DI_OP 19374#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" 19375 19376#undef TARGET_OPTION_OVERRIDE 19377#define TARGET_OPTION_OVERRIDE mips_option_override 19378 19379#undef TARGET_LEGITIMIZE_ADDRESS 19380#define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address 19381 19382#undef TARGET_ASM_FUNCTION_PROLOGUE 19383#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue 19384#undef TARGET_ASM_FUNCTION_EPILOGUE 19385#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue 19386#undef TARGET_ASM_SELECT_RTX_SECTION 19387#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section 19388#undef TARGET_ASM_FUNCTION_RODATA_SECTION 19389#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section 19390 19391#undef TARGET_SCHED_INIT 19392#define TARGET_SCHED_INIT mips_sched_init 19393#undef TARGET_SCHED_REORDER 19394#define TARGET_SCHED_REORDER mips_sched_reorder 19395#undef TARGET_SCHED_REORDER2 19396#define TARGET_SCHED_REORDER2 mips_sched_reorder2 19397#undef TARGET_SCHED_VARIABLE_ISSUE 19398#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue 19399#undef TARGET_SCHED_ADJUST_COST 19400#define TARGET_SCHED_ADJUST_COST mips_adjust_cost 19401#undef TARGET_SCHED_ISSUE_RATE 19402#define TARGET_SCHED_ISSUE_RATE mips_issue_rate 19403#undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN 19404#define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn 19405#undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE 19406#define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle 19407#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 19408#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ 19409 mips_multipass_dfa_lookahead 19410#undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P 19411#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 19412 mips_small_register_classes_for_mode_p 19413 19414#undef TARGET_FUNCTION_OK_FOR_SIBCALL 19415#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall 19416 19417#undef TARGET_INSERT_ATTRIBUTES 19418#define TARGET_INSERT_ATTRIBUTES mips_insert_attributes 19419#undef TARGET_MERGE_DECL_ATTRIBUTES 19420#define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes 19421#undef TARGET_CAN_INLINE_P 19422#define TARGET_CAN_INLINE_P mips_can_inline_p 19423#undef TARGET_SET_CURRENT_FUNCTION 19424#define TARGET_SET_CURRENT_FUNCTION mips_set_current_function 19425 19426#undef TARGET_VALID_POINTER_MODE 19427#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode 19428#undef TARGET_REGISTER_MOVE_COST 19429#define TARGET_REGISTER_MOVE_COST mips_register_move_cost 19430#undef TARGET_REGISTER_PRIORITY 19431#define TARGET_REGISTER_PRIORITY mips_register_priority 19432#undef TARGET_MEMORY_MOVE_COST 19433#define TARGET_MEMORY_MOVE_COST mips_memory_move_cost 19434#undef TARGET_RTX_COSTS 19435#define TARGET_RTX_COSTS mips_rtx_costs 19436#undef TARGET_ADDRESS_COST 19437#define TARGET_ADDRESS_COST mips_address_cost 19438 19439#undef TARGET_IN_SMALL_DATA_P 19440#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p 19441 19442#undef TARGET_MACHINE_DEPENDENT_REORG 19443#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg 19444 19445#undef TARGET_PREFERRED_RELOAD_CLASS 19446#define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class 19447 19448#undef TARGET_EXPAND_TO_RTL_HOOK 19449#define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook 19450#undef TARGET_ASM_FILE_START 19451#define TARGET_ASM_FILE_START mips_file_start 19452#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 19453#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 19454#undef TARGET_ASM_CODE_END 19455#define TARGET_ASM_CODE_END mips_code_end 19456 19457#undef TARGET_INIT_LIBFUNCS 19458#define TARGET_INIT_LIBFUNCS mips_init_libfuncs 19459 19460#undef TARGET_BUILD_BUILTIN_VA_LIST 19461#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list 19462#undef TARGET_EXPAND_BUILTIN_VA_START 19463#define TARGET_EXPAND_BUILTIN_VA_START mips_va_start 19464#undef TARGET_GIMPLIFY_VA_ARG_EXPR 19465#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr 19466 19467#undef TARGET_PROMOTE_FUNCTION_MODE 19468#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote 19469#undef TARGET_PROMOTE_PROTOTYPES 19470#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true 19471 19472#undef TARGET_FUNCTION_VALUE 19473#define TARGET_FUNCTION_VALUE mips_function_value 19474#undef TARGET_LIBCALL_VALUE 19475#define TARGET_LIBCALL_VALUE mips_libcall_value 19476#undef TARGET_FUNCTION_VALUE_REGNO_P 19477#define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p 19478#undef TARGET_RETURN_IN_MEMORY 19479#define TARGET_RETURN_IN_MEMORY mips_return_in_memory 19480#undef TARGET_RETURN_IN_MSB 19481#define TARGET_RETURN_IN_MSB mips_return_in_msb 19482 19483#undef TARGET_ASM_OUTPUT_MI_THUNK 19484#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk 19485#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 19486#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true 19487 19488#undef TARGET_PRINT_OPERAND 19489#define TARGET_PRINT_OPERAND mips_print_operand 19490#undef TARGET_PRINT_OPERAND_ADDRESS 19491#define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address 19492#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 19493#define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p 19494 19495#undef TARGET_SETUP_INCOMING_VARARGS 19496#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs 19497#undef TARGET_STRICT_ARGUMENT_NAMING 19498#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming 19499#undef TARGET_MUST_PASS_IN_STACK 19500#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 19501#undef TARGET_PASS_BY_REFERENCE 19502#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference 19503#undef TARGET_CALLEE_COPIES 19504#define TARGET_CALLEE_COPIES mips_callee_copies 19505#undef TARGET_ARG_PARTIAL_BYTES 19506#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes 19507#undef TARGET_FUNCTION_ARG 19508#define TARGET_FUNCTION_ARG mips_function_arg 19509#undef TARGET_FUNCTION_ARG_ADVANCE 19510#define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance 19511#undef TARGET_FUNCTION_ARG_BOUNDARY 19512#define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary 19513#undef TARGET_GET_RAW_RESULT_MODE 19514#define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode 19515#undef TARGET_GET_RAW_ARG_MODE 19516#define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode 19517 19518#undef TARGET_MODE_REP_EXTENDED 19519#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended 19520 19521#undef TARGET_VECTOR_MODE_SUPPORTED_P 19522#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p 19523 19524#undef TARGET_SCALAR_MODE_SUPPORTED_P 19525#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p 19526 19527#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE 19528#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode 19529 19530#undef TARGET_INIT_BUILTINS 19531#define TARGET_INIT_BUILTINS mips_init_builtins 19532#undef TARGET_BUILTIN_DECL 19533#define TARGET_BUILTIN_DECL mips_builtin_decl 19534#undef TARGET_EXPAND_BUILTIN 19535#define TARGET_EXPAND_BUILTIN mips_expand_builtin 19536 19537#undef TARGET_HAVE_TLS 19538#define TARGET_HAVE_TLS HAVE_AS_TLS 19539 19540#undef TARGET_CANNOT_FORCE_CONST_MEM 19541#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem 19542 19543#undef TARGET_LEGITIMATE_CONSTANT_P 19544#define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p 19545 19546#undef TARGET_ENCODE_SECTION_INFO 19547#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info 19548 19549#undef TARGET_ATTRIBUTE_TABLE 19550#define TARGET_ATTRIBUTE_TABLE mips_attribute_table 19551/* All our function attributes are related to how out-of-line copies should 19552 be compiled or called. They don't in themselves prevent inlining. */ 19553#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P 19554#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true 19555 19556#undef TARGET_EXTRA_LIVE_ON_ENTRY 19557#define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry 19558 19559#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 19560#define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p 19561#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P 19562#define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p 19563 19564#undef TARGET_COMP_TYPE_ATTRIBUTES 19565#define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes 19566 19567#ifdef HAVE_AS_DTPRELWORD 19568#undef TARGET_ASM_OUTPUT_DWARF_DTPREL 19569#define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel 19570#endif 19571#undef TARGET_DWARF_REGISTER_SPAN 19572#define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span 19573#undef TARGET_DWARF_FRAME_REG_MODE 19574#define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode 19575 19576#undef TARGET_ASM_FINAL_POSTSCAN_INSN 19577#define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn 19578 19579#undef TARGET_LEGITIMATE_ADDRESS_P 19580#define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p 19581 19582#undef TARGET_FRAME_POINTER_REQUIRED 19583#define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required 19584 19585#undef TARGET_CAN_ELIMINATE 19586#define TARGET_CAN_ELIMINATE mips_can_eliminate 19587 19588#undef TARGET_CONDITIONAL_REGISTER_USAGE 19589#define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage 19590 19591#undef TARGET_TRAMPOLINE_INIT 19592#define TARGET_TRAMPOLINE_INIT mips_trampoline_init 19593 19594#undef TARGET_ASM_OUTPUT_SOURCE_FILENAME 19595#define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename 19596 19597#undef TARGET_SHIFT_TRUNCATION_MASK 19598#define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask 19599 19600#undef TARGET_PREPARE_PCH_SAVE 19601#define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save 19602 19603#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK 19604#define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok 19605 19606#undef TARGET_CASE_VALUES_THRESHOLD 19607#define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold 19608 19609#undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV 19610#define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv 19611 19612#undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS 19613#define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true 19614 19615#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P 19616#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ 19617 mips_use_by_pieces_infrastructure_p 19618 19619#undef TARGET_SPILL_CLASS 19620#define TARGET_SPILL_CLASS mips_spill_class 19621#undef TARGET_LRA_P 19622#define TARGET_LRA_P mips_lra_p 19623 19624struct gcc_target targetm = TARGET_INITIALIZER; 19625 19626#include "gt-mips.h" 19627