1/* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2015 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22#ifndef GCC_AARCH64_H 23#define GCC_AARCH64_H 24 25/* Target CPU builtins. */ 26#define TARGET_CPU_CPP_BUILTINS() \ 27 do \ 28 { \ 29 builtin_define ("__aarch64__"); \ 30 builtin_define ("__ARM_64BIT_STATE"); \ 31 builtin_define_with_int_value \ 32 ("__ARM_ARCH", aarch64_architecture_version); \ 33 cpp_define_formatted \ 34 (parse_in, "__ARM_ARCH_%dA", aarch64_architecture_version); \ 35 builtin_define ("__ARM_ARCH_ISA_A64"); \ 36 builtin_define_with_int_value \ 37 ("__ARM_ARCH_PROFILE", 'A'); \ 38 builtin_define ("__ARM_FEATURE_CLZ"); \ 39 builtin_define ("__ARM_FEATURE_IDIV"); \ 40 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 41 if (flag_unsafe_math_optimizations) \ 42 builtin_define ("__ARM_FP_FAST"); \ 43 builtin_define ("__ARM_PCS_AAPCS64"); \ 44 builtin_define_with_int_value \ 45 ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); \ 46 builtin_define_with_int_value \ 47 ("__ARM_SIZEOF_MINIMAL_ENUM", \ 48 flag_short_enums? 1 : 4); \ 49 if (TARGET_BIG_END) \ 50 { \ 51 builtin_define ("__AARCH64EB__"); \ 52 builtin_define ("__ARM_BIG_ENDIAN"); \ 53 } \ 54 else \ 55 builtin_define ("__AARCH64EL__"); \ 56 \ 57 if (TARGET_FLOAT) \ 58 { \ 59 builtin_define ("__ARM_FEATURE_FMA"); \ 60 builtin_define_with_int_value ("__ARM_FP", 0x0C); \ 61 } \ 62 if (TARGET_SIMD) \ 63 { \ 64 builtin_define ("__ARM_FEATURE_NUMERIC_MAXMIN"); \ 65 builtin_define ("__ARM_NEON"); \ 66 builtin_define_with_int_value ("__ARM_NEON_FP", 0x0C);\ 67 } \ 68 \ 69 if (TARGET_CRC32) \ 70 builtin_define ("__ARM_FEATURE_CRC32"); \ 71 \ 72 switch (aarch64_cmodel) \ 73 { \ 74 case AARCH64_CMODEL_TINY: \ 75 case AARCH64_CMODEL_TINY_PIC: \ 76 builtin_define ("__AARCH64_CMODEL_TINY__"); \ 77 break; \ 78 case AARCH64_CMODEL_SMALL: \ 79 case AARCH64_CMODEL_SMALL_PIC: \ 80 builtin_define ("__AARCH64_CMODEL_SMALL__");\ 81 break; \ 82 case AARCH64_CMODEL_LARGE: \ 83 builtin_define ("__AARCH64_CMODEL_LARGE__"); \ 84 break; \ 85 default: \ 86 break; \ 87 } \ 88 \ 89 if (TARGET_ILP32) \ 90 { \ 91 cpp_define (parse_in, "_ILP32"); \ 92 cpp_define (parse_in, "__ILP32__"); \ 93 } \ 94 if (TARGET_CRYPTO) \ 95 builtin_define ("__ARM_FEATURE_CRYPTO"); \ 96 } while (0) 97 98 99 100/* Target machine storage layout. */ 101 102#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 103 if (GET_MODE_CLASS (MODE) == MODE_INT \ 104 && GET_MODE_SIZE (MODE) < 4) \ 105 { \ 106 if (MODE == QImode || MODE == HImode) \ 107 { \ 108 MODE = SImode; \ 109 } \ 110 } 111 112/* Bits are always numbered from the LSBit. */ 113#define BITS_BIG_ENDIAN 0 114 115/* Big/little-endian flavour. */ 116#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 117#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 118 119/* AdvSIMD is supported in the default configuration, unless disabled by 120 -mgeneral-regs-only or by the +nosimd extension. */ 121#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 122#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 123 124#define UNITS_PER_WORD 8 125 126#define UNITS_PER_VREG 16 127 128#define PARM_BOUNDARY 64 129 130#define STACK_BOUNDARY 128 131 132#define FUNCTION_BOUNDARY 32 133 134#define EMPTY_FIELD_BOUNDARY 32 135 136#define BIGGEST_ALIGNMENT 128 137 138#define SHORT_TYPE_SIZE 16 139 140#define INT_TYPE_SIZE 32 141 142#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 143 144#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 145 146#define LONG_LONG_TYPE_SIZE 64 147 148#define FLOAT_TYPE_SIZE 32 149 150#define DOUBLE_TYPE_SIZE 64 151 152#define LONG_DOUBLE_TYPE_SIZE 128 153 154#define TARGET_SUPPORTS_WIDE_INT 1 155 156/* The architecture reserves all bits of the address for hardware use, 157 so the vbit must go into the delta field of pointers to member 158 functions. This is the same config as that in the AArch32 159 port. */ 160#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 161 162/* Make strings word-aligned so that strcpy from constants will be 163 faster. */ 164#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 165 ((TREE_CODE (EXP) == STRING_CST \ 166 && !optimize_size \ 167 && (ALIGN) < BITS_PER_WORD) \ 168 ? BITS_PER_WORD : ALIGN) 169 170#define DATA_ALIGNMENT(EXP, ALIGN) \ 171 ((((ALIGN) < BITS_PER_WORD) \ 172 && (TREE_CODE (EXP) == ARRAY_TYPE \ 173 || TREE_CODE (EXP) == UNION_TYPE \ 174 || TREE_CODE (EXP) == RECORD_TYPE)) \ 175 ? BITS_PER_WORD : (ALIGN)) 176 177#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 178 179#define STRUCTURE_SIZE_BOUNDARY 8 180 181/* Defined by the ABI */ 182#define WCHAR_TYPE "unsigned int" 183#define WCHAR_TYPE_SIZE 32 184 185/* Using long long breaks -ansi and -std=c90, so these will need to be 186 made conditional for an LLP64 ABI. */ 187 188#define SIZE_TYPE "long unsigned int" 189 190#define PTRDIFF_TYPE "long int" 191 192#define PCC_BITFIELD_TYPE_MATTERS 1 193 194/* Major revision number of the ARM Architecture implemented by the target. */ 195extern unsigned aarch64_architecture_version; 196 197/* Instruction tuning/selection flags. */ 198 199/* Bit values used to identify processor capabilities. */ 200#define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 201#define AARCH64_FL_FP (1 << 1) /* Has FP. */ 202#define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 203#define AARCH64_FL_SLOWMUL (1 << 3) /* A slow multiply core. */ 204#define AARCH64_FL_CRC (1 << 4) /* Has CRC. */ 205 206/* Has FP and SIMD. */ 207#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 208 209/* Has FP without SIMD. */ 210#define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 211 212/* Architecture flags that effect instruction selection. */ 213#define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 214 215/* Macros to test ISA flags. */ 216extern unsigned long aarch64_isa_flags; 217#define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 218#define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 219#define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 220#define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 221 222/* Macros to test tuning flags. */ 223extern unsigned long aarch64_tune_flags; 224#define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL) 225 226/* Crypto is an optional extension to AdvSIMD. */ 227#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 228 229/* CRC instructions that can be enabled through +crc arch extension. */ 230#define TARGET_CRC32 (AARCH64_ISA_CRC) 231 232/* Standard register usage. */ 233 234/* 31 64-bit general purpose registers R0-R30: 235 R30 LR (link register) 236 R29 FP (frame pointer) 237 R19-R28 Callee-saved registers 238 R18 The platform register; use as temporary register. 239 R17 IP1 The second intra-procedure-call temporary register 240 (can be used by call veneers and PLT code); otherwise use 241 as a temporary register 242 R16 IP0 The first intra-procedure-call temporary register (can 243 be used by call veneers and PLT code); otherwise use as a 244 temporary register 245 R9-R15 Temporary registers 246 R8 Structure value parameter / temporary register 247 R0-R7 Parameter/result registers 248 249 SP stack pointer, encoded as X/R31 where permitted. 250 ZR zero register, encoded as X/R31 elsewhere 251 252 32 x 128-bit floating-point/vector registers 253 V16-V31 Caller-saved (temporary) registers 254 V8-V15 Callee-saved registers 255 V0-V7 Parameter/result registers 256 257 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 258 significant bits. Unlike AArch32 S1 is not packed into D0, 259 etc. */ 260 261/* Note that we don't mark X30 as a call-clobbered register. The idea is 262 that it's really the call instructions themselves which clobber X30. 263 We don't care what the called function does with it afterwards. 264 265 This approach makes it easier to implement sibcalls. Unlike normal 266 calls, sibcalls don't clobber X30, so the register reaches the 267 called function intact. EPILOGUE_USES says that X30 is useful 268 to the called function. */ 269 270#define FIXED_REGISTERS \ 271 { \ 272 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 273 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 274 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 275 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 276 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 277 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 278 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 279 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 280 1, 1, 1, /* SFP, AP, CC */ \ 281 } 282 283#define CALL_USED_REGISTERS \ 284 { \ 285 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 286 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 287 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 288 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 289 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 290 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 291 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 292 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 293 1, 1, 1, /* SFP, AP, CC */ \ 294 } 295 296#define REGISTER_NAMES \ 297 { \ 298 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 299 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 300 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 301 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 302 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 303 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 304 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 305 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 306 "sfp", "ap", "cc", \ 307 } 308 309/* Generate the register aliases for core register N */ 310#define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 311 {"w" # N, R0_REGNUM + (N)} 312 313#define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 314 {"d" # N, V0_REGNUM + (N)}, \ 315 {"s" # N, V0_REGNUM + (N)}, \ 316 {"h" # N, V0_REGNUM + (N)}, \ 317 {"b" # N, V0_REGNUM + (N)} 318 319/* Provide aliases for all of the ISA defined register name forms. 320 These aliases are convenient for use in the clobber lists of inline 321 asm statements. */ 322 323#define ADDITIONAL_REGISTER_NAMES \ 324 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 325 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 326 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 327 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 328 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 329 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 330 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 331 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 332 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 333 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 334 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 335 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 336 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 337 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 338 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 339 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 340 } 341 342/* Say that the epilogue uses the return address register. Note that 343 in the case of sibcalls, the values "used by the epilogue" are 344 considered live at the start of the called function. */ 345 346#define EPILOGUE_USES(REGNO) \ 347 (epilogue_completed && (REGNO) == LR_REGNUM) 348 349/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 350 the stack pointer does not matter. The value is tested only in 351 functions that have frame pointers. */ 352#define EXIT_IGNORE_STACK 1 353 354#define STATIC_CHAIN_REGNUM R18_REGNUM 355#define HARD_FRAME_POINTER_REGNUM R29_REGNUM 356#define FRAME_POINTER_REGNUM SFP_REGNUM 357#define STACK_POINTER_REGNUM SP_REGNUM 358#define ARG_POINTER_REGNUM AP_REGNUM 359#define FIRST_PSEUDO_REGISTER 67 360 361/* The number of (integer) argument register available. */ 362#define NUM_ARG_REGS 8 363#define NUM_FP_ARG_REGS 8 364 365/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 366 four members. */ 367#define HA_MAX_NUM_FLDS 4 368 369/* External dwarf register number scheme. These number are used to 370 identify registers in dwarf debug information, the values are 371 defined by the AArch64 ABI. The numbering scheme is independent of 372 GCC's internal register numbering scheme. */ 373 374#define AARCH64_DWARF_R0 0 375 376/* The number of R registers, note 31! not 32. */ 377#define AARCH64_DWARF_NUMBER_R 31 378 379#define AARCH64_DWARF_SP 31 380#define AARCH64_DWARF_V0 64 381 382/* The number of V registers. */ 383#define AARCH64_DWARF_NUMBER_V 32 384 385/* For signal frames we need to use an alternative return column. This 386 value must not correspond to a hard register and must be out of the 387 range of DWARF_FRAME_REGNUM(). */ 388#define DWARF_ALT_FRAME_RETURN_COLUMN \ 389 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 390 391/* We add 1 extra frame register for use as the 392 DWARF_ALT_FRAME_RETURN_COLUMN. */ 393#define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 394 395 396#define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 397/* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 398 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 399 as the default definition in dwarf2out.c. */ 400#undef DWARF_FRAME_REGNUM 401#define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 402 403#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 404 405#define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) 406 407#define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) 408 409#define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2) 410 411#define DWARF2_UNWIND_INFO 1 412 413/* Use R0 through R3 to pass exception handling information. */ 414#define EH_RETURN_DATA_REGNO(N) \ 415 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 416 417/* Select a format to encode pointers in exception handling data. */ 418#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 419 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 420 421/* The register that holds the return address in exception handlers. */ 422#define AARCH64_EH_STACKADJ_REGNUM (R0_REGNUM + 4) 423#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM) 424 425/* Don't use __builtin_setjmp until we've defined it. */ 426#undef DONT_USE_BUILTIN_SETJMP 427#define DONT_USE_BUILTIN_SETJMP 1 428 429/* Register in which the structure value is to be returned. */ 430#define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 431 432/* Non-zero if REGNO is part of the Core register set. 433 434 The rather unusual way of expressing this check is to avoid 435 warnings when building the compiler when R0_REGNUM is 0 and REGNO 436 is unsigned. */ 437#define GP_REGNUM_P(REGNO) \ 438 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 439 440#define FP_REGNUM_P(REGNO) \ 441 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 442 443#define FP_LO_REGNUM_P(REGNO) \ 444 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 445 446 447/* Register and constant classes. */ 448 449enum reg_class 450{ 451 NO_REGS, 452 CALLER_SAVE_REGS, 453 GENERAL_REGS, 454 STACK_REG, 455 POINTER_REGS, 456 FP_LO_REGS, 457 FP_REGS, 458 ALL_REGS, 459 LIM_REG_CLASSES /* Last */ 460}; 461 462#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 463 464#define REG_CLASS_NAMES \ 465{ \ 466 "NO_REGS", \ 467 "CALLER_SAVE_REGS", \ 468 "GENERAL_REGS", \ 469 "STACK_REG", \ 470 "POINTER_REGS", \ 471 "FP_LO_REGS", \ 472 "FP_REGS", \ 473 "ALL_REGS" \ 474} 475 476#define REG_CLASS_CONTENTS \ 477{ \ 478 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 479 { 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 480 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 481 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 482 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 483 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 484 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 485 { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ 486} 487 488#define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 489 490#define INDEX_REG_CLASS GENERAL_REGS 491#define BASE_REG_CLASS POINTER_REGS 492 493/* Register pairs used to eliminate unneeded registers that point into 494 the stack frame. */ 495#define ELIMINABLE_REGS \ 496{ \ 497 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 498 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 499 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 500 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 501} 502 503#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 504 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 505 506/* CPU/ARCH option handling. */ 507#include "config/aarch64/aarch64-opts.h" 508 509enum target_cpus 510{ 511#define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS) \ 512 TARGET_CPU_##INTERNAL_IDENT, 513#include "aarch64-cores.def" 514#undef AARCH64_CORE 515 TARGET_CPU_generic 516}; 517 518/* If there is no CPU defined at configure, use generic as default. */ 519#ifndef TARGET_CPU_DEFAULT 520#define TARGET_CPU_DEFAULT \ 521 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 522#endif 523 524/* If inserting NOP before a mult-accumulate insn remember to adjust the 525 length so that conditional branching code is updated appropriately. */ 526#define ADJUST_INSN_LENGTH(insn, length) \ 527 do \ 528 { \ 529 if (aarch64_madd_needs_nop (insn)) \ 530 length += 4; \ 531 } while (0) 532 533#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 534 aarch64_final_prescan_insn (INSN); \ 535 536/* The processor for which instructions should be scheduled. */ 537extern enum aarch64_processor aarch64_tune; 538 539/* RTL generation support. */ 540#define INIT_EXPANDERS aarch64_init_expanders () 541 542 543/* Stack layout; function entry, exit and calling. */ 544#define STACK_GROWS_DOWNWARD 1 545 546#define FRAME_GROWS_DOWNWARD 1 547 548#define STARTING_FRAME_OFFSET 0 549 550#define ACCUMULATE_OUTGOING_ARGS 1 551 552#define FIRST_PARM_OFFSET(FNDECL) 0 553 554/* Fix for VFP */ 555#define LIBCALL_VALUE(MODE) \ 556 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 557 558#define DEFAULT_PCC_STRUCT_RETURN 0 559 560#define AARCH64_ROUND_UP(X, ALIGNMENT) \ 561 (((X) + ((ALIGNMENT) - 1)) & ~((ALIGNMENT) - 1)) 562 563#define AARCH64_ROUND_DOWN(X, ALIGNMENT) \ 564 ((X) & ~((ALIGNMENT) - 1)) 565 566#ifdef HOST_WIDE_INT 567struct GTY (()) aarch64_frame 568{ 569 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 570 571 /* The number of extra stack bytes taken up by register varargs. 572 This area is allocated by the callee at the very top of the 573 frame. This value is rounded up to a multiple of 574 STACK_BOUNDARY. */ 575 HOST_WIDE_INT saved_varargs_size; 576 577 HOST_WIDE_INT saved_regs_size; 578 /* Padding if needed after the all the callee save registers have 579 been saved. */ 580 HOST_WIDE_INT padding0; 581 HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ 582 583 /* Offset from the base of the frame (incomming SP) to the 584 hard_frame_pointer. This value is always a multiple of 585 STACK_BOUNDARY. */ 586 HOST_WIDE_INT hard_fp_offset; 587 588 /* The size of the frame. This value is the offset from base of the 589 * frame (incomming SP) to the stack_pointer. This value is always 590 * a multiple of STACK_BOUNDARY. */ 591 592 unsigned wb_candidate1; 593 unsigned wb_candidate2; 594 595 HOST_WIDE_INT frame_size; 596 597 bool laid_out; 598}; 599 600typedef struct GTY (()) machine_function 601{ 602 struct aarch64_frame frame; 603} machine_function; 604#endif 605 606/* Which ABI to use. */ 607enum aarch64_abi_type 608{ 609 AARCH64_ABI_LP64 = 0, 610 AARCH64_ABI_ILP32 = 1 611}; 612 613#ifndef AARCH64_ABI_DEFAULT 614#define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 615#endif 616 617#define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 618 619enum arm_pcs 620{ 621 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 622 ARM_PCS_UNKNOWN 623}; 624 625 626 627 628/* We can't use machine_mode inside a generator file because it 629 hasn't been created yet; we shouldn't be using any code that 630 needs the real definition though, so this ought to be safe. */ 631#ifdef GENERATOR_FILE 632#define MACHMODE int 633#else 634#include "insn-modes.h" 635#define MACHMODE machine_mode 636#endif 637 638#ifndef USED_FOR_TARGET 639/* AAPCS related state tracking. */ 640typedef struct 641{ 642 enum arm_pcs pcs_variant; 643 int aapcs_arg_processed; /* No need to lay out this argument again. */ 644 int aapcs_ncrn; /* Next Core register number. */ 645 int aapcs_nextncrn; /* Next next core register number. */ 646 int aapcs_nvrn; /* Next Vector register number. */ 647 int aapcs_nextnvrn; /* Next Next Vector register number. */ 648 rtx aapcs_reg; /* Register assigned to this argument. This 649 is NULL_RTX if this parameter goes on 650 the stack. */ 651 MACHMODE aapcs_vfp_rmode; 652 int aapcs_stack_words; /* If the argument is passed on the stack, this 653 is the number of words needed, after rounding 654 up. Only meaningful when 655 aapcs_reg == NULL_RTX. */ 656 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 657 stack arg area so far. */ 658} CUMULATIVE_ARGS; 659#endif 660 661#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 662 (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) 663 664#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 665 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 666 667#define PAD_VARARGS_DOWN 0 668 669#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 670 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 671 672#define FUNCTION_ARG_REGNO_P(REGNO) \ 673 aarch64_function_arg_regno_p(REGNO) 674 675 676/* ISA Features. */ 677 678/* Addressing modes, etc. */ 679#define HAVE_POST_INCREMENT 1 680#define HAVE_PRE_INCREMENT 1 681#define HAVE_POST_DECREMENT 1 682#define HAVE_PRE_DECREMENT 1 683#define HAVE_POST_MODIFY_DISP 1 684#define HAVE_PRE_MODIFY_DISP 1 685 686#define MAX_REGS_PER_ADDRESS 2 687 688#define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 689 690/* Try a machine-dependent way of reloading an illegitimate address 691 operand. If we find one, push the reload and jump to WIN. This 692 macro is used in only one place: `find_reloads_address' in reload.c. */ 693 694#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 695do { \ 696 rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ 697 IND_L); \ 698 if (new_x) \ 699 { \ 700 X = new_x; \ 701 goto WIN; \ 702 } \ 703} while (0) 704 705#define REGNO_OK_FOR_BASE_P(REGNO) \ 706 aarch64_regno_ok_for_base_p (REGNO, true) 707 708#define REGNO_OK_FOR_INDEX_P(REGNO) \ 709 aarch64_regno_ok_for_index_p (REGNO, true) 710 711#define LEGITIMATE_PIC_OPERAND_P(X) \ 712 aarch64_legitimate_pic_operand_p (X) 713 714#define CASE_VECTOR_MODE Pmode 715 716#define DEFAULT_SIGNED_CHAR 0 717 718/* An integer expression for the size in bits of the largest integer machine 719 mode that should actually be used. We allow pairs of registers. */ 720#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 721 722/* Maximum bytes moved by a single instruction (load/store pair). */ 723#define MOVE_MAX (UNITS_PER_WORD * 2) 724 725/* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 726#define AARCH64_CALL_RATIO 8 727 728/* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 729 move_by_pieces will continually copy the largest safe chunks. So a 730 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 731 for both size and speed of copy, so we will instead use the "movmem" 732 standard name to implement the copy. This logic does not apply when 733 targeting -mstrict-align, so keep a sensible default in that case. */ 734#define MOVE_RATIO(speed) \ 735 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 736 737/* For CLEAR_RATIO, when optimizing for size, give a better estimate 738 of the length of a memset call, but use the default otherwise. */ 739#define CLEAR_RATIO(speed) \ 740 ((speed) ? 15 : AARCH64_CALL_RATIO) 741 742/* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 743 optimizing for size adjust the ratio to account for the overhead of loading 744 the constant. */ 745#define SET_RATIO(speed) \ 746 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 747 748/* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 749 rarely a good idea in straight-line code since it adds an extra address 750 dependency between each instruction. Better to use incrementing offsets. */ 751#define USE_LOAD_POST_INCREMENT(MODE) 0 752#define USE_LOAD_POST_DECREMENT(MODE) 0 753#define USE_LOAD_PRE_INCREMENT(MODE) 0 754#define USE_LOAD_PRE_DECREMENT(MODE) 0 755#define USE_STORE_POST_INCREMENT(MODE) 0 756#define USE_STORE_POST_DECREMENT(MODE) 0 757#define USE_STORE_PRE_INCREMENT(MODE) 0 758#define USE_STORE_PRE_DECREMENT(MODE) 0 759 760/* ?? #define WORD_REGISTER_OPERATIONS */ 761 762/* Define if loading from memory in MODE, an integral mode narrower than 763 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 764 macro should be the code that says which one of the two operations is 765 implicitly done, or UNKNOWN if none. */ 766#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 767 768/* Define this macro to be non-zero if instructions will fail to work 769 if given data not on the nominal alignment. */ 770#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 771 772/* Define this macro to be non-zero if accessing less than a word of 773 memory is no faster than accessing a word of memory, i.e., if such 774 accesses require more than one instruction or if there is no 775 difference in cost. 776 Although there's no difference in instruction count or cycles, 777 in AArch64 we don't want to expand to a sub-word to a 64-bit access 778 if we don't have to, for power-saving reasons. */ 779#define SLOW_BYTE_ACCESS 0 780 781#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 782 783#define NO_FUNCTION_CSE 1 784 785/* Specify the machine mode that the hardware addresses have. 786 After generation of rtl, the compiler makes no further distinction 787 between pointers and any other objects of this machine mode. */ 788#define Pmode DImode 789 790/* A C expression whose value is zero if pointers that need to be extended 791 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 792 greater then zero if they are zero-extended and less then zero if the 793 ptr_extend instruction should be used. */ 794#define POINTERS_EXTEND_UNSIGNED 1 795 796/* Mode of a function address in a call instruction (for indexing purposes). */ 797#define FUNCTION_MODE Pmode 798 799#define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 800 801#define REVERSIBLE_CC_MODE(MODE) 1 802 803#define REVERSE_CONDITION(CODE, MODE) \ 804 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 805 ? reverse_condition_maybe_unordered (CODE) \ 806 : reverse_condition (CODE)) 807 808#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 809 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 810#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 811 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 812 813#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 814 815#define RETURN_ADDR_RTX aarch64_return_addr 816 817/* 3 insns + padding + 2 pointer-sized entries. */ 818#define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) 819 820/* Trampolines contain dwords, so must be dword aligned. */ 821#define TRAMPOLINE_ALIGNMENT 64 822 823/* Put trampolines in the text section so that mapping symbols work 824 correctly. */ 825#define TRAMPOLINE_SECTION text_section 826 827/* To start with. */ 828#define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2 829 830 831/* Assembly output. */ 832 833/* For now we'll make all jump tables pc-relative. */ 834#define CASE_VECTOR_PC_RELATIVE 1 835 836#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 837 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 838 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 839 : QImode) 840 841/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 842#define ADDR_VEC_ALIGN(JUMPTABLE) 0 843 844#define PRINT_OPERAND(STREAM, X, CODE) aarch64_print_operand (STREAM, X, CODE) 845 846#define PRINT_OPERAND_ADDRESS(STREAM, X) \ 847 aarch64_print_operand_address (STREAM, X) 848 849#define MCOUNT_NAME "_mcount" 850 851#define NO_PROFILE_COUNTERS 1 852 853/* Emit rtl for profiling. Output assembler code to FILE 854 to call "_mcount" for profiling a function entry. */ 855#define PROFILE_HOOK(LABEL) \ 856 { \ 857 rtx fun, lr; \ 858 lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ 859 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 860 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ 861 } 862 863/* All the work done in PROFILE_HOOK, but still required. */ 864#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 865 866/* For some reason, the Linux headers think they know how to define 867 these macros. They don't!!! */ 868#undef ASM_APP_ON 869#undef ASM_APP_OFF 870#define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 871#define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 872 873#define CONSTANT_POOL_BEFORE_FUNCTION 0 874 875/* This definition should be relocated to aarch64-elf-raw.h. This macro 876 should be undefined in aarch64-linux.h and a clear_cache pattern 877 implmented to emit either the call to __aarch64_sync_cache_range() 878 directly or preferably the appropriate sycall or cache clear 879 instructions inline. */ 880#define CLEAR_INSN_CACHE(beg, end) \ 881 extern void __aarch64_sync_cache_range (void *, void *); \ 882 __aarch64_sync_cache_range (beg, end) 883 884#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 885 aarch64_cannot_change_mode_class (FROM, TO, CLASS) 886 887#define SHIFT_COUNT_TRUNCATED !TARGET_SIMD 888 889/* Choose appropriate mode for caller saves, so we do the minimum 890 required size of load/store. */ 891#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 892 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 893 894/* Callee only saves lower 64-bits of a 128-bit register. Tell the 895 compiler the callee clobbers the top 64-bits when restoring the 896 bottom 64-bits. */ 897#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 898 (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) 899 900/* Check TLS Descriptors mechanism is selected. */ 901#define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 902 903extern enum aarch64_code_model aarch64_cmodel; 904 905/* When using the tiny addressing model conditional and unconditional branches 906 can span the whole of the available address space (1MB). */ 907#define HAS_LONG_COND_BRANCH \ 908 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 909 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 910 911#define HAS_LONG_UNCOND_BRANCH \ 912 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 913 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 914 915/* Modes valid for AdvSIMD Q registers. */ 916#define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 917 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 918 || (MODE) == V4SFmode || (MODE) == V2DImode || mode == V2DFmode) 919 920#define ENDIAN_LANE_N(mode, n) \ 921 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 922 923/* Support for a configure-time default CPU, etc. We currently support 924 --with-arch and --with-cpu. Both are ignored if either is specified 925 explicitly on the command line at run time. */ 926#define OPTION_DEFAULT_SPECS \ 927 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 928 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, 929 930#define BIG_LITTLE_SPEC \ 931 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 932 933extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 934#define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 935 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 936 937#define ASM_CPU_SPEC \ 938 BIG_LITTLE_SPEC 939 940#define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 941 942#define EXTRA_SPECS \ 943 { "asm_cpu_spec", ASM_CPU_SPEC } 944 945#endif /* GCC_AARCH64_H */ 946