1/* -*- c -*- */ 2/* Copyright (C) 2012-2017 Free Software Foundation, Inc. 3 Contributed by Red Hat. 4 Written by DJ Delorie. 5 6 This file is part of the GNU opcodes library. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#include "sysdep.h" 24#include <stdio.h> 25#include <stdlib.h> 26#include <string.h> 27#include "ansidecl.h" 28#include "opcode/rl78.h" 29 30static int trace = 0; 31 32typedef struct 33{ 34 RL78_Opcode_Decoded * rl78; 35 int (* getbyte)(void *); 36 void * ptr; 37 unsigned char * op; 38} LocalData; 39 40#define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__ 41#define OP(n,t,r,a) (rl78->op[n].type = t, \ 42 rl78->op[n].reg = r, \ 43 rl78->op[n].addend = a ) 44#define OPX(n,t,r1,r2,a) \ 45 (rl78->op[n].type = t, \ 46 rl78->op[n].reg = r1, \ 47 rl78->op[n].reg2 = r2, \ 48 rl78->op[n].addend = a ) 49 50#define W() rl78->size = RL78_Word 51 52#define AU ATTRIBUTE_UNUSED 53#define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr)) 54#define B ((unsigned long) GETBYTE()) 55 56#define SYNTAX(x) rl78->syntax = x 57 58#define UNSUPPORTED() \ 59 rl78->syntax = "*unknown*" 60 61#define RB(x) ((x)+RL78_Reg_X) 62#define RW(x) ((x)+RL78_Reg_AX) 63 64#define Fz rl78->flags = RL78_PSW_Z 65#define Fza rl78->flags = RL78_PSW_Z | RL78_PSW_AC 66#define Fzc rl78->flags = RL78_PSW_Z | RL78_PSW_CY 67#define Fzac rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY 68#define Fa rl78->flags = RL78_PSW_AC 69#define Fc rl78->flags = RL78_PSW_CY 70#define Fac rl78->flags = RL78_PSW_AC | RL78_PSW_CY 71 72#define IMMU(bytes) immediate (bytes, 0, ld) 73#define IMMS(bytes) immediate (bytes, 1, ld) 74 75static int 76immediate (int bytes, int sign_extend, LocalData * ld) 77{ 78 unsigned long i = 0; 79 80 switch (bytes) 81 { 82 case 1: 83 i |= B; 84 if (sign_extend && (i & 0x80)) 85 i -= 0x100; 86 break; 87 case 2: 88 i |= B; 89 i |= B << 8; 90 if (sign_extend && (i & 0x8000)) 91 i -= 0x10000; 92 break; 93 case 3: 94 i |= B; 95 i |= B << 8; 96 i |= B << 16; 97 if (sign_extend && (i & 0x800000)) 98 i -= 0x1000000; 99 break; 100 default: 101 fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes); 102 abort(); 103 } 104 return i; 105} 106 107#define DC(c) OP (0, RL78_Operand_Immediate, 0, c) 108#define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0) 109#define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0) 110#define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0) 111#define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a) 112#define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a) 113#define DE() rl78->op[0].use_es = 1 114#define DB(b) set_bit (rl78->op, b) 115#define DCY() DR(PSW); DB(0) 116#define DPUSH() OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0); 117 118#define SC(c) OP (1, RL78_Operand_Immediate, 0, c) 119#define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0) 120#define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0) 121#define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0) 122#define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a) 123#define SM2(r1,r2,a) OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a) 124#define SE() rl78->op[1].use_es = 1 125#define SB(b) set_bit (rl78->op+1, b) 126#define SCY() SR(PSW); SB(0) 127#define COND(c) rl78->op[1].condition = RL78_Condition_##c 128#define SPOP() OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0); 129 130static void 131set_bit (RL78_Opcode_Operand *op, int bit) 132{ 133 op->bit_number = bit; 134 switch (op->type) { 135 case RL78_Operand_Register: 136 op->type = RL78_Operand_Bit; 137 break; 138 case RL78_Operand_Indirect: 139 op->type = RL78_Operand_BitIndirect; 140 break; 141 default: 142 break; 143 } 144} 145 146static int 147saddr (int x) 148{ 149 if (x < 0x20) 150 return 0xfff00 + x; 151 return 0xffe00 + x; 152} 153 154static int 155sfr (int x) 156{ 157 return 0xfff00 + x; 158} 159 160#define SADDR saddr (IMMU (1)) 161#define SFR sfr (IMMU (1)) 162 163int 164rl78_decode_opcode (unsigned long pc AU, 165 RL78_Opcode_Decoded * rl78, 166 int (* getbyte)(void *), 167 void * ptr, 168 RL78_Dis_Isa isa) 169{ 170 LocalData lds, * ld = &lds; 171 unsigned char op_buf[20] = {0}; 172 unsigned char *op = op_buf; 173 int op0, op1; 174 175 lds.rl78 = rl78; 176 lds.getbyte = getbyte; 177 lds.ptr = ptr; 178 lds.op = op; 179 180 memset (rl78, 0, sizeof (*rl78)); 181 182 start_again: 183 184/* Byte registers, not including A. */ 185/** VARY rba 000 010 011 100 101 110 111 */ 186/* Word registers, not including AX. */ 187/** VARY ra 01 10 11 */ 188 189/*----------------------------------------------------------------------*/ 190/* ES: prefix */ 191 192/** 0001 0001 es: */ 193 DE(); SE(); 194 op ++; 195 pc ++; 196 goto start_again; 197 198/*----------------------------------------------------------------------*/ 199 200/** 0000 1111 add %0, %e!1 */ 201 ID(add); DR(A); SM(None, IMMU(2)); Fzac; 202 203/** 0000 1101 add %0, %e1 */ 204 ID(add); DR(A); SM(HL, 0); Fzac; 205 206/** 0110 0001 1000 000 add %0, %e1 */ 207 ID(add); DR(A); SM2(HL, B, 0); Fzac; 208 209/** 0000 1110 add %0, %ea1 */ 210 ID(add); DR(A); SM(HL, IMMU(1)); Fzac; 211 212/** 0110 0001 1000 0010 add %0, %e1 */ 213 ID(add); DR(A); SM2(HL, C, 0); Fzac; 214 215/** 0000 1100 add %0, #%1 */ 216 ID(add); DR(A); SC(IMMU(1)); Fzac; 217 218/** 0110 0001 0000 1rba add %0, %1 */ 219 ID(add); DR(A); SRB(rba); Fzac; 220 221/** 0000 1011 add %0, %1 */ 222 ID(add); DR(A); SM(None, SADDR); Fzac; 223 224/** 0110 0001 0000 0reg add %0, %1 */ 225 ID(add); DRB(reg); SR(A); Fzac; 226 227/** 0000 1010 add %0, #%1 */ 228 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac; 229 230/*----------------------------------------------------------------------*/ 231 232/** 0001 1111 addc %0, %e!1 */ 233 ID(addc); DR(A); SM(None, IMMU(2)); Fzac; 234 235/** 0001 1101 addc %0, %e1 */ 236 ID(addc); DR(A); SM(HL, 0); Fzac; 237 238/** 0110 0001 1001 0000 addc %0, %e1 */ 239 ID(addc); DR(A); SM2(HL, B, 0); Fzac; 240 241/** 0110 0001 1001 0010 addc %0, %e1 */ 242 ID(addc); DR(A); SM2(HL, C, 0); Fzac; 243 244/** 0001 1110 addc %0, %ea1 */ 245 ID(addc); DR(A); SM(HL, IMMU(1)); Fzac; 246 247/** 0001 1100 addc %0, #%1 */ 248 ID(addc); DR(A); SC(IMMU(1)); Fzac; 249 250/** 0110 0001 0001 1rba addc %0, %1 */ 251 ID(addc); DR(A); SRB(rba); Fzac; 252 253/** 0110 0001 0001 0reg addc %0, %1 */ 254 ID(addc); DRB(reg); SR(A); Fzac; 255 256/** 0001 1011 addc %0, %1 */ 257 ID(addc); DR(A); SM(None, SADDR); Fzac; 258 259/** 0001 1010 addc %0, #%1 */ 260 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac; 261 262/*----------------------------------------------------------------------*/ 263 264/** 0000 0010 addw %0, %e!1 */ 265 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac; 266 267/** 0110 0001 0000 1001 addw %0, %ea1 */ 268 ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac; 269 270/** 0000 0100 addw %0, #%1 */ 271 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; 272 273/** 0000 0rw1 addw %0, %1 */ 274 ID(add); W(); DR(AX); SRW(rw); Fzac; 275 276/** 0000 0110 addw %0, %1 */ 277 ID(add); W(); DR(AX); SM(None, SADDR); Fzac; 278 279/** 0001 0000 addw %0, #%1 */ 280 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac; 281 282/*----------------------------------------------------------------------*/ 283 284/** 0101 1111 and %0, %e!1 */ 285 ID(and); DR(A); SM(None, IMMU(2)); Fz; 286 287/** 0101 1101 and %0, %e1 */ 288 ID(and); DR(A); SM(HL, 0); Fz; 289 290/** 0110 0001 1101 0000 and %0, %e1 */ 291 ID(and); DR(A); SM2(HL, B, 0); Fz; 292 293/** 0101 1110 and %0, %ea1 */ 294 ID(and); DR(A); SM(HL, IMMU(1)); Fz; 295 296/** 0110 0001 1101 0010 and %0, %e1 */ 297 ID(and); DR(A); SM2(HL, C, 0); Fz; 298 299/** 0101 1100 and %0, #%1 */ 300 ID(and); DR(A); SC(IMMU(1)); Fz; 301 302/** 0110 0001 0101 1rba and %0, %1 */ 303 ID(and); DR(A); SRB(rba); Fz; 304 305/** 0110 0001 0101 0reg and %0, %1 */ 306 ID(and); DRB(reg); SR(A); Fz; 307 308/** 0101 1011 and %0, %1 */ 309 ID(and); DR(A); SM(None, SADDR); Fz; 310 311/** 0101 1010 and %0, #%1 */ 312 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz; 313 314/*----------------------------------------------------------------------*/ 315 316/** 0111 0001 1bit 0101 and1 cy, %e1 */ 317 ID(and); DCY(); SM(HL, 0); SB(bit); 318 319/** 0111 0001 1bit 1101 and1 cy, %1 */ 320 ID(and); DCY(); SR(A); SB(bit); 321 322/** 0111 0001 0bit 1101 and1 cy, %s1 */ 323 ID(and); DCY(); SM(None, SFR); SB(bit); 324 325/** 0111 0001 0bit 0101 and1 cy, %s1 */ 326 ID(and); DCY(); SM(None, SADDR); SB(bit); 327 328/*----------------------------------------------------------------------*/ 329 330/* Note that the branch insns need to be listed before the shift 331 ones, as "shift count of zero" means "branch insn" */ 332 333/** 1101 1100 bc $%a0 */ 334 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C); 335 336/** 1101 1110 bnc $%a0 */ 337 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC); 338 339/** 0110 0001 1100 0011 bh $%a0 */ 340 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H); 341 342/** 0110 0001 1101 0011 bnh $%a0 */ 343 ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH); 344 345/** 1101 1101 bz $%a0 */ 346 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z); 347 348/** 1101 1111 bnz $%a0 */ 349 ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ); 350 351/*----------------------------------------------------------------------*/ 352 353/** 0011 0001 1bit 0101 bf %e1, $%a0 */ 354 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F); 355 356/** 0011 0001 0bit 0101 bf %1, $%a0 */ 357 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F); 358 359/** 0011 0001 1bit 0100 bf %s1, $%a0 */ 360 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F); 361 362/** 0011 0001 0bit 0100 bf %s1, $%a0 */ 363 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F); 364 365/*----------------------------------------------------------------------*/ 366 367/** 1110 1100 br !%!a0 */ 368 ID(branch); DC(IMMU(3)); 369 370/** 1110 1101 br %!a0 */ 371 ID(branch); DC(IMMU(2)); 372 373/** 1110 1110 br $%!a0 */ 374 ID(branch); DC(pc+IMMS(2)+3); 375 376/** 1110 1111 br $%a0 */ 377 ID(branch); DC(pc+IMMS(1)+2); 378 379/** 0110 0001 1100 1011 br ax */ 380 ID(branch); DR(AX); 381 382/*----------------------------------------------------------------------*/ 383 384/** 1111 1111 brk1 */ 385 ID(break); 386 387/** 0110 0001 1100 1100 brk */ 388 ID(break); 389 390/*----------------------------------------------------------------------*/ 391 392/** 0011 0001 1bit 0011 bt %e1, $%a0 */ 393 ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); 394 395/** 0011 0001 0bit 0011 bt %1, $%a0 */ 396 ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); 397 398/** 0011 0001 1bit 0010 bt %s1, $%a0 */ 399 ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); 400 401/** 0011 0001 0bit 0010 bt %s1, $%a0 */ 402 ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); 403 404/*----------------------------------------------------------------------*/ 405 406/** 0011 0001 1bit 0001 btclr %e1, $%a0 */ 407 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T); 408 409/** 0011 0001 0bit 0001 btclr %1, $%a0 */ 410 ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T); 411 412/** 0011 0001 1bit 0000 btclr %s1, $%a0 */ 413 ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T); 414 415/** 0011 0001 0bit 0000 btclr %s1, $%a0 */ 416 ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T); 417 418/*----------------------------------------------------------------------*/ 419 420/** 1111 1100 call !%!a0 */ 421 ID(call); DC(IMMU(3)); 422 423/** 1111 1101 call %!a0 */ 424 ID(call); DC(IMMU(2)); 425 426/** 1111 1110 call $%!a0 */ 427 ID(call); DC(pc+IMMS(2)+3); 428 429/** 0110 0001 11rg 1010 call %0 */ 430 ID(call); DRW(rg); 431 432/** 0110 0001 1nnn 01mm callt [%x0] */ 433 ID(call); DM(None, 0x80 + mm*16 + nnn*2); 434 435/*----------------------------------------------------------------------*/ 436 437/** 0111 0001 0bit 1000 clr1 %e!0 */ 438 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0); 439 440/** 0111 0001 1bit 0011 clr1 %e0 */ 441 ID(mov); DM(HL, 0); DB(bit); SC(0); 442 443/** 0111 0001 1bit 1011 clr1 %0 */ 444 ID(mov); DR(A); DB(bit); SC(0); 445 446/** 0111 0001 1000 1000 clr1 cy */ 447 ID(mov); DCY(); SC(0); 448 449/** 0111 0001 0bit 1011 clr1 %s0 */ 450 op0 = SFR; 451 ID(mov); DM(None, op0); DB(bit); SC(0); 452 if (op0 == RL78_SFR_PSW && bit == 7) 453 rl78->syntax = "di"; 454 455/** 0111 0001 0bit 0011 clr1 %0 */ 456 ID(mov); DM(None, SADDR); DB(bit); SC(0); 457 458/*----------------------------------------------------------------------*/ 459 460/** 1111 0101 clrb %e!0 */ 461 ID(mov); DM(None, IMMU(2)); SC(0); 462 463/** 1111 00rg clrb %0 */ 464 ID(mov); DRB(rg); SC(0); 465 466/** 1111 0100 clrb %0 */ 467 ID(mov); DM(None, SADDR); SC(0); 468 469/*----------------------------------------------------------------------*/ 470 471/** 1111 0110 clrw %0 */ 472 ID(mov); DR(AX); SC(0); 473 474/** 1111 0111 clrw %0 */ 475 ID(mov); DR(BC); SC(0); 476 477/*----------------------------------------------------------------------*/ 478 479/** 0100 0000 cmp %e!0, #%1 */ 480 ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac; 481 482/** 0100 1010 cmp %0, #%1 */ 483 ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac; 484 485/** 0100 1111 cmp %0, %e!1 */ 486 ID(cmp); DR(A); SM(None, IMMU(2)); Fzac; 487 488/** 0100 1101 cmp %0, %e1 */ 489 ID(cmp); DR(A); SM(HL, 0); Fzac; 490 491/** 0110 0001 1100 0000 cmp %0, %e1 */ 492 ID(cmp); DR(A); SM2(HL, B, 0); Fzac; 493 494/** 0110 0001 1100 0010 cmp %0, %e1 */ 495 ID(cmp); DR(A); SM2(HL, C, 0); Fzac; 496 497/** 0100 1110 cmp %0, %ea1 */ 498 ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac; 499 500/** 0100 1100 cmp %0, #%1 */ 501 ID(cmp); DR(A); SC(IMMU(1)); Fzac; 502 503/** 0110 0001 0100 1rba cmp %0, %1 */ 504 ID(cmp); DR(A); SRB(rba); Fzac; 505 506/** 0110 0001 0100 0reg cmp %0, %1 */ 507 ID(cmp); DRB(reg); SR(A); Fzac; 508 509/** 0100 1011 cmp %0, %1 */ 510 ID(cmp); DR(A); SM(None, SADDR); Fzac; 511 512/*----------------------------------------------------------------------*/ 513 514/** 1101 0101 cmp0 %e!0 */ 515 ID(cmp); DM(None, IMMU(2)); SC(0); Fzac; 516 517/** 1101 00rg cmp0 %0 */ 518 ID(cmp); DRB(rg); SC(0); Fzac; 519 520/** 1101 0100 cmp0 %0 */ 521 ID(cmp); DM(None, SADDR); SC(0); Fzac; 522 523/*----------------------------------------------------------------------*/ 524 525/** 0110 0001 1101 1110 cmps %0, %ea1 */ 526 ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac; 527 528/*----------------------------------------------------------------------*/ 529 530/** 0100 0010 cmpw %0, %e!1 */ 531 ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac; 532 533/** 0110 0001 0100 1001 cmpw %0, %ea1 */ 534 ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac; 535 536/** 0100 0100 cmpw %0, #%1 */ 537 ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac; 538 539/** 0100 0ra1 cmpw %0, %1 */ 540 ID(cmp); W(); DR(AX); SRW(ra); Fzac; 541 542/** 0100 0110 cmpw %0, %1 */ 543 ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac; 544 545/*----------------------------------------------------------------------*/ 546 547/** 1011 0000 dec %e!0 */ 548 ID(sub); DM(None, IMMU(2)); SC(1); Fza; 549 550/** 0110 0001 0110 1001 dec %ea0 */ 551 ID(sub); DM(HL, IMMU(1)); SC(1); Fza; 552 553/** 1001 0reg dec %0 */ 554 ID(sub); DRB(reg); SC(1); Fza; 555 556/** 1011 0100 dec %0 */ 557 ID(sub); DM(None, SADDR); SC(1); Fza; 558 559/*----------------------------------------------------------------------*/ 560 561/** 1011 0010 decw %e!0 */ 562 ID(sub); W(); DM(None, IMMU(2)); SC(1); 563 564/** 0110 0001 1000 1001 decw %ea0 */ 565 ID(sub); W(); DM(HL, IMMU(1)); SC(1); 566 567/** 1011 0rg1 decw %0 */ 568 ID(sub); W(); DRW(rg); SC(1); 569 570/** 1011 0110 decw %0 */ 571 ID(sub); W(); DM(None, SADDR); SC(1); 572 573/*----------------------------------------------------------------------*/ 574 575/** 0110 0001 1110 1101 halt */ 576 ID(halt); 577 578/*----------------------------------------------------------------------*/ 579 580/** 1010 0000 inc %e!0 */ 581 ID(add); DM(None, IMMU(2)); SC(1); Fza; 582 583/** 0110 0001 0101 1001 inc %ea0 */ 584 ID(add); DM(HL, IMMU(1)); SC(1); Fza; 585 586/** 1000 0reg inc %0 */ 587 ID(add); DRB(reg); SC(1); Fza; 588 589/** 1010 0100 inc %0 */ 590 ID(add); DM(None, SADDR); SC(1); Fza; 591 592/*----------------------------------------------------------------------*/ 593 594/** 1010 0010 incw %e!0 */ 595 ID(add); W(); DM(None, IMMU(2)); SC(1); 596 597/** 0110 0001 0111 1001 incw %ea0 */ 598 ID(add); W(); DM(HL, IMMU(1)); SC(1); 599 600/** 1010 0rg1 incw %0 */ 601 ID(add); W(); DRW(rg); SC(1); 602 603/** 1010 0110 incw %0 */ 604 ID(add); W(); DM(None, SADDR); SC(1); 605 606/*----------------------------------------------------------------------*/ 607 608/** 1100 1111 mov %e!0, #%1 */ 609 ID(mov); DM(None, IMMU(2)); SC(IMMU(1)); 610 611/** 1001 1111 mov %e!0, %1 */ 612 ID(mov); DM(None, IMMU(2)); SR(A); 613 614/** 1001 1001 mov %e0, %1 */ 615 ID(mov); DM(DE, 0); SR(A); 616 617/** 1100 1010 mov %ea0, #%1 */ 618 ID(mov); DM(DE, IMMU(1)); SC(IMMU(1)); 619 620/** 1001 1010 mov %ea0, %1 */ 621 ID(mov); DM(DE, IMMU(1)); SR(A); 622 623/** 1001 1011 mov %e0, %1 */ 624 ID(mov); DM(HL, 0); SR(A); 625 626/** 0110 0001 1101 1001 mov %e0, %1 */ 627 ID(mov); DM2(HL, B, 0); SR(A); 628 629/** 1100 1100 mov %ea0, #%1 */ 630 ID(mov); DM(HL, IMMU(1)); SC(IMMU(1)); 631 632/** 1001 1100 mov %ea0, %1 */ 633 ID(mov); DM(HL, IMMU(1)); SR(A); 634 635/** 0110 0001 1111 1001 mov %e0, %1 */ 636 ID(mov); DM2(HL, C, 0); SR(A); 637 638/** 1100 1000 mov %a0, #%1 */ 639 ID(mov); DM(SP, IMMU(1)); SC(IMMU(1)); 640 641/** 1001 1000 mov %a0, %1 */ 642 ID(mov); DM(SP, IMMU(1)); SR(A); 643 644/** 1000 1111 mov %0, %e!1 */ 645 ID(mov); DR(A); SM(None, IMMU(2)); 646 647/** 1000 1001 mov %0, %e1 */ 648 ID(mov); DR(A); SM(DE, 0); 649 650/** 1000 1010 mov %0, %ea1 */ 651 ID(mov); DR(A); SM(DE, IMMU(1)); 652 653/** 1000 1011 mov %0, %e1 */ 654 ID(mov); DR(A); SM(HL, 0); 655 656/** 1000 1100 mov %0, %ea1 */ 657 ID(mov); DR(A); SM(HL, IMMU(1)); 658 659/** 0110 0001 1100 1001 mov %0, %e1 */ 660 ID(mov); DR(A); SM2(HL, B, 0); 661 662/** 0110 0001 1110 1001 mov %0, %e1 */ 663 ID(mov); DR(A); SM2(HL, C, 0); 664 665/** 1000 1000 mov %0, %ea1 */ 666 ID(mov); DR(A); SM(SP, IMMU(1)); 667 668/** 0101 0reg mov %0, #%1 */ 669 ID(mov); DRB(reg); SC(IMMU(1)); 670 671/** 0110 0rba mov %0, %1 */ 672 ID(mov); DR(A); SRB(rba); 673 674/** 1000 1110 1111 1101 mov %0, %1 */ 675 ID(mov); DR(A); SR(ES); 676 677/** 0000 1001 mov %0, %e1 */ 678 ID(mov); DR(A); SM(B, IMMU(2)); 679 680/** 0100 1001 mov %0, %e1 */ 681 ID(mov); DR(A); SM(BC, IMMU(2)); 682 683/** 0010 1001 mov %0, %e1 */ 684 ID(mov); DR(A); SM(C, IMMU(2)); 685 686/** 1000 1110 mov %0, %s1 */ 687 ID(mov); DR(A); SM(None, SFR); 688 689/** 1000 1101 mov %0, %1 */ 690 ID(mov); DR(A); SM(None, SADDR); 691 692/** 1110 1001 mov %0, %e!1 */ 693 ID(mov); DR(B); SM(None, IMMU(2)); 694 695/** 0111 0rba mov %0, %1 */ 696 ID(mov); DRB(rba); SR(A); 697 698/** 1110 1000 mov %0, %1 */ 699 ID(mov); DR(B); SM(None, SADDR); 700 701/** 1111 1001 mov %0, %e!1 */ 702 ID(mov); DR(C); SM(None, IMMU(2)); 703 704/** 1111 1000 mov %0, %1 */ 705 ID(mov); DR(C); SM(None, SADDR); 706 707/** 1101 1001 mov %0, %e!1 */ 708 ID(mov); DR(X); SM(None, IMMU(2)); 709 710/** 1101 1000 mov %0, %1 */ 711 ID(mov); DR(X); SM(None, SADDR); 712 713/** 1001 1110 1111 1100 mov %0, %1 */ 714 ID(mov); DR(CS); SR(A); 715 716/** 0100 0001 mov %0, #%1 */ 717 ID(mov); DR(ES); SC(IMMU(1)); 718 719/** 1001 1110 1111 1101 mov %0, %1 */ 720 ID(mov); DR(ES); SR(A); 721 722/** 0110 0001 1011 1000 mov %0, %1 */ 723 ID(mov); DR(ES); SM(None, SADDR); 724 725/** 0001 1001 mov %e0, #%1 */ 726 ID(mov); DM(B, IMMU(2)); SC(IMMU(1)); 727 728/** 0001 1000 mov %e0, %1 */ 729 ID(mov); DM(B, IMMU(2)); SR(A); 730 731/** 0011 1001 mov %e0, #%1 */ 732 ID(mov); DM(BC, IMMU(2)); SC(IMMU(1)); 733 734/** 0100 1000 mov %e0, %1 */ 735 ID(mov); DM(BC, IMMU(2)); SR(A); 736 737/** 0011 1000 mov %e0, #%1 */ 738 ID(mov); DM(C, IMMU(2)); SC(IMMU(1)); 739 740/** 0010 1000 mov %e0, %1 */ 741 ID(mov); DM(C, IMMU(2)); SR(A); 742 743/** 1100 1101 mov %0, #%1 */ 744 ID(mov); DM(None, SADDR); SC(IMMU(1)); 745 746/** 1001 1101 mov %0, %1 */ 747 ID(mov); DM(None, SADDR); SR(A); 748 749/** 1100 1110 mov %s0, #%1 */ 750 op0 = SFR; 751 op1 = IMMU(1); 752 ID(mov); DM(None, op0); SC(op1); 753 if (op0 == 0xffffb && isa == RL78_ISA_G14) 754 switch (op1) 755 { 756 case 0x01: 757 rl78->syntax = "mulhu"; ID(mulhu); 758 break; 759 case 0x02: 760 rl78->syntax = "mulh"; ID(mulh); 761 break; 762 case 0x03: 763 rl78->syntax = "divhu"; ID(divhu); 764 break; 765 case 0x04: 766 rl78->syntax = "divwu <old-encoding>"; ID(divwu); 767 break; 768 case 0x05: 769 rl78->syntax = "machu"; ID(machu); 770 break; 771 case 0x06: 772 rl78->syntax = "mach"; ID(mach); 773 break; 774 case 0x0b: 775 rl78->syntax = "divwu"; ID(divwu); 776 break; 777 } 778 779/** 1001 1110 mov %s0, %1 */ 780 ID(mov); DM(None, SFR); SR(A); 781 782/*----------------------------------------------------------------------*/ 783 784/** 0111 0001 1bit 0001 mov1 %e0, cy */ 785 ID(mov); DM(HL, 0); DB(bit); SCY(); 786 787/** 0111 0001 1bit 1001 mov1 %e0, cy */ 788 ID(mov); DR(A); DB(bit); SCY(); 789 790/** 0111 0001 1bit 0100 mov1 cy, %e1 */ 791 ID(mov); DCY(); SM(HL, 0); SB(bit); 792 793/** 0111 0001 1bit 1100 mov1 cy, %e1 */ 794 ID(mov); DCY(); SR(A); SB(bit); 795 796/** 0111 0001 0bit 0100 mov1 cy, %1 */ 797 ID(mov); DCY(); SM(None, SADDR); SB(bit); 798 799/** 0111 0001 0bit 1100 mov1 cy, %s1 */ 800 ID(mov); DCY(); SM(None, SFR); SB(bit); 801 802/** 0111 0001 0bit 0001 mov1 %0, cy */ 803 ID(mov); DM(None, SADDR); DB(bit); SCY(); 804 805/** 0111 0001 0bit 1001 mov1 %s0, cy */ 806 ID(mov); DM(None, SFR); DB(bit); SCY(); 807 808/*----------------------------------------------------------------------*/ 809 810/** 0110 0001 1100 1110 movs %ea0, %1 */ 811 ID(mov); DM(HL, IMMU(1)); SR(X); Fzc; 812 813/*----------------------------------------------------------------------*/ 814 815/** 1011 1111 movw %e!0, %1 */ 816 ID(mov); W(); DM(None, IMMU(2)); SR(AX); 817 818/** 1011 1001 movw %e0, %1 */ 819 ID(mov); W(); DM(DE, 0); SR(AX); 820 821/** 1011 1010 movw %ea0, %1 */ 822 ID(mov); W(); DM(DE, IMMU(1)); SR(AX); 823 824/** 1011 1011 movw %e0, %1 */ 825 ID(mov); W(); DM(HL, 0); SR(AX); 826 827/** 1011 1100 movw %ea0, %1 */ 828 ID(mov); W(); DM(HL, IMMU(1)); SR(AX); 829 830/** 1011 1000 movw %a0, %1 */ 831 ID(mov); W(); DM(SP, IMMU(1)); SR(AX); 832 833/** 1010 1111 movw %0, %e!1 */ 834 ID(mov); W(); DR(AX); SM(None, IMMU(2)); 835 836 837/** 1010 1001 movw %0, %e1 */ 838 ID(mov); W(); DR(AX); SM(DE, 0); 839 840/** 1010 1010 movw %0, %ea1 */ 841 ID(mov); W(); DR(AX); SM(DE, IMMU(1)); 842 843/** 1010 1011 movw %0, %e1 */ 844 ID(mov); W(); DR(AX); SM(HL, 0); 845 846/** 1010 1100 movw %0, %ea1 */ 847 ID(mov); W(); DR(AX); SM(HL, IMMU(1)); 848 849/** 1010 1000 movw %0, %a1 */ 850 ID(mov); W(); DR(AX); SM(SP, IMMU(1)); 851 852/** 0011 0rg0 movw %0, #%1 */ 853 ID(mov); W(); DRW(rg); SC(IMMU(2)); 854 855/** 0001 0ra1 movw %0, %1 */ 856 ID(mov); W(); DR(AX); SRW(ra); 857 858/** 0001 0ra0 movw %0, %1 */ 859 ID(mov); W(); DRW(ra); SR(AX); 860 861/** 0101 1001 movw %0, %e1 */ 862 ID(mov); W(); DR(AX); SM(B, IMMU(2)); 863 864/** 0110 1001 movw %0, %e1 */ 865 ID(mov); W(); DR(AX); SM(C, IMMU(2)); 866 867/** 0111 1001 movw %0, %e1 */ 868 ID(mov); W(); DR(AX); SM(BC, IMMU(2)); 869 870/** 0101 1000 movw %e0, %1 */ 871 ID(mov); W(); DM(B, IMMU(2)); SR(AX); 872 873/** 0110 1000 movw %e0, %1 */ 874 ID(mov); W(); DM(C, IMMU(2)); SR(AX); 875 876/** 0111 1000 movw %e0, %1 */ 877 ID(mov); W(); DM(BC, IMMU(2)); SR(AX); 878 879/** 1010 1101 movw %0, %1 */ 880 ID(mov); W(); DR(AX); SM(None, SADDR); 881 882/** 1010 1110 movw %0, %s1 */ 883 ID(mov); W(); DR(AX); SM(None, SFR); 884 885/** 11ra 1011 movw %0, %es!1 */ 886 ID(mov); W(); DRW(ra); SM(None, IMMU(2)); 887 888/** 11ra 1010 movw %0, %1 */ 889 ID(mov); W(); DRW(ra); SM(None, SADDR); 890 891/** 1100 1001 movw %0, #%1 */ 892 ID(mov); W(); DM(None, SADDR); SC(IMMU(2)); 893 894/** 1011 1101 movw %0, %1 */ 895 ID(mov); W(); DM(None, SADDR); SR(AX); 896 897/** 1100 1011 movw %s0, #%1 */ 898 ID(mov); W(); DM(None, SFR); SC(IMMU(2)); 899 900/** 1011 1110 movw %s0, %1 */ 901 ID(mov); W(); DM(None, SFR); SR(AX); 902 903/*----------------------------------------------------------------------*/ 904 905/** 1101 0110 mulu x */ 906 ID(mulu); 907 908/*----------------------------------------------------------------------*/ 909 910/** 0000 0000 nop */ 911 ID(nop); 912 913/*----------------------------------------------------------------------*/ 914 915/** 0111 0001 1100 0000 not1 cy */ 916 ID(xor); DCY(); SC(1); 917 918/*----------------------------------------------------------------------*/ 919 920/** 1110 0101 oneb %e!0 */ 921 ID(mov); DM(None, IMMU(2)); SC(1); 922 923/** 1110 00rg oneb %0 */ 924 ID(mov); DRB(rg); SC(1); 925 926/** 1110 0100 oneb %0 */ 927 ID(mov); DM(None, SADDR); SC(1); 928 929/*----------------------------------------------------------------------*/ 930 931/** 1110 0110 onew %0 */ 932 ID(mov); DR(AX); SC(1); 933 934/** 1110 0111 onew %0 */ 935 ID(mov); DR(BC); SC(1); 936 937/*----------------------------------------------------------------------*/ 938 939/** 0110 1111 or %0, %e!1 */ 940 ID(or); DR(A); SM(None, IMMU(2)); Fz; 941 942/** 0110 1101 or %0, %e1 */ 943 ID(or); DR(A); SM(HL, 0); Fz; 944 945/** 0110 0001 1110 0000 or %0, %e1 */ 946 ID(or); DR(A); SM2(HL, B, 0); Fz; 947 948/** 0110 1110 or %0, %ea1 */ 949 ID(or); DR(A); SM(HL, IMMU(1)); Fz; 950 951/** 0110 0001 1110 0010 or %0, %e1 */ 952 ID(or); DR(A); SM2(HL, C, 0); Fz; 953 954/** 0110 1100 or %0, #%1 */ 955 ID(or); DR(A); SC(IMMU(1)); Fz; 956 957/** 0110 0001 0110 1rba or %0, %1 */ 958 ID(or); DR(A); SRB(rba); Fz; 959 960/** 0110 0001 0110 0reg or %0, %1 */ 961 ID(or); DRB(reg); SR(A); Fz; 962 963/** 0110 1011 or %0, %1 */ 964 ID(or); DR(A); SM(None, SADDR); Fz; 965 966/** 0110 1010 or %0, #%1 */ 967 ID(or); DM(None, SADDR); SC(IMMU(1)); Fz; 968 969/*----------------------------------------------------------------------*/ 970 971/** 0111 0001 1bit 0110 or1 cy, %e1 */ 972 ID(or); DCY(); SM(HL, 0); SB(bit); 973 974/** 0111 0001 1bit 1110 or1 cy, %1 */ 975 ID(or); DCY(); SR(A); SB(bit); 976 977/** 0111 0001 0bit 1110 or1 cy, %s1 */ 978 ID(or); DCY(); SM(None, SFR); SB(bit); 979 980/** 0111 0001 0bit 0110 or1 cy, %s1 */ 981 ID(or); DCY(); SM(None, SADDR); SB(bit); 982 983/*----------------------------------------------------------------------*/ 984 985/** 1100 0rg0 pop %0 */ 986 ID(mov); W(); DRW(rg); SPOP(); 987 988/** 0110 0001 1100 1101 pop %s0 */ 989 ID(mov); W(); DR(PSW); SPOP(); 990 991/*----------------------------------------------------------------------*/ 992 993/** 1100 0rg1 push %1 */ 994 ID(mov); W(); DPUSH(); SRW(rg); 995 996/** 0110 0001 1101 1101 push %s1 */ 997 ID(mov); W(); DPUSH(); SR(PSW); 998 999/*----------------------------------------------------------------------*/ 1000 1001/** 1101 0111 ret */ 1002 ID(ret); 1003 1004/** 0110 0001 1111 1100 reti */ 1005 ID(reti); 1006 1007/** 0110 0001 1110 1100 retb */ 1008 ID(reti); 1009 1010/*----------------------------------------------------------------------*/ 1011 1012/** 0110 0001 1110 1011 rol %0, %1 */ 1013 ID(rol); DR(A); SC(1); 1014 1015/** 0110 0001 1101 1100 rolc %0, %1 */ 1016 ID(rolc); DR(A); SC(1); 1017 1018/** 0110 0001 111r 1110 rolwc %0, %1 */ 1019 ID(rolc); W(); DRW(r); SC(1); 1020 1021/** 0110 0001 1101 1011 ror %0, %1 */ 1022 ID(ror); DR(A); SC(1); 1023 1024/** 0110 0001 1111 1011 rorc %0, %1 */ 1025 ID(rorc); DR(A); SC(1); 1026 1027/*----------------------------------------------------------------------*/ 1028 1029/* Note that the branch insns need to be listed before the shift 1030 ones, as "shift count of zero" means "branch insn" */ 1031 1032/** 0011 0001 0cnt 1011 sar %0, %1 */ 1033 ID(sar); DR(A); SC(cnt); 1034 1035/** 0011 0001 wcnt 1111 sarw %0, %1 */ 1036 ID(sar); W(); DR(AX); SC(wcnt); 1037 1038/*----------------------------------------------------------------------*/ 1039 1040/** 0110 0001 11rb 1111 sel rb%1 */ 1041 ID(sel); SC(rb); 1042 1043/*----------------------------------------------------------------------*/ 1044 1045/** 0111 0001 0bit 0000 set1 %e!0 */ 1046 ID(mov); DM(None, IMMU(2)); DB(bit); SC(1); 1047 1048/** 0111 0001 1bit 0010 set1 %e0 */ 1049 ID(mov); DM(HL, 0); DB(bit); SC(1); 1050 1051/** 0111 0001 1bit 1010 set1 %0 */ 1052 ID(mov); DR(A); DB(bit); SC(1); 1053 1054/** 0111 0001 1000 0000 set1 cy */ 1055 ID(mov); DCY(); SC(1); 1056 1057/** 0111 0001 0bit 1010 set1 %s0 */ 1058 op0 = SFR; 1059 ID(mov); DM(None, op0); DB(bit); SC(1); 1060 if (op0 == RL78_SFR_PSW && bit == 7) 1061 rl78->syntax = "ei"; 1062 1063/** 0111 0001 0bit 0010 set1 %0 */ 1064 ID(mov); DM(None, SADDR); DB(bit); SC(1); 1065 1066/*----------------------------------------------------------------------*/ 1067 1068/** 0011 0001 0cnt 1001 shl %0, %1 */ 1069 ID(shl); DR(A); SC(cnt); 1070 1071/** 0011 0001 0cnt 1000 shl %0, %1 */ 1072 ID(shl); DR(B); SC(cnt); 1073 1074/** 0011 0001 0cnt 0111 shl %0, %1 */ 1075 ID(shl); DR(C); SC(cnt); 1076 1077/** 0011 0001 wcnt 1101 shlw %0, %1 */ 1078 ID(shl); W(); DR(AX); SC(wcnt); 1079 1080/** 0011 0001 wcnt 1100 shlw %0, %1 */ 1081 ID(shl); W(); DR(BC); SC(wcnt); 1082 1083/*----------------------------------------------------------------------*/ 1084 1085/** 0011 0001 0cnt 1010 shr %0, %1 */ 1086 ID(shr); DR(A); SC(cnt); 1087 1088/** 0011 0001 wcnt 1110 shrw %0, %1 */ 1089 ID(shr); W(); DR(AX); SC(wcnt); 1090 1091/*----------------------------------------------------------------------*/ 1092 1093/** 0110 0001 1100 1000 sk%c1 */ 1094 ID(skip); COND(C); 1095 1096/** 0110 0001 1110 0011 sk%c1 */ 1097 ID(skip); COND(H); 1098 1099/** 0110 0001 1101 1000 sk%c1 */ 1100 ID(skip); COND(NC); 1101 1102/** 0110 0001 1111 0011 sk%c1 */ 1103 ID(skip); COND(NH); 1104 1105/** 0110 0001 1111 1000 sk%c1 */ 1106 ID(skip); COND(NZ); 1107 1108/** 0110 0001 1110 1000 sk%c1 */ 1109 ID(skip); COND(Z); 1110 1111/*----------------------------------------------------------------------*/ 1112 1113/** 0110 0001 1111 1101 stop */ 1114 ID(stop); 1115 1116/*----------------------------------------------------------------------*/ 1117 1118/** 0010 1111 sub %0, %e!1 */ 1119 ID(sub); DR(A); SM(None, IMMU(2)); Fzac; 1120 1121/** 0010 1101 sub %0, %e1 */ 1122 ID(sub); DR(A); SM(HL, 0); Fzac; 1123 1124/** 0110 0001 1010 000 sub %0, %e1 */ 1125 ID(sub); DR(A); SM2(HL, B, 0); Fzac; 1126 1127/** 0010 1110 sub %0, %ea1 */ 1128 ID(sub); DR(A); SM(HL, IMMU(1)); Fzac; 1129 1130/** 0110 0001 1010 0010 sub %0, %e1 */ 1131 ID(sub); DR(A); SM2(HL, C, 0); Fzac; 1132 1133/** 0010 1100 sub %0, #%1 */ 1134 ID(sub); DR(A); SC(IMMU(1)); Fzac; 1135 1136/** 0110 0001 0010 1rba sub %0, %1 */ 1137 ID(sub); DR(A); SRB(rba); Fzac; 1138 1139/** 0010 1011 sub %0, %1 */ 1140 ID(sub); DR(A); SM(None, SADDR); Fzac; 1141 1142/** 0110 0001 0010 0reg sub %0, %1 */ 1143 ID(sub); DRB(reg); SR(A); Fzac; 1144 1145/** 0010 1010 sub %0, #%1 */ 1146 ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac; 1147 1148/*----------------------------------------------------------------------*/ 1149 1150/** 0011 1111 subc %0, %e!1 */ 1151 ID(subc); DR(A); SM(None, IMMU(2)); Fzac; 1152 1153/** 0011 1101 subc %0, %e1 */ 1154 ID(subc); DR(A); SM(HL, 0); Fzac; 1155 1156/** 0110 0001 1011 0000 subc %0, %e1 */ 1157 ID(subc); DR(A); SM2(HL, B, 0); Fzac; 1158 1159/** 0110 0001 1011 0010 subc %0, %e1 */ 1160 ID(subc); DR(A); SM2(HL, C, 0); Fzac; 1161 1162/** 0011 1110 subc %0, %ea1 */ 1163 ID(subc); DR(A); SM(HL, IMMU(1)); Fzac; 1164 1165/** 0011 1100 subc %0, #%1 */ 1166 ID(subc); DR(A); SC(IMMU(1)); Fzac; 1167 1168/** 0110 0001 0011 1rba subc %0, %1 */ 1169 ID(subc); DR(A); SRB(rba); Fzac; 1170 1171/** 0110 0001 0011 0reg subc %0, %1 */ 1172 ID(subc); DRB(reg); SR(A); Fzac; 1173 1174/** 0011 1011 subc %0, %1 */ 1175 ID(subc); DR(A); SM(None, SADDR); Fzac; 1176 1177/** 0011 1010 subc %0, #%1 */ 1178 ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac; 1179 1180/*----------------------------------------------------------------------*/ 1181 1182/** 0010 0010 subw %0, %e!1 */ 1183 ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac; 1184 1185/** 0110 0001 0010 1001 subw %0, %ea1 */ 1186 ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac; 1187 1188/** 0010 0100 subw %0, #%1 */ 1189 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac; 1190 1191/** 0010 0rw1 subw %0, %1 */ 1192 ID(sub); W(); DR(AX); SRW(rw); Fzac; 1193 1194/** 0010 0110 subw %0, %1 */ 1195 ID(sub); W(); DR(AX); SM(None, SADDR); Fzac; 1196 1197/** 0010 0000 subw %0, #%1 */ 1198 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac; 1199 1200/*----------------------------------------------------------------------*/ 1201 1202/** 0110 0001 1010 1010 xch %0, %e!1 */ 1203 ID(xch); DR(A); SM(None, IMMU(2)); 1204 1205/** 0110 0001 1010 1110 xch %0, %e1 */ 1206 ID(xch); DR(A); SM(DE, 0); 1207 1208/** 0110 0001 1010 1111 xch %0, %ea1 */ 1209 ID(xch); DR(A); SM(DE, IMMU(1)); 1210 1211/** 0110 0001 1010 1100 xch %0, %e1 */ 1212 ID(xch); DR(A); SM(HL, 0); 1213 1214/** 0110 0001 1011 1001 xch %0, %e1 */ 1215 ID(xch); DR(A); SM2(HL, B, 0); 1216 1217/** 0110 0001 1010 1101 xch %0, %ea1 */ 1218 ID(xch); DR(A); SM(HL, IMMU(1)); 1219 1220/** 0110 0001 1010 1001 xch %0, %e1 */ 1221 ID(xch); DR(A); SM2(HL, C, 0); 1222 1223/** 0110 0001 1000 1reg xch %0, %1 */ 1224 /* Note: DECW uses reg == X, so this must follow DECW */ 1225 ID(xch); DR(A); SRB(reg); 1226 1227/** 0110 0001 1010 1000 xch %0, %1 */ 1228 ID(xch); DR(A); SM(None, SADDR); 1229 1230/** 0110 0001 1010 1011 xch %0, %s1 */ 1231 ID(xch); DR(A); SM(None, SFR); 1232 1233/** 0000 1000 xch a, x */ 1234 ID(xch); DR(A); SR(X); 1235 1236/*----------------------------------------------------------------------*/ 1237 1238/** 0011 0ra1 xchw %0, %1 */ 1239 ID(xch); W(); DR(AX); SRW(ra); 1240 1241/*----------------------------------------------------------------------*/ 1242 1243/** 0111 1111 xor %0, %e!1 */ 1244 ID(xor); DR(A); SM(None, IMMU(2)); Fz; 1245 1246/** 0111 1101 xor %0, %e1 */ 1247 ID(xor); DR(A); SM(HL, 0); Fz; 1248 1249/** 0110 0001 1111 0000 xor %0, %e1 */ 1250 ID(xor); DR(A); SM2(HL, B, 0); Fz; 1251 1252/** 0111 1110 xor %0, %ea1 */ 1253 ID(xor); DR(A); SM(HL, IMMU(1)); Fz; 1254 1255/** 0110 0001 1111 0010 xor %0, %e1 */ 1256 ID(xor); DR(A); SM2(HL, C, 0); Fz; 1257 1258/** 0111 1100 xor %0, #%1 */ 1259 ID(xor); DR(A); SC(IMMU(1)); Fz; 1260 1261/** 0110 0001 0111 1rba xor %0, %1 */ 1262 ID(xor); DR(A); SRB(rba); Fz; 1263 1264/** 0110 0001 0111 0reg xor %0, %1 */ 1265 ID(xor); DRB(reg); SR(A); Fz; 1266 1267/** 0111 1011 xor %0, %1 */ 1268 ID(xor); DR(A); SM(None, SADDR); Fz; 1269 1270/** 0111 1010 xor %0, #%1 */ 1271 ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz; 1272 1273/*----------------------------------------------------------------------*/ 1274 1275/** 0111 0001 1bit 0111 xor1 cy, %e1 */ 1276 ID(xor); DCY(); SM(HL, 0); SB(bit); 1277 1278/** 0111 0001 1bit 1111 xor1 cy, %1 */ 1279 ID(xor); DCY(); SR(A); SB(bit); 1280 1281/** 0111 0001 0bit 1111 xor1 cy, %s1 */ 1282 ID(xor); DCY(); SM(None, SFR); SB(bit); 1283 1284/** 0111 0001 0bit 0111 xor1 cy, %s1 */ 1285 ID(xor); DCY(); SM(None, SADDR); SB(bit); 1286 1287/*----------------------------------------------------------------------*/ 1288 1289/** */ 1290 1291 return rl78->n_bytes; 1292} 1293