1/* ppc-opc.c -- PowerPC opcode list 2 Copyright (C) 1994-2017 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22#include "sysdep.h" 23#include <stdio.h> 24#include "opcode/ppc.h" 25#include "opintl.h" 26 27/* This file holds the PowerPC opcode table. The opcode table 28 includes almost all of the extended instruction mnemonics. This 29 permits the disassembler to use them, and simplifies the assembler 30 logic, at the cost of increasing the table size. The table is 31 strictly constant data, so the compiler should be able to put it in 32 the .text section. 33 34 This file also holds the operand table. All knowledge about 35 inserting operands into instructions and vice-versa is kept in this 36 file. */ 37 38/* Local insertion and extraction functions. */ 39 40static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **); 41static long extract_arx (unsigned long, ppc_cpu_t, int *); 42static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **); 43static long extract_ary (unsigned long, ppc_cpu_t, int *); 44static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); 45static long extract_bat (unsigned long, ppc_cpu_t, int *); 46static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); 47static long extract_bba (unsigned long, ppc_cpu_t, int *); 48static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); 49static long extract_bdm (unsigned long, ppc_cpu_t, int *); 50static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); 51static long extract_bdp (unsigned long, ppc_cpu_t, int *); 52static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); 53static long extract_bo (unsigned long, ppc_cpu_t, int *); 54static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); 55static long extract_boe (unsigned long, ppc_cpu_t, int *); 56static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **); 57static long extract_esync (unsigned long, ppc_cpu_t, int *); 58static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **); 59static long extract_dcmxs (unsigned long, ppc_cpu_t, int *); 60static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **); 61static long extract_dxd (unsigned long, ppc_cpu_t, int *); 62static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **); 63static long extract_dxdn (unsigned long, ppc_cpu_t, int *); 64static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); 65static long extract_fxm (unsigned long, ppc_cpu_t, int *); 66static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); 67static long extract_li20 (unsigned long, ppc_cpu_t, int *); 68static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); 69static long extract_ls (unsigned long, ppc_cpu_t, int *); 70static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); 71static long extract_mbe (unsigned long, ppc_cpu_t, int *); 72static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); 73static long extract_mb6 (unsigned long, ppc_cpu_t, int *); 74static long extract_nb (unsigned long, ppc_cpu_t, int *); 75static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **); 76static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); 77static long extract_nsi (unsigned long, ppc_cpu_t, int *); 78static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **); 79static long extract_oimm (unsigned long, ppc_cpu_t, int *); 80static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); 81static long extract_ral (unsigned long, ppc_cpu_t, int *); 82static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); 83static long extract_ram (unsigned long, ppc_cpu_t, int *); 84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); 85static long extract_raq (unsigned long, ppc_cpu_t, int *); 86static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); 87static long extract_ras (unsigned long, ppc_cpu_t, int *); 88static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); 89static long extract_rbs (unsigned long, ppc_cpu_t, int *); 90static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **); 91static long extract_rbx (unsigned long, ppc_cpu_t, int *); 92static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **); 93static long extract_rx (unsigned long, ppc_cpu_t, int *); 94static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **); 95static long extract_ry (unsigned long, ppc_cpu_t, int *); 96static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); 97static long extract_sh6 (unsigned long, ppc_cpu_t, int *); 98static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **); 99static long extract_sci8 (unsigned long, ppc_cpu_t, int *); 100static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **); 101static long extract_sci8n (unsigned long, ppc_cpu_t, int *); 102static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **); 103static long extract_sd4h (unsigned long, ppc_cpu_t, int *); 104static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **); 105static long extract_sd4w (unsigned long, ppc_cpu_t, int *); 106static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); 107static long extract_spr (unsigned long, ppc_cpu_t, int *); 108static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); 109static long extract_sprg (unsigned long, ppc_cpu_t, int *); 110static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); 111static long extract_tbr (unsigned long, ppc_cpu_t, int *); 112static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); 113static long extract_xt6 (unsigned long, ppc_cpu_t, int *); 114static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **); 115static long extract_xtq6 (unsigned long, ppc_cpu_t, int *); 116static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); 117static long extract_xa6 (unsigned long, ppc_cpu_t, int *); 118static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); 119static long extract_xb6 (unsigned long, ppc_cpu_t, int *); 120static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); 121static long extract_xb6s (unsigned long, ppc_cpu_t, int *); 122static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); 123static long extract_xc6 (unsigned long, ppc_cpu_t, int *); 124static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); 125static long extract_dm (unsigned long, ppc_cpu_t, int *); 126static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **); 127static long extract_vlesi (unsigned long, ppc_cpu_t, int *); 128static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **); 129static long extract_vlensi (unsigned long, ppc_cpu_t, int *); 130static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **); 131static long extract_vleui (unsigned long, ppc_cpu_t, int *); 132static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); 133static long extract_vleil (unsigned long, ppc_cpu_t, int *); 134 135/* The operands table. 136 137 The fields are bitm, shift, insert, extract, flags. 138 139 We used to put parens around the various additions, like the one 140 for BA just below. However, that caused trouble with feeble 141 compilers with a limit on depth of a parenthesized expression, like 142 (reportedly) the compiler in Microsoft Developer Studio 5. So we 143 omit the parens, since the macros are never used in a context where 144 the addition will be ambiguous. */ 145 146const struct powerpc_operand powerpc_operands[] = 147{ 148 /* The zero index is used to indicate the end of the list of 149 operands. */ 150#define UNUSED 0 151 { 0, 0, NULL, NULL, 0 }, 152 153 /* The BA field in an XL form instruction. */ 154#define BA UNUSED + 1 155 /* The BI field in a B form or XL form instruction. */ 156#define BI BA 157#define BI_MASK (0x1f << 16) 158 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 159 160 /* The BA field in an XL form instruction when it must be the same 161 as the BT field in the same instruction. */ 162#define BAT BA + 1 163 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 164 165 /* The BB field in an XL form instruction. */ 166#define BB BAT + 1 167#define BB_MASK (0x1f << 11) 168 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, 169 170 /* The BB field in an XL form instruction when it must be the same 171 as the BA field in the same instruction. */ 172#define BBA BB + 1 173 /* The VB field in a VX form instruction when it must be the same 174 as the VA field in the same instruction. */ 175#define VBA BBA 176 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 177 178 /* The BD field in a B form instruction. The lower two bits are 179 forced to zero. */ 180#define BD BBA + 1 181 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 182 183 /* The BD field in a B form instruction when absolute addressing is 184 used. */ 185#define BDA BD + 1 186 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 187 188 /* The BD field in a B form instruction when the - modifier is used. 189 This sets the y bit of the BO field appropriately. */ 190#define BDM BDA + 1 191 { 0xfffc, 0, insert_bdm, extract_bdm, 192 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 193 194 /* The BD field in a B form instruction when the - modifier is used 195 and absolute address is used. */ 196#define BDMA BDM + 1 197 { 0xfffc, 0, insert_bdm, extract_bdm, 198 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 199 200 /* The BD field in a B form instruction when the + modifier is used. 201 This sets the y bit of the BO field appropriately. */ 202#define BDP BDMA + 1 203 { 0xfffc, 0, insert_bdp, extract_bdp, 204 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 205 206 /* The BD field in a B form instruction when the + modifier is used 207 and absolute addressing is used. */ 208#define BDPA BDP + 1 209 { 0xfffc, 0, insert_bdp, extract_bdp, 210 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 211 212 /* The BF field in an X or XL form instruction. */ 213#define BF BDPA + 1 214 /* The CRFD field in an X form instruction. */ 215#define CRFD BF 216 /* The CRD field in an XL form instruction. */ 217#define CRD BF 218 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, 219 220 /* The BF field in an X or XL form instruction. */ 221#define BFF BF + 1 222 { 0x7, 23, NULL, NULL, 0 }, 223 224 /* An optional BF field. This is used for comparison instructions, 225 in which an omitted BF field is taken as zero. */ 226#define OBF BFF + 1 227 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 228 229 /* The BFA field in an X or XL form instruction. */ 230#define BFA OBF + 1 231 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, 232 233 /* The BO field in a B form instruction. Certain values are 234 illegal. */ 235#define BO BFA + 1 236#define BO_MASK (0x1f << 21) 237 { 0x1f, 21, insert_bo, extract_bo, 0 }, 238 239 /* The BO field in a B form instruction when the + or - modifier is 240 used. This is like the BO field, but it must be even. */ 241#define BOE BO + 1 242 { 0x1e, 21, insert_boe, extract_boe, 0 }, 243 244 /* The RM field in an X form instruction. */ 245#define RM BOE + 1 246 { 0x3, 11, NULL, NULL, 0 }, 247 248#define BH RM + 1 249 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 250 251 /* The BT field in an X or XL form instruction. */ 252#define BT BH + 1 253 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, 254 255 /* The BI16 field in a BD8 form instruction. */ 256#define BI16 BT + 1 257 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, 258 259 /* The BI32 field in a BD15 form instruction. */ 260#define BI32 BI16 + 1 261 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 262 263 /* The BO32 field in a BD15 form instruction. */ 264#define BO32 BI32 + 1 265 { 0x3, 20, NULL, NULL, 0 }, 266 267 /* The B8 field in a BD8 form instruction. */ 268#define B8 BO32 + 1 269 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 270 271 /* The B15 field in a BD15 form instruction. The lowest bit is 272 forced to zero. */ 273#define B15 B8 + 1 274 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 275 276 /* The B24 field in a BD24 form instruction. The lowest bit is 277 forced to zero. */ 278#define B24 B15 + 1 279 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 280 281 /* The condition register number portion of the BI field in a B form 282 or XL form instruction. This is used for the extended 283 conditional branch mnemonics, which set the lower two bits of the 284 BI field. This field is optional. */ 285#define CR B24 + 1 286 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 287 288 /* The CRB field in an X form instruction. */ 289#define CRB CR + 1 290 /* The MB field in an M form instruction. */ 291#define MB CRB 292#define MB_MASK (0x1f << 6) 293 { 0x1f, 6, NULL, NULL, 0 }, 294 295 /* The CRD32 field in an XL form instruction. */ 296#define CRD32 CRB + 1 297 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, 298 299 /* The CRFS field in an X form instruction. */ 300#define CRFS CRD32 + 1 301 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, 302 303#define CRS CRFS + 1 304 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 305 306 /* The CT field in an X form instruction. */ 307#define CT CRS + 1 308 /* The MO field in an mbar instruction. */ 309#define MO CT 310 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 311 312 /* The D field in a D form instruction. This is a displacement off 313 a register, and implies that the next operand is a register in 314 parentheses. */ 315#define D CT + 1 316 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 317 318 /* The D8 field in a D form instruction. This is a displacement off 319 a register, and implies that the next operand is a register in 320 parentheses. */ 321#define D8 D + 1 322 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 323 324 /* The DCMX field in an X form instruction. */ 325#define DCMX D8 + 1 326 { 0x7f, 16, NULL, NULL, 0 }, 327 328 /* The split DCMX field in an X form instruction. */ 329#define DCMXS DCMX + 1 330 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, 331 332 /* The DQ field in a DQ form instruction. This is like D, but the 333 lower four bits are forced to zero. */ 334#define DQ DCMXS + 1 335 { 0xfff0, 0, NULL, NULL, 336 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 337 338 /* The DS field in a DS form instruction. This is like D, but the 339 lower two bits are forced to zero. */ 340#define DS DQ + 1 341 { 0xfffc, 0, NULL, NULL, 342 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 343 344 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits 345 unsigned imediate */ 346#define DUIS DS + 1 347#define BHRBE DUIS 348 { 0x3ff, 11, NULL, NULL, 0 }, 349 350 /* The split D field in a DX form instruction. */ 351#define DXD DUIS + 1 352 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, 353 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 354 355 /* The split ND field in a DX form instruction. 356 This is the same as the DX field, only negated. */ 357#define NDXD DXD + 1 358 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, 359 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 360 361 /* The E field in a wrteei instruction. */ 362 /* And the W bit in the pair singles instructions. */ 363 /* And the ST field in a VX form instruction. */ 364#define E NDXD + 1 365#define PSW E 366#define ST E 367 { 0x1, 15, NULL, NULL, 0 }, 368 369 /* The FL1 field in a POWER SC form instruction. */ 370#define FL1 E + 1 371 /* The U field in an X form instruction. */ 372#define U FL1 373 { 0xf, 12, NULL, NULL, 0 }, 374 375 /* The FL2 field in a POWER SC form instruction. */ 376#define FL2 FL1 + 1 377 { 0x7, 2, NULL, NULL, 0 }, 378 379 /* The FLM field in an XFL form instruction. */ 380#define FLM FL2 + 1 381 { 0xff, 17, NULL, NULL, 0 }, 382 383 /* The FRA field in an X or A form instruction. */ 384#define FRA FLM + 1 385#define FRA_MASK (0x1f << 16) 386 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 387 388 /* The FRAp field of DFP instructions. */ 389#define FRAp FRA + 1 390 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, 391 392 /* The FRB field in an X or A form instruction. */ 393#define FRB FRAp + 1 394#define FRB_MASK (0x1f << 11) 395 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 396 397 /* The FRBp field of DFP instructions. */ 398#define FRBp FRB + 1 399 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, 400 401 /* The FRC field in an A form instruction. */ 402#define FRC FRBp + 1 403#define FRC_MASK (0x1f << 6) 404 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 405 406 /* The FRS field in an X form instruction or the FRT field in a D, X 407 or A form instruction. */ 408#define FRS FRC + 1 409#define FRT FRS 410 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 411 412 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP 413 instructions. */ 414#define FRSp FRS + 1 415#define FRTp FRSp 416 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, 417 418 /* The FXM field in an XFX instruction. */ 419#define FXM FRSp + 1 420 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 421 422 /* Power4 version for mfcr. */ 423#define FXM4 FXM + 1 424 { 0xff, 12, insert_fxm, extract_fxm, 425 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 426 /* If the FXM4 operand is ommitted, use the sentinel value -1. */ 427 { -1, -1, NULL, NULL, 0}, 428 429 /* The IMM20 field in an LI instruction. */ 430#define IMM20 FXM4 + 2 431 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, 432 433 /* The L field in a D or X form instruction. */ 434#define L IMM20 + 1 435 { 0x1, 21, NULL, NULL, 0 }, 436 437 /* The optional L field in tlbie and tlbiel instructions. */ 438#define LOPT L + 1 439 /* The R field in a HTM X form instruction. */ 440#define HTM_R LOPT 441 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 442 443 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ 444#define L32OPT LOPT + 1 445 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, 446 447 /* The L field in dcbf instruction. */ 448#define L2OPT L32OPT + 1 449 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 450 451 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ 452#define SVC_LEV L2OPT + 1 453 { 0x7f, 5, NULL, NULL, 0 }, 454 455 /* The LEV field in an SC form instruction. */ 456#define LEV SVC_LEV + 1 457 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 458 459 /* The LI field in an I form instruction. The lower two bits are 460 forced to zero. */ 461#define LI LEV + 1 462 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 463 464 /* The LI field in an I form instruction when used as an absolute 465 address. */ 466#define LIA LI + 1 467 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 468 469 /* The LS or WC field in an X (sync or wait) form instruction. */ 470#define LS LIA + 1 471#define WC LS 472 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, 473 474 /* The ME field in an M form instruction. */ 475#define ME LS + 1 476#define ME_MASK (0x1f << 1) 477 { 0x1f, 1, NULL, NULL, 0 }, 478 479 /* The MB and ME fields in an M form instruction expressed a single 480 operand which is a bitmask indicating which bits to select. This 481 is a two operand form using PPC_OPERAND_NEXT. See the 482 description in opcode/ppc.h for what this means. */ 483#define MBE ME + 1 484 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 485 { -1, 0, insert_mbe, extract_mbe, 0 }, 486 487 /* The MB or ME field in an MD or MDS form instruction. The high 488 bit is wrapped to the low end. */ 489#define MB6 MBE + 2 490#define ME6 MB6 491#define MB6_MASK (0x3f << 5) 492 { 0x3f, 5, insert_mb6, extract_mb6, 0 }, 493 494 /* The NB field in an X form instruction. The value 32 is stored as 495 0. */ 496#define NB MB6 + 1 497 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 498 499 /* The NBI field in an lswi instruction, which has special value 500 restrictions. The value 32 is stored as 0. */ 501#define NBI NB + 1 502 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, 503 504 /* The NSI field in a D form instruction. This is the same as the 505 SI field, only negated. */ 506#define NSI NBI + 1 507 { 0xffff, 0, insert_nsi, extract_nsi, 508 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 509 510 /* The NSI field in a D form instruction when we accept a wide range 511 of positive values. */ 512#define NSISIGNOPT NSI + 1 513 { 0xffff, 0, insert_nsi, extract_nsi, 514 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 515 516 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 517#define RA NSISIGNOPT + 1 518#define RA_MASK (0x1f << 16) 519 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 520 521 /* As above, but 0 in the RA field means zero, not r0. */ 522#define RA0 RA + 1 523 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 524 525 /* The RA field in the DQ form lq or an lswx instruction, which have special 526 value restrictions. */ 527#define RAQ RA0 + 1 528#define RAX RAQ 529 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 }, 530 531 /* The RA field in a D or X form instruction which is an updating 532 load, which means that the RA field may not be zero and may not 533 equal the RT field. */ 534#define RAL RAQ + 1 535 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 }, 536 537 /* The RA field in an lmw instruction, which has special value 538 restrictions. */ 539#define RAM RAL + 1 540 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, 541 542 /* The RA field in a D or X form instruction which is an updating 543 store or an updating floating point load, which means that the RA 544 field may not be zero. */ 545#define RAS RAM + 1 546 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, 547 548 /* The RA field of the tlbwe, dccci and iccci instructions, 549 which are optional. */ 550#define RAOPT RAS + 1 551 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 552 553 /* The RB field in an X, XO, M, or MDS form instruction. */ 554#define RB RAOPT + 1 555#define RB_MASK (0x1f << 11) 556 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, 557 558 /* The RB field in an X form instruction when it must be the same as 559 the RS field in the instruction. This is used for extended 560 mnemonics like mr. */ 561#define RBS RB + 1 562 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 563 564 /* The RB field in an lswx instruction, which has special value 565 restrictions. */ 566#define RBX RBS + 1 567 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR }, 568 569 /* The RB field of the dccci and iccci instructions, which are optional. */ 570#define RBOPT RBX + 1 571 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 572 573 /* The RC register field in an maddld, maddhd or maddhdu instruction. */ 574#define RC RBOPT + 1 575 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, 576 577 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 578 instruction or the RT field in a D, DS, X, XFX or XO form 579 instruction. */ 580#define RS RC + 1 581#define RT RS 582#define RT_MASK (0x1f << 21) 583#define RD RS 584 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 585 586 /* The RS and RT fields of the DS form stq and DQ form lq instructions, 587 which have special value restrictions. */ 588#define RSQ RS + 1 589#define RTQ RSQ 590#define Q_MASK (1 << 21) 591 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, 592 593 /* The RS field of the tlbwe instruction, which is optional. */ 594#define RSO RSQ + 1 595#define RTO RSO 596 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 597 598 /* The RX field of the SE_RR form instruction. */ 599#define RX RSO + 1 600 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, 601 602 /* The ARX field of the SE_RR form instruction. */ 603#define ARX RX + 1 604 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, 605 606 /* The RY field of the SE_RR form instruction. */ 607#define RY ARX + 1 608#define RZ RY 609 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, 610 611 /* The ARY field of the SE_RR form instruction. */ 612#define ARY RY + 1 613 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, 614 615 /* The SCLSCI8 field in a D form instruction. */ 616#define SCLSCI8 ARY + 1 617 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, 618 619 /* The SCLSCI8N field in a D form instruction. This is the same as the 620 SCLSCI8 field, only negated. */ 621#define SCLSCI8N SCLSCI8 + 1 622 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, 623 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 624 625 /* The SD field of the SD4 form instruction. */ 626#define SE_SD SCLSCI8N + 1 627 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, 628 629 /* The SD field of the SD4 form instruction, for halfword. */ 630#define SE_SDH SE_SD + 1 631 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, 632 633 /* The SD field of the SD4 form instruction, for word. */ 634#define SE_SDW SE_SDH + 1 635 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, 636 637 /* The SH field in an X or M form instruction. */ 638#define SH SE_SDW + 1 639#define SH_MASK (0x1f << 11) 640 /* The other UIMM field in a EVX form instruction. */ 641#define EVUIMM SH 642 /* The FC field in an atomic X form instruction. */ 643#define FC SH 644 { 0x1f, 11, NULL, NULL, 0 }, 645 646 /* The SI field in a HTM X form instruction. */ 647#define HTM_SI SH + 1 648 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, 649 650 /* The SH field in an MD form instruction. This is split. */ 651#define SH6 HTM_SI + 1 652#define SH6_MASK ((0x1f << 11) | (1 << 1)) 653 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, 654 655 /* The SH field of the tlbwe instruction, which is optional. */ 656#define SHO SH6 + 1 657 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 658 659 /* The SI field in a D form instruction. */ 660#define SI SHO + 1 661 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 662 663 /* The SI field in a D form instruction when we accept a wide range 664 of positive values. */ 665#define SISIGNOPT SI + 1 666 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 667 668 /* The SI8 field in a D form instruction. */ 669#define SI8 SISIGNOPT + 1 670 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 671 672 /* The SPR field in an XFX form instruction. This is flipped--the 673 lower 5 bits are stored in the upper 5 and vice- versa. */ 674#define SPR SI8 + 1 675#define PMR SPR 676#define TMR SPR 677#define SPR_MASK (0x3ff << 11) 678 { 0x3ff, 11, insert_spr, extract_spr, 0 }, 679 680 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 681#define SPRBAT SPR + 1 682#define SPRBAT_MASK (0x3 << 17) 683 { 0x3, 17, NULL, NULL, 0 }, 684 685 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 686#define SPRG SPRBAT + 1 687 { 0x1f, 16, insert_sprg, extract_sprg, 0 }, 688 689 /* The SR field in an X form instruction. */ 690#define SR SPRG + 1 691 /* The 4-bit UIMM field in a VX form instruction. */ 692#define UIMM4 SR 693 { 0xf, 16, NULL, NULL, 0 }, 694 695 /* The STRM field in an X AltiVec form instruction. */ 696#define STRM SR + 1 697 /* The T field in a tlbilx form instruction. */ 698#define T STRM 699 /* The L field in wclr instructions. */ 700#define L2 STRM 701 { 0x3, 21, NULL, NULL, 0 }, 702 703 /* The ESYNC field in an X (sync) form instruction. */ 704#define ESYNC STRM + 1 705 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL }, 706 707 /* The SV field in a POWER SC form instruction. */ 708#define SV ESYNC + 1 709 { 0x3fff, 2, NULL, NULL, 0 }, 710 711 /* The TBR field in an XFX form instruction. This is like the SPR 712 field, but it is optional. */ 713#define TBR SV + 1 714 { 0x3ff, 11, insert_tbr, extract_tbr, 715 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 716 /* If the TBR operand is ommitted, use the value 268. */ 717 { -1, 268, NULL, NULL, 0}, 718 719 /* The TO field in a D or X form instruction. */ 720#define TO TBR + 2 721#define DUI TO 722#define TO_MASK (0x1f << 21) 723 { 0x1f, 21, NULL, NULL, 0 }, 724 725 /* The UI field in a D form instruction. */ 726#define UI TO + 1 727 { 0xffff, 0, NULL, NULL, 0 }, 728 729#define UISIGNOPT UI + 1 730 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, 731 732 /* The IMM field in an SE_IM5 instruction. */ 733#define UI5 UISIGNOPT + 1 734 { 0x1f, 4, NULL, NULL, 0 }, 735 736 /* The OIMM field in an SE_OIM5 instruction. */ 737#define OIMM5 UI5 + 1 738 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, 739 740 /* The UI7 field in an SE_LI instruction. */ 741#define UI7 OIMM5 + 1 742 { 0x7f, 4, NULL, NULL, 0 }, 743 744 /* The VA field in a VA, VX or VXR form instruction. */ 745#define VA UI7 + 1 746 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 747 748 /* The VB field in a VA, VX or VXR form instruction. */ 749#define VB VA + 1 750 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, 751 752 /* The VC field in a VA form instruction. */ 753#define VC VB + 1 754 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, 755 756 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 757#define VD VC + 1 758#define VS VD 759 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 760 761 /* The SIMM field in a VX form instruction, and TE in Z form. */ 762#define SIMM VD + 1 763#define TE SIMM 764 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 765 766 /* The UIMM field in a VX form instruction. */ 767#define UIMM SIMM + 1 768#define DCTL UIMM 769 { 0x1f, 16, NULL, NULL, 0 }, 770 771 /* The 3-bit UIMM field in a VX form instruction. */ 772#define UIMM3 UIMM + 1 773 { 0x7, 16, NULL, NULL, 0 }, 774 775 /* The 6-bit UIM field in a X form instruction. */ 776#define UIM6 UIMM3 + 1 777 { 0x3f, 16, NULL, NULL, 0 }, 778 779 /* The SIX field in a VX form instruction. */ 780#define SIX UIM6 + 1 781 { 0xf, 11, NULL, NULL, 0 }, 782 783 /* The PS field in a VX form instruction. */ 784#define PS SIX + 1 785 { 0x1, 9, NULL, NULL, 0 }, 786 787 /* The SHB field in a VA form instruction. */ 788#define SHB PS + 1 789 { 0xf, 6, NULL, NULL, 0 }, 790 791 /* The other UIMM field in a half word EVX form instruction. */ 792#define EVUIMM_2 SHB + 1 793 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, 794 795 /* The other UIMM field in a word EVX form instruction. */ 796#define EVUIMM_4 EVUIMM_2 + 1 797 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, 798 799 /* The other UIMM field in a double EVX form instruction. */ 800#define EVUIMM_8 EVUIMM_4 + 1 801 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 802 803 /* The WS or DRM field in an X form instruction. */ 804#define WS EVUIMM_8 + 1 805#define DRM WS 806 { 0x7, 11, NULL, NULL, 0 }, 807 808 /* PowerPC paired singles extensions. */ 809 /* W bit in the pair singles instructions for x type instructions. */ 810#define PSWM WS + 1 811 /* The BO16 field in a BD8 form instruction. */ 812#define BO16 PSWM 813 { 0x1, 10, 0, 0, 0 }, 814 815 /* IDX bits for quantization in the pair singles instructions. */ 816#define PSQ PSWM + 1 817 { 0x7, 12, 0, 0, 0 }, 818 819 /* IDX bits for quantization in the pair singles x-type instructions. */ 820#define PSQM PSQ + 1 821 { 0x7, 7, 0, 0, 0 }, 822 823 /* Smaller D field for quantization in the pair singles instructions. */ 824#define PSD PSQM + 1 825 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 826 827 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */ 828#define A_L PSD + 1 829#define W A_L 830#define X_R A_L 831 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 832 833 /* The RMC or CY field in a Z23 form instruction. */ 834#define RMC A_L + 1 835#define CY RMC 836 { 0x3, 9, NULL, NULL, 0 }, 837 838#define R RMC + 1 839 { 0x1, 16, NULL, NULL, 0 }, 840 841#define RIC R + 1 842 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, 843 844#define PRS RIC + 1 845 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, 846 847#define SP PRS + 1 848 { 0x3, 19, NULL, NULL, 0 }, 849 850#define S SP + 1 851 { 0x1, 20, NULL, NULL, 0 }, 852 853 /* The S field in a XL form instruction. */ 854#define SXL S + 1 855 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, 856 /* If the SXL operand is ommitted, use the value 1. */ 857 { -1, 1, NULL, NULL, 0}, 858 859 /* SH field starting at bit position 16. */ 860#define SH16 SXL + 2 861 /* The DCM and DGM fields in a Z form instruction. */ 862#define DCM SH16 863#define DGM DCM 864 { 0x3f, 10, NULL, NULL, 0 }, 865 866 /* The EH field in larx instruction. */ 867#define EH SH16 + 1 868 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 869 870 /* The L field in an mtfsf or XFL form instruction. */ 871 /* The A field in a HTM X form instruction. */ 872#define XFL_L EH + 1 873#define HTM_A XFL_L 874 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 875 876 /* Xilinx APU related masks and macros */ 877#define FCRT XFL_L + 1 878#define FCRT_MASK (0x1f << 21) 879 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, 880 881 /* Xilinx FSL related masks and macros */ 882#define FSL FCRT + 1 883#define FSL_MASK (0x1f << 11) 884 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, 885 886 /* Xilinx UDI related masks and macros */ 887#define URT FSL + 1 888 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, 889 890#define URA URT + 1 891 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, 892 893#define URB URA + 1 894 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, 895 896#define URC URB + 1 897 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, 898 899 /* The VLESIMM field in a D form instruction. */ 900#define VLESIMM URC + 1 901 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, 902 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 903 904 /* The VLENSIMM field in a D form instruction. */ 905#define VLENSIMM VLESIMM + 1 906 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, 907 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 908 909 /* The VLEUIMM field in a D form instruction. */ 910#define VLEUIMM VLENSIMM + 1 911 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, 912 913 /* The VLEUIMML field in a D form instruction. */ 914#define VLEUIMML VLEUIMM + 1 915 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, 916 917 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 918#define XS6 VLEUIMML + 1 919#define XT6 XS6 920 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, 921 922 /* The XT and XS fields in an DQ form VSX instruction. This is split. */ 923#define XSQ6 XT6 + 1 924#define XTQ6 XSQ6 925 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, 926 927 /* The XA field in an XX3 form instruction. This is split. */ 928#define XA6 XTQ6 + 1 929 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, 930 931 /* The XB field in an XX2 or XX3 form instruction. This is split. */ 932#define XB6 XA6 + 1 933 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, 934 935 /* The XB field in an XX3 form instruction when it must be the same as 936 the XA field in the instruction. This is used in extended mnemonics 937 like xvmovdp. This is split. */ 938#define XB6S XB6 + 1 939 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, 940 941 /* The XC field in an XX4 form instruction. This is split. */ 942#define XC6 XB6S + 1 943 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, 944 945 /* The DM or SHW field in an XX3 form instruction. */ 946#define DM XC6 + 1 947#define SHW DM 948 { 0x3, 8, NULL, NULL, 0 }, 949 950 /* The DM field in an extended mnemonic XX3 form instruction. */ 951#define DMEX DM + 1 952 { 0x3, 8, insert_dm, extract_dm, 0 }, 953 954 /* The UIM field in an XX2 form instruction. */ 955#define UIM DMEX + 1 956 /* The 2-bit UIMM field in a VX form instruction. */ 957#define UIMM2 UIM 958 /* The 2-bit L field in a darn instruction. */ 959#define LRAND UIM 960 { 0x3, 16, NULL, NULL, 0 }, 961 962#define ERAT_T UIM + 1 963 { 0x7, 21, NULL, NULL, 0 }, 964 965#define IH ERAT_T + 1 966 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 967 968 /* The 8-bit IMM8 field in a XX1 form instruction. */ 969#define IMM8 IH + 1 970 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, 971}; 972 973const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 974 / sizeof (powerpc_operands[0])); 975 976/* The functions used to insert and extract complicated operands. */ 977 978/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ 979 980static unsigned long 981insert_arx (unsigned long insn, 982 long value, 983 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 984 const char **errmsg ATTRIBUTE_UNUSED) 985{ 986 if (value >= 8 && value < 24) 987 return insn | ((value - 8) & 0xf); 988 else 989 { 990 *errmsg = _("invalid register"); 991 return 0; 992 } 993} 994 995static long 996extract_arx (unsigned long insn, 997 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 998 int *invalid ATTRIBUTE_UNUSED) 999{ 1000 return (insn & 0xf) + 8; 1001} 1002 1003static unsigned long 1004insert_ary (unsigned long insn, 1005 long value, 1006 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1007 const char **errmsg ATTRIBUTE_UNUSED) 1008{ 1009 if (value >= 8 && value < 24) 1010 return insn | (((value - 8) & 0xf) << 4); 1011 else 1012 { 1013 *errmsg = _("invalid register"); 1014 return 0; 1015 } 1016} 1017 1018static long 1019extract_ary (unsigned long insn, 1020 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1021 int *invalid ATTRIBUTE_UNUSED) 1022{ 1023 return ((insn >> 4) & 0xf) + 8; 1024} 1025 1026static unsigned long 1027insert_rx (unsigned long insn, 1028 long value, 1029 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1030 const char **errmsg) 1031{ 1032 if (value >= 0 && value < 8) 1033 return insn | value; 1034 else if (value >= 24 && value <= 31) 1035 return insn | (value - 16); 1036 else 1037 { 1038 *errmsg = _("invalid register"); 1039 return 0; 1040 } 1041} 1042 1043static long 1044extract_rx (unsigned long insn, 1045 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1046 int *invalid ATTRIBUTE_UNUSED) 1047{ 1048 int value = insn & 0xf; 1049 if (value >= 0 && value < 8) 1050 return value; 1051 else 1052 return value + 16; 1053} 1054 1055static unsigned long 1056insert_ry (unsigned long insn, 1057 long value, 1058 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1059 const char **errmsg) 1060{ 1061 if (value >= 0 && value < 8) 1062 return insn | (value << 4); 1063 else if (value >= 24 && value <= 31) 1064 return insn | ((value - 16) << 4); 1065 else 1066 { 1067 *errmsg = _("invalid register"); 1068 return 0; 1069 } 1070} 1071 1072static long 1073extract_ry (unsigned long insn, 1074 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1075 int *invalid ATTRIBUTE_UNUSED) 1076{ 1077 int value = (insn >> 4) & 0xf; 1078 if (value >= 0 && value < 8) 1079 return value; 1080 else 1081 return value + 16; 1082} 1083 1084/* The BA field in an XL form instruction when it must be the same as 1085 the BT field in the same instruction. This operand is marked FAKE. 1086 The insertion function just copies the BT field into the BA field, 1087 and the extraction function just checks that the fields are the 1088 same. */ 1089 1090static unsigned long 1091insert_bat (unsigned long insn, 1092 long value ATTRIBUTE_UNUSED, 1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1094 const char **errmsg ATTRIBUTE_UNUSED) 1095{ 1096 return insn | (((insn >> 21) & 0x1f) << 16); 1097} 1098 1099static long 1100extract_bat (unsigned long insn, 1101 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1102 int *invalid) 1103{ 1104 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 1105 *invalid = 1; 1106 return 0; 1107} 1108 1109/* The BB field in an XL form instruction when it must be the same as 1110 the BA field in the same instruction. This operand is marked FAKE. 1111 The insertion function just copies the BA field into the BB field, 1112 and the extraction function just checks that the fields are the 1113 same. */ 1114 1115static unsigned long 1116insert_bba (unsigned long insn, 1117 long value ATTRIBUTE_UNUSED, 1118 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1119 const char **errmsg ATTRIBUTE_UNUSED) 1120{ 1121 return insn | (((insn >> 16) & 0x1f) << 11); 1122} 1123 1124static long 1125extract_bba (unsigned long insn, 1126 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1127 int *invalid) 1128{ 1129 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 1130 *invalid = 1; 1131 return 0; 1132} 1133 1134/* The BD field in a B form instruction when the - modifier is used. 1135 This modifier means that the branch is not expected to be taken. 1136 For chips built to versions of the architecture prior to version 2 1137 (ie. not Power4 compatible), we set the y bit of the BO field to 1 1138 if the offset is negative. When extracting, we require that the y 1139 bit be 1 and that the offset be positive, since if the y bit is 0 1140 we just want to print the normal form of the instruction. 1141 Power4 compatible targets use two bits, "a", and "t", instead of 1142 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 1143 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 1144 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 1145 for branch on CTR. We only handle the taken/not-taken hint here. 1146 Note that we don't relax the conditions tested here when 1147 disassembling with -Many because insns using extract_bdm and 1148 extract_bdp always occur in pairs. One or the other will always 1149 be valid. */ 1150 1151#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 1152 1153static unsigned long 1154insert_bdm (unsigned long insn, 1155 long value, 1156 ppc_cpu_t dialect, 1157 const char **errmsg ATTRIBUTE_UNUSED) 1158{ 1159 if ((dialect & ISA_V2) == 0) 1160 { 1161 if ((value & 0x8000) != 0) 1162 insn |= 1 << 21; 1163 } 1164 else 1165 { 1166 if ((insn & (0x14 << 21)) == (0x04 << 21)) 1167 insn |= 0x02 << 21; 1168 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 1169 insn |= 0x08 << 21; 1170 } 1171 return insn | (value & 0xfffc); 1172} 1173 1174static long 1175extract_bdm (unsigned long insn, 1176 ppc_cpu_t dialect, 1177 int *invalid) 1178{ 1179 if ((dialect & ISA_V2) == 0) 1180 { 1181 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 1182 *invalid = 1; 1183 } 1184 else 1185 { 1186 if ((insn & (0x17 << 21)) != (0x06 << 21) 1187 && (insn & (0x1d << 21)) != (0x18 << 21)) 1188 *invalid = 1; 1189 } 1190 1191 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1192} 1193 1194/* The BD field in a B form instruction when the + modifier is used. 1195 This is like BDM, above, except that the branch is expected to be 1196 taken. */ 1197 1198static unsigned long 1199insert_bdp (unsigned long insn, 1200 long value, 1201 ppc_cpu_t dialect, 1202 const char **errmsg ATTRIBUTE_UNUSED) 1203{ 1204 if ((dialect & ISA_V2) == 0) 1205 { 1206 if ((value & 0x8000) == 0) 1207 insn |= 1 << 21; 1208 } 1209 else 1210 { 1211 if ((insn & (0x14 << 21)) == (0x04 << 21)) 1212 insn |= 0x03 << 21; 1213 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 1214 insn |= 0x09 << 21; 1215 } 1216 return insn | (value & 0xfffc); 1217} 1218 1219static long 1220extract_bdp (unsigned long insn, 1221 ppc_cpu_t dialect, 1222 int *invalid) 1223{ 1224 if ((dialect & ISA_V2) == 0) 1225 { 1226 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 1227 *invalid = 1; 1228 } 1229 else 1230 { 1231 if ((insn & (0x17 << 21)) != (0x07 << 21) 1232 && (insn & (0x1d << 21)) != (0x19 << 21)) 1233 *invalid = 1; 1234 } 1235 1236 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1237} 1238 1239static inline int 1240valid_bo_pre_v2 (long value) 1241{ 1242 /* Certain encodings have bits that are required to be zero. 1243 These are (z must be zero, y may be anything): 1244 0000y 1245 0001y 1246 001zy 1247 0100y 1248 0101y 1249 011zy 1250 1z00y 1251 1z01y 1252 1z1zz 1253 */ 1254 if ((value & 0x14) == 0) 1255 return 1; 1256 else if ((value & 0x14) == 0x4) 1257 return (value & 0x2) == 0; 1258 else if ((value & 0x14) == 0x10) 1259 return (value & 0x8) == 0; 1260 else 1261 return value == 0x14; 1262} 1263 1264static inline int 1265valid_bo_post_v2 (long value) 1266{ 1267 /* Certain encodings have bits that are required to be zero. 1268 These are (z must be zero, a & t may be anything): 1269 0000z 1270 0001z 1271 001at 1272 0100z 1273 0101z 1274 011at 1275 1a00t 1276 1a01t 1277 1z1zz 1278 */ 1279 if ((value & 0x14) == 0) 1280 return (value & 0x1) == 0; 1281 else if ((value & 0x14) == 0x14) 1282 return value == 0x14; 1283 else 1284 return 1; 1285} 1286 1287/* Check for legal values of a BO field. */ 1288 1289static int 1290valid_bo (long value, ppc_cpu_t dialect, int extract) 1291{ 1292 int valid_y = valid_bo_pre_v2 (value); 1293 int valid_at = valid_bo_post_v2 (value); 1294 1295 /* When disassembling with -Many, accept either encoding on the 1296 second pass through opcodes. */ 1297 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) 1298 return valid_y || valid_at; 1299 if ((dialect & ISA_V2) == 0) 1300 return valid_y; 1301 else 1302 return valid_at; 1303} 1304 1305/* The BO field in a B form instruction. Warn about attempts to set 1306 the field to an illegal value. */ 1307 1308static unsigned long 1309insert_bo (unsigned long insn, 1310 long value, 1311 ppc_cpu_t dialect, 1312 const char **errmsg) 1313{ 1314 if (!valid_bo (value, dialect, 0)) 1315 *errmsg = _("invalid conditional option"); 1316 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) 1317 *errmsg = _("invalid counter access"); 1318 return insn | ((value & 0x1f) << 21); 1319} 1320 1321static long 1322extract_bo (unsigned long insn, 1323 ppc_cpu_t dialect, 1324 int *invalid) 1325{ 1326 long value; 1327 1328 value = (insn >> 21) & 0x1f; 1329 if (!valid_bo (value, dialect, 1)) 1330 *invalid = 1; 1331 return value; 1332} 1333 1334/* The BO field in a B form instruction when the + or - modifier is 1335 used. This is like the BO field, but it must be even. When 1336 extracting it, we force it to be even. */ 1337 1338static unsigned long 1339insert_boe (unsigned long insn, 1340 long value, 1341 ppc_cpu_t dialect, 1342 const char **errmsg) 1343{ 1344 if (!valid_bo (value, dialect, 0)) 1345 *errmsg = _("invalid conditional option"); 1346 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) 1347 *errmsg = _("invalid counter access"); 1348 else if ((value & 1) != 0) 1349 *errmsg = _("attempt to set y bit when using + or - modifier"); 1350 1351 return insn | ((value & 0x1f) << 21); 1352} 1353 1354static long 1355extract_boe (unsigned long insn, 1356 ppc_cpu_t dialect, 1357 int *invalid) 1358{ 1359 long value; 1360 1361 value = (insn >> 21) & 0x1f; 1362 if (!valid_bo (value, dialect, 1)) 1363 *invalid = 1; 1364 return value & 0x1e; 1365} 1366 1367/* The DCMX field in a X form instruction when the field is split 1368 into separate DC, DM and DX fields. */ 1369 1370static unsigned long 1371insert_dcmxs (unsigned long insn, 1372 long value, 1373 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1374 const char **errmsg ATTRIBUTE_UNUSED) 1375{ 1376 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40); 1377} 1378 1379static long 1380extract_dcmxs (unsigned long insn, 1381 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1382 int *invalid ATTRIBUTE_UNUSED) 1383{ 1384 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 1385} 1386 1387/* The D field in a DX form instruction when the field is split 1388 into separate D0, D1 and D2 fields. */ 1389 1390static unsigned long 1391insert_dxd (unsigned long insn, 1392 long value, 1393 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1394 const char **errmsg ATTRIBUTE_UNUSED) 1395{ 1396 return insn | (value & 0xffc1) | ((value & 0x3e) << 15); 1397} 1398 1399static long 1400extract_dxd (unsigned long insn, 1401 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1402 int *invalid ATTRIBUTE_UNUSED) 1403{ 1404 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); 1405 return (dxd ^ 0x8000) - 0x8000; 1406} 1407 1408static unsigned long 1409insert_dxdn (unsigned long insn, 1410 long value, 1411 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1412 const char **errmsg ATTRIBUTE_UNUSED) 1413{ 1414 return insert_dxd (insn, -value, dialect, errmsg); 1415} 1416 1417static long 1418extract_dxdn (unsigned long insn, 1419 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1420 int *invalid ATTRIBUTE_UNUSED) 1421{ 1422 return -extract_dxd (insn, dialect, invalid); 1423} 1424 1425/* FXM mask in mfcr and mtcrf instructions. */ 1426 1427static unsigned long 1428insert_fxm (unsigned long insn, 1429 long value, 1430 ppc_cpu_t dialect, 1431 const char **errmsg) 1432{ 1433 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 1434 one bit of the mask field is set. */ 1435 if ((insn & (1 << 20)) != 0) 1436 { 1437 if (value == 0 || (value & -value) != value) 1438 { 1439 *errmsg = _("invalid mask field"); 1440 value = 0; 1441 } 1442 } 1443 1444 /* If only one bit of the FXM field is set, we can use the new form 1445 of the instruction, which is faster. Unlike the Power4 branch hint 1446 encoding, this is not backward compatible. Do not generate the 1447 new form unless -mpower4 has been given, or -many and the two 1448 operand form of mfcr was used. */ 1449 else if (value > 0 1450 && (value & -value) == value 1451 && ((dialect & PPC_OPCODE_POWER4) != 0 1452 || ((dialect & PPC_OPCODE_ANY) != 0 1453 && (insn & (0x3ff << 1)) == 19 << 1))) 1454 insn |= 1 << 20; 1455 1456 /* Any other value on mfcr is an error. */ 1457 else if ((insn & (0x3ff << 1)) == 19 << 1) 1458 { 1459 /* A value of -1 means we used the one operand form of 1460 mfcr which is valid. */ 1461 if (value != -1) 1462 *errmsg = _("invalid mfcr mask"); 1463 value = 0; 1464 } 1465 1466 return insn | ((value & 0xff) << 12); 1467} 1468 1469static long 1470extract_fxm (unsigned long insn, 1471 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1472 int *invalid) 1473{ 1474 long mask = (insn >> 12) & 0xff; 1475 1476 /* Is this a Power4 insn? */ 1477 if ((insn & (1 << 20)) != 0) 1478 { 1479 /* Exactly one bit of MASK should be set. */ 1480 if (mask == 0 || (mask & -mask) != mask) 1481 *invalid = 1; 1482 } 1483 1484 /* Check that non-power4 form of mfcr has a zero MASK. */ 1485 else if ((insn & (0x3ff << 1)) == 19 << 1) 1486 { 1487 if (mask != 0) 1488 *invalid = 1; 1489 else 1490 mask = -1; 1491 } 1492 1493 return mask; 1494} 1495 1496static unsigned long 1497insert_li20 (unsigned long insn, 1498 long value, 1499 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1500 const char **errmsg ATTRIBUTE_UNUSED) 1501{ 1502 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff); 1503} 1504 1505static long 1506extract_li20 (unsigned long insn, 1507 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1508 int *invalid ATTRIBUTE_UNUSED) 1509{ 1510 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000; 1511 1512 return ext 1513 | (((insn >> 11) & 0xf) << 16) 1514 | (((insn >> 17) & 0xf) << 12) 1515 | (((insn >> 16) & 0x1) << 11) 1516 | (insn & 0x7ff); 1517} 1518 1519/* The 2-bit L field in a SYNC or WC field in a WAIT instruction. 1520 For SYNC, some L values are reserved: 1521 * Value 3 is reserved on newer server cpus. 1522 * Values 2 and 3 are reserved on all other cpus. */ 1523 1524static unsigned long 1525insert_ls (unsigned long insn, 1526 long value, 1527 ppc_cpu_t dialect, 1528 const char **errmsg) 1529{ 1530 /* For SYNC, some L values are illegal. */ 1531 if (((insn >> 1) & 0x3ff) == 598) 1532 { 1533 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; 1534 if (value > max_lvalue) 1535 { 1536 *errmsg = _("illegal L operand value"); 1537 return insn; 1538 } 1539 } 1540 1541 return insn | ((value & 0x3) << 21); 1542} 1543 1544static long 1545extract_ls (unsigned long insn, 1546 ppc_cpu_t dialect, 1547 int *invalid) 1548{ 1549 unsigned long lvalue = (insn >> 21) & 3; 1550 1551 if (((insn >> 1) & 0x3ff) == 598) 1552 { 1553 unsigned long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; 1554 if (lvalue > max_lvalue) 1555 *invalid = 1; 1556 } 1557 return lvalue; 1558} 1559 1560/* The 4-bit E field in a sync instruction that accepts 2 operands. 1561 If ESYNC is non-zero, then the L field must be either 0 or 1 and 1562 the complement of ESYNC-bit2. */ 1563 1564static unsigned long 1565insert_esync (unsigned long insn, 1566 long value, 1567 ppc_cpu_t dialect, 1568 const char **errmsg) 1569{ 1570 unsigned long ls = (insn >> 21) & 0x03; 1571 1572 if (value == 0) 1573 { 1574 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) 1575 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) 1576 *errmsg = _("illegal L operand value"); 1577 return insn; 1578 } 1579 1580 if ((ls & ~0x1) 1581 || (((value >> 1) & 0x1) ^ ls) == 0) 1582 *errmsg = _("incompatible L operand value"); 1583 1584 return insn | ((value & 0xf) << 16); 1585} 1586 1587static long 1588extract_esync (unsigned long insn, 1589 ppc_cpu_t dialect, 1590 int *invalid) 1591{ 1592 unsigned long ls = (insn >> 21) & 0x3; 1593 unsigned long lvalue = (insn >> 16) & 0xf; 1594 1595 if (lvalue == 0) 1596 { 1597 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) 1598 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) 1599 *invalid = 1; 1600 } 1601 else if ((ls & ~0x1) 1602 || (((lvalue >> 1) & 0x1) ^ ls) == 0) 1603 *invalid = 1; 1604 1605 return lvalue; 1606} 1607 1608/* The MB and ME fields in an M form instruction expressed as a single 1609 operand which is itself a bitmask. The extraction function always 1610 marks it as invalid, since we never want to recognize an 1611 instruction which uses a field of this type. */ 1612 1613static unsigned long 1614insert_mbe (unsigned long insn, 1615 long value, 1616 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1617 const char **errmsg) 1618{ 1619 unsigned long uval, mask; 1620 int mb, me, mx, count, last; 1621 1622 uval = value; 1623 1624 if (uval == 0) 1625 { 1626 *errmsg = _("illegal bitmask"); 1627 return insn; 1628 } 1629 1630 mb = 0; 1631 me = 32; 1632 if ((uval & 1) != 0) 1633 last = 1; 1634 else 1635 last = 0; 1636 count = 0; 1637 1638 /* mb: location of last 0->1 transition */ 1639 /* me: location of last 1->0 transition */ 1640 /* count: # transitions */ 1641 1642 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) 1643 { 1644 if ((uval & mask) && !last) 1645 { 1646 ++count; 1647 mb = mx; 1648 last = 1; 1649 } 1650 else if (!(uval & mask) && last) 1651 { 1652 ++count; 1653 me = mx; 1654 last = 0; 1655 } 1656 } 1657 if (me == 0) 1658 me = 32; 1659 1660 if (count != 2 && (count != 0 || ! last)) 1661 *errmsg = _("illegal bitmask"); 1662 1663 return insn | (mb << 6) | ((me - 1) << 1); 1664} 1665 1666static long 1667extract_mbe (unsigned long insn, 1668 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1669 int *invalid) 1670{ 1671 long ret; 1672 int mb, me; 1673 int i; 1674 1675 *invalid = 1; 1676 1677 mb = (insn >> 6) & 0x1f; 1678 me = (insn >> 1) & 0x1f; 1679 if (mb < me + 1) 1680 { 1681 ret = 0; 1682 for (i = mb; i <= me; i++) 1683 ret |= 1L << (31 - i); 1684 } 1685 else if (mb == me + 1) 1686 ret = ~0; 1687 else /* (mb > me + 1) */ 1688 { 1689 ret = ~0; 1690 for (i = me + 1; i < mb; i++) 1691 ret &= ~(1L << (31 - i)); 1692 } 1693 return ret; 1694} 1695 1696/* The MB or ME field in an MD or MDS form instruction. The high bit 1697 is wrapped to the low end. */ 1698 1699static unsigned long 1700insert_mb6 (unsigned long insn, 1701 long value, 1702 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1703 const char **errmsg ATTRIBUTE_UNUSED) 1704{ 1705 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1706} 1707 1708static long 1709extract_mb6 (unsigned long insn, 1710 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1711 int *invalid ATTRIBUTE_UNUSED) 1712{ 1713 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1714} 1715 1716/* The NB field in an X form instruction. The value 32 is stored as 1717 0. */ 1718 1719static long 1720extract_nb (unsigned long insn, 1721 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1722 int *invalid ATTRIBUTE_UNUSED) 1723{ 1724 long ret; 1725 1726 ret = (insn >> 11) & 0x1f; 1727 if (ret == 0) 1728 ret = 32; 1729 return ret; 1730} 1731 1732/* The NB field in an lswi instruction, which has special value 1733 restrictions. The value 32 is stored as 0. */ 1734 1735static unsigned long 1736insert_nbi (unsigned long insn, 1737 long value, 1738 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1739 const char **errmsg ATTRIBUTE_UNUSED) 1740{ 1741 long rtvalue = (insn & RT_MASK) >> 21; 1742 long ravalue = (insn & RA_MASK) >> 16; 1743 1744 if (value == 0) 1745 value = 32; 1746 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 1747 : ravalue)) 1748 *errmsg = _("address register in load range"); 1749 return insn | ((value & 0x1f) << 11); 1750} 1751 1752/* The NSI field in a D form instruction. This is the same as the SI 1753 field, only negated. The extraction function always marks it as 1754 invalid, since we never want to recognize an instruction which uses 1755 a field of this type. */ 1756 1757static unsigned long 1758insert_nsi (unsigned long insn, 1759 long value, 1760 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1761 const char **errmsg ATTRIBUTE_UNUSED) 1762{ 1763 return insn | (-value & 0xffff); 1764} 1765 1766static long 1767extract_nsi (unsigned long insn, 1768 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1769 int *invalid) 1770{ 1771 *invalid = 1; 1772 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1773} 1774 1775/* The RA field in a D or X form instruction which is an updating 1776 load, which means that the RA field may not be zero and may not 1777 equal the RT field. */ 1778 1779static unsigned long 1780insert_ral (unsigned long insn, 1781 long value, 1782 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1783 const char **errmsg) 1784{ 1785 if (value == 0 1786 || (unsigned long) value == ((insn >> 21) & 0x1f)) 1787 *errmsg = "invalid register operand when updating"; 1788 return insn | ((value & 0x1f) << 16); 1789} 1790 1791static long 1792extract_ral (unsigned long insn, 1793 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1794 int *invalid) 1795{ 1796 long rtvalue = (insn >> 21) & 0x1f; 1797 long ravalue = (insn >> 16) & 0x1f; 1798 1799 if (rtvalue == ravalue || ravalue == 0) 1800 *invalid = 1; 1801 return ravalue; 1802} 1803 1804/* The RA field in an lmw instruction, which has special value 1805 restrictions. */ 1806 1807static unsigned long 1808insert_ram (unsigned long insn, 1809 long value, 1810 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1811 const char **errmsg) 1812{ 1813 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1814 *errmsg = _("index register in load range"); 1815 return insn | ((value & 0x1f) << 16); 1816} 1817 1818static long 1819extract_ram (unsigned long insn, 1820 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1821 int *invalid) 1822{ 1823 unsigned long rtvalue = (insn >> 21) & 0x1f; 1824 unsigned long ravalue = (insn >> 16) & 0x1f; 1825 1826 if (ravalue >= rtvalue) 1827 *invalid = 1; 1828 return ravalue; 1829} 1830 1831/* The RA field in the DQ form lq or an lswx instruction, which have special 1832 value restrictions. */ 1833 1834static unsigned long 1835insert_raq (unsigned long insn, 1836 long value, 1837 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1838 const char **errmsg) 1839{ 1840 long rtvalue = (insn & RT_MASK) >> 21; 1841 1842 if (value == rtvalue) 1843 *errmsg = _("source and target register operands must be different"); 1844 return insn | ((value & 0x1f) << 16); 1845} 1846 1847static long 1848extract_raq (unsigned long insn, 1849 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1850 int *invalid) 1851{ 1852 unsigned long rtvalue = (insn >> 21) & 0x1f; 1853 unsigned long ravalue = (insn >> 16) & 0x1f; 1854 1855 if (ravalue == rtvalue) 1856 *invalid = 1; 1857 return ravalue; 1858} 1859 1860/* The RA field in a D or X form instruction which is an updating 1861 store or an updating floating point load, which means that the RA 1862 field may not be zero. */ 1863 1864static unsigned long 1865insert_ras (unsigned long insn, 1866 long value, 1867 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1868 const char **errmsg) 1869{ 1870 if (value == 0) 1871 *errmsg = _("invalid register operand when updating"); 1872 return insn | ((value & 0x1f) << 16); 1873} 1874 1875static long 1876extract_ras (unsigned long insn, 1877 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1878 int *invalid) 1879{ 1880 unsigned long ravalue = (insn >> 16) & 0x1f; 1881 1882 if (ravalue == 0) 1883 *invalid = 1; 1884 return ravalue; 1885} 1886 1887/* The RB field in an X form instruction when it must be the same as 1888 the RS field in the instruction. This is used for extended 1889 mnemonics like mr. This operand is marked FAKE. The insertion 1890 function just copies the BT field into the BA field, and the 1891 extraction function just checks that the fields are the same. */ 1892 1893static unsigned long 1894insert_rbs (unsigned long insn, 1895 long value ATTRIBUTE_UNUSED, 1896 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1897 const char **errmsg ATTRIBUTE_UNUSED) 1898{ 1899 return insn | (((insn >> 21) & 0x1f) << 11); 1900} 1901 1902static long 1903extract_rbs (unsigned long insn, 1904 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1905 int *invalid) 1906{ 1907 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1908 *invalid = 1; 1909 return 0; 1910} 1911 1912/* The RB field in an lswx instruction, which has special value 1913 restrictions. */ 1914 1915static unsigned long 1916insert_rbx (unsigned long insn, 1917 long value, 1918 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1919 const char **errmsg) 1920{ 1921 long rtvalue = (insn & RT_MASK) >> 21; 1922 1923 if (value == rtvalue) 1924 *errmsg = _("source and target register operands must be different"); 1925 return insn | ((value & 0x1f) << 11); 1926} 1927 1928static long 1929extract_rbx (unsigned long insn, 1930 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1931 int *invalid) 1932{ 1933 unsigned long rtvalue = (insn >> 21) & 0x1f; 1934 unsigned long rbvalue = (insn >> 11) & 0x1f; 1935 1936 if (rbvalue == rtvalue) 1937 *invalid = 1; 1938 return rbvalue; 1939} 1940 1941/* The SCI8 field is made up of SCL and {U,N}I8 fields. */ 1942static unsigned long 1943insert_sci8 (unsigned long insn, 1944 long value, 1945 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1946 const char **errmsg) 1947{ 1948 unsigned int fill_scale = 0; 1949 unsigned long ui8 = value; 1950 1951 if ((ui8 & 0xffffff00) == 0) 1952 ; 1953 else if ((ui8 & 0xffffff00) == 0xffffff00) 1954 fill_scale = 0x400; 1955 else if ((ui8 & 0xffff00ff) == 0) 1956 { 1957 fill_scale = 1 << 8; 1958 ui8 >>= 8; 1959 } 1960 else if ((ui8 & 0xffff00ff) == 0xffff00ff) 1961 { 1962 fill_scale = 0x400 | (1 << 8); 1963 ui8 >>= 8; 1964 } 1965 else if ((ui8 & 0xff00ffff) == 0) 1966 { 1967 fill_scale = 2 << 8; 1968 ui8 >>= 16; 1969 } 1970 else if ((ui8 & 0xff00ffff) == 0xff00ffff) 1971 { 1972 fill_scale = 0x400 | (2 << 8); 1973 ui8 >>= 16; 1974 } 1975 else if ((ui8 & 0x00ffffff) == 0) 1976 { 1977 fill_scale = 3 << 8; 1978 ui8 >>= 24; 1979 } 1980 else if ((ui8 & 0x00ffffff) == 0x00ffffff) 1981 { 1982 fill_scale = 0x400 | (3 << 8); 1983 ui8 >>= 24; 1984 } 1985 else 1986 { 1987 *errmsg = _("illegal immediate value"); 1988 ui8 = 0; 1989 } 1990 1991 return insn | fill_scale | (ui8 & 0xff); 1992} 1993 1994static long 1995extract_sci8 (unsigned long insn, 1996 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1997 int *invalid ATTRIBUTE_UNUSED) 1998{ 1999 int fill = insn & 0x400; 2000 int scale_factor = (insn & 0x300) >> 5; 2001 long value = (insn & 0xff) << scale_factor; 2002 2003 if (fill != 0) 2004 value |= ~((long) 0xff << scale_factor); 2005 return value; 2006} 2007 2008static unsigned long 2009insert_sci8n (unsigned long insn, 2010 long value, 2011 ppc_cpu_t dialect, 2012 const char **errmsg) 2013{ 2014 return insert_sci8 (insn, -value, dialect, errmsg); 2015} 2016 2017static long 2018extract_sci8n (unsigned long insn, 2019 ppc_cpu_t dialect, 2020 int *invalid) 2021{ 2022 return -extract_sci8 (insn, dialect, invalid); 2023} 2024 2025static unsigned long 2026insert_sd4h (unsigned long insn, 2027 long value, 2028 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2029 const char **errmsg ATTRIBUTE_UNUSED) 2030{ 2031 return insn | ((value & 0x1e) << 7); 2032} 2033 2034static long 2035extract_sd4h (unsigned long insn, 2036 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2037 int *invalid ATTRIBUTE_UNUSED) 2038{ 2039 return ((insn >> 8) & 0xf) << 1; 2040} 2041 2042static unsigned long 2043insert_sd4w (unsigned long insn, 2044 long value, 2045 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2046 const char **errmsg ATTRIBUTE_UNUSED) 2047{ 2048 return insn | ((value & 0x3c) << 6); 2049} 2050 2051static long 2052extract_sd4w (unsigned long insn, 2053 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2054 int *invalid ATTRIBUTE_UNUSED) 2055{ 2056 return ((insn >> 8) & 0xf) << 2; 2057} 2058 2059static unsigned long 2060insert_oimm (unsigned long insn, 2061 long value, 2062 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2063 const char **errmsg ATTRIBUTE_UNUSED) 2064{ 2065 return insn | (((value - 1) & 0x1f) << 4); 2066} 2067 2068static long 2069extract_oimm (unsigned long insn, 2070 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2071 int *invalid ATTRIBUTE_UNUSED) 2072{ 2073 return ((insn >> 4) & 0x1f) + 1; 2074} 2075 2076/* The SH field in an MD form instruction. This is split. */ 2077 2078static unsigned long 2079insert_sh6 (unsigned long insn, 2080 long value, 2081 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2082 const char **errmsg ATTRIBUTE_UNUSED) 2083{ 2084 /* SH6 operand in the rldixor instructions. */ 2085 if (PPC_OP (insn) == 4) 2086 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); 2087 else 2088 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 2089} 2090 2091static long 2092extract_sh6 (unsigned long insn, 2093 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2094 int *invalid ATTRIBUTE_UNUSED) 2095{ 2096 /* SH6 operand in the rldixor instructions. */ 2097 if (PPC_OP (insn) == 4) 2098 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); 2099 else 2100 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 2101} 2102 2103/* The SPR field in an XFX form instruction. This is flipped--the 2104 lower 5 bits are stored in the upper 5 and vice- versa. */ 2105 2106static unsigned long 2107insert_spr (unsigned long insn, 2108 long value, 2109 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2110 const char **errmsg ATTRIBUTE_UNUSED) 2111{ 2112 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2113} 2114 2115static long 2116extract_spr (unsigned long insn, 2117 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2118 int *invalid ATTRIBUTE_UNUSED) 2119{ 2120 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2121} 2122 2123/* Some dialects have 8 SPRG registers instead of the standard 4. */ 2124#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) 2125 2126static unsigned long 2127insert_sprg (unsigned long insn, 2128 long value, 2129 ppc_cpu_t dialect, 2130 const char **errmsg) 2131{ 2132 if (value > 7 2133 || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) 2134 *errmsg = _("invalid sprg number"); 2135 2136 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 2137 user mode. Anything else must use spr 272..279. */ 2138 if (value <= 3 || (insn & 0x100) != 0) 2139 value |= 0x10; 2140 2141 return insn | ((value & 0x17) << 16); 2142} 2143 2144static long 2145extract_sprg (unsigned long insn, 2146 ppc_cpu_t dialect, 2147 int *invalid) 2148{ 2149 unsigned long val = (insn >> 16) & 0x1f; 2150 2151 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 2152 If not BOOKE, 405 or VLE, then both use only 272..275. */ 2153 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) 2154 || (val - 0x10 > 7 && (insn & 0x100) != 0) 2155 || val <= 3 2156 || (val & 8) != 0) 2157 *invalid = 1; 2158 return val & 7; 2159} 2160 2161/* The TBR field in an XFX instruction. This is just like SPR, but it 2162 is optional. */ 2163 2164static unsigned long 2165insert_tbr (unsigned long insn, 2166 long value, 2167 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2168 const char **errmsg) 2169{ 2170 if (value != 268 && value != 269) 2171 *errmsg = _("invalid tbr number"); 2172 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2173} 2174 2175static long 2176extract_tbr (unsigned long insn, 2177 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2178 int *invalid) 2179{ 2180 long ret; 2181 2182 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2183 if (ret != 268 && ret != 269) 2184 *invalid = 1; 2185 return ret; 2186} 2187 2188/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 2189 2190static unsigned long 2191insert_xt6 (unsigned long insn, 2192 long value, 2193 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2194 const char **errmsg ATTRIBUTE_UNUSED) 2195{ 2196 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); 2197} 2198 2199static long 2200extract_xt6 (unsigned long insn, 2201 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2202 int *invalid ATTRIBUTE_UNUSED) 2203{ 2204 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); 2205} 2206 2207/* The XT and XS fields in an DQ form VSX instruction. This is split. */ 2208static unsigned long 2209insert_xtq6 (unsigned long insn, 2210 long value, 2211 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2212 const char **errmsg ATTRIBUTE_UNUSED) 2213{ 2214 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); 2215} 2216 2217static long 2218extract_xtq6 (unsigned long insn, 2219 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2220 int *invalid ATTRIBUTE_UNUSED) 2221{ 2222 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); 2223} 2224 2225/* The XA field in an XX3 form instruction. This is split. */ 2226 2227static unsigned long 2228insert_xa6 (unsigned long insn, 2229 long value, 2230 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2231 const char **errmsg ATTRIBUTE_UNUSED) 2232{ 2233 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); 2234} 2235 2236static long 2237extract_xa6 (unsigned long insn, 2238 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2239 int *invalid ATTRIBUTE_UNUSED) 2240{ 2241 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 2242} 2243 2244/* The XB field in an XX3 form instruction. This is split. */ 2245 2246static unsigned long 2247insert_xb6 (unsigned long insn, 2248 long value, 2249 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2250 const char **errmsg ATTRIBUTE_UNUSED) 2251{ 2252 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 2253} 2254 2255static long 2256extract_xb6 (unsigned long insn, 2257 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2258 int *invalid ATTRIBUTE_UNUSED) 2259{ 2260 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); 2261} 2262 2263/* The XB field in an XX3 form instruction when it must be the same as 2264 the XA field in the instruction. This is used for extended 2265 mnemonics like xvmovdp. This operand is marked FAKE. The insertion 2266 function just copies the XA field into the XB field, and the 2267 extraction function just checks that the fields are the same. */ 2268 2269static unsigned long 2270insert_xb6s (unsigned long insn, 2271 long value ATTRIBUTE_UNUSED, 2272 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2273 const char **errmsg ATTRIBUTE_UNUSED) 2274{ 2275 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); 2276} 2277 2278static long 2279extract_xb6s (unsigned long insn, 2280 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2281 int *invalid) 2282{ 2283 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 2284 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) 2285 *invalid = 1; 2286 return 0; 2287} 2288 2289/* The XC field in an XX4 form instruction. This is split. */ 2290 2291static unsigned long 2292insert_xc6 (unsigned long insn, 2293 long value, 2294 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2295 const char **errmsg ATTRIBUTE_UNUSED) 2296{ 2297 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); 2298} 2299 2300static long 2301extract_xc6 (unsigned long insn, 2302 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2303 int *invalid ATTRIBUTE_UNUSED) 2304{ 2305 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); 2306} 2307 2308static unsigned long 2309insert_dm (unsigned long insn, 2310 long value, 2311 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2312 const char **errmsg) 2313{ 2314 if (value != 0 && value != 1) 2315 *errmsg = _("invalid constant"); 2316 return insn | (((value) ? 3 : 0) << 8); 2317} 2318 2319static long 2320extract_dm (unsigned long insn, 2321 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2322 int *invalid) 2323{ 2324 long value; 2325 2326 value = (insn >> 8) & 3; 2327 if (value != 0 && value != 3) 2328 *invalid = 1; 2329 return (value) ? 1 : 0; 2330} 2331 2332/* The VLESIMM field in an I16A form instruction. This is split. */ 2333 2334static unsigned long 2335insert_vlesi (unsigned long insn, 2336 long value, 2337 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2338 const char **errmsg ATTRIBUTE_UNUSED) 2339{ 2340 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2341} 2342 2343static long 2344extract_vlesi (unsigned long insn, 2345 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2346 int *invalid ATTRIBUTE_UNUSED) 2347{ 2348 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2349 value = (value ^ 0x8000) - 0x8000; 2350 return value; 2351} 2352 2353static unsigned long 2354insert_vlensi (unsigned long insn, 2355 long value, 2356 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2357 const char **errmsg ATTRIBUTE_UNUSED) 2358{ 2359 value = -value; 2360 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2361} 2362static long 2363extract_vlensi (unsigned long insn, 2364 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2365 int *invalid ATTRIBUTE_UNUSED) 2366{ 2367 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2368 value = (value ^ 0x8000) - 0x8000; 2369 /* Don't use for disassembly. */ 2370 *invalid = 1; 2371 return -value; 2372} 2373 2374/* The VLEUIMM field in an I16A form instruction. This is split. */ 2375 2376static unsigned long 2377insert_vleui (unsigned long insn, 2378 long value, 2379 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2380 const char **errmsg ATTRIBUTE_UNUSED) 2381{ 2382 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2383} 2384 2385static long 2386extract_vleui (unsigned long insn, 2387 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2388 int *invalid ATTRIBUTE_UNUSED) 2389{ 2390 return ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2391} 2392 2393/* The VLEUIMML field in an I16L form instruction. This is split. */ 2394 2395static unsigned long 2396insert_vleil (unsigned long insn, 2397 long value, 2398 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2399 const char **errmsg ATTRIBUTE_UNUSED) 2400{ 2401 return insn | ((value & 0xf800) << 5) | (value & 0x7ff); 2402} 2403 2404static long 2405extract_vleil (unsigned long insn, 2406 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2407 int *invalid ATTRIBUTE_UNUSED) 2408{ 2409 return ((insn >> 5) & 0xf800) | (insn & 0x7ff); 2410} 2411 2412 2413/* Macros used to form opcodes. */ 2414 2415/* The main opcode. */ 2416#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) 2417#define OP_MASK OP (0x3f) 2418 2419/* The main opcode combined with a trap code in the TO field of a D 2420 form instruction. Used for extended mnemonics for the trap 2421 instructions. */ 2422#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) 2423#define OPTO_MASK (OP_MASK | TO_MASK) 2424 2425/* The main opcode combined with a comparison size bit in the L field 2426 of a D form or X form instruction. Used for extended mnemonics for 2427 the comparison instructions. */ 2428#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 2429#define OPL_MASK OPL (0x3f,1) 2430 2431/* The main opcode combined with an update code in D form instruction. 2432 Used for extended mnemonics for VLE memory instructions. */ 2433#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8)) 2434#define OPVUP_MASK OPVUP (0x3f, 0xff) 2435 2436/* The main opcode combined with an update code and the RT fields specified in 2437 D form instruction. Used for VLE volatile context save/restore 2438 instructions. */ 2439#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21)) 2440#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) 2441 2442/* An A form instruction. */ 2443#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 2444#define A_MASK A (0x3f, 0x1f, 1) 2445 2446/* An A_MASK with the FRB field fixed. */ 2447#define AFRB_MASK (A_MASK | FRB_MASK) 2448 2449/* An A_MASK with the FRC field fixed. */ 2450#define AFRC_MASK (A_MASK | FRC_MASK) 2451 2452/* An A_MASK with the FRA and FRC fields fixed. */ 2453#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 2454 2455/* An AFRAFRC_MASK, but with L bit clear. */ 2456#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) 2457 2458/* A B form instruction. */ 2459#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 2460#define B_MASK B (0x3f, 1, 1) 2461 2462/* A BD8 form instruction. This is a 16-bit instruction. */ 2463#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8)) 2464#define BD8_MASK BD8 (0x3f, 1, 1) 2465 2466/* Another BD8 form instruction. This is a 16-bit instruction. */ 2467#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11) 2468#define BD8IO_MASK BD8IO (0x1f) 2469 2470/* A BD8 form instruction for simplified mnemonics. */ 2471#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) 2472/* A mask that excludes BO32 and BI32. */ 2473#define EBD8IO1_MASK 0xf800 2474/* A mask that includes BO32 and excludes BI32. */ 2475#define EBD8IO2_MASK 0xfc00 2476/* A mask that include BO32 AND BI32. */ 2477#define EBD8IO3_MASK 0xff00 2478 2479/* A BD15 form instruction. */ 2480#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1)) 2481#define BD15_MASK BD15 (0x3f, 0xf, 1) 2482 2483/* A BD15 form instruction for extended conditional branch mnemonics. */ 2484#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1) 2485#define EBD15_MASK 0xfff00001 2486 2487/* A BD15 form instruction for extended conditional branch mnemonics with BI. */ 2488#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \ 2489 | (((aa) & 0xf) << 22) \ 2490 | (((bo) & 0x3) << 20) \ 2491 | (((bi) & 0x3) << 16) \ 2492 | ((lk) & 1) 2493#define EBD15BI_MASK 0xfff30001 2494 2495/* A BD24 form instruction. */ 2496#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1)) 2497#define BD24_MASK BD24 (0x3f, 1, 1) 2498 2499/* A B form instruction setting the BO field. */ 2500#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2501#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 2502 2503/* A BBO_MASK with the y bit of the BO field removed. This permits 2504 matching a conditional branch regardless of the setting of the y 2505 bit. Similarly for the 'at' bits used for power4 branch hints. */ 2506#define Y_MASK (((unsigned long) 1) << 21) 2507#define AT1_MASK (((unsigned long) 3) << 21) 2508#define AT2_MASK (((unsigned long) 9) << 21) 2509#define BBOY_MASK (BBO_MASK &~ Y_MASK) 2510#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 2511 2512/* A B form instruction setting the BO field and the condition bits of 2513 the BI field. */ 2514#define BBOCB(op, bo, cb, aa, lk) \ 2515 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) 2516#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 2517 2518/* A BBOCB_MASK with the y bit of the BO field removed. */ 2519#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 2520#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 2521#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 2522 2523/* A BBOYCB_MASK in which the BI field is fixed. */ 2524#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 2525#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 2526 2527/* A VLE C form instruction. */ 2528#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1)) 2529#define C_LK_MASK C_LK(0x7fff, 1) 2530#define C(x) ((((unsigned long)(x)) & 0xffff)) 2531#define C_MASK C(0xffff) 2532 2533/* An Context form instruction. */ 2534#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 2535#define CTX_MASK CTX(0x3f, 0x7) 2536 2537/* An User Context form instruction. */ 2538#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 2539#define UCTX_MASK UCTX(0x3f, 0x1f) 2540 2541/* The main opcode mask with the RA field clear. */ 2542#define DRA_MASK (OP_MASK | RA_MASK) 2543 2544/* A DQ form VSX instruction. */ 2545#define DQX(op, xop) (OP (op) | ((xop) & 0x7)) 2546#define DQX_MASK DQX (0x3f, 7) 2547 2548/* A DS form instruction. */ 2549#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 2550#define DS_MASK DSO (0x3f, 3) 2551 2552/* An DX form instruction. */ 2553#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2554#define DX_MASK DX (0x3f, 0x1f) 2555/* An DX form instruction with the D bits specified. */ 2556#define NODX_MASK (DX_MASK | 0x1fffc1) 2557 2558/* An EVSEL form instruction. */ 2559#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 2560#define EVSEL_MASK EVSEL(0x3f, 0xff) 2561 2562/* An IA16 form instruction. */ 2563#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) 2564#define IA16_MASK IA16(0x3f, 0x1f) 2565 2566/* An I16A form instruction. */ 2567#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) 2568#define I16A_MASK I16A(0x3f, 0x1f) 2569 2570/* An I16L form instruction. */ 2571#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) 2572#define I16L_MASK I16L(0x3f, 0x1f) 2573 2574/* An IM7 form instruction. */ 2575#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11) 2576#define IM7_MASK IM7(0x1f) 2577 2578/* An M form instruction. */ 2579#define M(op, rc) (OP (op) | ((rc) & 1)) 2580#define M_MASK M (0x3f, 1) 2581 2582/* An LI20 form instruction. */ 2583#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15) 2584#define LI20_MASK LI20(0x3f, 0x1) 2585 2586/* An M form instruction with the ME field specified. */ 2587#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 2588 2589/* An M_MASK with the MB and ME fields fixed. */ 2590#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 2591 2592/* An M_MASK with the SH and ME fields fixed. */ 2593#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 2594 2595/* An MD form instruction. */ 2596#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) 2597#define MD_MASK MD (0x3f, 0x7, 1) 2598 2599/* An MD_MASK with the MB field fixed. */ 2600#define MDMB_MASK (MD_MASK | MB6_MASK) 2601 2602/* An MD_MASK with the SH field fixed. */ 2603#define MDSH_MASK (MD_MASK | SH6_MASK) 2604 2605/* An MDS form instruction. */ 2606#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) 2607#define MDS_MASK MDS (0x3f, 0xf, 1) 2608 2609/* An MDS_MASK with the MB field fixed. */ 2610#define MDSMB_MASK (MDS_MASK | MB6_MASK) 2611 2612/* An SC form instruction. */ 2613#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 2614#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 2615 2616/* An SCI8 form instruction. */ 2617#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11)) 2618#define SCI8_MASK SCI8(0x3f, 0x1f) 2619 2620/* An SCI8 form instruction. */ 2621#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23)) 2622#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) 2623 2624/* An SD4 form instruction. This is a 16-bit instruction. */ 2625#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) 2626#define SD4_MASK SD4(0xf) 2627 2628/* An SE_IM5 form instruction. This is a 16-bit instruction. */ 2629#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9)) 2630#define SE_IM5_MASK SE_IM5(0x3f, 1) 2631 2632/* An SE_R form instruction. This is a 16-bit instruction. */ 2633#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4)) 2634#define SE_R_MASK SE_R(0x3f, 0x3f) 2635 2636/* An SE_RR form instruction. This is a 16-bit instruction. */ 2637#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8)) 2638#define SE_RR_MASK SE_RR(0x3f, 3) 2639 2640/* A VX form instruction. */ 2641#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 2642 2643/* The mask for an VX form instruction. */ 2644#define VX_MASK VX(0x3f, 0x7ff) 2645 2646/* A VX_MASK with the VA field fixed. */ 2647#define VXVA_MASK (VX_MASK | (0x1f << 16)) 2648 2649/* A VX_MASK with the VB field fixed. */ 2650#define VXVB_MASK (VX_MASK | (0x1f << 11)) 2651 2652/* A VX_MASK with the VA and VB fields fixed. */ 2653#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) 2654 2655/* A VX_MASK with the VD and VA fields fixed. */ 2656#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) 2657 2658/* A VX_MASK with a UIMM4 field. */ 2659#define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) 2660 2661/* A VX_MASK with a UIMM3 field. */ 2662#define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) 2663 2664/* A VX_MASK with a UIMM2 field. */ 2665#define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) 2666 2667/* A VX_MASK with a PS field. */ 2668#define VXPS_MASK (VX_MASK & ~(0x1 << 9)) 2669 2670/* A VX_MASK with the VA field fixed with a PS field. */ 2671#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) 2672 2673/* A VA form instruction. */ 2674#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 2675 2676/* The mask for an VA form instruction. */ 2677#define VXA_MASK VXA(0x3f, 0x3f) 2678 2679/* A VXA_MASK with a SHB field. */ 2680#define VXASHB_MASK (VXA_MASK | (1 << 10)) 2681 2682/* A VXR form instruction. */ 2683#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 2684 2685/* The mask for a VXR form instruction. */ 2686#define VXR_MASK VXR(0x3f, 0x3ff, 1) 2687 2688/* A VX form instruction with a VA tertiary opcode. */ 2689#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) 2690 2691#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2692#define VXASH_MASK VXASH (0x3f, 0x1f) 2693 2694/* An X form instruction. */ 2695#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2696 2697/* A X form instruction for Quad-Precision FP Instructions. */ 2698#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) 2699 2700/* An EX form instruction. */ 2701#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 2702 2703/* The mask for an EX form instruction. */ 2704#define EX_MASK EX (0x3f, 0x7ff) 2705 2706/* An XX2 form instruction. */ 2707#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) 2708 2709/* A XX2 form instruction with the VA bits specified. */ 2710#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) 2711 2712/* An XX3 form instruction. */ 2713#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) 2714 2715/* An XX3 form instruction with the RC bit specified. */ 2716#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) 2717 2718/* An XX4 form instruction. */ 2719#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) 2720 2721/* A Z form instruction. */ 2722#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 2723 2724/* An X form instruction with the RC bit specified. */ 2725#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 2726 2727/* A X form instruction for Quad-Precision FP Instructions with RC bit. */ 2728#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) 2729 2730/* An X form instruction with the RA bits specified as two ops. */ 2731#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16) 2732 2733/* A Z form instruction with the RC bit specified. */ 2734#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 2735 2736/* The mask for an X form instruction. */ 2737#define X_MASK XRC (0x3f, 0x3ff, 1) 2738 2739/* The mask for an X form instruction with the BF bits specified. */ 2740#define XBF_MASK (X_MASK | (3 << 21)) 2741 2742/* An X form wait instruction with everything filled in except the WC field. */ 2743#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 2744 2745/* The mask for an XX1 form instruction. */ 2746#define XX1_MASK X (0x3f, 0x3ff) 2747 2748/* An XX1_MASK with the RB field fixed. */ 2749#define XX1RB_MASK (XX1_MASK | RB_MASK) 2750 2751/* The mask for an XX2 form instruction. */ 2752#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) 2753 2754/* The mask for an XX2 form instruction with the UIM bits specified. */ 2755#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) 2756 2757/* The mask for an XX2 form instruction with the 4 UIM bits specified. */ 2758#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) 2759 2760/* The mask for an XX2 form instruction with the BF bits specified. */ 2761#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) 2762 2763/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */ 2764#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) 2765 2766/* The mask for an XX2 form instruction with a split DCMX bits specified. */ 2767#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) 2768 2769/* The mask for an XX3 form instruction. */ 2770#define XX3_MASK XX3 (0x3f, 0xff) 2771 2772/* The mask for an XX3 form instruction with the BF bits specified. */ 2773#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) 2774 2775/* The mask for an XX3 form instruction with the DM or SHW bits specified. */ 2776#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) 2777#define XX3SHW_MASK XX3DM_MASK 2778 2779/* The mask for an XX4 form instruction. */ 2780#define XX4_MASK XX4 (0x3f, 0x3) 2781 2782/* An X form wait instruction with everything filled in except the WC field. */ 2783#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 2784 2785/* The mask for an XMMF form instruction. */ 2786#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) 2787 2788/* The mask for a Z form instruction. */ 2789#define Z_MASK ZRC (0x3f, 0x1ff, 1) 2790#define Z2_MASK ZRC (0x3f, 0xff, 1) 2791 2792/* An X_MASK with the RA/VA field fixed. */ 2793#define XRA_MASK (X_MASK | RA_MASK) 2794#define XVA_MASK XRA_MASK 2795 2796/* An XRA_MASK with the A_L/W field clear. */ 2797#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) 2798#define XRLA_MASK XWRA_MASK 2799 2800/* An X_MASK with the RB field fixed. */ 2801#define XRB_MASK (X_MASK | RB_MASK) 2802 2803/* An X_MASK with the RT field fixed. */ 2804#define XRT_MASK (X_MASK | RT_MASK) 2805 2806/* An XRT_MASK mask with the L bits clear. */ 2807#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) 2808 2809/* An X_MASK with the RA and RB fields fixed. */ 2810#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 2811 2812/* An XBF_MASK with the RA and RB fields fixed. */ 2813#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) 2814 2815/* An XRARB_MASK, but with the L bit clear. */ 2816#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 2817 2818/* An XRARB_MASK, but with the L bits in a darn instruction clear. */ 2819#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16)) 2820 2821/* An X_MASK with the RT and RA fields fixed. */ 2822#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 2823 2824/* An X_MASK with the RT and RB fields fixed. */ 2825#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) 2826 2827/* An XRTRA_MASK, but with L bit clear. */ 2828#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 2829 2830/* An X_MASK with the RT, RA and RB fields fixed. */ 2831#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) 2832 2833/* An XRTRARB_MASK, but with L bit clear. */ 2834#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21)) 2835 2836/* An XRTRARB_MASK, but with A bit clear. */ 2837#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25)) 2838 2839/* An XRTRARB_MASK, but with BF bits clear. */ 2840#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23)) 2841 2842/* An X form instruction with the L bit specified. */ 2843#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 2844 2845/* An X form instruction with the L bits specified. */ 2846#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 2847 2848/* An X form instruction with the L bit and RC bit specified. */ 2849#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21)) 2850 2851/* An X form instruction with RT fields specified */ 2852#define XRT(op, xop, rt) (X ((op), (xop)) \ 2853 | ((((unsigned long)(rt)) & 0x1f) << 21)) 2854 2855/* An X form instruction with RT and RA fields specified */ 2856#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ 2857 | ((((unsigned long)(rt)) & 0x1f) << 21) \ 2858 | ((((unsigned long)(ra)) & 0x1f) << 16)) 2859 2860/* The mask for an X form comparison instruction. */ 2861#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 2862 2863/* The mask for an X form comparison instruction with the L field 2864 fixed. */ 2865#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) 2866 2867/* An X form trap instruction with the TO field specified. */ 2868#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) 2869#define XTO_MASK (X_MASK | TO_MASK) 2870 2871/* An X form tlb instruction with the SH field specified. */ 2872#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) 2873#define XTLB_MASK (X_MASK | SH_MASK) 2874 2875/* An X form sync instruction. */ 2876#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 2877 2878/* An X form sync instruction with everything filled in except the LS field. */ 2879#define XSYNC_MASK (0xff9fffff) 2880 2881/* An X form sync instruction with everything filled in except the L and E fields. */ 2882#define XSYNCLE_MASK (0xff90ffff) 2883 2884/* An X_MASK, but with the EH bit clear. */ 2885#define XEH_MASK (X_MASK & ~((unsigned long )1)) 2886 2887/* An X form AltiVec dss instruction. */ 2888#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 2889#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 2890 2891/* An XFL form instruction. */ 2892#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 2893#define XFL_MASK XFL (0x3f, 0x3ff, 1) 2894 2895/* An X form isel instruction. */ 2896#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2897#define XISEL_MASK XISEL(0x3f, 0x1f) 2898 2899/* An XL form instruction with the LK field set to 0. */ 2900#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2901 2902/* An XL form instruction which uses the LK field. */ 2903#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 2904 2905/* The mask for an XL form instruction. */ 2906#define XL_MASK XLLK (0x3f, 0x3ff, 1) 2907 2908/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ 2909#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) 2910 2911/* An XL form instruction which explicitly sets the BO field. */ 2912#define XLO(op, bo, xop, lk) \ 2913 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2914#define XLO_MASK (XL_MASK | BO_MASK) 2915 2916/* An XL form instruction which explicitly sets the y bit of the BO 2917 field. */ 2918#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) 2919#define XLYLK_MASK (XL_MASK | Y_MASK) 2920 2921/* An XL form instruction which sets the BO field and the condition 2922 bits of the BI field. */ 2923#define XLOCB(op, bo, cb, xop, lk) \ 2924 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) 2925#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 2926 2927/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 2928#define XLBB_MASK (XL_MASK | BB_MASK) 2929#define XLYBB_MASK (XLYLK_MASK | BB_MASK) 2930#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 2931 2932/* A mask for branch instructions using the BH field. */ 2933#define XLBH_MASK (XL_MASK | (0x1c << 11)) 2934 2935/* An XL_MASK with the BO and BB fields fixed. */ 2936#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 2937 2938/* An XL_MASK with the BO, BI and BB fields fixed. */ 2939#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 2940 2941/* An X form mbar instruction with MO field. */ 2942#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21)) 2943 2944/* An XO form instruction. */ 2945#define XO(op, xop, oe, rc) \ 2946 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 2947#define XO_MASK XO (0x3f, 0x1ff, 1, 1) 2948 2949/* An XO_MASK with the RB field fixed. */ 2950#define XORB_MASK (XO_MASK | RB_MASK) 2951 2952/* An XOPS form instruction for paired singles. */ 2953#define XOPS(op, xop, rc) \ 2954 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 2955#define XOPS_MASK XOPS (0x3f, 0x3ff, 1) 2956 2957 2958/* An XS form instruction. */ 2959#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 2960#define XS_MASK XS (0x3f, 0x1ff, 1) 2961 2962/* A mask for the FXM version of an XFX form instruction. */ 2963#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 2964 2965/* An XFX form instruction with the FXM field filled in. */ 2966#define XFXM(op, xop, fxm, p4) \ 2967 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ 2968 | ((unsigned long)(p4) << 20)) 2969 2970/* An XFX form instruction with the SPR field filled in. */ 2971#define XSPR(op, xop, spr) \ 2972 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) 2973#define XSPR_MASK (X_MASK | SPR_MASK) 2974 2975/* An XFX form instruction with the SPR field filled in except for the 2976 SPRBAT field. */ 2977#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 2978 2979/* An XFX form instruction with the SPR field filled in except for the 2980 SPRG field. */ 2981#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) 2982 2983/* An X form instruction with everything filled in except the E field. */ 2984#define XE_MASK (0xffff7fff) 2985 2986/* An X form user context instruction. */ 2987#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 2988#define XUC_MASK XUC(0x3f, 0x1f) 2989 2990/* An XW form instruction. */ 2991#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1)) 2992/* The mask for a G form instruction. rc not supported at present. */ 2993#define XW_MASK XW (0x3f, 0x3f, 0) 2994 2995/* An APU form instruction. */ 2996#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) 2997 2998/* The mask for an APU form instruction. */ 2999#define APU_MASK APU (0x3f, 0x3ff, 1) 3000#define APU_RT_MASK (APU_MASK | RT_MASK) 3001#define APU_RA_MASK (APU_MASK | RA_MASK) 3002 3003/* The BO encodings used in extended conditional branch mnemonics. */ 3004#define BODNZF (0x0) 3005#define BODNZFP (0x1) 3006#define BODZF (0x2) 3007#define BODZFP (0x3) 3008#define BODNZT (0x8) 3009#define BODNZTP (0x9) 3010#define BODZT (0xa) 3011#define BODZTP (0xb) 3012 3013#define BOF (0x4) 3014#define BOFP (0x5) 3015#define BOFM4 (0x6) 3016#define BOFP4 (0x7) 3017#define BOT (0xc) 3018#define BOTP (0xd) 3019#define BOTM4 (0xe) 3020#define BOTP4 (0xf) 3021 3022#define BODNZ (0x10) 3023#define BODNZP (0x11) 3024#define BODZ (0x12) 3025#define BODZP (0x13) 3026#define BODNZM4 (0x18) 3027#define BODNZP4 (0x19) 3028#define BODZM4 (0x1a) 3029#define BODZP4 (0x1b) 3030 3031#define BOU (0x14) 3032 3033/* The BO16 encodings used in extended VLE conditional branch mnemonics. */ 3034#define BO16F (0x0) 3035#define BO16T (0x1) 3036 3037/* The BO32 encodings used in extended VLE conditional branch mnemonics. */ 3038#define BO32F (0x0) 3039#define BO32T (0x1) 3040#define BO32DNZ (0x2) 3041#define BO32DZ (0x3) 3042 3043/* The BI condition bit encodings used in extended conditional branch 3044 mnemonics. */ 3045#define CBLT (0) 3046#define CBGT (1) 3047#define CBEQ (2) 3048#define CBSO (3) 3049 3050/* The TO encodings used in extended trap mnemonics. */ 3051#define TOLGT (0x1) 3052#define TOLLT (0x2) 3053#define TOEQ (0x4) 3054#define TOLGE (0x5) 3055#define TOLNL (0x5) 3056#define TOLLE (0x6) 3057#define TOLNG (0x6) 3058#define TOGT (0x8) 3059#define TOGE (0xc) 3060#define TONL (0xc) 3061#define TOLT (0x10) 3062#define TOLE (0x14) 3063#define TONG (0x14) 3064#define TONE (0x18) 3065#define TOU (0x1f) 3066 3067/* Smaller names for the flags so each entry in the opcodes table will 3068 fit on a single line. */ 3069#undef PPC 3070#define PPC PPC_OPCODE_PPC 3071#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 3072#define POWER4 PPC_OPCODE_POWER4 3073#define POWER5 PPC_OPCODE_POWER5 3074#define POWER6 PPC_OPCODE_POWER6 3075#define POWER7 PPC_OPCODE_POWER7 3076#define POWER8 PPC_OPCODE_POWER8 3077#define POWER9 PPC_OPCODE_POWER9 3078#define CELL PPC_OPCODE_CELL 3079#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE 3080#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ 3081 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 3082#define PPC403 PPC_OPCODE_403 3083#define PPC405 PPC_OPCODE_405 3084#define PPC440 PPC_OPCODE_440 3085#define PPC464 PPC440 3086#define PPC476 PPC_OPCODE_476 3087#define PPC750 PPC_OPCODE_750 3088#define PPC7450 PPC_OPCODE_7450 3089#define PPC860 PPC_OPCODE_860 3090#define PPCPS PPC_OPCODE_PPCPS 3091#define PPCVEC PPC_OPCODE_ALTIVEC 3092#define PPCVEC2 PPC_OPCODE_ALTIVEC2 3093#define PPCVEC3 PPC_OPCODE_ALTIVEC2 3094#define PPCVSX PPC_OPCODE_VSX 3095#define PPCVSX2 PPC_OPCODE_VSX 3096#define PPCVSX3 PPC_OPCODE_VSX3 3097#define POWER PPC_OPCODE_POWER 3098#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 3099#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON 3100#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON 3101#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 3102#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 3103#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 3104#define MFDEC1 PPC_OPCODE_POWER 3105#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN 3106#define BOOKE PPC_OPCODE_BOOKE 3107#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS 3108#define PPCE300 PPC_OPCODE_E300 3109#define PPCSPE PPC_OPCODE_SPE 3110#define PPCISEL PPC_OPCODE_ISEL 3111#define PPCEFS PPC_OPCODE_EFS 3112#define PPCBRLK PPC_OPCODE_BRLOCK 3113#define PPCPMR PPC_OPCODE_PMR 3114#define PPCTMR PPC_OPCODE_TMR 3115#define PPCCHLK PPC_OPCODE_CACHELCK 3116#define PPCRFMCI PPC_OPCODE_RFMCI 3117#define E500MC PPC_OPCODE_E500MC 3118#define PPCA2 PPC_OPCODE_A2 3119#define TITAN PPC_OPCODE_TITAN 3120#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN 3121#define E500 PPC_OPCODE_E500 3122#define E6500 PPC_OPCODE_E6500 3123#define PPCVLE PPC_OPCODE_VLE 3124#define PPCHTM PPC_OPCODE_HTM 3125#define E200Z4 PPC_OPCODE_E200Z4 3126/* The list of embedded processors that use the embedded operand ordering 3127 for the 3 operand dcbt and dcbtst instructions. */ 3128#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ 3129 | PPC_OPCODE_A2) 3130 3131 3132 3133/* The opcode table. 3134 3135 The format of the opcode table is: 3136 3137 NAME OPCODE MASK FLAGS ANTI {OPERANDS} 3138 3139 NAME is the name of the instruction. 3140 OPCODE is the instruction opcode. 3141 MASK is the opcode mask; this is used to tell the disassembler 3142 which bits in the actual opcode must match OPCODE. 3143 FLAGS are flags indicating which processors support the instruction. 3144 ANTI indicates which processors don't support the instruction. 3145 OPERANDS is the list of operands. 3146 3147 The disassembler reads the table in order and prints the first 3148 instruction which matches, so this table is sorted to put more 3149 specific instructions before more general instructions. 3150 3151 This table must be sorted by major opcode. Please try to keep it 3152 vaguely sorted within major opcode too, except of course where 3153 constrained otherwise by disassembler operation. */ 3154 3155const struct powerpc_opcode powerpc_opcodes[] = { 3156{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, 3157{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3158{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3159{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3160{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3161{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3162{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3163{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3164{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3165{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3166{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3167{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3168{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3169{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3170{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3171{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, 3172{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, 3173 3174{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3175{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3176{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3177{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3178{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3179{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3180{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3181{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3182{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3183{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3184{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3185{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3186{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3187{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3188{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3189{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3190{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3191{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3192{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3193{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3194{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3195{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3196{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3197{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3198{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3199{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3200{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3201{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3202{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, 3203{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, 3204{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, 3205{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, 3206 3207{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3208{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3209{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 3210{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3211{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3212{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3213{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3214{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3215{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3216{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 3217{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3218{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 3219{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3220{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3221{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3222{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3223{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3224{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3225{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3226{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3227{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3228{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3229{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3230{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3231{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3232{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3233{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3234{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3235{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3236{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3237{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3238{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3239{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 3240{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3241{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3242{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3243{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3244{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3245{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3246{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3247{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3248{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3249{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3250{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3251{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3252{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3253{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 3254{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, 3255{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3256{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3257{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 3258{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3259{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 3260{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3261{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3262{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3263{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3264{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3265{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 3266{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 3267{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3268{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 3269{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3270{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3271{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3272{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3273{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 3274{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3275{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3276{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3277{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3278{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3279{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3280{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 3281{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 3282{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3283{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3284{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3285{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3286{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3287{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3288{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3289{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3290{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3291{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 3292{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3293{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 3294{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3295{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3296{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3297{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3298{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3299{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3300{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3301{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3302{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3303{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3304{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3305{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3306{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3307{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3308{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3309{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3310{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3311{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3312{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3313{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3314{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3315{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3316{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3317{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3318{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 3319{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3320{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3321{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3322{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3323{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3324{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3325{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3326{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3327{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3328{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3329{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3330{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3331{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3332{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3333{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3334{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3335{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3336{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3337{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3338{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3339{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3340{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3341{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3342{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3343{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3344{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3345{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3346{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3347{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3348{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3349{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3350{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3351{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3352{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3353{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3354{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3355{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3356{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3357{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3358{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3359{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3360{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3361{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3362{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3363{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3364{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3365{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3366{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3367{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3368{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3369{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3370{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3371{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3372{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3373{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3374{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3375{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3376{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3377{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3378{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3379{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3380{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3381{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 3382{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3383{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3384{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3385{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, 3386{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3387{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, 3388{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3389{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3390{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, 3391{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3392{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, 3393{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, 3394{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3395{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, 3396{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, 3397{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, 3398{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3399{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, 3400{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, 3401{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3402{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3403{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3404{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 3405{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3406{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3407{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3408{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, 3409{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3410{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3411{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, 3412{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3413{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3414{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3415{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3416{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3417{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3418{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3419{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3420{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3421{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3422{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3423{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3424{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 3425{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 3426{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3427{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3428{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3429{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3430{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3431{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3432{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3433{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3434{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3435{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3436{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3437{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3438{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3439{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3440{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3441{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3442{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3443{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, 3444{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3445{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3446{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3447{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, 3448{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 3449{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3450{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3451{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3452{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3453{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, 3454{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3455{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, 3456{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, 3457{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3458{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3459{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3460{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3461{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3462{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3463{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, 3464{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3465{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3466{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3467{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3468{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, 3469{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, 3470{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, 3471{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, 3472{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, 3473{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, 3474{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, 3475{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, 3476{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, 3477{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3478{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, 3479{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3480{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3481{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 3482{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3483{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3484{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3485{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3486{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, 3487{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3488{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, 3489{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, 3490{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3491{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3492{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3493{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3494{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3495{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3496{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3497{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3498{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3499{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3500{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, 3501{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, 3502{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, 3503{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, 3504{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, 3505{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, 3506{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, 3507{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, 3508{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, 3509{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, 3510{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3511{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, 3512{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3513{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3514{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3515{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3516{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3517{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, 3518{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, 3519{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, 3520{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, 3521{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, 3522{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3523{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 3524{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, 3525{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, 3526{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3527{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3528{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3529{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, 3530{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, 3531{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, 3532{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, 3533{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, 3534{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, 3535{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, 3536{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, 3537{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, 3538{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, 3539{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 3540{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, 3541{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3542{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3543{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 3544{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3545{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3546{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3547{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3548{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3549{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3550{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3551{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3552{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3553{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3554{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3555{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3556{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 3557{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3558{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3559{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3560{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3561{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3562{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 3563{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3564{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3565{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 3566{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3567{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3568{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3569{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3570{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3571{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3572{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3573{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3574{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3575{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3576{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3577{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3578{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3579{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3580{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3581{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3582{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3583{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3584{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3585{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 3586{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3587{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3588{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3589{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3590{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3591{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3592{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3593{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 3594{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3595{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3596{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3597{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3598{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3599{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3600{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3601{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3602{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3603{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3604{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3605{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 3606{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 3607{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3608{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3609{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3610{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 3611{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3612{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3613{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3614{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3615{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3616{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3617{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3618{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 3619{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3620{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3621{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3622{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3623{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3624{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3625{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3626{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3627{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 3628{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 3629{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 3630{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3631{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3632{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3633{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3634{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3635{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 3636{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3637{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3638{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3639{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3640{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3641{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3642{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3643{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3644{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3645{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3646{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3647{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3648{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3649{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3650{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3651{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3652{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3653{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3654{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3655{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3656{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3657{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3658{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3659{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3660{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3661{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3662{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3663{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3664{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3665{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3666{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3667{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 3668{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3669{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3670{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3671{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3672{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3673{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3674{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3675{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3676{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3677{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3678{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3679{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3680{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3681{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3682{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3683{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3684{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3685{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3686{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3687{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3688{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3689{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3690{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3691{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3692{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3693{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3694{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3695{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3696{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3697{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3698{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3699{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3700{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3701{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3702{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3703{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3704{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3705{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3706{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3707{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}}, 3708{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3709{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3710{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3711{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3712{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3713{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3714{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3715{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3716{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3717{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3718{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3719{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, 3720{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 3721{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, 3722{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, 3723{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, 3724{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, 3725{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3726{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3727{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3728{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3729{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3730{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3731{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3732{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3733{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, 3734{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, 3735{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, 3736{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, 3737{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3738{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3739{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3740{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3741{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3742{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3743{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 3744{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3745{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3746{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 3747{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3748{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3749{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3750{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3751{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}}, 3752{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3753{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3754{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3755{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3756{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3757{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3758{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3759{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3760{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3761{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3762{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3763{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3764{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3765{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3766{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3767{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3768{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3769{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3770{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3771{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3772{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3773{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3774{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3775{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3776{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3777{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3778{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3779{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3780{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3781{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3782{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3783{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3784{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3785{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3786{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3787{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3788{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3789{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3790{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3791{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3792{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3793{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3794{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3795{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3796{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3797{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3798{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3799{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3800{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3801{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3802{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3803{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3804{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3805{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3806{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3807{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 3808{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3809{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3810{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3811{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3812{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3813{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3814{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3815{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3816{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3817{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3818{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3819{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3820{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3821{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3822{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3823{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3824{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3825{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3826{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3827{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3828{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3829{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3830{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3831{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3832{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 3833{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3834{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3835{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3836{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3837{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, 3838{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, 3839{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3840{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3841{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3842{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3843{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3844{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3845{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3846{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3847{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3848{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3849{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3850{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3851{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3852{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 3853{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 3854{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3855{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3856{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3857{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3858{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3859{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3860{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3861{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3862{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3863{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3864{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3865{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3866{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3867{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 3868{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, 3869{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3870{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3871{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3872{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3873{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3874{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3875{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, 3876{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3877{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3878{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3879{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3880{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3881{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3882{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3883{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 3884{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3885{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3886{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3887{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3888{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3889{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3890{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3891{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 3892{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3893{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3894{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3895{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3896{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3897{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3898{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3899{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3900{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3901{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3902{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3903{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3904{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3905{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3906{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3907{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3908{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3909{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3910{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3911{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3912{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 3913{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3914{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3915{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3916{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3917{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3918{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3919{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3920{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3921{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3922{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3923{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3924{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3925{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3926{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3927{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 3928{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3929{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 3930{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3931{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3932{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3933{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 3934{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 3935{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3936{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 3937{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, 3938{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3939{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3940{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3941{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 3942{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, 3943 3944{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3945{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3946 3947{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3948{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3949 3950{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, 3951 3952{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, 3953{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, 3954{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, 3955{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, 3956 3957{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, 3958{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, 3959{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, 3960{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, 3961 3962{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3963{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3964{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, 3965 3966{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 3967{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 3968{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, 3969 3970{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, 3971{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, 3972{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, 3973{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 3974{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, 3975{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 3976 3977{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, 3978{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, 3979{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 3980{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 3981{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, 3982 3983{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 3984{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 3985{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, 3986{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, 3987{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 3988{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 3989{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, 3990{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, 3991{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 3992{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 3993{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, 3994{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, 3995{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 3996{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 3997{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, 3998{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, 3999{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 4000{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 4001{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, 4002{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, 4003{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, 4004{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, 4005{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 4006{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 4007{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, 4008{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, 4009{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, 4010{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, 4011 4012{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4013{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4014{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4015{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4016{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4017{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4018{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4019{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4020{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4021{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4022{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4023{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4024{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4025{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4026{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4027{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4028{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4029{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4030{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4031{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4032{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4033{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4034{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4035{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4036{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4037{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4038{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4039{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4040{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4041{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4042{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4043{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4044{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4045{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4046{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4047{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4048{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4049{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4050{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4051{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4052{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4053{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4054{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4055{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4056{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4057{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4058{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4059{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4060{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4061{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4062{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4063{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4064{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4065{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4066{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4067{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4068{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4069{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4070{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4071{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4072{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4073{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4074{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4075{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4076{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4077{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4078{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4079{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4080{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4081{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4082{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4083{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4084{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4085{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4086{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4087{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4088{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4089{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4090{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4091{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4092{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4093{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4094{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4095{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4096 4097{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4098{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4099{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4100{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4101{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4102{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4103{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4104{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4105{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4106{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4107{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4108{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4109{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4110{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4111{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4112{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4113{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4114{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4115{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4116{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4117{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4118{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4119{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4120{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4121{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4122{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4123{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4124{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4125{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4126{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4127{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4128{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4129{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4130{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4131{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4132{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4133{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4134{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4135{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4136{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4137{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4138{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4139{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4140{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4141{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, 4142{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, 4143{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, 4144{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, 4145{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4146{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4147{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4148{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4149{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4150{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4151{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4152{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4153{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, 4154{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, 4155{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, 4156{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, 4157 4158{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4159{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4160{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4161{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4162{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4163{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4164{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4165{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4166{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4167{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4168{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4169{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4170{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4171{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4172{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4173{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4174{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4175{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4176{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4177{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4178{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4179{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4180{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4181{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4182 4183{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4184{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4185{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4186{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4187{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4188{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4189{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4190{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4191{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4192{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4193{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4194{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4195{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4196{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4197{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4198{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4199 4200{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4201{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4202{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4203{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4204{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4205{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4206{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4207{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4208{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4209{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4210{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4211{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4212{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4213{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4214{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4215{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, 4216{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, 4217{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4218{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4219{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4220{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4221{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, 4222{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, 4223{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4224 4225{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4226{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4227{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4228{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4229{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, 4230{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, 4231{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, 4232{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, 4233{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4234{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4235{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4236{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4237{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, 4238{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, 4239{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, 4240{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, 4241 4242{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, 4243{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, 4244{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 4245{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, 4246{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, 4247{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 4248{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, 4249{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, 4250{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 4251{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, 4252{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, 4253{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 4254 4255{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 4256{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, 4257{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 4258{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, 4259{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, 4260{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, 4261 4262{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, 4263{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, 4264{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, 4265{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, 4266 4267{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 4268 4269{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, 4270{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, 4271{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, 4272 4273{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4274{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4275{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4276{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4277{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4278{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4279{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4280{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4281{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4282{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4283{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4284{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, 4285{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4286{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, 4287{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, 4288{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, 4289{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4290{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4291{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4292{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4293{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4294{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4295{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4296{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, 4297 4298{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4299{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4300{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4301{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4302{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4303{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4304{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4305{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4306{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4307{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4308{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4309{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4310{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4311{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4312{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4313{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4314{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4315{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4316{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4317{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4318{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4319{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4320{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4321{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4322{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4323{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4324{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4325{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4326{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4327{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4328{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4329{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4330{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4331{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4332{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4333{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4334{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4335{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4336{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4337{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4338{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4339{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4340{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4341{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4342{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4343{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4344{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4345{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4346{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4347{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4348{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4349{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4350{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4351{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4352{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4353{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4354{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4355{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4356{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4357{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4358{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4359{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4360{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4361{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4362{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4363{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4364{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4365{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4366{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4367{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4368{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4369{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4370{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4371{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4372{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4373{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4374{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4375{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4376{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4377{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4378{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4379{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4380{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4381{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4382{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4383{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4384{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4385{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4386{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4387{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4388{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4389{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4390{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4391{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4392{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4393{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4394{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4395{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4396{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4397{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4398{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4399{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4400{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4401{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4402{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4403{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4404{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4405{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, 4406{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4407{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4408{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4409{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4410{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4411{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4412{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4413{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4414{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4415{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4416{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4417{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4418{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4419{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4420{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4421{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4422{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4423{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4424{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4425{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4426{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4427{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4428{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4429{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4430{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4431{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4432{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4433{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4434{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4435{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4436{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4437{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4438 4439{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4440{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4441{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4442{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4443{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4444{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4445{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4446{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4447{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4448{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4449{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4450{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4451{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4452{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4453{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4454{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4455{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4456{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4457{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4458{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4459{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4460{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4461{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4462{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4463{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4464{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4465{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4466{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4467{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4468{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4469{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4470{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4471{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4472{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4473{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4474{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4475{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4476{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4477{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4478{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4479{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4480{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, 4481{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4482{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4483{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4484{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4485{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4486{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4487 4488{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4489{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4490{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4491{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4492{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4493{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4494{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4495{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4496 4497{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, 4498 4499{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}}, 4500{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4501{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 4502 4503{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, 4504{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, 4505{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, 4506 4507{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, 4508{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, 4509 4510{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, 4511 4512{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4513 4514{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, 4515 4516{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4517{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, 4518 4519{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}}, 4520{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4521 4522{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, 4523 4524{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4525 4526{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4527 4528{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, 4529 4530{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}}, 4531{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4532 4533{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, 4534{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, 4535 4536{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4537 4538{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4539 4540{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4541 4542{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}}, 4543{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 4544 4545{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4546{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 4547 4548{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, 4549{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, 4550 4551{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4552{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4553{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4554{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4555{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4556{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4557{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4558{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4559{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4560{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4561{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4562{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4563{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4564{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4565{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4566{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4567{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4568{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4569{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4570{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4571{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4572{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4573{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4574{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4575{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4576{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4577{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4578{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4579{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4580{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4581{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4582{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4583{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4584{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4585{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4586{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4587{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4588{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4589{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4590{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4591{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4592{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4593{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4594{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4595{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4596{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4597{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4598{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4599{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4600{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4601{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4602{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4603{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4604{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4605{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4606{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4607{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4608{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4609{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4610{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4611{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4612{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4613{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4614{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4615{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4616{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4617{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4618{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4619{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4620{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4621{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4622{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4623{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4624{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4625{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4626{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4627{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4628{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4629{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4630{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4631{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4632{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4633{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4634{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4635{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4636{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4637{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4638{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4639{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, 4640{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4641{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4642{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4643{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4644{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4645{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4646{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4647{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4648{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4649{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4650{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, 4651{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4652{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4653{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4654{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4655{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4656{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4657{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4658{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4659{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4660{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4661{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4662{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4663{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4664{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4665{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4666{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4667{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4668{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4669{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4670{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, 4671 4672{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4673{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4674{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4675{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4676{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4677{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4678{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4679{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4680{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4681{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4682{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4683{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4684{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, 4685{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4686{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4687{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, 4688{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4689{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4690{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4691{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, 4692 4693{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4694{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4695{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4696{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, 4697{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4698{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4699{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 4700{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, 4701 4702{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4703{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4704{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4705{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, 4706{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 4707{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 4708 4709{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4710{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4711 4712{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4713{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4714 4715{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, 4716{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, 4717{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4718{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4719{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, 4720{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, 4721{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4722{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 4723 4724{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 4725{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 4726 4727{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, 4728{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4729{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4730{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, 4731{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4732{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 4733 4734{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4735{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4736{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4737 4738{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4739{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4740 4741{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, 4742{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4743{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4744 4745{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4746{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4747 4748{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4749{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4750 4751{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 4752{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 4753 4754{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, 4755{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, 4756{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4757{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, 4758{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, 4759{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4760 4761{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 4762{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 4763 4764{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4765{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4766 4767{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4768{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 4769 4770{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, 4771{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 4772{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, 4773{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 4774 4775{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 4776{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 4777 4778{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, 4779{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, 4780{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, 4781{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 4782 4783{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4784{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4785{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4786{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4787{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4788{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4789{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4790{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4791{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4792{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4793{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4794{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4795{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4796{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4797{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4798{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4799{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4800{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4801{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4802{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4803{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4804{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4805{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4806{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4807{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4808{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4809{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4810{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4811{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, 4812{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, 4813{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, 4814{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 4815{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, 4816 4817{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4818{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4819{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4820 4821{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4822{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4823{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 4824{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4825{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4826{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 4827 4828{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4829{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4830 4831{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4832{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4833{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 4834{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 4835 4836{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 4837{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 4838 4839{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 4840 4841{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 4842 4843{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, 4844{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, 4845{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 4846{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, 4847 4848{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, 4849{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, 4850 4851{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, 4852 4853{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, 4854 4855{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, 4856 4857{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 4858{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 4859 4860{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 4861{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 4862{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 4863{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 4864 4865{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 4866{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 4867{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 4868{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 4869 4870{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 4871{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 4872 4873{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, 4874{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, 4875 4876{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, 4877{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, 4878 4879{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 4880 4881{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, 4882{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}}, 4883 4884{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 4885 4886{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, 4887{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, 4888{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, 4889{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 4890 4891{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4892{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4893{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4894 4895{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, 4896 4897{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 4898 4899{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4900 4901{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, 4902 4903{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 4904 4905{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, 4906 4907{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, 4908 4909{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 4910{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, 4911{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 4912{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, 4913 4914{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 4915{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, 4916{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, 4917{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, 4918 4919{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 4920 4921{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, 4922 4923{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 4924 4925{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, 4926{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 4927 4928{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, 4929{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, 4930 4931{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, 4932{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, 4933 4934{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, 4935{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, 4936{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, 4937 4938{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 4939 4940{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, 4941{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, 4942{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, 4943{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, 4944{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, 4945{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, 4946{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, 4947{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, 4948{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, 4949{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, 4950{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, 4951{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, 4952{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, 4953{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, 4954{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, 4955{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, 4956 4957{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4958{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4959{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 4960 4961{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 4962{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 4963 4964{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, 4965{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, 4966 4967{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, 4968 4969{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, 4970 4971{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, 4972 4973{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, 4974{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, 4975 4976{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, 4977 4978{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 4979 4980{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, 4981 4982{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 4983{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 4984 4985{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, 4986{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, 4987 4988{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 4989{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 4990 4991{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, 4992 4993{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, 4994 4995{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, 4996{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, 4997{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 4998 4999{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 5000 5001{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 5002 5003{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, 5004 5005{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, 5006 5007{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}}, 5008{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, 5009{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}}, 5010{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, 5011 5012{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 5013 5014{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, 5015 5016{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, 5017 5018{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5019 5020{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5021{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5022 5023{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5024{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5025{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5026{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5027 5028{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5029{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5030{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5031{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5032 5033{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 5034 5035{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 5036{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 5037 5038{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, 5039{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, 5040{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, 5041 5042{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, 5043 5044{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, 5045 5046{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5047{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5048 5049{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, 5050 5051{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, 5052 5053{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 5054{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, 5055 5056{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, 5057{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, 5058 5059{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, 5060{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, 5061 5062{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, 5063 5064{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5065 5066{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5067 5068{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, 5069 5070{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5071 5072{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5073{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5074 5075{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, 5076 5077{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 5078{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 5079 5080{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, 5081 5082{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5083{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5084{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5085{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, 5086 5087{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, 5088 5089{"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 5090{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, 5091 5092{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, 5093{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 5094 5095{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, 5096{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, 5097 5098{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, 5099 5100{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, 5101 5102{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 5103 5104{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5105{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5106 5107{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5108{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5109{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5110{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5111 5112{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5113{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5114{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5115{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5116 5117{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 5118 5119{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, 5120 5121{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5122{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5123{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5124{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, 5125 5126{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 5127 5128{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, 5129 5130{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, 5131 5132{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, 5133{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, 5134 5135{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, 5136{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, 5137 5138{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5139 5140{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, 5141 5142{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5143 5144{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5145{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5146 5147{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5148{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5149{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5150{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5151 5152{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5153{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5154 5155{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5156{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5157{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 5158{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 5159 5160{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5161{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5162{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5163{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5164 5165{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, 5166{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 5167{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, 5168{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, 5169 5170{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, 5171{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, 5172{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 5173 5174{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, 5175{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 5176{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 5177{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 5178 5179{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, 5180 5181{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, 5182{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, 5183 5184{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, 5185 5186{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5187 5188{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, 5189{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, 5190 5191{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5192 5193{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, 5194 5195{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5196 5197{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5198{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5199{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5200 5201{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, 5202 5203{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5204{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5205{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5206{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5207 5208{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, 5209 5210{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, 5211{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5212 5213{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, 5214 5215{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}}, 5216{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, 5217 5218{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, 5219 5220{"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, 5221 5222{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, 5223{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, 5224 5225{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, 5226{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 5227{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 5228{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 5229 5230{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, 5231 5232{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, 5233 5234{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, 5235{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, 5236 5237{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5238 5239{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}}, 5240 5241{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5242{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5243 5244{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5245 5246{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, 5247 5248{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, 5249{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, 5250{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, 5251{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, 5252 5253{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, 5254 5255{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, 5256 5257{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 5258 5259{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, 5260 5261{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, 5262 5263{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, 5264{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, 5265 5266{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 5267 5268{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, 5269{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, 5270{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, 5271{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, 5272{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, 5273{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, 5274{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, 5275{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, 5276{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, 5277{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, 5278{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, 5279{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, 5280{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, 5281{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, 5282{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, 5283{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, 5284{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, 5285{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, 5286{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, 5287{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, 5288{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, 5289{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, 5290{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, 5291{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, 5292{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, 5293{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, 5294{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, 5295{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, 5296{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, 5297{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, 5298{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, 5299{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, 5300{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, 5301{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, 5302{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, 5303{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, 5304 5305{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5306 5307{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, 5308 5309{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5310{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5311 5312{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 5313 5314{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, 5315{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}}, 5316 5317{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, 5318 5319{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, 5320{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, 5321{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, 5322{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, 5323{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, 5324{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, 5325{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, 5326{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, 5327{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, 5328{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, 5329{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, 5330{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, 5331{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, 5332{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, 5333{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, 5334{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, 5335{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, 5336{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, 5337{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, 5338{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, 5339{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, 5340{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, 5341{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, 5342{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, 5343{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, 5344{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, 5345{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, 5346{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, 5347{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, 5348{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, 5349{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, 5350{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, 5351{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, 5352{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, 5353{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, 5354{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, 5355{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, 5356{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, 5357{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, 5358{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, 5359{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, 5360{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, 5361{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, 5362{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5363{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5364{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5365{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, 5366{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, 5367{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, 5368{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, 5369{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, 5370{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, 5371{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, 5372{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, 5373{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, 5374{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, 5375{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, 5376{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, 5377{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, 5378{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, 5379{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, 5380{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, 5381{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, 5382{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, 5383{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, 5384{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, 5385{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, 5386{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, 5387{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, 5388{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, 5389{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, 5390{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, 5391{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, 5392{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, 5393{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, 5394{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, 5395{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, 5396{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, 5397{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, 5398{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, 5399{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, 5400{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, 5401{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, 5402{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, 5403{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, 5404{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, 5405{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, 5406{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, 5407{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, 5408{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, 5409{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, 5410{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}}, 5411{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5412{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}}, 5413{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5414{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, 5415{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, 5416{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5417{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, 5418{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, 5419{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, 5420{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, 5421{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, 5422{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, 5423{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, 5424{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5425{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5426{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, 5427{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, 5428{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, 5429{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, 5430{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, 5431{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, 5432{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, 5433{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, 5434{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, 5435{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, 5436{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, 5437{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, 5438{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, 5439{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, 5440{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, 5441{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, 5442{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, 5443{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, 5444{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, 5445{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, 5446{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, 5447{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, 5448{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, 5449{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, 5450{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, 5451{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, 5452{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, 5453{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, 5454{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, 5455{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, 5456{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, 5457{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, 5458{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, 5459{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, 5460{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, 5461{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, 5462{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, 5463{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, 5464{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, 5465{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, 5466{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, 5467{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, 5468{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, 5469{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, 5470{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, 5471{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, 5472{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, 5473{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, 5474{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, 5475{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, 5476{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, 5477{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, 5478{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, 5479{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, 5480{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, 5481{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, 5482{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, 5483{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, 5484{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, 5485{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, 5486{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, 5487{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, 5488{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, 5489{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, 5490{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, 5491{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, 5492{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, 5493{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, 5494{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, 5495{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, 5496{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, 5497{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, 5498{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, 5499{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, 5500{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, 5501{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, 5502{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, 5503{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, 5504{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, 5505{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, 5506{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, 5507{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, 5508{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, 5509{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, 5510{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, 5511{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, 5512{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, 5513{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, 5514{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, 5515{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, 5516{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, 5517{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, 5518{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, 5519{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, 5520 5521{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, 5522 5523{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 5524 5525{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, 5526 5527{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 5528 5529{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, 5530{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, 5531 5532{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5533{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5534 5535{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5536 5537{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, 5538 5539{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, 5540{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, 5541{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, 5542 5543{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, 5544 5545{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 5546 5547{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, 5548 5549{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 5550 5551{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, 5552{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, 5553 5554{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5555 5556{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5557{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5558 5559{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5560{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5561{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5562{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5563 5564{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 5565{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 5566 5567{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 5568 5569{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, 5570 5571{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, 5572 5573{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, 5574 5575{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 5576{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 5577 5578{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, 5579 5580{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, 5581{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, 5582 5583{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 5584 5585{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}}, 5586 5587{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5588 5589{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 5590 5591{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5592{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5593{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5594{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 5595 5596{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 5597 5598{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, 5599 5600{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 5601 5602{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 5603 5604{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 5605 5606{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, 5607 5608{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, 5609 5610{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, 5611 5612/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for 5613 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ 5614{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, 5615{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, 5616{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, 5617{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}}, 5618{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, 5619{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}}, 5620{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, 5621 5622{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, 5623{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, 5624{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, 5625{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, 5626{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, 5627{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, 5628{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, 5629{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, 5630{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, 5631{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, 5632{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, 5633{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, 5634{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, 5635{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, 5636{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, 5637{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, 5638{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, 5639{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, 5640{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, 5641{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, 5642{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, 5643{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, 5644{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, 5645{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, 5646{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, 5647{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, 5648{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, 5649{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, 5650{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, 5651{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, 5652{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, 5653{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, 5654{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, 5655{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, 5656{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, 5657{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, 5658 5659{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 5660 5661{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 5662{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 5663 5664{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5665{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5666 5667{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5668{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5669 5670{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, 5671{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}}, 5672 5673{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, 5674 5675{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, 5676{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, 5677{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, 5678{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, 5679{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, 5680{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, 5681{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, 5682{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, 5683{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, 5684{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, 5685{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, 5686{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, 5687{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, 5688{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, 5689{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, 5690{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, 5691{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, 5692{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, 5693{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, 5694{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, 5695{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, 5696{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, 5697{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, 5698{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, 5699{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, 5700{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, 5701{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, 5702{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, 5703{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, 5704{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, 5705{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, 5706{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, 5707{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, 5708{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, 5709{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, 5710{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, 5711{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, 5712{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, 5713{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, 5714{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, 5715{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, 5716{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, 5717{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, 5718{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, 5719{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, 5720{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, 5721{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, 5722{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5723{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5724{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5725{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, 5726{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, 5727{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, 5728{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, 5729{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, 5730{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, 5731{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, 5732{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, 5733{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, 5734{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, 5735{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, 5736{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, 5737{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, 5738{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, 5739{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, 5740{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, 5741{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, 5742{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, 5743{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, 5744{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, 5745{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, 5746{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, 5747{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, 5748{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, 5749{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, 5750{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, 5751{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, 5752{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, 5753{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, 5754{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, 5755{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, 5756{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, 5757{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, 5758{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, 5759{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, 5760{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, 5761{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, 5762{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, 5763{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}}, 5764{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5765{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}}, 5766{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5767{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, 5768{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, 5769{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5770{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, 5771{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5772{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5773{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, 5774{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, 5775{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, 5776{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, 5777{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, 5778{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, 5779{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, 5780{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, 5781{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, 5782{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, 5783{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, 5784{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, 5785{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, 5786{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, 5787{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, 5788{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, 5789{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, 5790{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, 5791{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, 5792{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, 5793{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, 5794{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, 5795{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, 5796{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, 5797{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, 5798{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, 5799{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, 5800{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, 5801{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, 5802{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, 5803{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, 5804{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, 5805{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, 5806{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, 5807{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, 5808{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, 5809{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, 5810{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, 5811{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, 5812{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, 5813{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, 5814{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, 5815{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, 5816{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, 5817{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, 5818{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, 5819{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, 5820{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, 5821{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, 5822{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, 5823{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, 5824{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, 5825{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, 5826{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, 5827{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, 5828{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, 5829{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, 5830{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, 5831{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, 5832{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, 5833{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, 5834{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, 5835{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, 5836{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, 5837{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, 5838{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, 5839{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, 5840 5841{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 5842 5843{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, 5844{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, 5845 5846{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, 5847 5848{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}}, 5849 5850{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 5851 5852{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 5853 5854{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, 5855{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, 5856 5857{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5858{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 5859 5860{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5861{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5862 5863{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 5864 5865{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, 5866{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, 5867 5868{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, 5869 5870{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 5871 5872{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, 5873 5874{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, 5875 5876{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, 5877{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}}, 5878 5879{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, 5880 5881{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, 5882{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5883 5884{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5885{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5886{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 5887{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5888{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5889{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, 5890 5891{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5892{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5893{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 5894{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 5895 5896{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 5897 5898{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, 5899 5900{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, 5901 5902{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, 5903{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 5904 5905{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 5906{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 5907 5908{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 5909 5910{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 5911{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 5912{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 5913{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 5914 5915{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, 5916{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, 5917 5918{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, 5919{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, 5920 5921{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 5922{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 5923 5924{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, 5925{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, 5926 5927{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, 5928{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, 5929 5930{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5931 5932{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, 5933 5934{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, 5935{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5936 5937{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 5938{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, 5939{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 5940{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, 5941 5942{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, 5943 5944{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 5945 5946{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, 5947{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, 5948 5949{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, 5950 5951{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, 5952{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, 5953 5954{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5955 5956{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, 5957 5958{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5959 5960{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 5961 5962{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, 5963 5964{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, 5965{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, 5966 5967{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, 5968{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, 5969{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, 5970{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, 5971{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, 5972{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, 5973{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, 5974{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, 5975{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, 5976 5977{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 5978 5979{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, 5980{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, 5981 5982{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, 5983 5984{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 5985 5986{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, 5987 5988{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 5989 5990{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, 5991{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, 5992 5993{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 5994{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 5995 5996{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, 5997 5998{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, 5999 6000{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 6001 6002{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, 6003{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}}, 6004 6005{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, 6006{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6007 6008{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 6009 6010{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, 6011 6012{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6013{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6014{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6015{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6016 6017{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6018{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6019{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6020{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6021 6022{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, 6023 6024{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, 6025 6026{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, 6027{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 6028 6029{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 6030{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 6031 6032{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 6033 6034{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, 6035{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, 6036 6037{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, 6038{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, 6039 6040{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, 6041{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, 6042 6043{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6044 6045{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, 6046{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6047 6048{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, 6049{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, 6050 6051{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 6052 6053{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 6054 6055{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, 6056{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, 6057 6058{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, 6059{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, 6060 6061{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6062 6063{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, 6064 6065{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6066 6067{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6068 6069{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, 6070 6071{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6072{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6073{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6074{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6075 6076{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6077{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6078{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6079{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6080 6081{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, 6082{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, 6083 6084{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 6085 6086{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 6087 6088{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, 6089{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, 6090 6091{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, 6092{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, 6093 6094{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, 6095{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, 6096 6097{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, 6098 6099{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6100 6101{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, 6102 6103{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6104 6105{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6106{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6107{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6108{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6109 6110{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6111{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6112 6113{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6114{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6115{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 6116{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 6117 6118{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6119{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6120{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6121{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6122 6123{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6124{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6125{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, 6126 6127{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, 6128 6129{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 6130{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, 6131 6132{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 6133 6134{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, 6135{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, 6136 6137{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6138 6139{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, 6140 6141{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6142{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, 6143{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6144 6145{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6146{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6147 6148{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6149{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6150{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6151{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6152 6153{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, 6154{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, 6155 6156{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6157{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6158 6159{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 6160 6161{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 6162 6163{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6164 6165{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, 6166 6167{"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, 6168{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, 6169 6170{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6171{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6172{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6173{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6174 6175{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 6176{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 6177 6178{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, 6179 6180{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6181{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6182{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, 6183 6184{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6185{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6186 6187{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 6188 6189{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, 6190 6191{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, 6192 6193{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6194 6195{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, 6196 6197{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, 6198 6199{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 6200{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 6201{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 6202{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 6203 6204{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 6205{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 6206 6207{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6208 6209{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, 6210 6211{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6212{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6213 6214{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 6215{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, 6216 6217{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 6218 6219{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, 6220 6221{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}}, 6222{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 6223{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, 6224 6225{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6226 6227{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, 6228{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, 6229{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, 6230{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, 6231 6232{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, 6233 6234{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, 6235 6236{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, 6237{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, 6238 6239{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 6240{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 6241 6242{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 6243 6244{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 6245 6246{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 6247 6248{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, 6249 6250{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, 6251 6252{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, 6253 6254{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 6255{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 6256 6257{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, 6258 6259{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, 6260{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6261 6262{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6263{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6264{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6265{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6266 6267{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6268{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6269 6270{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 6271 6272{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 6273{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 6274 6275{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 6276{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, 6277 6278{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6279 6280{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, 6281 6282{"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, 6283{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, 6284 6285{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, 6286{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, 6287 6288{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, 6289{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, 6290 6291{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6292{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6293{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6294{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6295 6296{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, 6297 6298{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6299 6300{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, 6301{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, 6302{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, 6303 6304{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, 6305 6306{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6307{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6308{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6309{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 6310 6311{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6312{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6313 6314{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 6315 6316{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, 6317{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, 6318{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 6319 6320{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6321 6322{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, 6323{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, 6324 6325{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, 6326 6327{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, 6328{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, 6329 6330{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, 6331{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, 6332 6333{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6334 6335{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 6336{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 6337 6338{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6339{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6340 6341{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6342{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6343 6344{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 6345{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, 6346 6347{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, 6348{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, 6349{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, 6350{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 6351 6352{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, 6353 6354{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6355 6356{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 6357 6358{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, 6359 6360{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, 6361{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, 6362 6363{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6364 6365{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, 6366 6367{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, 6368 6369{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, 6370{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, 6371 6372{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6373{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6374 6375{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6376{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6377 6378{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 6379 6380{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 6381 6382{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 6383 6384{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, 6385 6386{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 6387{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 6388 6389{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6390 6391{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, 6392 6393{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}}, 6394{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}}, 6395{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}}, 6396 6397{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6398{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 6399{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, 6400 6401{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, 6402{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, 6403{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}}, 6404{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, 6405 6406{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 6407{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6408 6409{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, 6410{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6411 6412{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6413 6414{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6415 6416{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 6417{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6418 6419{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, 6420{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6421 6422{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 6423 6424{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 6425 6426{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6427 6428{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6429 6430{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 6431 6432{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 6433 6434{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 6435 6436{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 6437 6438{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, 6439{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 6440 6441{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 6442{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 6443 6444{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 6445 6446{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 6447 6448{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 6449 6450{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 6451 6452{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 6453 6454{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 6455 6456{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 6457 6458{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 6459 6460{"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, 6461{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 6462{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 6463 6464{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 6465{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 6466{"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, 6467{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 6468{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 6469 6470{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 6471{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, 6472{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 6473 6474{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6475{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6476 6477{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 6478{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 6479 6480{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6481{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6482 6483{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6484{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6485 6486{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6487{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6488 6489{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 6490{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 6491 6492{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6493{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6494{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6495{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6496 6497{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6498{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6499 6500{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6501{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6502{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6503{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6504 6505{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6506{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6507 6508{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6509{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6510 6511{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6512{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6513 6514{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6515{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6516 6517{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6518{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6519 6520{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 6521{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 6522 6523{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6524{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6525 6526{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 6527{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 6528 6529{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6530{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 6531 6532{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6533{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6534 6535{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6536 6537{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6538{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, 6539{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, 6540 6541{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6542{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 6543 6544{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6545{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6546 6547{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6548{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6549 6550{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 6551{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 6552 6553{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6554{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6555 6556{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6557{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6558 6559{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6560{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6561 6562{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6563 6564{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 6565{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, 6566 6567{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6568{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 6569 6570{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6571{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6572 6573{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 6574{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 6575 6576{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6577{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6578 6579{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6580{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 6581 6582{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6583{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 6584 6585{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6586{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6587{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, 6588{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6589{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6590{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6591{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, 6592{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6593{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6594{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}}, 6595{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6596{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, 6597{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6598{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, 6599{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6600{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6601{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6602{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6603{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6604{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6605{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6606{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6607{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6608{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6609{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6610{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6611{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6612{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6613{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6614{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6615{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6616{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6617{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6618{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6619{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6620{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6621{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6622{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6623{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6624{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6625{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 6626{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6627{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6628{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6629{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6630{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, 6631{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6632{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6633{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6634{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6635{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6636{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6637{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6638{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6639{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6640{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6641{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6642{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6643{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6644{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6645{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6646{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6647{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6648{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6649{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6650{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, 6651{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 6652{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6653{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6654{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6655{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6656{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 6657{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6658{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6659{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6660{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, 6661{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 6662{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6663{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6664{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6665{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6666{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6667{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6668{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6669{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6670{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6671{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6672{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6673{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6674{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6675{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6676{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6677{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6678{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6679{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6680{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6681{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6682{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6683{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6684{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6685{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6686{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 6687{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6688{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6689{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6690{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6691{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6692{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 6693{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6694{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6695{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6696{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6697{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6698{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6699{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6700{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6701{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6702{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6703{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6704{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6705{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6706{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 6707{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6708{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6709{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6710{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6711{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6712{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6713{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6714{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6715{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6716{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 6717{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6718{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6719{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6720{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6721{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6722{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 6723{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 6724{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6725{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6726{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6727{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6728{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6729{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6730{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6731{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 6732{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6733{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 6734{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6735{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6736{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6737{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6738{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6739{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6740{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6741{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6742{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6743{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6744{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, 6745{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6746{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6747{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6748{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6749{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 6750{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6751{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6752{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6753{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6754{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6755{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6756{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6757{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6758{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, 6759{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6760{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6761{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6762{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6763{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6764{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6765{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6766{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6767{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6768{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6769{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6770{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6771{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6772{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 6773{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, 6774{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6775{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6776{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6777{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6778{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 6779{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 6780{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 6781{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6782{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 6783 6784{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 6785{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 6786 6787{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, 6788{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, 6789{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 6790{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 6791{"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, 6792{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 6793{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 6794 6795{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, 6796{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, 6797{"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 6798 6799{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 6800 6801{"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6802{"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6803 6804{"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 6805{"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 6806 6807{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6808{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6809 6810{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 6811{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 6812 6813{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 6814{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 6815 6816{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6817{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6818 6819{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6820{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6821{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6822{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6823 6824{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6825{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6826{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 6827{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 6828 6829{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6830{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6831{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6832{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6833 6834{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6835{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6836{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6837{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6838 6839{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6840{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6841{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 6842{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 6843 6844{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 6845{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 6846 6847{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6848{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6849 6850{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6851{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6852{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6853{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6854 6855{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6856{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 6857{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 6858{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 6859 6860{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6861{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6862{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6863{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 6864 6865{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6866{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6867{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6868{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6869 6870{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6871{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6872{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6873{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6874 6875{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6876{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6877{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6878{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6879 6880{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6881{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6882{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 6883{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 6884 6885{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 6886 6887{"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6888{"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6889 6890{"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 6891{"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 6892 6893{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6894{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6895 6896{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 6897 6898{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}}, 6899{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}}, 6900 6901{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6902{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6903 6904{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 6905 6906{"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6907{"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6908 6909{"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 6910{"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 6911 6912{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, 6913{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, 6914 6915{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6916{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6917 6918{"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6919{"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 6920 6921{"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6922{"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6923 6924{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6925 6926{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, 6927 6928{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 6929 6930{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 6931 6932{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 6933{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 6934{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 6935{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 6936 6937{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6938{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6939 6940{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6941{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6942{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6943{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 6944 6945{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, 6946 6947{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 6948 6949{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 6950 6951{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, 6952{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, 6953 6954{"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6955{"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 6956 6957{"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 6958{"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 6959 6960{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6961{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 6962 6963{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6964{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6965 6966{"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 6967{"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 6968 6969{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6970{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 6971 6972{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6973{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6974 6975{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6976{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6977 6978{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6979{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6980 6981{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6982{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6983 6984{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6985{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6986 6987{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6988{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6989 6990{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6991{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 6992 6993{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6994{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 6995 6996{"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6997{"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 6998 6999{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7000{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7001 7002{"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7003{"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 7004 7005{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7006{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7007 7008{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 7009{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 7010 7011{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 7012{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 7013{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, 7014{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 7015{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, 7016{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 7017 7018{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 7019 7020{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 7021 7022{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, 7023{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, 7024 7025{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, 7026 7027{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 7028{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 7029{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 7030{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 7031 7032{"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 7033{"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 7034 7035{"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 7036{"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 7037 7038{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7039{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7040{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7041{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7042{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7043{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7044{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7045 7046{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7047{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7048{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7049{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7050 7051{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7052{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7053{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7054{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7055 7056{"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 7057{"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 7058 7059{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7060{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7061{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7062{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7063{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7064{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7065{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7066{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7067{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 7068 7069{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 7070 7071{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7072{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7073{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 7074{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 7075 7076{"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 7077{"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 7078 7079{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 7080 7081{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7082{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7083 7084{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7085{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7086 7087{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 7088 7089{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7090{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 7091}; 7092 7093const int powerpc_num_opcodes = 7094 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 7095 7096/* The VLE opcode table. 7097 7098 The format of this opcode table is the same as the main opcode table. */ 7099 7100const struct powerpc_opcode vle_opcodes[] = { 7101{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, 7102{"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, 7103{"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, 7104{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, 7105{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, 7106{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, 7107{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, 7108{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, 7109{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, 7110{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, 7111{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, 7112{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, 7113{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, 7114{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, 7115{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, 7116{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, 7117{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, 7118{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, 7119{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, 7120{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, 7121{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, 7122{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7123{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, 7124{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, 7125{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7126{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7127{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7128{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7129{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7130{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7131{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7132{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7133 7134{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 7135{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 7136{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 7137{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 7138{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7139{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 7140{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7141{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7142{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 7143{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7144{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 7145{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7146{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7147{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 7148{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7149{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7150{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, 7151{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7152{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7153{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7154{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 7155{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7156{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7157{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7158{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7159{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7160{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7161{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7162{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7163{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 7164{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7165{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7166{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7167{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7168{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7169{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7170{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7171{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7172{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7173{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 7174{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, 7175{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7176{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, 7177 7178{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7179{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7180{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7181{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 7182{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7183{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7184{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7185 7186{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7187{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7188{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7189 7190{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7191{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7192{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7193{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, 7194{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7195{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7196{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7197{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 7198{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, 7199 7200{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7201{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7202{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7203{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 7204 7205{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7206{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7207{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7208{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7209{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7210{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7211{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 7212 7213{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7214{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7215{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7216{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7217{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 7218{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 7219{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7220{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 7221{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7222{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7223{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, 7224{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7225{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, 7226{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 7227{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, 7228{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, 7229{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, 7230{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, 7231{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, 7232{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, 7233{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, 7234{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, 7235{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, 7236{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7237{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7238{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7239{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7240{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7241{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7242{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7243{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7244{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7245{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7246{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7247{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7248{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7249{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7250{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7251{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7252{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7253{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7254{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7255{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7256{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7257{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7258{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7259{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, 7260{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 7261{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 7262 7263{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7264{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7265{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7266{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, 7267 7268{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 7269{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 7270{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7271{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7272{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}}, 7273{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7274{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}}, 7275{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7276{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, 7277{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7278{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7279 7280{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7281 7282{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 7283{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 7284 7285{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}}, 7286{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7287 7288{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7289{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7290 7291{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7292 7293{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}}, 7294{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 7295 7296{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, 7297 7298{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7299{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 7300 7301{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 7302 7303{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 7304 7305{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 7306 7307{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 7308 7309{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 7310 7311{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 7312 7313{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7314{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7315{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7316{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7317{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7318{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7319{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7320{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, 7321{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7322{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7323{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7324{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7325{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, 7326{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, 7327{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, 7328{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, 7329{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, 7330}; 7331 7332const int vle_num_opcodes = 7333 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); 7334 7335/* The macro table. This is only used by the assembler. */ 7336 7337/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 7338 when x=0; 32-x when x is between 1 and 31; are negative if x is 7339 negative; and are 32 or more otherwise. This is what you want 7340 when, for instance, you are emulating a right shift by a 7341 rotate-left-and-mask, because the underlying instructions support 7342 shifts of size 0 but not shifts of size 32. By comparison, when 7343 extracting x bits from some word you want to use just 32-x, because 7344 the underlying instructions don't support extracting 0 bits but do 7345 support extracting the whole word (32 bits in this case). */ 7346 7347const struct powerpc_macro powerpc_macros[] = { 7348{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, 7349{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, 7350{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, 7351{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, 7352{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, 7353{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, 7354{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, 7355{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, 7356{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, 7357{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, 7358{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, 7359{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, 7360{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, 7361{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, 7362{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, 7363{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, 7364 7365{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, 7366{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, 7367{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 7368{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 7369{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7370{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7371{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7372{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7373{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 7374{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 7375{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"}, 7376{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"}, 7377{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"}, 7378{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"}, 7379{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7380{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7381{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7382{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7383{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"}, 7384{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"}, 7385{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 7386{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"}, 7387 7388{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"}, 7389{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, 7390{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7391{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7392{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"}, 7393{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"}, 7394{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"}, 7395{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"}, 7396{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"}, 7397{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"}, 7398{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"}, 7399}; 7400 7401const int powerpc_num_macros = 7402 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 7403