1/* CPU data for mt. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright (C) 1996-2017 Free Software Foundation, Inc. 6 7This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23*/ 24 25#include "sysdep.h" 26#include <stdio.h> 27#include <stdarg.h> 28#include "ansidecl.h" 29#include "bfd.h" 30#include "symcat.h" 31#include "mt-desc.h" 32#include "mt-opc.h" 33#include "opintl.h" 34#include "libiberty.h" 35#include "xregex.h" 36 37/* Attributes. */ 38 39static const CGEN_ATTR_ENTRY bool_attr[] = 40{ 41 { "#f", 0 }, 42 { "#t", 1 }, 43 { 0, 0 } 44}; 45 46static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 47{ 48 { "base", MACH_BASE }, 49 { "ms1", MACH_MS1 }, 50 { "ms1_003", MACH_MS1_003 }, 51 { "ms2", MACH_MS2 }, 52 { "max", MACH_MAX }, 53 { 0, 0 } 54}; 55 56static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 57{ 58 { "mt", ISA_MT }, 59 { "max", ISA_MAX }, 60 { 0, 0 } 61}; 62 63const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] = 64{ 65 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 66 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 67 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 68 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 69 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 70 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 71 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 72 { 0, 0, 0 } 73}; 74 75const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] = 76{ 77 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 78 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 79 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 80 { "PC", &bool_attr[0], &bool_attr[0] }, 81 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 82 { 0, 0, 0 } 83}; 84 85const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] = 86{ 87 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 88 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 89 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 90 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 91 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 92 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 93 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 94 { "RELAX", &bool_attr[0], &bool_attr[0] }, 95 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 96 { 0, 0, 0 } 97}; 98 99const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] = 100{ 101 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 102 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 103 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 104 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 105 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 106 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 107 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 108 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 109 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 110 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 111 { "PBB", &bool_attr[0], &bool_attr[0] }, 112 { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, 113 { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] }, 114 { "AL-INSN", &bool_attr[0], &bool_attr[0] }, 115 { "IO-INSN", &bool_attr[0], &bool_attr[0] }, 116 { "BR-INSN", &bool_attr[0], &bool_attr[0] }, 117 { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] }, 118 { "USES-FRDR", &bool_attr[0], &bool_attr[0] }, 119 { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] }, 120 { "USES-FRSR1", &bool_attr[0], &bool_attr[0] }, 121 { "USES-FRSR2", &bool_attr[0], &bool_attr[0] }, 122 { "SKIPA", &bool_attr[0], &bool_attr[0] }, 123 { 0, 0, 0 } 124}; 125 126/* Instruction set variants. */ 127 128static const CGEN_ISA mt_cgen_isa_table[] = { 129 { "mt", 32, 32, 32, 32 }, 130 { 0, 0, 0, 0, 0 } 131}; 132 133/* Machine variants. */ 134 135static const CGEN_MACH mt_cgen_mach_table[] = { 136 { "ms1", "ms1", MACH_MS1, 0 }, 137 { "ms1-003", "ms1-003", MACH_MS1_003, 0 }, 138 { "ms2", "ms2", MACH_MS2, 0 }, 139 { 0, 0, 0, 0 } 140}; 141 142static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] = 143{ 144 { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 }, 145 { "XX", 0, {0, {{{0, 0}}}}, 0, 0 } 146}; 147 148CGEN_KEYWORD mt_cgen_opval_msys_syms = 149{ 150 & mt_cgen_opval_msys_syms_entries[0], 151 2, 152 0, 0, 0, 0, "" 153}; 154 155static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] = 156{ 157 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, 158 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, 159 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, 160 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, 161 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, 162 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, 163 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, 164 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, 165 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, 166 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, 167 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, 168 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, 169 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, 170 { "fp", 12, {0, {{{0, 0}}}}, 0, 0 }, 171 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, 172 { "sp", 13, {0, {{{0, 0}}}}, 0, 0 }, 173 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 }, 174 { "ra", 14, {0, {{{0, 0}}}}, 0, 0 }, 175 { "R15", 15, {0, {{{0, 0}}}}, 0, 0 }, 176 { "ira", 15, {0, {{{0, 0}}}}, 0, 0 } 177}; 178 179CGEN_KEYWORD mt_cgen_opval_h_spr = 180{ 181 & mt_cgen_opval_h_spr_entries[0], 182 20, 183 0, 0, 0, 0, "" 184}; 185 186 187/* The hardware table. */ 188 189#define A(a) (1 << CGEN_HW_##a) 190 191const CGEN_HW_ENTRY mt_cgen_hw_table[] = 192{ 193 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 194 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 195 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 196 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 197 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 198 { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 199 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 200 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 201}; 202 203#undef A 204 205 206/* The instruction field table. */ 207 208#define A(a) (1 << CGEN_IFLD_##a) 209 210const CGEN_IFLD mt_cgen_ifld_table[] = 211{ 212 { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 213 { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 214 { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 215 { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 216 { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 217 { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 218 { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 219 { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 220 { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 221 { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 222 { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 223 { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 224 { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 225 { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 226 { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 227 { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 228 { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 229 { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 230 { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 231 { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 232 { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 233 { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 234 { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 235 { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 236 { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 237 { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 238 { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 239 { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 240 { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 241 { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 242 { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 243 { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 244 { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 245 { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 246 { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 247 { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 248 { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 249 { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 250 { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 251 { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 252 { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 253 { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 254 { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 255 { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 256 { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 257 { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 258 { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 259 { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 260 { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 261 { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 262 { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 263 { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 264 { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 265 { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 266 { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 267 { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 268 { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 269 { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 270 { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 271 { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 272 { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 273 { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 274 { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 275 { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 276 { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 277 { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 278 { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 279 { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 280 { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 281 { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 282 { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 283 { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 284 { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } }, 285 { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } }, 286 { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 287 { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 288 { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 289 { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 290 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 291}; 292 293#undef A 294 295 296 297/* multi ifield declarations */ 298 299 300 301/* multi ifield definitions */ 302 303 304/* The operand table. */ 305 306#define A(a) (1 << CGEN_OPERAND_##a) 307#define OPERAND(op) MT_OPERAND_##op 308 309const CGEN_OPERAND mt_cgen_operand_table[] = 310{ 311/* pc: program counter */ 312 { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0, 313 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } }, 314 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 315/* frsr1: register */ 316 { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4, 317 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } }, 318 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 319/* frsr2: register */ 320 { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4, 321 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } }, 322 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 323/* frdr: register */ 324 { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4, 325 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } }, 326 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 327/* frdrrr: register */ 328 { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4, 329 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } }, 330 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 331/* imm16: immediate value - sign extd */ 332 { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16, 333 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } }, 334 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 335/* imm16z: immediate value - zero extd */ 336 { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16, 337 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } }, 338 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 339/* imm16o: immediate value */ 340 { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16, 341 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } }, 342 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 343/* rc: rc */ 344 { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1, 345 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } }, 346 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 347/* rcnum: rcnum */ 348 { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3, 349 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } }, 350 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 351/* contnum: context number */ 352 { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9, 353 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } }, 354 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 355/* rbbc: omega network configuration */ 356 { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2, 357 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } }, 358 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 359/* colnum: column number */ 360 { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3, 361 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } }, 362 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 363/* rownum: row number */ 364 { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3, 365 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } }, 366 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 367/* rownum1: row number */ 368 { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3, 369 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } }, 370 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 371/* rownum2: row number */ 372 { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3, 373 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } }, 374 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 375/* rc1: rc1 */ 376 { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1, 377 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } }, 378 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 379/* rc2: rc2 */ 380 { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1, 381 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } }, 382 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 383/* cbrb: data-bus orientation */ 384 { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1, 385 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } }, 386 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 387/* cell: cell */ 388 { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3, 389 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } }, 390 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 391/* dup: dup */ 392 { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1, 393 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } }, 394 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 395/* ctxdisp: context displacement */ 396 { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6, 397 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } }, 398 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 399/* fbdisp: frame buffer displacement */ 400 { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6, 401 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } }, 402 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 403/* type: type */ 404 { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2, 405 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } }, 406 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 407/* mask: mask */ 408 { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16, 409 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } }, 410 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 411/* bankaddr: bank address */ 412 { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13, 413 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } }, 414 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 415/* incamt: increment amount */ 416 { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8, 417 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } }, 418 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 419/* xmode: xmode */ 420 { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1, 421 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } }, 422 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 423/* mask1: mask1 */ 424 { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3, 425 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } }, 426 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 427/* ball: b_all */ 428 { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1, 429 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } }, 430 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 431/* brc: b_r_c */ 432 { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3, 433 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } }, 434 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 435/* rda: rd */ 436 { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1, 437 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } }, 438 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 439/* wr: wr */ 440 { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1, 441 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } }, 442 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 443/* ball2: b_all2 */ 444 { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1, 445 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } }, 446 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 447/* brc2: b_r_c2 */ 448 { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3, 449 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } }, 450 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 451/* perm: perm */ 452 { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2, 453 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } }, 454 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 455/* a23: a23 */ 456 { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1, 457 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } }, 458 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 459/* cr: c-r */ 460 { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3, 461 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } }, 462 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 463/* cbs: cbs */ 464 { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2, 465 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } }, 466 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 467/* incr: incr */ 468 { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6, 469 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } }, 470 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 471/* length: length */ 472 { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3, 473 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } }, 474 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 475/* cbx: cbx */ 476 { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3, 477 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } }, 478 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 479/* ccb: ccb */ 480 { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1, 481 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } }, 482 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 483/* cdb: cdb */ 484 { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1, 485 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } }, 486 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 487/* mode: mode */ 488 { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2, 489 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } }, 490 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 491/* id: i/d */ 492 { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1, 493 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } }, 494 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 495/* size: size */ 496 { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14, 497 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } }, 498 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 499/* fbincr: fb incr */ 500 { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4, 501 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } }, 502 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 503/* loopsize: immediate value */ 504 { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8, 505 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } }, 506 { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } } }, 507/* imm16l: immediate value */ 508 { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16, 509 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } }, 510 { 0, { { { (1<<MACH_MS2), 0 } } } } }, 511/* rc3: rc3 */ 512 { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1, 513 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } }, 514 { 0, { { { (1<<MACH_MS2), 0 } } } } }, 515/* cb1sel: cb1sel */ 516 { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3, 517 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } }, 518 { 0, { { { (1<<MACH_MS2), 0 } } } } }, 519/* cb2sel: cb2sel */ 520 { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3, 521 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } }, 522 { 0, { { { (1<<MACH_MS2), 0 } } } } }, 523/* cb1incr: cb1incr */ 524 { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6, 525 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } }, 526 { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } }, 527/* cb2incr: cb2incr */ 528 { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6, 529 { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } }, 530 { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } } }, 531/* sentinel */ 532 { 0, 0, 0, 0, 0, 533 { 0, { (const PTR) 0 } }, 534 { 0, { { { (1<<MACH_BASE), 0 } } } } } 535}; 536 537#undef A 538 539 540/* The instruction table. */ 541 542#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 543#define A(a) (1 << CGEN_INSN_##a) 544 545static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] = 546{ 547 /* Special null first entry. 548 A `num' value of zero is thus invalid. 549 Also, the special `invalid' insn resides here. */ 550 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 551/* add $frdrrr,$frsr1,$frsr2 */ 552 { 553 MT_INSN_ADD, "add", "add", 32, 554 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 555 }, 556/* addu $frdrrr,$frsr1,$frsr2 */ 557 { 558 MT_INSN_ADDU, "addu", "addu", 32, 559 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 560 }, 561/* addi $frdr,$frsr1,#$imm16 */ 562 { 563 MT_INSN_ADDI, "addi", "addi", 32, 564 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 565 }, 566/* addui $frdr,$frsr1,#$imm16z */ 567 { 568 MT_INSN_ADDUI, "addui", "addui", 32, 569 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 570 }, 571/* sub $frdrrr,$frsr1,$frsr2 */ 572 { 573 MT_INSN_SUB, "sub", "sub", 32, 574 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 575 }, 576/* subu $frdrrr,$frsr1,$frsr2 */ 577 { 578 MT_INSN_SUBU, "subu", "subu", 32, 579 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 580 }, 581/* subi $frdr,$frsr1,#$imm16 */ 582 { 583 MT_INSN_SUBI, "subi", "subi", 32, 584 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 585 }, 586/* subui $frdr,$frsr1,#$imm16z */ 587 { 588 MT_INSN_SUBUI, "subui", "subui", 32, 589 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 590 }, 591/* mul $frdrrr,$frsr1,$frsr2 */ 592 { 593 MT_INSN_MUL, "mul", "mul", 32, 594 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 595 }, 596/* muli $frdr,$frsr1,#$imm16 */ 597 { 598 MT_INSN_MULI, "muli", "muli", 32, 599 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 600 }, 601/* and $frdrrr,$frsr1,$frsr2 */ 602 { 603 MT_INSN_AND, "and", "and", 32, 604 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 605 }, 606/* andi $frdr,$frsr1,#$imm16z */ 607 { 608 MT_INSN_ANDI, "andi", "andi", 32, 609 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 610 }, 611/* or $frdrrr,$frsr1,$frsr2 */ 612 { 613 MT_INSN_OR, "or", "or", 32, 614 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 615 }, 616/* nop */ 617 { 618 MT_INSN_NOP, "nop", "nop", 32, 619 { 0, { { { (1<<MACH_BASE), 0 } } } } 620 }, 621/* ori $frdr,$frsr1,#$imm16z */ 622 { 623 MT_INSN_ORI, "ori", "ori", 32, 624 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 625 }, 626/* xor $frdrrr,$frsr1,$frsr2 */ 627 { 628 MT_INSN_XOR, "xor", "xor", 32, 629 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 630 }, 631/* xori $frdr,$frsr1,#$imm16z */ 632 { 633 MT_INSN_XORI, "xori", "xori", 32, 634 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 635 }, 636/* nand $frdrrr,$frsr1,$frsr2 */ 637 { 638 MT_INSN_NAND, "nand", "nand", 32, 639 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 640 }, 641/* nandi $frdr,$frsr1,#$imm16z */ 642 { 643 MT_INSN_NANDI, "nandi", "nandi", 32, 644 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 645 }, 646/* nor $frdrrr,$frsr1,$frsr2 */ 647 { 648 MT_INSN_NOR, "nor", "nor", 32, 649 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 650 }, 651/* nori $frdr,$frsr1,#$imm16z */ 652 { 653 MT_INSN_NORI, "nori", "nori", 32, 654 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 655 }, 656/* xnor $frdrrr,$frsr1,$frsr2 */ 657 { 658 MT_INSN_XNOR, "xnor", "xnor", 32, 659 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 660 }, 661/* xnori $frdr,$frsr1,#$imm16z */ 662 { 663 MT_INSN_XNORI, "xnori", "xnori", 32, 664 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 665 }, 666/* ldui $frdr,#$imm16z */ 667 { 668 MT_INSN_LDUI, "ldui", "ldui", 32, 669 { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } } 670 }, 671/* lsl $frdrrr,$frsr1,$frsr2 */ 672 { 673 MT_INSN_LSL, "lsl", "lsl", 32, 674 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } 675 }, 676/* lsli $frdr,$frsr1,#$imm16 */ 677 { 678 MT_INSN_LSLI, "lsli", "lsli", 32, 679 { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } 680 }, 681/* lsr $frdrrr,$frsr1,$frsr2 */ 682 { 683 MT_INSN_LSR, "lsr", "lsr", 32, 684 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } 685 }, 686/* lsri $frdr,$frsr1,#$imm16 */ 687 { 688 MT_INSN_LSRI, "lsri", "lsri", 32, 689 { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } 690 }, 691/* asr $frdrrr,$frsr1,$frsr2 */ 692 { 693 MT_INSN_ASR, "asr", "asr", 32, 694 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } } 695 }, 696/* asri $frdr,$frsr1,#$imm16 */ 697 { 698 MT_INSN_ASRI, "asri", "asri", 32, 699 { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } } 700 }, 701/* brlt $frsr1,$frsr2,$imm16o */ 702 { 703 MT_INSN_BRLT, "brlt", "brlt", 32, 704 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } 705 }, 706/* brle $frsr1,$frsr2,$imm16o */ 707 { 708 MT_INSN_BRLE, "brle", "brle", 32, 709 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } 710 }, 711/* breq $frsr1,$frsr2,$imm16o */ 712 { 713 MT_INSN_BREQ, "breq", "breq", 32, 714 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } 715 }, 716/* brne $frsr1,$frsr2,$imm16o */ 717 { 718 MT_INSN_BRNE, "brne", "brne", 32, 719 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } } 720 }, 721/* jmp $imm16o */ 722 { 723 MT_INSN_JMP, "jmp", "jmp", 32, 724 { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 725 }, 726/* jal $frdrrr,$frsr1 */ 727 { 728 MT_INSN_JAL, "jal", "jal", 32, 729 { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 730 }, 731/* dbnz $frsr1,$imm16o */ 732 { 733 MT_INSN_DBNZ, "dbnz", "dbnz", 32, 734 { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 735 }, 736/* ei */ 737 { 738 MT_INSN_EI, "ei", "ei", 32, 739 { 0, { { { (1<<MACH_BASE), 0 } } } } 740 }, 741/* di */ 742 { 743 MT_INSN_DI, "di", "di", 32, 744 { 0, { { { (1<<MACH_BASE), 0 } } } } 745 }, 746/* si $frdrrr */ 747 { 748 MT_INSN_SI, "si", "si", 32, 749 { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 750 }, 751/* reti $frsr1 */ 752 { 753 MT_INSN_RETI, "reti", "reti", 32, 754 { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 755 }, 756/* ldw $frdr,$frsr1,#$imm16 */ 757 { 758 MT_INSN_LDW, "ldw", "ldw", 32, 759 { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } 760 }, 761/* stw $frsr2,$frsr1,#$imm16 */ 762 { 763 MT_INSN_STW, "stw", "stw", 32, 764 { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } } 765 }, 766/* break */ 767 { 768 MT_INSN_BREAK, "break", "break", 32, 769 { 0, { { { (1<<MACH_BASE), 0 } } } } 770 }, 771/* iflush */ 772 { 773 MT_INSN_IFLUSH, "iflush", "iflush", 32, 774 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 775 }, 776/* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ 777 { 778 MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32, 779 { 0, { { { (1<<MACH_MS1), 0 } } } } 780 }, 781/* ldfb $frsr1,$frsr2,#$imm16z */ 782 { 783 MT_INSN_LDFB, "ldfb", "ldfb", 32, 784 { 0, { { { (1<<MACH_MS1), 0 } } } } 785 }, 786/* stfb $frsr1,$frsr2,#$imm16z */ 787 { 788 MT_INSN_STFB, "stfb", "stfb", 32, 789 { 0, { { { (1<<MACH_MS1), 0 } } } } 790 }, 791/* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 792 { 793 MT_INSN_FBCB, "fbcb", "fbcb", 32, 794 { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } } 795 }, 796/* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 797 { 798 MT_INSN_MFBCB, "mfbcb", "mfbcb", 32, 799 { 0, { { { (1<<MACH_BASE), 0 } } } } 800 }, 801/* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 802 { 803 MT_INSN_FBCCI, "fbcci", "fbcci", 32, 804 { 0, { { { (1<<MACH_BASE), 0 } } } } 805 }, 806/* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 807 { 808 MT_INSN_FBRCI, "fbrci", "fbrci", 32, 809 { 0, { { { (1<<MACH_BASE), 0 } } } } 810 }, 811/* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 812 { 813 MT_INSN_FBCRI, "fbcri", "fbcri", 32, 814 { 0, { { { (1<<MACH_BASE), 0 } } } } 815 }, 816/* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 817 { 818 MT_INSN_FBRRI, "fbrri", "fbrri", 32, 819 { 0, { { { (1<<MACH_BASE), 0 } } } } 820 }, 821/* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 822 { 823 MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32, 824 { 0, { { { (1<<MACH_BASE), 0 } } } } 825 }, 826/* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 827 { 828 MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32, 829 { 0, { { { (1<<MACH_BASE), 0 } } } } 830 }, 831/* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 832 { 833 MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32, 834 { 0, { { { (1<<MACH_BASE), 0 } } } } 835 }, 836/* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 837 { 838 MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32, 839 { 0, { { { (1<<MACH_BASE), 0 } } } } 840 }, 841/* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 842 { 843 MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32, 844 { 0, { { { (1<<MACH_BASE), 0 } } } } 845 }, 846/* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 847 { 848 MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32, 849 { 0, { { { (1<<MACH_BASE), 0 } } } } 850 }, 851/* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 852 { 853 MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32, 854 { 0, { { { (1<<MACH_BASE), 0 } } } } 855 }, 856/* cbcast #$mask,#$rc2,#$ctxdisp */ 857 { 858 MT_INSN_CBCAST, "cbcast", "cbcast", 32, 859 { 0, { { { (1<<MACH_BASE), 0 } } } } 860 }, 861/* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ 862 { 863 MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32, 864 { 0, { { { (1<<MACH_BASE), 0 } } } } 865 }, 866/* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ 867 { 868 MT_INSN_WFBI, "wfbi", "wfbi", 32, 869 { 0, { { { (1<<MACH_BASE), 0 } } } } 870 }, 871/* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ 872 { 873 MT_INSN_WFB, "wfb", "wfb", 32, 874 { 0, { { { (1<<MACH_BASE), 0 } } } } 875 }, 876/* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 877 { 878 MT_INSN_RCRISC, "rcrisc", "rcrisc", 32, 879 { 0, { { { (1<<MACH_BASE), 0 } } } } 880 }, 881/* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 882 { 883 MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32, 884 { 0, { { { (1<<MACH_BASE), 0 } } } } 885 }, 886/* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ 887 { 888 MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32, 889 { 0, { { { (1<<MACH_BASE), 0 } } } } 890 }, 891/* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ 892 { 893 MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32, 894 { 0, { { { (1<<MACH_BASE), 0 } } } } 895 }, 896/* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 897 { 898 MT_INSN_WFBINC, "wfbinc", "wfbinc", 32, 899 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 900 }, 901/* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 902 { 903 MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32, 904 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 905 }, 906/* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 907 { 908 MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32, 909 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 910 }, 911/* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 912 { 913 MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32, 914 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 915 }, 916/* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 917 { 918 MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32, 919 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 920 }, 921/* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 922 { 923 MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32, 924 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 925 }, 926/* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 927 { 928 MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32, 929 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 930 }, 931/* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 932 { 933 MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32, 934 { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } } 935 }, 936/* loop $frsr1,$loopsize */ 937 { 938 MT_INSN_LOOP, "loop", "loop", 32, 939 { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } } 940 }, 941/* loopi #$imm16l,$loopsize */ 942 { 943 MT_INSN_LOOPI, "loopi", "loopi", 32, 944 { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } } 945 }, 946/* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ 947 { 948 MT_INSN_DFBC, "dfbc", "dfbc", 32, 949 { 0, { { { (1<<MACH_MS2), 0 } } } } 950 }, 951/* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */ 952 { 953 MT_INSN_DWFB, "dwfb", "dwfb", 32, 954 { 0, { { { (1<<MACH_MS2), 0 } } } } 955 }, 956/* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ 957 { 958 MT_INSN_FBWFB, "fbwfb", "fbwfb", 32, 959 { 0, { { { (1<<MACH_MS2), 0 } } } } 960 }, 961/* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */ 962 { 963 MT_INSN_DFBR, "dfbr", "dfbr", 32, 964 { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } } 965 }, 966}; 967 968#undef OP 969#undef A 970 971/* Initialize anything needed to be done once, before any cpu_open call. */ 972 973static void 974init_tables (void) 975{ 976} 977 978static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 979static void build_hw_table (CGEN_CPU_TABLE *); 980static void build_ifield_table (CGEN_CPU_TABLE *); 981static void build_operand_table (CGEN_CPU_TABLE *); 982static void build_insn_table (CGEN_CPU_TABLE *); 983static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *); 984 985/* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name. */ 986 987static const CGEN_MACH * 988lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 989{ 990 while (table->name) 991 { 992 if (strcmp (name, table->bfd_name) == 0) 993 return table; 994 ++table; 995 } 996 abort (); 997} 998 999/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ 1000 1001static void 1002build_hw_table (CGEN_CPU_TABLE *cd) 1003{ 1004 int i; 1005 int machs = cd->machs; 1006 const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0]; 1007 /* MAX_HW is only an upper bound on the number of selected entries. 1008 However each entry is indexed by it's enum so there can be holes in 1009 the table. */ 1010 const CGEN_HW_ENTRY **selected = 1011 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1012 1013 cd->hw_table.init_entries = init; 1014 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 1015 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1016 /* ??? For now we just use machs to determine which ones we want. */ 1017 for (i = 0; init[i].name != NULL; ++i) 1018 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 1019 & machs) 1020 selected[init[i].type] = &init[i]; 1021 cd->hw_table.entries = selected; 1022 cd->hw_table.num_entries = MAX_HW; 1023} 1024 1025/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ 1026 1027static void 1028build_ifield_table (CGEN_CPU_TABLE *cd) 1029{ 1030 cd->ifld_table = & mt_cgen_ifld_table[0]; 1031} 1032 1033/* Subroutine of mt_cgen_cpu_open to build the hardware table. */ 1034 1035static void 1036build_operand_table (CGEN_CPU_TABLE *cd) 1037{ 1038 int i; 1039 int machs = cd->machs; 1040 const CGEN_OPERAND *init = & mt_cgen_operand_table[0]; 1041 /* MAX_OPERANDS is only an upper bound on the number of selected entries. 1042 However each entry is indexed by it's enum so there can be holes in 1043 the table. */ 1044 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 1045 1046 cd->operand_table.init_entries = init; 1047 cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 1048 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 1049 /* ??? For now we just use mach to determine which ones we want. */ 1050 for (i = 0; init[i].name != NULL; ++i) 1051 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 1052 & machs) 1053 selected[init[i].type] = &init[i]; 1054 cd->operand_table.entries = selected; 1055 cd->operand_table.num_entries = MAX_OPERANDS; 1056} 1057 1058/* Subroutine of mt_cgen_cpu_open to build the hardware table. 1059 ??? This could leave out insns not supported by the specified mach/isa, 1060 but that would cause errors like "foo only supported by bar" to become 1061 "unknown insn", so for now we include all insns and require the app to 1062 do the checking later. 1063 ??? On the other hand, parsing of such insns may require their hardware or 1064 operand elements to be in the table [which they mightn't be]. */ 1065 1066static void 1067build_insn_table (CGEN_CPU_TABLE *cd) 1068{ 1069 int i; 1070 const CGEN_IBASE *ib = & mt_cgen_insn_table[0]; 1071 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 1072 1073 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 1074 for (i = 0; i < MAX_INSNS; ++i) 1075 insns[i].base = &ib[i]; 1076 cd->insn_table.init_entries = insns; 1077 cd->insn_table.entry_size = sizeof (CGEN_IBASE); 1078 cd->insn_table.num_init_entries = MAX_INSNS; 1079} 1080 1081/* Subroutine of mt_cgen_cpu_open to rebuild the tables. */ 1082 1083static void 1084mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 1085{ 1086 int i; 1087 CGEN_BITSET *isas = cd->isas; 1088 unsigned int machs = cd->machs; 1089 1090 cd->int_insn_p = CGEN_INT_INSN_P; 1091 1092 /* Data derived from the isa spec. */ 1093#define UNSET (CGEN_SIZE_UNKNOWN + 1) 1094 cd->default_insn_bitsize = UNSET; 1095 cd->base_insn_bitsize = UNSET; 1096 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 1097 cd->max_insn_bitsize = 0; 1098 for (i = 0; i < MAX_ISAS; ++i) 1099 if (cgen_bitset_contains (isas, i)) 1100 { 1101 const CGEN_ISA *isa = & mt_cgen_isa_table[i]; 1102 1103 /* Default insn sizes of all selected isas must be 1104 equal or we set the result to 0, meaning "unknown". */ 1105 if (cd->default_insn_bitsize == UNSET) 1106 cd->default_insn_bitsize = isa->default_insn_bitsize; 1107 else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 1108 ; /* This is ok. */ 1109 else 1110 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 1111 1112 /* Base insn sizes of all selected isas must be equal 1113 or we set the result to 0, meaning "unknown". */ 1114 if (cd->base_insn_bitsize == UNSET) 1115 cd->base_insn_bitsize = isa->base_insn_bitsize; 1116 else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 1117 ; /* This is ok. */ 1118 else 1119 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 1120 1121 /* Set min,max insn sizes. */ 1122 if (isa->min_insn_bitsize < cd->min_insn_bitsize) 1123 cd->min_insn_bitsize = isa->min_insn_bitsize; 1124 if (isa->max_insn_bitsize > cd->max_insn_bitsize) 1125 cd->max_insn_bitsize = isa->max_insn_bitsize; 1126 } 1127 1128 /* Data derived from the mach spec. */ 1129 for (i = 0; i < MAX_MACHS; ++i) 1130 if (((1 << i) & machs) != 0) 1131 { 1132 const CGEN_MACH *mach = & mt_cgen_mach_table[i]; 1133 1134 if (mach->insn_chunk_bitsize != 0) 1135 { 1136 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 1137 { 1138 fprintf (stderr, "mt_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", 1139 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 1140 abort (); 1141 } 1142 1143 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 1144 } 1145 } 1146 1147 /* Determine which hw elements are used by MACH. */ 1148 build_hw_table (cd); 1149 1150 /* Build the ifield table. */ 1151 build_ifield_table (cd); 1152 1153 /* Determine which operands are used by MACH/ISA. */ 1154 build_operand_table (cd); 1155 1156 /* Build the instruction table. */ 1157 build_insn_table (cd); 1158} 1159 1160/* Initialize a cpu table and return a descriptor. 1161 It's much like opening a file, and must be the first function called. 1162 The arguments are a set of (type/value) pairs, terminated with 1163 CGEN_CPU_OPEN_END. 1164 1165 Currently supported values: 1166 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 1167 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 1168 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 1169 CGEN_CPU_OPEN_ENDIAN: specify endian choice 1170 CGEN_CPU_OPEN_END: terminates arguments 1171 1172 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 1173 precluded. */ 1174 1175CGEN_CPU_DESC 1176mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 1177{ 1178 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 1179 static int init_p; 1180 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 1181 unsigned int machs = 0; /* 0 = "unspecified" */ 1182 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 1183 va_list ap; 1184 1185 if (! init_p) 1186 { 1187 init_tables (); 1188 init_p = 1; 1189 } 1190 1191 memset (cd, 0, sizeof (*cd)); 1192 1193 va_start (ap, arg_type); 1194 while (arg_type != CGEN_CPU_OPEN_END) 1195 { 1196 switch (arg_type) 1197 { 1198 case CGEN_CPU_OPEN_ISAS : 1199 isas = va_arg (ap, CGEN_BITSET *); 1200 break; 1201 case CGEN_CPU_OPEN_MACHS : 1202 machs = va_arg (ap, unsigned int); 1203 break; 1204 case CGEN_CPU_OPEN_BFDMACH : 1205 { 1206 const char *name = va_arg (ap, const char *); 1207 const CGEN_MACH *mach = 1208 lookup_mach_via_bfd_name (mt_cgen_mach_table, name); 1209 1210 machs |= 1 << mach->num; 1211 break; 1212 } 1213 case CGEN_CPU_OPEN_ENDIAN : 1214 endian = va_arg (ap, enum cgen_endian); 1215 break; 1216 default : 1217 fprintf (stderr, "mt_cgen_cpu_open: unsupported argument `%d'\n", 1218 arg_type); 1219 abort (); /* ??? return NULL? */ 1220 } 1221 arg_type = va_arg (ap, enum cgen_cpu_open_arg); 1222 } 1223 va_end (ap); 1224 1225 /* Mach unspecified means "all". */ 1226 if (machs == 0) 1227 machs = (1 << MAX_MACHS) - 1; 1228 /* Base mach is always selected. */ 1229 machs |= 1; 1230 if (endian == CGEN_ENDIAN_UNKNOWN) 1231 { 1232 /* ??? If target has only one, could have a default. */ 1233 fprintf (stderr, "mt_cgen_cpu_open: no endianness specified\n"); 1234 abort (); 1235 } 1236 1237 cd->isas = cgen_bitset_copy (isas); 1238 cd->machs = machs; 1239 cd->endian = endian; 1240 /* FIXME: for the sparc case we can determine insn-endianness statically. 1241 The worry here is where both data and insn endian can be independently 1242 chosen, in which case this function will need another argument. 1243 Actually, will want to allow for more arguments in the future anyway. */ 1244 cd->insn_endian = endian; 1245 1246 /* Table (re)builder. */ 1247 cd->rebuild_tables = mt_cgen_rebuild_tables; 1248 mt_cgen_rebuild_tables (cd); 1249 1250 /* Default to not allowing signed overflow. */ 1251 cd->signed_overflow_ok_p = 0; 1252 1253 return (CGEN_CPU_DESC) cd; 1254} 1255 1256/* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 1257 MACH_NAME is the bfd name of the mach. */ 1258 1259CGEN_CPU_DESC 1260mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 1261{ 1262 return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 1263 CGEN_CPU_OPEN_ENDIAN, endian, 1264 CGEN_CPU_OPEN_END); 1265} 1266 1267/* Close a cpu table. 1268 ??? This can live in a machine independent file, but there's currently 1269 no place to put this file (there's no libcgen). libopcodes is the wrong 1270 place as some simulator ports use this but they don't use libopcodes. */ 1271 1272void 1273mt_cgen_cpu_close (CGEN_CPU_DESC cd) 1274{ 1275 unsigned int i; 1276 const CGEN_INSN *insns; 1277 1278 if (cd->macro_insn_table.init_entries) 1279 { 1280 insns = cd->macro_insn_table.init_entries; 1281 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 1282 if (CGEN_INSN_RX ((insns))) 1283 regfree (CGEN_INSN_RX (insns)); 1284 } 1285 1286 if (cd->insn_table.init_entries) 1287 { 1288 insns = cd->insn_table.init_entries; 1289 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 1290 if (CGEN_INSN_RX (insns)) 1291 regfree (CGEN_INSN_RX (insns)); 1292 } 1293 1294 if (cd->macro_insn_table.init_entries) 1295 free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 1296 1297 if (cd->insn_table.init_entries) 1298 free ((CGEN_INSN *) cd->insn_table.init_entries); 1299 1300 if (cd->hw_table.entries) 1301 free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 1302 1303 if (cd->operand_table.entries) 1304 free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 1305 1306 free (cd); 1307} 1308 1309