1139804Simp/* CPU data for m32r. 2185435Sbz 3185435SbzTHIS FILE IS MACHINE GENERATED WITH CGEN. 4191673Sjamie 5185435SbzCopyright (C) 1996-2017 Free Software Foundation, Inc. 6190466Sjamie 7185404SbzThis file is part of the GNU Binutils and/or GDB, the GNU debugger. 8185404Sbz 9185404Sbz This file is free software; you can redistribute it and/or modify 10185404Sbz it under the terms of the GNU General Public License as published by 11185404Sbz the Free Software Foundation; either version 3, or (at your option) 12185404Sbz any later version. 13185404Sbz 14185404Sbz It is distributed in the hope that it will be useful, but WITHOUT 15185404Sbz ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16185404Sbz or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17185404Sbz License for more details. 18185404Sbz 19185404Sbz You should have received a copy of the GNU General Public License along 20185404Sbz with this program; if not, write to the Free Software Foundation, Inc., 21185404Sbz 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22185404Sbz 23185404Sbz*/ 24185404Sbz 25185404Sbz#include "sysdep.h" 26185404Sbz#include <stdio.h> 2746197Sphk#include <stdarg.h> 2846155Sphk#include "ansidecl.h" 29116182Sobrien#include "bfd.h" 30116182Sobrien#include "symcat.h" 31116182Sobrien#include "m32r-desc.h" 32193066Sjamie#include "m32r-opc.h" 33185435Sbz#include "opintl.h" 34185435Sbz#include "libiberty.h" 35185435Sbz#include "xregex.h" 36131177Spjd 3746155Sphk/* Attributes. */ 3846155Sphk 3946155Sphkstatic const CGEN_ATTR_ENTRY bool_attr[] = 4046155Sphk{ 4146155Sphk { "#f", 0 }, 4246155Sphk { "#t", 1 }, 4346155Sphk { 0, 0 } 44192895Sjamie}; 45164032Srwatson 4646155Sphkstatic const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 47124882Srwatson{ 48177785Skib { "base", MACH_BASE }, 4946155Sphk { "m32r", MACH_M32R }, 5087275Srwatson { "m32rx", MACH_M32RX }, 5187275Srwatson { "m32r2", MACH_M32R2 }, 52168401Spjd { "max", MACH_MAX }, 53193066Sjamie { 0, 0 } 54113275Smike}; 55147185Spjd 56113275Smikestatic const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 5746155Sphk{ 58113275Smike { "m32r", ISA_M32R }, 5957163Srwatson { "max", ISA_MAX }, 60113275Smike { 0, 0 } 61181803Sbz}; 6246155Sphk 6346155Sphkstatic const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED = 64185435Sbz{ 65185435Sbz { "NONE", PIPE_NONE }, 66185435Sbz { "O", PIPE_O }, 67185435Sbz { "S", PIPE_S }, 68185435Sbz { "OS", PIPE_OS }, 69185435Sbz { "O_OS", PIPE_O_OS }, 7046155Sphk { 0, 0 } 71163606Srwatson}; 72163606Srwatson 73195944Sjamieconst CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] = 74195944Sjamie{ 7546155Sphk { "MACH", & MACH_attr[0], & MACH_attr[0] }, 7646155Sphk { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 77192895Sjamie { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 78192895Sjamie { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 79192895Sjamie { "RESERVED", &bool_attr[0], &bool_attr[0] }, 80192895Sjamie { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 81192895Sjamie { "SIGNED", &bool_attr[0], &bool_attr[0] }, 82192895Sjamie { "RELOC", &bool_attr[0], &bool_attr[0] }, 83192895Sjamie { 0, 0, 0 } 84192895Sjamie}; 85194762Sjamie 86195944Sjamieconst CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] = 87192895Sjamie{ 88193066Sjamie { "MACH", & MACH_attr[0], & MACH_attr[0] }, 89192895Sjamie { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 90192895Sjamie { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 91192895Sjamie { "PC", &bool_attr[0], &bool_attr[0] }, 9257163Srwatson { "PROFILE", &bool_attr[0], &bool_attr[0] }, 93192895Sjamie { 0, 0, 0 } 94168401Spjd}; 95191673Sjamie 96191673Sjamieconst CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = 97179881Sdelphij{ 98113275Smike { "MACH", & MACH_attr[0], & MACH_attr[0] }, 99191673Sjamie { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 100190466Sjamie { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 101191673Sjamie { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 102192895Sjamie { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 103192895Sjamie { "SIGNED", &bool_attr[0], &bool_attr[0] }, 104185435Sbz { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 105190466Sjamie { "RELAX", &bool_attr[0], &bool_attr[0] }, 106192895Sjamie { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 107185435Sbz { "RELOC", &bool_attr[0], &bool_attr[0] }, 108185435Sbz { 0, 0, 0 } 109190466Sjamie}; 110192895Sjamie 111185435Sbzconst CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = 112113275Smike{ 113191673Sjamie { "MACH", & MACH_attr[0], & MACH_attr[0] }, 114191673Sjamie { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, 115191673Sjamie { "ALIAS", &bool_attr[0], &bool_attr[0] }, 116191673Sjamie { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 117191673Sjamie { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 118191673Sjamie { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 119113275Smike { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 120192895Sjamie { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 121192895Sjamie { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 122192895Sjamie { "RELAXED", &bool_attr[0], &bool_attr[0] }, 123192895Sjamie { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 124192895Sjamie { "PBB", &bool_attr[0], &bool_attr[0] }, 125192895Sjamie { "FILL-SLOT", &bool_attr[0], &bool_attr[0] }, 126192895Sjamie { "SPECIAL", &bool_attr[0], &bool_attr[0] }, 127192895Sjamie { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] }, 128192895Sjamie { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] }, 129195870Sjamie { 0, 0, 0 } 130195870Sjamie}; 131195870Sjamie 132195870Sjamie/* Instruction set variants. */ 133195870Sjamie 134195870Sjamiestatic const CGEN_ISA m32r_cgen_isa_table[] = { 135195870Sjamie { "m32r", 32, 32, 16, 32 }, 136195870Sjamie { 0, 0, 0, 0, 0 } 137195870Sjamie}; 138195870Sjamie 139195870Sjamie/* Machine variants. */ 140192895Sjamie 141195870Sjamiestatic const CGEN_MACH m32r_cgen_mach_table[] = { 142192895Sjamie { "m32r", "m32r", MACH_M32R, 0 }, 143192895Sjamie { "m32rx", "m32rx", MACH_M32RX, 0 }, 144195870Sjamie { "m32r2", "m32r2", MACH_M32R2, 0 }, 145192895Sjamie { 0, 0, 0, 0 } 146192895Sjamie}; 147192895Sjamie 148192895Sjamiestatic CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] = 149192895Sjamie{ 150192895Sjamie { "fp", 13, {0, {{{0, 0}}}}, 0, 0 }, 151192895Sjamie { "lr", 14, {0, {{{0, 0}}}}, 0, 0 }, 152192895Sjamie { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }, 153192895Sjamie { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 154192895Sjamie { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 155192895Sjamie { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 156192895Sjamie { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 157192895Sjamie { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 158192895Sjamie { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 159192895Sjamie { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 160192895Sjamie { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 161192895Sjamie { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 162192895Sjamie { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 163192895Sjamie { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 164192895Sjamie { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 165192895Sjamie { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 166192895Sjamie { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 167192895Sjamie { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 168192895Sjamie { "r15", 15, {0, {{{0, 0}}}}, 0, 0 } 169192895Sjamie}; 170192895Sjamie 171192895SjamieCGEN_KEYWORD m32r_cgen_opval_gr_names = 172193865Sjamie{ 173192895Sjamie & m32r_cgen_opval_gr_names_entries[0], 174192895Sjamie 19, 175192895Sjamie 0, 0, 0, 0, "" 176185435Sbz}; 177185435Sbz 178185435Sbzstatic CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] = 179185435Sbz{ 180185435Sbz { "psw", 0, {0, {{{0, 0}}}}, 0, 0 }, 181185435Sbz { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 }, 182185435Sbz { "spi", 2, {0, {{{0, 0}}}}, 0, 0 }, 183185435Sbz { "spu", 3, {0, {{{0, 0}}}}, 0, 0 }, 184185435Sbz { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 }, 185185435Sbz { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 }, 186185435Sbz { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 }, 187185435Sbz { "evb", 5, {0, {{{0, 0}}}}, 0, 0 }, 188185435Sbz { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 }, 189185435Sbz { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 }, 190185435Sbz { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 }, 191185435Sbz { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 }, 192185435Sbz { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 }, 193185435Sbz { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 }, 194185435Sbz { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 }, 195185435Sbz { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 }, 196185435Sbz { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 }, 197185435Sbz { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 }, 198185435Sbz { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 }, 199185435Sbz { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 }, 200185435Sbz { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 }, 201185435Sbz { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 }, 202185435Sbz { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 }, 203185435Sbz { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 } 204185435Sbz}; 205185435Sbz 206185435SbzCGEN_KEYWORD m32r_cgen_opval_cr_names = 207185435Sbz{ 208185435Sbz & m32r_cgen_opval_cr_names_entries[0], 209185435Sbz 24, 210185435Sbz 0, 0, 0, 0, "" 211185435Sbz}; 212185435Sbz 213190466Sjamiestatic CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] = 214185435Sbz{ 215185435Sbz { "a0", 0, {0, {{{0, 0}}}}, 0, 0 }, 216185435Sbz { "a1", 1, {0, {{{0, 0}}}}, 0, 0 } 217185435Sbz}; 218185435Sbz 219185435SbzCGEN_KEYWORD m32r_cgen_opval_h_accums = 220185435Sbz{ 221185435Sbz & m32r_cgen_opval_h_accums_entries[0], 222185435Sbz 2, 223191673Sjamie 0, 0, 0, 0, "" 224191673Sjamie}; 225191673Sjamie 226191673Sjamie 227191673Sjamie/* The hardware table. */ 228191673Sjamie 229191673Sjamie#define A(a) (1 << CGEN_HW_##a) 230185435Sbz 231191673Sjamieconst CGEN_HW_ENTRY m32r_cgen_hw_table[] = 232191673Sjamie{ 233192895Sjamie { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 234185435Sbz { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 235191673Sjamie { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 236191673Sjamie { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 237191673Sjamie { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 238185435Sbz { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 239191673Sjamie { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 240191673Sjamie { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 241191673Sjamie { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 242191673Sjamie { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 243185435Sbz { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 244192895Sjamie { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 245192895Sjamie { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, 246191673Sjamie { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 247191673Sjamie { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 248191673Sjamie { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 249192895Sjamie { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 250192895Sjamie { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 251192895Sjamie { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 252192895Sjamie}; 253191673Sjamie 254191673Sjamie#undef A 255191673Sjamie 256191673Sjamie 257185435Sbz/* The instruction field table. */ 258191673Sjamie 259191673Sjamie#define A(a) (1 << CGEN_IFLD_##a) 260185435Sbz 261191673Sjamieconst CGEN_IFLD m32r_cgen_ifld_table[] = 262185435Sbz{ 263191673Sjamie { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 264191673Sjamie { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 265191673Sjamie { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 266191673Sjamie { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 267191673Sjamie { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 268192895Sjamie { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 269192895Sjamie { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 270192895Sjamie { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 271192895Sjamie { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 272192895Sjamie { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 273192895Sjamie { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 274192895Sjamie { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 275192895Sjamie { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 276192895Sjamie { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 277192895Sjamie { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 278192895Sjamie { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 279192895Sjamie { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 280193865Sjamie { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 281193865Sjamie { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 282193865Sjamie { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 283193865Sjamie { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 284193865Sjamie { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 285193865Sjamie { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 286193865Sjamie { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 287193865Sjamie { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 288193865Sjamie { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 289192895Sjamie { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 290192895Sjamie { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 291185435Sbz { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 292193865Sjamie { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 293192895Sjamie}; 294192895Sjamie 295192895Sjamie#undef A 296192895Sjamie 297192895Sjamie 298192895Sjamie 299192895Sjamie/* multi ifield declarations */ 300192895Sjamie 301192895Sjamie 302192895Sjamie 303192895Sjamie/* multi ifield definitions */ 304192895Sjamie 305192895Sjamie 306192895Sjamie/* The operand table. */ 307192895Sjamie 308192895Sjamie#define A(a) (1 << CGEN_OPERAND_##a) 309192895Sjamie#define OPERAND(op) M32R_OPERAND_##op 310192895Sjamie 311192895Sjamieconst CGEN_OPERAND m32r_cgen_operand_table[] = 312192895Sjamie{ 313192895Sjamie/* pc: program counter */ 314192895Sjamie { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0, 315192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } }, 316192895Sjamie { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 317192895Sjamie/* sr: source register */ 318192895Sjamie { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4, 319192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 320192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 321192895Sjamie/* dr: destination register */ 322192895Sjamie { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4, 323192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 324192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 325192895Sjamie/* src1: source register 1 */ 326192895Sjamie { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4, 327192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 328192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 329192895Sjamie/* src2: source register 2 */ 330192895Sjamie { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4, 331192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 332192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 333192895Sjamie/* scr: source control register */ 334192895Sjamie { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4, 335192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 336191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 337192895Sjamie/* dcr: destination control register */ 338192895Sjamie { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4, 339191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 340191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 341192895Sjamie/* simm8: 8 bit signed immediate */ 342192895Sjamie { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8, 343192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } }, 344191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 345192895Sjamie/* simm16: 16 bit signed immediate */ 346192895Sjamie { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16, 347191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 348192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 349192895Sjamie/* uimm3: 3 bit unsigned number */ 350192895Sjamie { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3, 351191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, 352192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 353191673Sjamie/* uimm4: 4 bit trap number */ 354191673Sjamie { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4, 355191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, 356192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 357191673Sjamie/* uimm5: 5 bit shift count */ 358192895Sjamie { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5, 359191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, 360191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 361192895Sjamie/* uimm8: 8 bit unsigned immediate */ 362192895Sjamie { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8, 363192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, 364192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 365192895Sjamie/* uimm16: 16 bit unsigned immediate */ 366192895Sjamie { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16, 367192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 368192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 369192895Sjamie/* imm1: 1 bit immediate */ 370192895Sjamie { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1, 371192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, 372192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, 373192895Sjamie/* accd: accumulator destination register */ 374192895Sjamie { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2, 375192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, 376192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, 377192895Sjamie/* accs: accumulator source register */ 378192895Sjamie { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2, 379192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, 380192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, 381192895Sjamie/* acc: accumulator reg (d) */ 382192895Sjamie { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1, 383192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, 384192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } }, 385192895Sjamie/* hash: # prefix */ 386192895Sjamie { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0, 387192895Sjamie { 0, { (const PTR) 0 } }, 388192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 389192895Sjamie/* hi16: high 16 bit immediate, sign optional */ 390191673Sjamie { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16, 391191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } }, 392191673Sjamie { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 393191673Sjamie/* slo16: 16 bit signed immediate, for low() */ 394192895Sjamie { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16, 395192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 396191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 397192895Sjamie/* ulo16: 16 bit unsigned immediate, for low() */ 398192895Sjamie { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16, 399192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 400192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } }, 401192895Sjamie/* uimm24: 24 bit address */ 402192895Sjamie { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24, 403192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } }, 404192895Sjamie { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 405192895Sjamie/* disp8: 8 bit displacement */ 406191673Sjamie { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8, 407191673Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } }, 408191673Sjamie { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 409191673Sjamie/* disp16: 16 bit displacement */ 410192895Sjamie { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16, 411192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } }, 412185435Sbz { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 413185435Sbz/* disp24: 24 bit displacement */ 414192895Sjamie { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24, 415192895Sjamie { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } }, 416192895Sjamie { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 417192895Sjamie/* condbit: condition bit */ 418192895Sjamie { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0, 419192895Sjamie { 0, { (const PTR) 0 } }, 420192895Sjamie { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 421192895Sjamie/* accum: accumulator */ 422192895Sjamie { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0, 423192895Sjamie { 0, { (const PTR) 0 } }, 424192895Sjamie { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 425185435Sbz/* sentinel */ 426192895Sjamie { 0, 0, 0, 0, 0, 427192895Sjamie { 0, { (const PTR) 0 } }, 428191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } } } } } 429191673Sjamie}; 430191673Sjamie 431185435Sbz#undef A 432185435Sbz 433192895Sjamie 434191673Sjamie/* The instruction table. */ 435191673Sjamie 436191673Sjamie#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 437191673Sjamie#define A(a) (1 << CGEN_INSN_##a) 438191673Sjamie 439191673Sjamiestatic const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] = 440191673Sjamie{ 441191673Sjamie /* Special null first entry. 442191673Sjamie A `num' value of zero is thus invalid. 443185435Sbz Also, the special `invalid' insn resides here. */ 444191673Sjamie { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, 445191673Sjamie/* add $dr,$sr */ 446191673Sjamie { 447191673Sjamie M32R_INSN_ADD, "add", "add", 16, 448191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 449191673Sjamie }, 450191673Sjamie/* add3 $dr,$sr,$hash$slo16 */ 451191673Sjamie { 452191673Sjamie M32R_INSN_ADD3, "add3", "add3", 32, 453191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 454191673Sjamie }, 455191673Sjamie/* and $dr,$sr */ 456191673Sjamie { 457191673Sjamie M32R_INSN_AND, "and", "and", 16, 458191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 459191673Sjamie }, 460191673Sjamie/* and3 $dr,$sr,$uimm16 */ 461191673Sjamie { 462191673Sjamie M32R_INSN_AND3, "and3", "and3", 32, 463185435Sbz { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 464190466Sjamie }, 465185435Sbz/* or $dr,$sr */ 466185435Sbz { 467185435Sbz M32R_INSN_OR, "or", "or", 16, 468185435Sbz { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 469191673Sjamie }, 470191673Sjamie/* or3 $dr,$sr,$hash$ulo16 */ 471195945Sjamie { 472191673Sjamie M32R_INSN_OR3, "or3", "or3", 32, 473193066Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 474192895Sjamie }, 475191673Sjamie/* xor $dr,$sr */ 476192895Sjamie { 477193066Sjamie M32R_INSN_XOR, "xor", "xor", 16, 478192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 479192895Sjamie }, 480195870Sjamie/* xor3 $dr,$sr,$uimm16 */ 481195870Sjamie { 482194762Sjamie M32R_INSN_XOR3, "xor3", "xor3", 32, 483191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 484192895Sjamie }, 485191673Sjamie/* addi $dr,$simm8 */ 486191673Sjamie { 487195974Sjamie M32R_INSN_ADDI, "addi", "addi", 16, 488191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 489191673Sjamie }, 490195974Sjamie/* addv $dr,$sr */ 491191673Sjamie { 492191673Sjamie M32R_INSN_ADDV, "addv", "addv", 16, 493192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 494191673Sjamie }, 495185435Sbz/* addv3 $dr,$sr,$simm16 */ 496191673Sjamie { 497191673Sjamie M32R_INSN_ADDV3, "addv3", "addv3", 32, 498191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 499191673Sjamie }, 500191673Sjamie/* addx $dr,$sr */ 501192895Sjamie { 502194762Sjamie M32R_INSN_ADDX, "addx", "addx", 16, 503192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 504191673Sjamie }, 505191673Sjamie/* bc.s $disp8 */ 506191673Sjamie { 507185435Sbz M32R_INSN_BC8, "bc8", "bc.s", 16, 508191673Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 509191673Sjamie }, 510191673Sjamie/* bc.l $disp24 */ 511191673Sjamie { 512185435Sbz M32R_INSN_BC24, "bc24", "bc.l", 32, 513191673Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 514191673Sjamie }, 515191673Sjamie/* beq $src1,$src2,$disp16 */ 516185435Sbz { 517191673Sjamie M32R_INSN_BEQ, "beq", "beq", 32, 518191673Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 519191673Sjamie }, 520185435Sbz/* beqz $src2,$disp16 */ 521185435Sbz { 522185435Sbz M32R_INSN_BEQZ, "beqz", "beqz", 32, 523185435Sbz { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 524185435Sbz }, 525185435Sbz/* bgez $src2,$disp16 */ 526191673Sjamie { 527191673Sjamie M32R_INSN_BGEZ, "bgez", "bgez", 32, 528191673Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 529191673Sjamie }, 530191673Sjamie/* bgtz $src2,$disp16 */ 531191673Sjamie { 532191673Sjamie M32R_INSN_BGTZ, "bgtz", "bgtz", 32, 533191673Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 534191673Sjamie }, 535191673Sjamie/* blez $src2,$disp16 */ 536191673Sjamie { 537191673Sjamie M32R_INSN_BLEZ, "blez", "blez", 32, 538191673Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 539191673Sjamie }, 540191673Sjamie/* bltz $src2,$disp16 */ 541194762Sjamie { 542194762Sjamie M32R_INSN_BLTZ, "bltz", "bltz", 32, 543194762Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 544194762Sjamie }, 545194762Sjamie/* bnez $src2,$disp16 */ 546194762Sjamie { 547194762Sjamie M32R_INSN_BNEZ, "bnez", "bnez", 32, 548194762Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 549194762Sjamie }, 550192895Sjamie/* bl.s $disp8 */ 551192895Sjamie { 552192895Sjamie M32R_INSN_BL8, "bl8", "bl.s", 16, 553192895Sjamie { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 554192895Sjamie }, 555192895Sjamie/* bl.l $disp24 */ 556192895Sjamie { 557192895Sjamie M32R_INSN_BL24, "bl24", "bl.l", 32, 558191673Sjamie { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 559192895Sjamie }, 560192895Sjamie/* bcl.s $disp8 */ 561192895Sjamie { 562192895Sjamie M32R_INSN_BCL8, "bcl8", "bcl.s", 16, 563192895Sjamie { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 564192895Sjamie }, 565192895Sjamie/* bcl.l $disp24 */ 566191673Sjamie { 567195870Sjamie M32R_INSN_BCL24, "bcl24", "bcl.l", 32, 568195870Sjamie { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 569195870Sjamie }, 570195870Sjamie/* bnc.s $disp8 */ 571195870Sjamie { 572195870Sjamie M32R_INSN_BNC8, "bnc8", "bnc.s", 16, 573195870Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 574195870Sjamie }, 575195870Sjamie/* bnc.l $disp24 */ 576195870Sjamie { 577195870Sjamie M32R_INSN_BNC24, "bnc24", "bnc.l", 32, 578195870Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 579195870Sjamie }, 580195870Sjamie/* bne $src1,$src2,$disp16 */ 581195870Sjamie { 582195870Sjamie M32R_INSN_BNE, "bne", "bne", 32, 583195870Sjamie { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 584195870Sjamie }, 585195870Sjamie/* bra.s $disp8 */ 586195870Sjamie { 587195870Sjamie M32R_INSN_BRA8, "bra8", "bra.s", 16, 588195870Sjamie { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 589195870Sjamie }, 590195870Sjamie/* bra.l $disp24 */ 591195870Sjamie { 592195870Sjamie M32R_INSN_BRA24, "bra24", "bra.l", 32, 593195870Sjamie { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 594195870Sjamie }, 595191673Sjamie/* bncl.s $disp8 */ 596191673Sjamie { 597191673Sjamie M32R_INSN_BNCL8, "bncl8", "bncl.s", 16, 598191673Sjamie { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 599191673Sjamie }, 600191673Sjamie/* bncl.l $disp24 */ 601194251Sjamie { 602194251Sjamie M32R_INSN_BNCL24, "bncl24", "bncl.l", 32, 603194251Sjamie { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 604194251Sjamie }, 605194251Sjamie/* cmp $src1,$src2 */ 606194251Sjamie { 607194251Sjamie M32R_INSN_CMP, "cmp", "cmp", 16, 608195974Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 609195974Sjamie }, 610195974Sjamie/* cmpi $src2,$simm16 */ 611195974Sjamie { 612195974Sjamie M32R_INSN_CMPI, "cmpi", "cmpi", 32, 613195974Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 614195974Sjamie }, 615195974Sjamie/* cmpu $src1,$src2 */ 616195974Sjamie { 617195974Sjamie M32R_INSN_CMPU, "cmpu", "cmpu", 16, 618195974Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 619195974Sjamie }, 620195974Sjamie/* cmpui $src2,$simm16 */ 621195974Sjamie { 622191673Sjamie M32R_INSN_CMPUI, "cmpui", "cmpui", 32, 623192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 624192895Sjamie }, 625192895Sjamie/* cmpeq $src1,$src2 */ 626192895Sjamie { 627192895Sjamie M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16, 628192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } } 629192895Sjamie }, 630192895Sjamie/* cmpz $src2 */ 631191673Sjamie { 632191673Sjamie M32R_INSN_CMPZ, "cmpz", "cmpz", 16, 633191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } } 634191673Sjamie }, 635191673Sjamie/* div $dr,$sr */ 636191673Sjamie { 637191673Sjamie M32R_INSN_DIV, "div", "div", 32, 638191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 639191673Sjamie }, 640191673Sjamie/* divu $dr,$sr */ 641191673Sjamie { 642191673Sjamie M32R_INSN_DIVU, "divu", "divu", 32, 643191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 644191673Sjamie }, 645191673Sjamie/* rem $dr,$sr */ 646191673Sjamie { 647191673Sjamie M32R_INSN_REM, "rem", "rem", 32, 648191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 649191673Sjamie }, 650191673Sjamie/* remu $dr,$sr */ 651191673Sjamie { 652191673Sjamie M32R_INSN_REMU, "remu", "remu", 32, 653193066Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 654193066Sjamie }, 655191673Sjamie/* remh $dr,$sr */ 656191673Sjamie { 657191673Sjamie M32R_INSN_REMH, "remh", "remh", 32, 658191673Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 659191673Sjamie }, 660191673Sjamie/* remuh $dr,$sr */ 661191673Sjamie { 662191673Sjamie M32R_INSN_REMUH, "remuh", "remuh", 32, 663191673Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 664191673Sjamie }, 665193066Sjamie/* remb $dr,$sr */ 666193066Sjamie { 667193066Sjamie M32R_INSN_REMB, "remb", "remb", 32, 668193066Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 669193066Sjamie }, 670193066Sjamie/* remub $dr,$sr */ 671193066Sjamie { 672193066Sjamie M32R_INSN_REMUB, "remub", "remub", 32, 673193066Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 674193066Sjamie }, 675193066Sjamie/* divuh $dr,$sr */ 676193066Sjamie { 677193066Sjamie M32R_INSN_DIVUH, "divuh", "divuh", 32, 678193066Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 679193066Sjamie }, 680193066Sjamie/* divb $dr,$sr */ 681193066Sjamie { 682193066Sjamie M32R_INSN_DIVB, "divb", "divb", 32, 683193066Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 684193066Sjamie }, 685193066Sjamie/* divub $dr,$sr */ 686193066Sjamie { 687193066Sjamie M32R_INSN_DIVUB, "divub", "divub", 32, 688193066Sjamie { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 689193066Sjamie }, 690193066Sjamie/* divh $dr,$sr */ 691193066Sjamie { 692193066Sjamie M32R_INSN_DIVH, "divh", "divh", 32, 693193066Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 694193066Sjamie }, 695193066Sjamie/* jc $sr */ 696193066Sjamie { 697193066Sjamie M32R_INSN_JC, "jc", "jc", 16, 698193066Sjamie { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 699193066Sjamie }, 700193066Sjamie/* jnc $sr */ 701193066Sjamie { 702193066Sjamie M32R_INSN_JNC, "jnc", "jnc", 16, 703193066Sjamie { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 704193066Sjamie }, 705193066Sjamie/* jl $sr */ 706193066Sjamie { 707193066Sjamie M32R_INSN_JL, "jl", "jl", 16, 708193066Sjamie { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 709193066Sjamie }, 710193066Sjamie/* jmp $sr */ 711193066Sjamie { 712193066Sjamie M32R_INSN_JMP, "jmp", "jmp", 16, 713193066Sjamie { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 714193066Sjamie }, 715193066Sjamie/* ld $dr,@$sr */ 716193066Sjamie { 717193066Sjamie M32R_INSN_LD, "ld", "ld", 16, 718193066Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 719193066Sjamie }, 720185435Sbz/* ld $dr,@($slo16,$sr) */ 721191673Sjamie { 722191673Sjamie M32R_INSN_LD_D, "ld-d", "ld", 32, 723195870Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 724191673Sjamie }, 725191673Sjamie/* ldb $dr,@$sr */ 726191673Sjamie { 727191673Sjamie M32R_INSN_LDB, "ldb", "ldb", 16, 728191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 729192895Sjamie }, 730195870Sjamie/* ldb $dr,@($slo16,$sr) */ 731195870Sjamie { 732195870Sjamie M32R_INSN_LDB_D, "ldb-d", "ldb", 32, 733195870Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 734195870Sjamie }, 735192895Sjamie/* ldh $dr,@$sr */ 736192895Sjamie { 737185435Sbz M32R_INSN_LDH, "ldh", "ldh", 16, 738192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 739192895Sjamie }, 740185435Sbz/* ldh $dr,@($slo16,$sr) */ 741195974Sjamie { 742192895Sjamie M32R_INSN_LDH_D, "ldh-d", "ldh", 32, 743192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 744192895Sjamie }, 745192895Sjamie/* ldub $dr,@$sr */ 746192895Sjamie { 747192895Sjamie M32R_INSN_LDUB, "ldub", "ldub", 16, 748192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 749192895Sjamie }, 750192895Sjamie/* ldub $dr,@($slo16,$sr) */ 751192895Sjamie { 752192895Sjamie M32R_INSN_LDUB_D, "ldub-d", "ldub", 32, 753192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 754192895Sjamie }, 755192895Sjamie/* lduh $dr,@$sr */ 756192895Sjamie { 757192895Sjamie M32R_INSN_LDUH, "lduh", "lduh", 16, 758192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 759192895Sjamie }, 760192895Sjamie/* lduh $dr,@($slo16,$sr) */ 761192895Sjamie { 762192895Sjamie M32R_INSN_LDUH_D, "lduh-d", "lduh", 32, 763192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 764192895Sjamie }, 765192895Sjamie/* ld $dr,@$sr+ */ 766192895Sjamie { 767192895Sjamie M32R_INSN_LD_PLUS, "ld-plus", "ld", 16, 768192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 769192895Sjamie }, 770192895Sjamie/* ld24 $dr,$uimm24 */ 771192895Sjamie { 772185435Sbz M32R_INSN_LD24, "ld24", "ld24", 32, 773191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 774191673Sjamie }, 775185435Sbz/* ldi8 $dr,$simm8 */ 776185435Sbz { 777191673Sjamie M32R_INSN_LDI8, "ldi8", "ldi8", 16, 778191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 779195870Sjamie }, 780191673Sjamie/* ldi16 $dr,$hash$slo16 */ 781191673Sjamie { 782191673Sjamie M32R_INSN_LDI16, "ldi16", "ldi16", 32, 783191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 784191673Sjamie }, 785192895Sjamie/* lock $dr,@$sr */ 786195870Sjamie { 787195870Sjamie M32R_INSN_LOCK, "lock", "lock", 16, 788195870Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 789195870Sjamie }, 790195870Sjamie/* machi $src1,$src2 */ 791192895Sjamie { 792192895Sjamie M32R_INSN_MACHI, "machi", "machi", 16, 793185435Sbz { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 794192895Sjamie }, 795192895Sjamie/* machi $src1,$src2,$acc */ 796185435Sbz { 797195974Sjamie M32R_INSN_MACHI_A, "machi-a", "machi", 16, 798192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 799192895Sjamie }, 800192895Sjamie/* maclo $src1,$src2 */ 801192895Sjamie { 802192895Sjamie M32R_INSN_MACLO, "maclo", "maclo", 16, 803192895Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 804192895Sjamie }, 805192895Sjamie/* maclo $src1,$src2,$acc */ 806192895Sjamie { 807192895Sjamie M32R_INSN_MACLO_A, "maclo-a", "maclo", 16, 808192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 809192895Sjamie }, 810192895Sjamie/* macwhi $src1,$src2 */ 811192895Sjamie { 812192895Sjamie M32R_INSN_MACWHI, "macwhi", "macwhi", 16, 813192895Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 814185435Sbz }, 815191673Sjamie/* macwhi $src1,$src2,$acc */ 816185435Sbz { 817185435Sbz M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16, 818195945Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 819195945Sjamie }, 820195945Sjamie/* macwlo $src1,$src2 */ 821195945Sjamie { 822195945Sjamie M32R_INSN_MACWLO, "macwlo", "macwlo", 16, 823195945Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 824195945Sjamie }, 825195945Sjamie/* macwlo $src1,$src2,$acc */ 826195945Sjamie { 827191673Sjamie M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16, 828191673Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 829191673Sjamie }, 830191673Sjamie/* mul $dr,$sr */ 831191673Sjamie { 832191673Sjamie M32R_INSN_MUL, "mul", "mul", 16, 833191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } } 834191673Sjamie }, 835191673Sjamie/* mulhi $src1,$src2 */ 836191673Sjamie { 837191673Sjamie M32R_INSN_MULHI, "mulhi", "mulhi", 16, 838191673Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 839191673Sjamie }, 840191673Sjamie/* mulhi $src1,$src2,$acc */ 841191673Sjamie { 842191673Sjamie M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16, 843191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 844191673Sjamie }, 845191673Sjamie/* mullo $src1,$src2 */ 846191673Sjamie { 847192895Sjamie M32R_INSN_MULLO, "mullo", "mullo", 16, 848192895Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 849192895Sjamie }, 850192895Sjamie/* mullo $src1,$src2,$acc */ 851192895Sjamie { 852192895Sjamie M32R_INSN_MULLO_A, "mullo-a", "mullo", 16, 853191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 854191673Sjamie }, 855191673Sjamie/* mulwhi $src1,$src2 */ 856191673Sjamie { 857191673Sjamie M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16, 858191673Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 859191673Sjamie }, 860191673Sjamie/* mulwhi $src1,$src2,$acc */ 861191673Sjamie { 862191673Sjamie M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16, 863191673Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 864191673Sjamie }, 865191673Sjamie/* mulwlo $src1,$src2 */ 866191673Sjamie { 867191673Sjamie M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16, 868191673Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 869191673Sjamie }, 870185435Sbz/* mulwlo $src1,$src2,$acc */ 871191673Sjamie { 872191673Sjamie M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16, 873191673Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 874191673Sjamie }, 875191673Sjamie/* mv $dr,$sr */ 876191673Sjamie { 877191673Sjamie M32R_INSN_MV, "mv", "mv", 16, 878191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 879191673Sjamie }, 880185435Sbz/* mvfachi $dr */ 881191673Sjamie { 882191673Sjamie M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16, 883191673Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 884191673Sjamie }, 885191673Sjamie/* mvfachi $dr,$accs */ 886191673Sjamie { 887191673Sjamie M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16, 888191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 889191673Sjamie }, 890185435Sbz/* mvfaclo $dr */ 891191673Sjamie { 892191673Sjamie M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16, 893185435Sbz { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 894191673Sjamie }, 895191673Sjamie/* mvfaclo $dr,$accs */ 896191673Sjamie { 897191673Sjamie M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16, 898191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 899191673Sjamie }, 900191673Sjamie/* mvfacmi $dr */ 901191673Sjamie { 902192895Sjamie M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16, 903192895Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 904192895Sjamie }, 905192895Sjamie/* mvfacmi $dr,$accs */ 906192895Sjamie { 907192895Sjamie M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16, 908192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 909191673Sjamie }, 910191673Sjamie/* mvfc $dr,$scr */ 911191673Sjamie { 912191673Sjamie M32R_INSN_MVFC, "mvfc", "mvfc", 16, 913191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 914191673Sjamie }, 915191673Sjamie/* mvtachi $src1 */ 916192895Sjamie { 917191673Sjamie M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16, 918191673Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 919191673Sjamie }, 920191673Sjamie/* mvtachi $src1,$accs */ 921191673Sjamie { 922191673Sjamie M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16, 923191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 924191673Sjamie }, 925192895Sjamie/* mvtaclo $src1 */ 926192895Sjamie { 927192895Sjamie M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16, 928192895Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 929191673Sjamie }, 930191673Sjamie/* mvtaclo $src1,$accs */ 931191673Sjamie { 932191673Sjamie M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16, 933191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 934191673Sjamie }, 935191673Sjamie/* mvtc $sr,$dcr */ 936191673Sjamie { 937191673Sjamie M32R_INSN_MVTC, "mvtc", "mvtc", 16, 938191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 939191673Sjamie }, 940191673Sjamie/* neg $dr,$sr */ 941191673Sjamie { 942191673Sjamie M32R_INSN_NEG, "neg", "neg", 16, 943191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 944191673Sjamie }, 945191673Sjamie/* nop */ 946192895Sjamie { 947191673Sjamie M32R_INSN_NOP, "nop", "nop", 16, 948191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 949191673Sjamie }, 950191673Sjamie/* not $dr,$sr */ 951191673Sjamie { 952191673Sjamie M32R_INSN_NOT, "not", "not", 16, 953191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 954191673Sjamie }, 955191673Sjamie/* rac */ 956191673Sjamie { 957191673Sjamie M32R_INSN_RAC, "rac", "rac", 16, 958191673Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 959191673Sjamie }, 960191673Sjamie/* rac $accd,$accs,$imm1 */ 961191673Sjamie { 962191673Sjamie M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16, 963191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 964191673Sjamie }, 965191673Sjamie/* rach */ 966191673Sjamie { 967192895Sjamie M32R_INSN_RACH, "rach", "rach", 16, 968192895Sjamie { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } } 969192895Sjamie }, 970192895Sjamie/* rach $accd,$accs,$imm1 */ 971192895Sjamie { 972192895Sjamie M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16, 973192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 974192895Sjamie }, 975192895Sjamie/* rte */ 976192895Sjamie { 977192895Sjamie M32R_INSN_RTE, "rte", "rte", 16, 978192895Sjamie { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 979192895Sjamie }, 980192895Sjamie/* seth $dr,$hash$hi16 */ 981192895Sjamie { 982192895Sjamie M32R_INSN_SETH, "seth", "seth", 32, 983192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 984192895Sjamie }, 985192895Sjamie/* sll $dr,$sr */ 986192895Sjamie { 987192895Sjamie M32R_INSN_SLL, "sll", "sll", 16, 988192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } 989192895Sjamie }, 990192895Sjamie/* sll3 $dr,$sr,$simm16 */ 991192895Sjamie { 992192895Sjamie M32R_INSN_SLL3, "sll3", "sll3", 32, 993192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 994192895Sjamie }, 995192895Sjamie/* slli $dr,$uimm5 */ 996191673Sjamie { 997192895Sjamie M32R_INSN_SLLI, "slli", "slli", 16, 998192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } 999192895Sjamie }, 1000191673Sjamie/* sra $dr,$sr */ 1001192895Sjamie { 1002191673Sjamie M32R_INSN_SRA, "sra", "sra", 16, 1003192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } 1004191673Sjamie }, 1005191673Sjamie/* sra3 $dr,$sr,$simm16 */ 1006191673Sjamie { 1007191673Sjamie M32R_INSN_SRA3, "sra3", "sra3", 32, 1008191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1009191673Sjamie }, 1010191673Sjamie/* srai $dr,$uimm5 */ 1011191673Sjamie { 1012191673Sjamie M32R_INSN_SRAI, "srai", "srai", 16, 1013191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } 1014191673Sjamie }, 1015191673Sjamie/* srl $dr,$sr */ 1016191673Sjamie { 1017191673Sjamie M32R_INSN_SRL, "srl", "srl", 16, 1018191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } 1019191673Sjamie }, 1020191673Sjamie/* srl3 $dr,$sr,$simm16 */ 1021191673Sjamie { 1022191673Sjamie M32R_INSN_SRL3, "srl3", "srl3", 32, 1023192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1024191673Sjamie }, 1025191673Sjamie/* srli $dr,$uimm5 */ 1026191673Sjamie { 1027191673Sjamie M32R_INSN_SRLI, "srli", "srli", 16, 1028191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } } 1029191673Sjamie }, 1030191673Sjamie/* st $src1,@$src2 */ 1031191673Sjamie { 1032191673Sjamie M32R_INSN_ST, "st", "st", 16, 1033191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1034191673Sjamie }, 1035191673Sjamie/* st $src1,@($slo16,$src2) */ 1036191673Sjamie { 1037191673Sjamie M32R_INSN_ST_D, "st-d", "st", 32, 1038191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1039191673Sjamie }, 1040191673Sjamie/* stb $src1,@$src2 */ 1041191673Sjamie { 1042191673Sjamie M32R_INSN_STB, "stb", "stb", 16, 1043191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1044191673Sjamie }, 1045191673Sjamie/* stb $src1,@($slo16,$src2) */ 1046191673Sjamie { 1047191673Sjamie M32R_INSN_STB_D, "stb-d", "stb", 32, 1048191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1049191673Sjamie }, 1050191673Sjamie/* sth $src1,@$src2 */ 1051191673Sjamie { 1052191673Sjamie M32R_INSN_STH, "sth", "sth", 16, 1053191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1054191673Sjamie }, 1055191673Sjamie/* sth $src1,@($slo16,$src2) */ 1056191673Sjamie { 1057191673Sjamie M32R_INSN_STH_D, "sth-d", "sth", 32, 1058191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1059191673Sjamie }, 1060191673Sjamie/* st $src1,@+$src2 */ 1061191673Sjamie { 1062191673Sjamie M32R_INSN_ST_PLUS, "st-plus", "st", 16, 1063191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1064191673Sjamie }, 1065191673Sjamie/* sth $src1,@$src2+ */ 1066185435Sbz { 1067191673Sjamie M32R_INSN_STH_PLUS, "sth-plus", "sth", 16, 1068191673Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 1069194762Sjamie }, 1070194762Sjamie/* stb $src1,@$src2+ */ 1071194762Sjamie { 1072194762Sjamie M32R_INSN_STB_PLUS, "stb-plus", "stb", 16, 1073194762Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 1074194762Sjamie }, 1075191673Sjamie/* st $src1,@-$src2 */ 1076192895Sjamie { 1077192895Sjamie M32R_INSN_ST_MINUS, "st-minus", "st", 16, 1078192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1079192895Sjamie }, 1080192895Sjamie/* sub $dr,$sr */ 1081192895Sjamie { 1082192895Sjamie M32R_INSN_SUB, "sub", "sub", 16, 1083192895Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1084192895Sjamie }, 1085192895Sjamie/* subv $dr,$sr */ 1086191673Sjamie { 1087191673Sjamie M32R_INSN_SUBV, "subv", "subv", 16, 1088191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1089191673Sjamie }, 1090191673Sjamie/* subx $dr,$sr */ 1091191673Sjamie { 1092191673Sjamie M32R_INSN_SUBX, "subx", "subx", 16, 1093191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1094191673Sjamie }, 1095191673Sjamie/* trap $uimm4 */ 1096191673Sjamie { 1097191673Sjamie M32R_INSN_TRAP, "trap", "trap", 16, 1098191673Sjamie { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1099191673Sjamie }, 1100191673Sjamie/* unlock $src1,@$src2 */ 1101191673Sjamie { 1102191673Sjamie M32R_INSN_UNLOCK, "unlock", "unlock", 16, 1103191673Sjamie { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1104191673Sjamie }, 1105192895Sjamie/* satb $dr,$sr */ 1106192895Sjamie { 1107192895Sjamie M32R_INSN_SATB, "satb", "satb", 32, 1108191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 1109191673Sjamie }, 1110191673Sjamie/* sath $dr,$sr */ 1111191673Sjamie { 1112191673Sjamie M32R_INSN_SATH, "sath", "sath", 32, 1113191673Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 1114191673Sjamie }, 1115191673Sjamie/* sat $dr,$sr */ 1116191673Sjamie { 1117191673Sjamie M32R_INSN_SAT, "sat", "sat", 32, 1118191673Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } } 1119191673Sjamie }, 1120191673Sjamie/* pcmpbz $src2 */ 1121191673Sjamie { 1122191673Sjamie M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16, 1123191673Sjamie { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } } 1124191673Sjamie }, 1125191673Sjamie/* sadd */ 1126192895Sjamie { 1127192895Sjamie M32R_INSN_SADD, "sadd", "sadd", 16, 1128194762Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1129185435Sbz }, 1130192895Sjamie/* macwu1 $src1,$src2 */ 1131191673Sjamie { 1132192895Sjamie M32R_INSN_MACWU1, "macwu1", "macwu1", 16, 1133192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1134191673Sjamie }, 1135191673Sjamie/* msblo $src1,$src2 */ 1136191673Sjamie { 1137191673Sjamie M32R_INSN_MSBLO, "msblo", "msblo", 16, 1138192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1139191673Sjamie }, 1140191673Sjamie/* mulwu1 $src1,$src2 */ 1141195944Sjamie { 1142195944Sjamie M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16, 1143195945Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1144195945Sjamie }, 1145195945Sjamie/* maclh1 $src1,$src2 */ 1146195945Sjamie { 1147195945Sjamie M32R_INSN_MACLH1, "maclh1", "maclh1", 16, 1148192895Sjamie { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } } 1149195974Sjamie }, 1150195974Sjamie/* sc */ 1151195974Sjamie { 1152195974Sjamie M32R_INSN_SC, "sc", "sc", 16, 1153195974Sjamie { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 1154195974Sjamie }, 1155195974Sjamie/* snc */ 1156195974Sjamie { 1157195974Sjamie M32R_INSN_SNC, "snc", "snc", 16, 1158195974Sjamie { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } } 1159195974Sjamie }, 1160195974Sjamie/* clrpsw $uimm8 */ 1161195974Sjamie { 1162195974Sjamie M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16, 1163192895Sjamie { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1164192895Sjamie }, 1165195974Sjamie/* setpsw $uimm8 */ 1166195974Sjamie { 1167195974Sjamie M32R_INSN_SETPSW, "setpsw", "setpsw", 16, 1168195974Sjamie { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1169195974Sjamie }, 1170195974Sjamie/* bset $uimm3,@($slo16,$sr) */ 1171195974Sjamie { 1172195974Sjamie M32R_INSN_BSET, "bset", "bset", 32, 1173195974Sjamie { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1174195974Sjamie }, 1175195974Sjamie/* bclr $uimm3,@($slo16,$sr) */ 1176195974Sjamie { 1177195974Sjamie M32R_INSN_BCLR, "bclr", "bclr", 32, 1178195974Sjamie { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } 1179192895Sjamie }, 1180195945Sjamie/* btst $uimm3,$sr */ 1181195945Sjamie { 1182192895Sjamie M32R_INSN_BTST, "btst", "btst", 16, 1183192895Sjamie { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } } 1184192895Sjamie }, 1185191673Sjamie}; 1186192895Sjamie 1187192895Sjamie#undef OP 1188191673Sjamie#undef A 1189194251Sjamie 1190194251Sjamie/* Initialize anything needed to be done once, before any cpu_open call. */ 1191194251Sjamie 1192194251Sjamiestatic void 1193194251Sjamieinit_tables (void) 1194185435Sbz{ 1195191673Sjamie} 1196191673Sjamie 1197185435Sbzstatic const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 1198192895Sjamiestatic void build_hw_table (CGEN_CPU_TABLE *); 1199191673Sjamiestatic void build_ifield_table (CGEN_CPU_TABLE *); 1200191673Sjamiestatic void build_operand_table (CGEN_CPU_TABLE *); 1201191673Sjamiestatic void build_insn_table (CGEN_CPU_TABLE *); 1202191673Sjamiestatic void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *); 1203185435Sbz 1204191673Sjamie/* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */ 1205185435Sbz 1206191673Sjamiestatic const CGEN_MACH * 1207191673Sjamielookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 1208191673Sjamie{ 1209185435Sbz while (table->name) 1210191673Sjamie { 1211191673Sjamie if (strcmp (name, table->bfd_name) == 0) 1212195974Sjamie return table; 1213195974Sjamie ++table; 1214195974Sjamie } 1215195974Sjamie abort (); 1216195974Sjamie} 1217195945Sjamie 1218195945Sjamie/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ 1219195945Sjamie 1220195945Sjamiestatic void 1221195945Sjamiebuild_hw_table (CGEN_CPU_TABLE *cd) 1222195945Sjamie{ 1223195945Sjamie int i; 1224195945Sjamie int machs = cd->machs; 1225195945Sjamie const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0]; 1226195974Sjamie /* MAX_HW is only an upper bound on the number of selected entries. 1227195974Sjamie However each entry is indexed by it's enum so there can be holes in 1228195974Sjamie the table. */ 1229195974Sjamie const CGEN_HW_ENTRY **selected = 1230195974Sjamie (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1231195974Sjamie 1232195974Sjamie cd->hw_table.init_entries = init; 1233195974Sjamie cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 1234195974Sjamie memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1235195974Sjamie /* ??? For now we just use machs to determine which ones we want. */ 1236195974Sjamie for (i = 0; init[i].name != NULL; ++i) 1237195974Sjamie if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 1238195974Sjamie & machs) 1239195974Sjamie selected[init[i].type] = &init[i]; 1240195974Sjamie cd->hw_table.entries = selected; 1241195974Sjamie cd->hw_table.num_entries = MAX_HW; 1242191673Sjamie} 1243185435Sbz 1244191673Sjamie/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ 1245192895Sjamie 1246192895Sjamiestatic void 1247192895Sjamiebuild_ifield_table (CGEN_CPU_TABLE *cd) 1248192895Sjamie{ 1249192895Sjamie cd->ifld_table = & m32r_cgen_ifld_table[0]; 1250192895Sjamie} 1251194762Sjamie 1252194762Sjamie/* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ 1253194762Sjamie 1254194762Sjamiestatic void 1255194762Sjamiebuild_operand_table (CGEN_CPU_TABLE *cd) 1256194762Sjamie{ 1257192895Sjamie int i; 1258192895Sjamie int machs = cd->machs; 1259192895Sjamie const CGEN_OPERAND *init = & m32r_cgen_operand_table[0]; 1260192895Sjamie /* MAX_OPERANDS is only an upper bound on the number of selected entries. 1261192895Sjamie However each entry is indexed by it's enum so there can be holes in 1262192895Sjamie the table. */ 1263185435Sbz const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 1264195974Sjamie 1265192895Sjamie cd->operand_table.init_entries = init; 1266195974Sjamie cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 1267195974Sjamie memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 1268195974Sjamie /* ??? For now we just use mach to determine which ones we want. */ 1269195974Sjamie for (i = 0; init[i].name != NULL; ++i) 1270195974Sjamie if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 1271195974Sjamie & machs) 1272195974Sjamie selected[init[i].type] = &init[i]; 1273195974Sjamie cd->operand_table.entries = selected; 1274195974Sjamie cd->operand_table.num_entries = MAX_OPERANDS; 1275195974Sjamie} 1276195974Sjamie 1277195974Sjamie/* Subroutine of m32r_cgen_cpu_open to build the hardware table. 1278195974Sjamie ??? This could leave out insns not supported by the specified mach/isa, 1279195974Sjamie but that would cause errors like "foo only supported by bar" to become 1280195974Sjamie "unknown insn", so for now we include all insns and require the app to 1281195974Sjamie do the checking later. 1282195974Sjamie ??? On the other hand, parsing of such insns may require their hardware or 1283195974Sjamie operand elements to be in the table [which they mightn't be]. */ 1284195974Sjamie 1285195974Sjamiestatic void 1286195974Sjamiebuild_insn_table (CGEN_CPU_TABLE *cd) 1287195974Sjamie{ 1288195974Sjamie int i; 1289195974Sjamie const CGEN_IBASE *ib = & m32r_cgen_insn_table[0]; 1290192895Sjamie CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 1291192895Sjamie 1292192895Sjamie memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 1293192895Sjamie for (i = 0; i < MAX_INSNS; ++i) 1294192895Sjamie insns[i].base = &ib[i]; 1295192895Sjamie cd->insn_table.init_entries = insns; 1296192895Sjamie cd->insn_table.entry_size = sizeof (CGEN_IBASE); 1297195974Sjamie cd->insn_table.num_init_entries = MAX_INSNS; 1298195974Sjamie} 1299195974Sjamie 1300195974Sjamie/* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */ 1301195974Sjamie 1302195974Sjamiestatic void 1303195974Sjamiem32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 1304195945Sjamie{ 1305195974Sjamie int i; 1306195974Sjamie CGEN_BITSET *isas = cd->isas; 1307195974Sjamie unsigned int machs = cd->machs; 1308195945Sjamie 1309195974Sjamie cd->int_insn_p = CGEN_INT_INSN_P; 1310195974Sjamie 1311195945Sjamie /* Data derived from the isa spec. */ 1312195974Sjamie#define UNSET (CGEN_SIZE_UNKNOWN + 1) 1313195945Sjamie cd->default_insn_bitsize = UNSET; 1314195974Sjamie cd->base_insn_bitsize = UNSET; 1315192895Sjamie cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 1316195974Sjamie cd->max_insn_bitsize = 0; 1317195974Sjamie for (i = 0; i < MAX_ISAS; ++i) 1318195974Sjamie if (cgen_bitset_contains (isas, i)) 1319195974Sjamie { 1320195974Sjamie const CGEN_ISA *isa = & m32r_cgen_isa_table[i]; 1321195974Sjamie 1322195974Sjamie /* Default insn sizes of all selected isas must be 1323195974Sjamie equal or we set the result to 0, meaning "unknown". */ 1324195974Sjamie if (cd->default_insn_bitsize == UNSET) 1325195974Sjamie cd->default_insn_bitsize = isa->default_insn_bitsize; 1326195974Sjamie else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 1327195974Sjamie ; /* This is ok. */ 1328195974Sjamie else 1329195974Sjamie cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 1330192895Sjamie 1331192895Sjamie /* Base insn sizes of all selected isas must be equal 1332192895Sjamie or we set the result to 0, meaning "unknown". */ 1333192895Sjamie if (cd->base_insn_bitsize == UNSET) 1334185435Sbz cd->base_insn_bitsize = isa->base_insn_bitsize; 1335191673Sjamie else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 1336195974Sjamie ; /* This is ok. */ 1337192895Sjamie else 1338195974Sjamie cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 1339195974Sjamie 1340195974Sjamie /* Set min,max insn sizes. */ 1341195974Sjamie if (isa->min_insn_bitsize < cd->min_insn_bitsize) 1342195974Sjamie cd->min_insn_bitsize = isa->min_insn_bitsize; 1343195974Sjamie if (isa->max_insn_bitsize > cd->max_insn_bitsize) 1344195974Sjamie cd->max_insn_bitsize = isa->max_insn_bitsize; 1345195974Sjamie } 1346195974Sjamie 1347195974Sjamie /* Data derived from the mach spec. */ 1348195974Sjamie for (i = 0; i < MAX_MACHS; ++i) 1349195974Sjamie if (((1 << i) & machs) != 0) 1350195974Sjamie { 1351195974Sjamie const CGEN_MACH *mach = & m32r_cgen_mach_table[i]; 1352195974Sjamie 1353195974Sjamie if (mach->insn_chunk_bitsize != 0) 1354195974Sjamie { 1355195974Sjamie if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 1356195974Sjamie { 1357195974Sjamie fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", 1358195974Sjamie cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 1359195974Sjamie abort (); 1360195974Sjamie } 1361192895Sjamie 1362192895Sjamie cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 1363192895Sjamie } 1364192895Sjamie } 1365192895Sjamie 1366192895Sjamie /* Determine which hw elements are used by MACH. */ 1367192895Sjamie build_hw_table (cd); 1368195974Sjamie 1369195974Sjamie /* Build the ifield table. */ 1370195945Sjamie build_ifield_table (cd); 1371195974Sjamie 1372195974Sjamie /* Determine which operands are used by MACH/ISA. */ 1373195974Sjamie build_operand_table (cd); 1374195945Sjamie 1375195974Sjamie /* Build the instruction table. */ 1376195974Sjamie build_insn_table (cd); 1377195945Sjamie} 1378195974Sjamie 1379195945Sjamie/* Initialize a cpu table and return a descriptor. 1380195974Sjamie It's much like opening a file, and must be the first function called. 1381192895Sjamie The arguments are a set of (type/value) pairs, terminated with 1382195974Sjamie CGEN_CPU_OPEN_END. 1383195974Sjamie 1384195974Sjamie Currently supported values: 1385195974Sjamie CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 1386195974Sjamie CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 1387195974Sjamie CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 1388195974Sjamie CGEN_CPU_OPEN_ENDIAN: specify endian choice 1389195974Sjamie CGEN_CPU_OPEN_END: terminates arguments 1390195974Sjamie 1391195974Sjamie ??? Simultaneous multiple isas might not make sense, but it's not (yet) 1392195974Sjamie precluded. */ 1393195974Sjamie 1394195974SjamieCGEN_CPU_DESC 1395195974Sjamiem32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 1396192895Sjamie{ 1397192895Sjamie CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 1398191673Sjamie static int init_p; 1399192895Sjamie CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 1400191673Sjamie unsigned int machs = 0; /* 0 = "unspecified" */ 1401192895Sjamie enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 1402192895Sjamie va_list ap; 1403191673Sjamie 1404191673Sjamie if (! init_p) 1405191673Sjamie { 1406191673Sjamie init_tables (); 1407191673Sjamie init_p = 1; 1408191673Sjamie } 1409192895Sjamie 1410191673Sjamie memset (cd, 0, sizeof (*cd)); 1411191673Sjamie 1412192895Sjamie va_start (ap, arg_type); 1413192895Sjamie while (arg_type != CGEN_CPU_OPEN_END) 1414191673Sjamie { 1415192895Sjamie switch (arg_type) 1416192895Sjamie { 1417192895Sjamie case CGEN_CPU_OPEN_ISAS : 1418192895Sjamie isas = va_arg (ap, CGEN_BITSET *); 1419192895Sjamie break; 1420192895Sjamie case CGEN_CPU_OPEN_MACHS : 1421192895Sjamie machs = va_arg (ap, unsigned int); 1422192895Sjamie break; 1423192895Sjamie case CGEN_CPU_OPEN_BFDMACH : 1424192895Sjamie { 1425192895Sjamie const char *name = va_arg (ap, const char *); 1426192895Sjamie const CGEN_MACH *mach = 1427192895Sjamie lookup_mach_via_bfd_name (m32r_cgen_mach_table, name); 1428191673Sjamie 1429192895Sjamie machs |= 1 << mach->num; 1430192895Sjamie break; 1431192895Sjamie } 1432192895Sjamie case CGEN_CPU_OPEN_ENDIAN : 1433185435Sbz endian = va_arg (ap, enum cgen_endian); 1434191673Sjamie break; 1435191673Sjamie default : 1436192895Sjamie fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n", 1437195974Sjamie arg_type); 1438195974Sjamie abort (); /* ??? return NULL? */ 1439195974Sjamie } 1440195974Sjamie arg_type = va_arg (ap, enum cgen_cpu_open_arg); 1441195974Sjamie } 1442195974Sjamie va_end (ap); 1443192895Sjamie 1444195945Sjamie /* Mach unspecified means "all". */ 1445195945Sjamie if (machs == 0) 1446195945Sjamie machs = (1 << MAX_MACHS) - 1; 1447195945Sjamie /* Base mach is always selected. */ 1448195945Sjamie machs |= 1; 1449195945Sjamie if (endian == CGEN_ENDIAN_UNKNOWN) 1450192895Sjamie { 1451192895Sjamie /* ??? If target has only one, could have a default. */ 1452192895Sjamie fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n"); 1453192895Sjamie abort (); 1454192895Sjamie } 1455185435Sbz 1456191673Sjamie cd->isas = cgen_bitset_copy (isas); 1457191673Sjamie cd->machs = machs; 1458192895Sjamie cd->endian = endian; 1459195974Sjamie /* FIXME: for the sparc case we can determine insn-endianness statically. 1460195974Sjamie The worry here is where both data and insn endian can be independently 1461195974Sjamie chosen, in which case this function will need another argument. 1462195974Sjamie Actually, will want to allow for more arguments in the future anyway. */ 1463195974Sjamie cd->insn_endian = endian; 1464195974Sjamie 1465192895Sjamie /* Table (re)builder. */ 1466195945Sjamie cd->rebuild_tables = m32r_cgen_rebuild_tables; 1467195945Sjamie m32r_cgen_rebuild_tables (cd); 1468195945Sjamie 1469195945Sjamie /* Default to not allowing signed overflow. */ 1470195945Sjamie cd->signed_overflow_ok_p = 0; 1471195945Sjamie 1472192895Sjamie return (CGEN_CPU_DESC) cd; 1473192895Sjamie} 1474192895Sjamie 1475192895Sjamie/* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 1476192895Sjamie MACH_NAME is the bfd name of the mach. */ 1477191673Sjamie 1478191673SjamieCGEN_CPU_DESC 1479192895Sjamiem32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 1480191673Sjamie{ 1481192895Sjamie return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 1482192895Sjamie CGEN_CPU_OPEN_ENDIAN, endian, 1483192895Sjamie CGEN_CPU_OPEN_END); 1484192895Sjamie} 1485192895Sjamie 1486194762Sjamie/* Close a cpu table. 1487194762Sjamie ??? This can live in a machine independent file, but there's currently 1488194762Sjamie no place to put this file (there's no libcgen). libopcodes is the wrong 1489194762Sjamie place as some simulator ports use this but they don't use libopcodes. */ 1490194762Sjamie 1491194762Sjamievoid 1492194762Sjamiem32r_cgen_cpu_close (CGEN_CPU_DESC cd) 1493194762Sjamie{ 1494192895Sjamie unsigned int i; 1495192895Sjamie const CGEN_INSN *insns; 1496192895Sjamie 1497192895Sjamie if (cd->macro_insn_table.init_entries) 1498192895Sjamie { 1499192895Sjamie insns = cd->macro_insn_table.init_entries; 1500192895Sjamie for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 1501192895Sjamie if (CGEN_INSN_RX ((insns))) 1502192895Sjamie regfree (CGEN_INSN_RX (insns)); 1503192895Sjamie } 1504192895Sjamie 1505192895Sjamie if (cd->insn_table.init_entries) 1506192895Sjamie { 1507192895Sjamie insns = cd->insn_table.init_entries; 1508192895Sjamie for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 1509192895Sjamie if (CGEN_INSN_RX (insns)) 1510192895Sjamie regfree (CGEN_INSN_RX (insns)); 1511192895Sjamie } 1512192895Sjamie 1513192895Sjamie if (cd->macro_insn_table.init_entries) 1514191673Sjamie free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 1515192895Sjamie 1516192895Sjamie if (cd->insn_table.init_entries) 1517192895Sjamie free ((CGEN_INSN *) cd->insn_table.init_entries); 1518192895Sjamie 1519192895Sjamie if (cd->hw_table.entries) 1520192895Sjamie free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 1521191673Sjamie 1522191673Sjamie if (cd->operand_table.entries) 1523193066Sjamie free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 1524193066Sjamie 1525193066Sjamie free (cd); 1526193066Sjamie} 1527193066Sjamie 1528193066Sjamie