1/* Disassemble i80960 instructions. 2 Copyright (C) 1990-2017 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; see the file COPYING. If not, write to the 18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21#include "sysdep.h" 22#include "dis-asm.h" 23 24static const char *const reg_names[] = { 25/* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7", 26/* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 27/* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 28/* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", 29/* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3" 30}; 31 32 33static FILE *stream; /* Output goes here */ 34static struct disassemble_info *info; 35static void print_addr (bfd_vma); 36static void ctrl (bfd_vma, unsigned long, unsigned long); 37static void cobr (bfd_vma, unsigned long, unsigned long); 38static void reg (unsigned long); 39static int mem (bfd_vma, unsigned long, unsigned long, int); 40static void ea (bfd_vma, int, const char *, const char *, int, unsigned int); 41static void dstop (int, int, int); 42static void regop (int, int, int, int); 43static void invalid (int); 44static int pinsn (bfd_vma, unsigned long, unsigned long); 45static void put_abs (unsigned long, unsigned long); 46 47 48/* Print the i960 instruction at address 'memaddr' in debugged memory, 49 on INFO->STREAM. Returns length of the instruction, in bytes. */ 50 51int 52print_insn_i960 (bfd_vma memaddr, struct disassemble_info *info_arg) 53{ 54 unsigned int word1, word2 = 0xdeadbeef; 55 bfd_byte buffer[8]; 56 int status; 57 58 info = info_arg; 59 stream = info->stream; 60 61 /* Read word1. Only read word2 if the instruction 62 needs it, to prevent reading past the end of a section. */ 63 64 status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info); 65 if (status != 0) 66 { 67 (*info->memory_error_func) (status, memaddr, info); 68 return -1; 69 } 70 71 word1 = bfd_getl32 (buffer); 72 73 /* Divide instruction set into classes based on high 4 bits of opcode. */ 74 switch ( (word1 >> 28) & 0xf ) 75 { 76 default: 77 break; 78 case 0x8: 79 case 0x9: 80 case 0xa: 81 case 0xb: 82 case 0xc: 83 /* Read word2. */ 84 status = (*info->read_memory_func) 85 (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info); 86 if (status != 0) 87 { 88 (*info->memory_error_func) (status, memaddr, info); 89 return -1; 90 } 91 word2 = bfd_getl32 (buffer + 4); 92 break; 93 } 94 95 return pinsn( memaddr, word1, word2 ); 96} 97 98#define IN_GDB 99 100/***************************************************************************** 101 * All code below this point should be identical with that of 102 * the disassembler in gdmp960. 103 104 A noble sentiment, but at least in cosmetic ways (info->fprintf_func), it 105 just ain't so. -kingdon, 31 Mar 93 106 *****************************************************************************/ 107 108struct tabent { 109 char *name; 110 short numops; 111}; 112 113struct sparse_tabent { 114 int opcode; 115 char *name; 116 short numops; 117}; 118 119static int 120pinsn (bfd_vma memaddr, unsigned long word1, unsigned long word2) 121{ 122 int instr_len; 123 124 instr_len = 4; 125 put_abs (word1, word2); 126 127 /* Divide instruction set into classes based on high 4 bits of opcode. */ 128 switch ((word1 >> 28) & 0xf) 129 { 130 case 0x0: 131 case 0x1: 132 ctrl (memaddr, word1, word2); 133 break; 134 case 0x2: 135 case 0x3: 136 cobr (memaddr, word1, word2); 137 break; 138 case 0x5: 139 case 0x6: 140 case 0x7: 141 reg (word1); 142 break; 143 case 0x8: 144 case 0x9: 145 case 0xa: 146 case 0xb: 147 case 0xc: 148 instr_len = mem (memaddr, word1, word2, 0); 149 break; 150 default: 151 /* Invalid instruction, print as data word. */ 152 invalid (word1); 153 break; 154 } 155 return instr_len; 156} 157 158/* CTRL format.. */ 159 160static void 161ctrl (bfd_vma memaddr, unsigned long word1, unsigned long word2 ATTRIBUTE_UNUSED) 162{ 163 int i; 164 static const struct tabent ctrl_tab[] = { 165 { NULL, 0, }, /* 0x00 */ 166 { NULL, 0, }, /* 0x01 */ 167 { NULL, 0, }, /* 0x02 */ 168 { NULL, 0, }, /* 0x03 */ 169 { NULL, 0, }, /* 0x04 */ 170 { NULL, 0, }, /* 0x05 */ 171 { NULL, 0, }, /* 0x06 */ 172 { NULL, 0, }, /* 0x07 */ 173 { "b", 1, }, /* 0x08 */ 174 { "call", 1, }, /* 0x09 */ 175 { "ret", 0, }, /* 0x0a */ 176 { "bal", 1, }, /* 0x0b */ 177 { NULL, 0, }, /* 0x0c */ 178 { NULL, 0, }, /* 0x0d */ 179 { NULL, 0, }, /* 0x0e */ 180 { NULL, 0, }, /* 0x0f */ 181 { "bno", 1, }, /* 0x10 */ 182 { "bg", 1, }, /* 0x11 */ 183 { "be", 1, }, /* 0x12 */ 184 { "bge", 1, }, /* 0x13 */ 185 { "bl", 1, }, /* 0x14 */ 186 { "bne", 1, }, /* 0x15 */ 187 { "ble", 1, }, /* 0x16 */ 188 { "bo", 1, }, /* 0x17 */ 189 { "faultno", 0, }, /* 0x18 */ 190 { "faultg", 0, }, /* 0x19 */ 191 { "faulte", 0, }, /* 0x1a */ 192 { "faultge", 0, }, /* 0x1b */ 193 { "faultl", 0, }, /* 0x1c */ 194 { "faultne", 0, }, /* 0x1d */ 195 { "faultle", 0, }, /* 0x1e */ 196 { "faulto", 0, }, /* 0x1f */ 197 }; 198 199 i = (word1 >> 24) & 0xff; 200 if ((ctrl_tab[i].name == NULL) || ((word1 & 1) != 0)) 201 { 202 invalid (word1); 203 return; 204 } 205 206 (*info->fprintf_func) (stream, "%s", ctrl_tab[i].name); 207 if (word1 & 2) 208 /* Predicts branch not taken. */ 209 (*info->fprintf_func) (stream, ".f"); 210 211 if (ctrl_tab[i].numops == 1) 212 { 213 /* Extract displacement and convert to address. */ 214 word1 &= 0x00ffffff; 215 216 if (word1 & 0x00800000) 217 { 218 /* Sign bit is set. */ 219 word1 |= (-1 & ~0xffffff); /* Sign extend. */ 220 } 221 222 (*info->fprintf_func) (stream, "\t"); 223 print_addr (word1 + memaddr); 224 } 225} 226 227/* COBR format. */ 228 229static void 230cobr (bfd_vma memaddr, unsigned long word1, unsigned long word2 ATTRIBUTE_UNUSED) 231{ 232 int src1; 233 int src2; 234 int i; 235 236 static const struct tabent cobr_tab[] = { 237 { "testno", 1, }, /* 0x20 */ 238 { "testg", 1, }, /* 0x21 */ 239 { "teste", 1, }, /* 0x22 */ 240 { "testge", 1, }, /* 0x23 */ 241 { "testl", 1, }, /* 0x24 */ 242 { "testne", 1, }, /* 0x25 */ 243 { "testle", 1, }, /* 0x26 */ 244 { "testo", 1, }, /* 0x27 */ 245 { NULL, 0, }, /* 0x28 */ 246 { NULL, 0, }, /* 0x29 */ 247 { NULL, 0, }, /* 0x2a */ 248 { NULL, 0, }, /* 0x2b */ 249 { NULL, 0, }, /* 0x2c */ 250 { NULL, 0, }, /* 0x2d */ 251 { NULL, 0, }, /* 0x2e */ 252 { NULL, 0, }, /* 0x2f */ 253 { "bbc", 3, }, /* 0x30 */ 254 { "cmpobg", 3, }, /* 0x31 */ 255 { "cmpobe", 3, }, /* 0x32 */ 256 { "cmpobge",3, }, /* 0x33 */ 257 { "cmpobl", 3, }, /* 0x34 */ 258 { "cmpobne",3, }, /* 0x35 */ 259 { "cmpoble",3, }, /* 0x36 */ 260 { "bbs", 3, }, /* 0x37 */ 261 { "cmpibno",3, }, /* 0x38 */ 262 { "cmpibg", 3, }, /* 0x39 */ 263 { "cmpibe", 3, }, /* 0x3a */ 264 { "cmpibge",3, }, /* 0x3b */ 265 { "cmpibl", 3, }, /* 0x3c */ 266 { "cmpibne",3, }, /* 0x3d */ 267 { "cmpible",3, }, /* 0x3e */ 268 { "cmpibo", 3, }, /* 0x3f */ 269 }; 270 271 i = ((word1 >> 24) & 0xff) - 0x20; 272 if (cobr_tab[i].name == NULL) 273 { 274 invalid (word1); 275 return; 276 } 277 278 (*info->fprintf_func) (stream, "%s", cobr_tab[i].name); 279 280 /* Predicts branch not taken. */ 281 if (word1 & 2) 282 (*info->fprintf_func) (stream, ".f"); 283 284 (*info->fprintf_func) (stream, "\t"); 285 286 src1 = (word1 >> 19) & 0x1f; 287 src2 = (word1 >> 14) & 0x1f; 288 289 if (word1 & 0x02000) 290 /* M1 is 1 */ 291 (*info->fprintf_func) (stream, "%d", src1); 292 else 293 (*info->fprintf_func) (stream, "%s", reg_names[src1]); 294 295 if (cobr_tab[i].numops > 1) 296 { 297 if (word1 & 1) 298 /* S2 is 1. */ 299 (*info->fprintf_func) (stream, ",sf%d,", src2); 300 else 301 /* S1 is 0. */ 302 (*info->fprintf_func) (stream, ",%s,", reg_names[src2]); 303 304 /* Extract displacement and convert to address. */ 305 word1 &= 0x00001ffc; 306 if (word1 & 0x00001000) 307 /* Negative displacement. */ 308 word1 |= (-1 & ~0x1fff); /* Sign extend. */ 309 310 print_addr (memaddr + word1); 311 } 312} 313 314/* MEM format. */ 315/* Returns instruction length: 4 or 8. */ 316 317static int 318mem (bfd_vma memaddr, unsigned long word1, unsigned long word2, int noprint) 319{ 320 int i, j; 321 int len; 322 int mode; 323 int offset; 324 const char *reg1, *reg2, *reg3; 325 326 /* This lookup table is too sparse to make it worth typing in, but not 327 so large as to make a sparse array necessary. We create the table 328 at runtime. */ 329 330 /* NOTE: In this table, the meaning of 'numops' is: 331 1: single operand 332 2: 2 operands, load instruction 333 -2: 2 operands, store instruction. */ 334 static struct tabent *mem_tab; 335 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ 336#define MEM_MIN 0x80 337#define MEM_MAX 0xcf 338#define MEM_SIZ ( * sizeof(struct tabent)) 339 340 static const struct sparse_tabent mem_init[] = { 341 { 0x80, "ldob", 2 }, 342 { 0x82, "stob", -2 }, 343 { 0x84, "bx", 1 }, 344 { 0x85, "balx", 2 }, 345 { 0x86, "callx", 1 }, 346 { 0x88, "ldos", 2 }, 347 { 0x8a, "stos", -2 }, 348 { 0x8c, "lda", 2 }, 349 { 0x90, "ld", 2 }, 350 { 0x92, "st", -2 }, 351 { 0x98, "ldl", 2 }, 352 { 0x9a, "stl", -2 }, 353 { 0xa0, "ldt", 2 }, 354 { 0xa2, "stt", -2 }, 355 { 0xac, "dcinva", 1 }, 356 { 0xb0, "ldq", 2 }, 357 { 0xb2, "stq", -2 }, 358 { 0xc0, "ldib", 2 }, 359 { 0xc2, "stib", -2 }, 360 { 0xc8, "ldis", 2 }, 361 { 0xca, "stis", -2 }, 362 { 0, NULL, 0 } 363 }; 364 static struct tabent mem_tab_buf[MEM_MAX - MEM_MIN + 1]; 365 366 if (mem_tab == NULL) 367 { 368 mem_tab = mem_tab_buf; 369 370 for (i = 0; mem_init[i].opcode != 0; i++) 371 { 372 j = mem_init[i].opcode - MEM_MIN; 373 mem_tab[j].name = mem_init[i].name; 374 mem_tab[j].numops = mem_init[i].numops; 375 } 376 } 377 378 i = ((word1 >> 24) & 0xff) - MEM_MIN; 379 mode = (word1 >> 10) & 0xf; 380 381 if ((mem_tab[i].name != NULL) /* Valid instruction */ 382 && ((mode == 5) || (mode >= 12))) 383 /* With 32-bit displacement. */ 384 len = 8; 385 else 386 len = 4; 387 388 if (noprint) 389 return len; 390 391 if ((mem_tab[i].name == NULL) || (mode == 6)) 392 { 393 invalid (word1); 394 return len; 395 } 396 397 (*info->fprintf_func) (stream, "%s\t", mem_tab[i].name); 398 399 reg1 = reg_names[ (word1 >> 19) & 0x1f ]; /* MEMB only */ 400 reg2 = reg_names[ (word1 >> 14) & 0x1f ]; 401 reg3 = reg_names[ word1 & 0x1f ]; /* MEMB only */ 402 offset = word1 & 0xfff; /* MEMA only */ 403 404 switch (mem_tab[i].numops) 405 { 406 case 2: /* LOAD INSTRUCTION */ 407 if (mode & 4) 408 { /* MEMB FORMAT */ 409 ea (memaddr, mode, reg2, reg3, word1, word2); 410 (*info->fprintf_func) (stream, ",%s", reg1); 411 } 412 else 413 { /* MEMA FORMAT */ 414 (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); 415 416 if (mode & 8) 417 (*info->fprintf_func) (stream, "(%s)", reg2); 418 419 (*info->fprintf_func)(stream, ",%s", reg1); 420 } 421 break; 422 423 case -2: /* STORE INSTRUCTION */ 424 if (mode & 4) 425 { 426 /* MEMB FORMAT */ 427 (*info->fprintf_func) (stream, "%s,", reg1); 428 ea (memaddr, mode, reg2, reg3, word1, word2); 429 } 430 else 431 { 432 /* MEMA FORMAT */ 433 (*info->fprintf_func) (stream, "%s,0x%x", reg1, (unsigned) offset); 434 435 if (mode & 8) 436 (*info->fprintf_func) (stream, "(%s)", reg2); 437 } 438 break; 439 440 case 1: /* BX/CALLX INSTRUCTION */ 441 if (mode & 4) 442 { 443 /* MEMB FORMAT */ 444 ea (memaddr, mode, reg2, reg3, word1, word2); 445 } 446 else 447 { 448 /* MEMA FORMAT */ 449 (*info->fprintf_func) (stream, "0x%x", (unsigned) offset); 450 if (mode & 8) 451 (*info->fprintf_func) (stream, "(%s)", reg2); 452 } 453 break; 454 } 455 456 return len; 457} 458 459/* REG format. */ 460 461static void 462reg (unsigned long word1) 463{ 464 int i, j; 465 int opcode; 466 int fp; 467 int m1, m2, m3; 468 int s1, s2; 469 int src, src2, dst; 470 char *mnemp; 471 472 /* This lookup table is too sparse to make it worth typing in, but not 473 so large as to make a sparse array necessary. We create the table 474 at runtime. */ 475 476 /* NOTE: In this table, the meaning of 'numops' is: 477 1: single operand, which is NOT a destination. 478 -1: single operand, which IS a destination. 479 2: 2 operands, the 2nd of which is NOT a destination. 480 -2: 2 operands, the 2nd of which IS a destination. 481 3: 3 operands 482 483 If an opcode mnemonic begins with "F", it is a floating-point 484 opcode (the "F" is not printed). */ 485 486 static struct tabent *reg_tab; 487 static const struct sparse_tabent reg_init[] = 488 { 489#define REG_MIN 0x580 490 { 0x580, "notbit", 3 }, 491 { 0x581, "and", 3 }, 492 { 0x582, "andnot", 3 }, 493 { 0x583, "setbit", 3 }, 494 { 0x584, "notand", 3 }, 495 { 0x586, "xor", 3 }, 496 { 0x587, "or", 3 }, 497 { 0x588, "nor", 3 }, 498 { 0x589, "xnor", 3 }, 499 { 0x58a, "not", -2 }, 500 { 0x58b, "ornot", 3 }, 501 { 0x58c, "clrbit", 3 }, 502 { 0x58d, "notor", 3 }, 503 { 0x58e, "nand", 3 }, 504 { 0x58f, "alterbit", 3 }, 505 { 0x590, "addo", 3 }, 506 { 0x591, "addi", 3 }, 507 { 0x592, "subo", 3 }, 508 { 0x593, "subi", 3 }, 509 { 0x594, "cmpob", 2 }, 510 { 0x595, "cmpib", 2 }, 511 { 0x596, "cmpos", 2 }, 512 { 0x597, "cmpis", 2 }, 513 { 0x598, "shro", 3 }, 514 { 0x59a, "shrdi", 3 }, 515 { 0x59b, "shri", 3 }, 516 { 0x59c, "shlo", 3 }, 517 { 0x59d, "rotate", 3 }, 518 { 0x59e, "shli", 3 }, 519 { 0x5a0, "cmpo", 2 }, 520 { 0x5a1, "cmpi", 2 }, 521 { 0x5a2, "concmpo", 2 }, 522 { 0x5a3, "concmpi", 2 }, 523 { 0x5a4, "cmpinco", 3 }, 524 { 0x5a5, "cmpinci", 3 }, 525 { 0x5a6, "cmpdeco", 3 }, 526 { 0x5a7, "cmpdeci", 3 }, 527 { 0x5ac, "scanbyte", 2 }, 528 { 0x5ad, "bswap", -2 }, 529 { 0x5ae, "chkbit", 2 }, 530 { 0x5b0, "addc", 3 }, 531 { 0x5b2, "subc", 3 }, 532 { 0x5b4, "intdis", 0 }, 533 { 0x5b5, "inten", 0 }, 534 { 0x5cc, "mov", -2 }, 535 { 0x5d8, "eshro", 3 }, 536 { 0x5dc, "movl", -2 }, 537 { 0x5ec, "movt", -2 }, 538 { 0x5fc, "movq", -2 }, 539 { 0x600, "synmov", 2 }, 540 { 0x601, "synmovl", 2 }, 541 { 0x602, "synmovq", 2 }, 542 { 0x603, "cmpstr", 3 }, 543 { 0x604, "movqstr", 3 }, 544 { 0x605, "movstr", 3 }, 545 { 0x610, "atmod", 3 }, 546 { 0x612, "atadd", 3 }, 547 { 0x613, "inspacc", -2 }, 548 { 0x614, "ldphy", -2 }, 549 { 0x615, "synld", -2 }, 550 { 0x617, "fill", 3 }, 551 { 0x630, "sdma", 3 }, 552 { 0x631, "udma", 0 }, 553 { 0x640, "spanbit", -2 }, 554 { 0x641, "scanbit", -2 }, 555 { 0x642, "daddc", 3 }, 556 { 0x643, "dsubc", 3 }, 557 { 0x644, "dmovt", -2 }, 558 { 0x645, "modac", 3 }, 559 { 0x646, "condrec", -2 }, 560 { 0x650, "modify", 3 }, 561 { 0x651, "extract", 3 }, 562 { 0x654, "modtc", 3 }, 563 { 0x655, "modpc", 3 }, 564 { 0x656, "receive", -2 }, 565 { 0x658, "intctl", -2 }, 566 { 0x659, "sysctl", 3 }, 567 { 0x65b, "icctl", 3 }, 568 { 0x65c, "dcctl", 3 }, 569 { 0x65d, "halt", 0 }, 570 { 0x660, "calls", 1 }, 571 { 0x662, "send", 3 }, 572 { 0x663, "sendserv", 1 }, 573 { 0x664, "resumprcs", 1 }, 574 { 0x665, "schedprcs", 1 }, 575 { 0x666, "saveprcs", 0 }, 576 { 0x668, "condwait", 1 }, 577 { 0x669, "wait", 1 }, 578 { 0x66a, "signal", 1 }, 579 { 0x66b, "mark", 0 }, 580 { 0x66c, "fmark", 0 }, 581 { 0x66d, "flushreg", 0 }, 582 { 0x66f, "syncf", 0 }, 583 { 0x670, "emul", 3 }, 584 { 0x671, "ediv", 3 }, 585 { 0x673, "ldtime", -1 }, 586 { 0x674, "Fcvtir", -2 }, 587 { 0x675, "Fcvtilr", -2 }, 588 { 0x676, "Fscalerl", 3 }, 589 { 0x677, "Fscaler", 3 }, 590 { 0x680, "Fatanr", 3 }, 591 { 0x681, "Flogepr", 3 }, 592 { 0x682, "Flogr", 3 }, 593 { 0x683, "Fremr", 3 }, 594 { 0x684, "Fcmpor", 2 }, 595 { 0x685, "Fcmpr", 2 }, 596 { 0x688, "Fsqrtr", -2 }, 597 { 0x689, "Fexpr", -2 }, 598 { 0x68a, "Flogbnr", -2 }, 599 { 0x68b, "Froundr", -2 }, 600 { 0x68c, "Fsinr", -2 }, 601 { 0x68d, "Fcosr", -2 }, 602 { 0x68e, "Ftanr", -2 }, 603 { 0x68f, "Fclassr", 1 }, 604 { 0x690, "Fatanrl", 3 }, 605 { 0x691, "Flogeprl", 3 }, 606 { 0x692, "Flogrl", 3 }, 607 { 0x693, "Fremrl", 3 }, 608 { 0x694, "Fcmporl", 2 }, 609 { 0x695, "Fcmprl", 2 }, 610 { 0x698, "Fsqrtrl", -2 }, 611 { 0x699, "Fexprl", -2 }, 612 { 0x69a, "Flogbnrl", -2 }, 613 { 0x69b, "Froundrl", -2 }, 614 { 0x69c, "Fsinrl", -2 }, 615 { 0x69d, "Fcosrl", -2 }, 616 { 0x69e, "Ftanrl", -2 }, 617 { 0x69f, "Fclassrl", 1 }, 618 { 0x6c0, "Fcvtri", -2 }, 619 { 0x6c1, "Fcvtril", -2 }, 620 { 0x6c2, "Fcvtzri", -2 }, 621 { 0x6c3, "Fcvtzril", -2 }, 622 { 0x6c9, "Fmovr", -2 }, 623 { 0x6d9, "Fmovrl", -2 }, 624 { 0x6e1, "Fmovre", -2 }, 625 { 0x6e2, "Fcpysre", 3 }, 626 { 0x6e3, "Fcpyrsre", 3 }, 627 { 0x701, "mulo", 3 }, 628 { 0x708, "remo", 3 }, 629 { 0x70b, "divo", 3 }, 630 { 0x741, "muli", 3 }, 631 { 0x748, "remi", 3 }, 632 { 0x749, "modi", 3 }, 633 { 0x74b, "divi", 3 }, 634 { 0x780, "addono", 3 }, 635 { 0x781, "addino", 3 }, 636 { 0x782, "subono", 3 }, 637 { 0x783, "subino", 3 }, 638 { 0x784, "selno", 3 }, 639 { 0x78b, "Fdivr", 3 }, 640 { 0x78c, "Fmulr", 3 }, 641 { 0x78d, "Fsubr", 3 }, 642 { 0x78f, "Faddr", 3 }, 643 { 0x790, "addog", 3 }, 644 { 0x791, "addig", 3 }, 645 { 0x792, "subog", 3 }, 646 { 0x793, "subig", 3 }, 647 { 0x794, "selg", 3 }, 648 { 0x79b, "Fdivrl", 3 }, 649 { 0x79c, "Fmulrl", 3 }, 650 { 0x79d, "Fsubrl", 3 }, 651 { 0x79f, "Faddrl", 3 }, 652 { 0x7a0, "addoe", 3 }, 653 { 0x7a1, "addie", 3 }, 654 { 0x7a2, "suboe", 3 }, 655 { 0x7a3, "subie", 3 }, 656 { 0x7a4, "sele", 3 }, 657 { 0x7b0, "addoge", 3 }, 658 { 0x7b1, "addige", 3 }, 659 { 0x7b2, "suboge", 3 }, 660 { 0x7b3, "subige", 3 }, 661 { 0x7b4, "selge", 3 }, 662 { 0x7c0, "addol", 3 }, 663 { 0x7c1, "addil", 3 }, 664 { 0x7c2, "subol", 3 }, 665 { 0x7c3, "subil", 3 }, 666 { 0x7c4, "sell", 3 }, 667 { 0x7d0, "addone", 3 }, 668 { 0x7d1, "addine", 3 }, 669 { 0x7d2, "subone", 3 }, 670 { 0x7d3, "subine", 3 }, 671 { 0x7d4, "selne", 3 }, 672 { 0x7e0, "addole", 3 }, 673 { 0x7e1, "addile", 3 }, 674 { 0x7e2, "subole", 3 }, 675 { 0x7e3, "subile", 3 }, 676 { 0x7e4, "selle", 3 }, 677 { 0x7f0, "addoo", 3 }, 678 { 0x7f1, "addio", 3 }, 679 { 0x7f2, "suboo", 3 }, 680 { 0x7f3, "subio", 3 }, 681 { 0x7f4, "selo", 3 }, 682#define REG_MAX 0x7f4 683 { 0, NULL, 0 } 684 }; 685 static struct tabent reg_tab_buf[REG_MAX - REG_MIN + 1]; 686 687 if (reg_tab == NULL) 688 { 689 reg_tab = reg_tab_buf; 690 691 for (i = 0; reg_init[i].opcode != 0; i++) 692 { 693 j = reg_init[i].opcode - REG_MIN; 694 reg_tab[j].name = reg_init[i].name; 695 reg_tab[j].numops = reg_init[i].numops; 696 } 697 } 698 699 opcode = ((word1 >> 20) & 0xff0) | ((word1 >> 7) & 0xf); 700 i = opcode - REG_MIN; 701 702 if ((opcode<REG_MIN) || (opcode>REG_MAX) || (reg_tab[i].name==NULL)) 703 { 704 invalid (word1); 705 return; 706 } 707 708 mnemp = reg_tab[i].name; 709 if (*mnemp == 'F') 710 { 711 fp = 1; 712 mnemp++; 713 } 714 else 715 { 716 fp = 0; 717 } 718 719 (*info->fprintf_func) (stream, "%s", mnemp); 720 721 s1 = (word1 >> 5) & 1; 722 s2 = (word1 >> 6) & 1; 723 m1 = (word1 >> 11) & 1; 724 m2 = (word1 >> 12) & 1; 725 m3 = (word1 >> 13) & 1; 726 src = word1 & 0x1f; 727 src2 = (word1 >> 14) & 0x1f; 728 dst = (word1 >> 19) & 0x1f; 729 730 if (reg_tab[i].numops != 0) 731 { 732 (*info->fprintf_func) (stream, "\t"); 733 734 switch (reg_tab[i].numops) 735 { 736 case 1: 737 regop (m1, s1, src, fp); 738 break; 739 case -1: 740 dstop (m3, dst, fp); 741 break; 742 case 2: 743 regop (m1, s1, src, fp); 744 (*info->fprintf_func) (stream, ","); 745 regop (m2, s2, src2, fp); 746 break; 747 case -2: 748 regop (m1, s1, src, fp); 749 (*info->fprintf_func) (stream, ","); 750 dstop (m3, dst, fp); 751 break; 752 case 3: 753 regop (m1, s1, src, fp); 754 (*info->fprintf_func) (stream, ","); 755 regop (m2, s2, src2, fp); 756 (*info->fprintf_func) (stream, ","); 757 dstop (m3, dst, fp); 758 break; 759 } 760 } 761} 762 763/* Print out effective address for memb instructions. */ 764 765static void 766ea (bfd_vma memaddr, int mode, const char *reg2, const char *reg3, int word1, 767 unsigned int word2) 768{ 769 int scale; 770 static const int scale_tab[] = { 1, 2, 4, 8, 16 }; 771 772 scale = (word1 >> 7) & 0x07; 773 774 if ((scale > 4) || (((word1 >> 5) & 0x03) != 0)) 775 { 776 invalid (word1); 777 return; 778 } 779 scale = scale_tab[scale]; 780 781 switch (mode) 782 { 783 case 4: /* (reg) */ 784 (*info->fprintf_func)( stream, "(%s)", reg2 ); 785 break; 786 case 5: /* displ+8(ip) */ 787 print_addr (word2 + 8 + memaddr); 788 break; 789 case 7: /* (reg)[index*scale] */ 790 if (scale == 1) 791 (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3); 792 else 793 (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale); 794 break; 795 case 12: /* displacement */ 796 print_addr ((bfd_vma) word2); 797 break; 798 case 13: /* displ(reg) */ 799 print_addr ((bfd_vma) word2); 800 (*info->fprintf_func) (stream, "(%s)", reg2); 801 break; 802 case 14: /* displ[index*scale] */ 803 print_addr ((bfd_vma) word2); 804 if (scale == 1) 805 (*info->fprintf_func) (stream, "[%s]", reg3); 806 else 807 (*info->fprintf_func) (stream, "[%s*%d]", reg3, scale); 808 break; 809 case 15: /* displ(reg)[index*scale] */ 810 print_addr ((bfd_vma) word2); 811 if (scale == 1) 812 (*info->fprintf_func) (stream, "(%s)[%s]", reg2, reg3); 813 else 814 (*info->fprintf_func) (stream, "(%s)[%s*%d]", reg2, reg3, scale); 815 break; 816 default: 817 invalid (word1); 818 return; 819 } 820} 821 822 823/* Register Instruction Operand. */ 824 825static void 826regop (int mode, int spec, int fp_reg, int fp) 827{ 828 if (fp) 829 { 830 /* Floating point instruction. */ 831 if (mode == 1) 832 { 833 /* FP operand. */ 834 switch (fp_reg) 835 { 836 case 0: (*info->fprintf_func) (stream, "fp0"); 837 break; 838 case 1: (*info->fprintf_func) (stream, "fp1"); 839 break; 840 case 2: (*info->fprintf_func) (stream, "fp2"); 841 break; 842 case 3: (*info->fprintf_func) (stream, "fp3"); 843 break; 844 case 16: (*info->fprintf_func) (stream, "0f0.0"); 845 break; 846 case 22: (*info->fprintf_func) (stream, "0f1.0"); 847 break; 848 default: (*info->fprintf_func) (stream, "?"); 849 break; 850 } 851 } 852 else 853 { 854 /* Non-FP register. */ 855 (*info->fprintf_func) (stream, "%s", reg_names[fp_reg]); 856 } 857 } 858 else 859 { 860 /* Not floating point. */ 861 if (mode == 1) 862 { 863 /* Literal. */ 864 (*info->fprintf_func) (stream, "%d", fp_reg); 865 } 866 else 867 { 868 /* Register. */ 869 if (spec == 0) 870 (*info->fprintf_func) (stream, "%s", reg_names[fp_reg]); 871 else 872 (*info->fprintf_func) (stream, "sf%d", fp_reg); 873 } 874 } 875} 876 877/* Register Instruction Destination Operand. */ 878 879static void 880dstop (int mode, int dest_reg, int fp) 881{ 882 /* 'dst' operand can't be a literal. On non-FP instructions, register 883 mode is assumed and "m3" acts as if were "s3"; on FP-instructions, 884 sf registers are not allowed so m3 acts normally. */ 885 if (fp) 886 regop (mode, 0, dest_reg, fp); 887 else 888 regop (0, mode, dest_reg, fp); 889} 890 891static void 892invalid (int word1) 893{ 894 (*info->fprintf_func) (stream, ".word\t0x%08x", (unsigned) word1); 895} 896 897static void 898print_addr (bfd_vma a) 899{ 900 (*info->print_address_func) (a, info); 901} 902 903static void 904put_abs (unsigned long word1 ATTRIBUTE_UNUSED, 905 unsigned long word2 ATTRIBUTE_UNUSED) 906{ 907#ifdef IN_GDB 908 return; 909#else 910 int len; 911 912 switch ((word1 >> 28) & 0xf) 913 { 914 case 0x8: 915 case 0x9: 916 case 0xa: 917 case 0xb: 918 case 0xc: 919 /* MEM format instruction. */ 920 len = mem (0, word1, word2, 1); 921 break; 922 default: 923 len = 4; 924 break; 925 } 926 927 if (len == 8) 928 (*info->fprintf_func) (stream, "%08x %08x\t", word1, word2); 929 else 930 (*info->fprintf_func) (stream, "%08x \t", word1); 931#endif 932} 933