12017-07-25  Tristan Gingold  <gingold@adacore.com>
2
3	* configure: Regenerate.
4
52017-07-05  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
6
7	Backport from mainline
8	2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
9	* arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr.
10
112017-05-01  Michael Clark  <michaeljclark@mac.com>
12
13	* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
14	register.
15
162017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
17
18	* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
19	RISCV_GP_SYMBOL.
20
212017-03-14  Kito Cheng  <kito.cheng@gmail.com>
22
23	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
24	<c.andi>: Likewise.
25	<c.addiw> Likewise.
26
272017-03-14  Kito Cheng  <kito.cheng@gmail.com>
28
29	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
30
312017-03-13  Andrew Waterman  <andrew@sifive.com>
32
33	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
34	<srl> Likewise.
35	<srai> Likewise.
36	<sra> Likewise.
37
382017-03-27  Alan Modra  <amodra@gmail.com>
39
40	PR 21303
41	* ppc-dis.c (struct ppc_mopt): Comment.
42	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
43
442017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
45
46	Backport from mainline
47	2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
48
49	* s390-mkopc.c (main): Remove vx2 check.
50	* s390-opc.txt: Remove vx2 instruction flags.
51
522017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
53
54	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
55	<vsx>: Do not use PPC_OPCODE_VSX3;
56
572017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
58
59	Apply from master.
60	2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
61	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
62
632017-03-07  Alan Modra  <amodra@gmail.com>
64
65	Apply from master
66	2017-03-06  Alan Modra  <amodra@gmail.com>
67	PR 21124
68	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
69	(extract_raq, extract_ras, extract_rbx): New functions.
70	(powerpc_operands): Use opposite corresponding insert function.
71	(Q_MASK): Define.
72	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
73	register restriction.
74
752017-03-02  Tristan Gingold  <gingold@adacore.com>
76
77	* configure: Regenerate.
78
792017-03-02  Tristan Gingold  <gingold@adacore.com>
80
81	* configure: Regenerate.
82
832017-02-14  Andrew Waterman  <andrew@sifive.com>
84
85	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
86	pseudoinstructions.
87
882017-02-27  Richard Sandiford  <richard.sandiford@arm.com>
89
90	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
91	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
92	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
93	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
94	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
95	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
96	(OP_SVE_V_HSD): New macros.
97	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
98	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
99	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
100	(aarch64_opcode_table): Add new SVE instructions.
101	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
102	for rotation operands.  Add new SVE operands.
103	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
104	(ins_sve_quad_index): Likewise.
105	(ins_imm_rotate): Split into...
106	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
107	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
108	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
109	functions.
110	(aarch64_ins_sve_addr_ri_s4): New function.
111	(aarch64_ins_sve_quad_index): Likewise.
112	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
113	* aarch64-asm-2.c: Regenerate.
114	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
115	(ext_sve_quad_index): Likewise.
116	(ext_imm_rotate): Split into...
117	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
118	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
119	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
120	functions.
121	(aarch64_ext_sve_addr_ri_s4): New function.
122	(aarch64_ext_sve_quad_index): Likewise.
123	(aarch64_ext_sve_index): Allow quad indices.
124	(do_misc_decoding): Likewise.
125	* aarch64-dis-2.c: Regenerate.
126	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
127	aarch64_field_kinds.
128	(OPD_F_OD_MASK): Widen by one bit.
129	(OPD_F_NO_ZR): Bump accordingly.
130	(get_operand_field_width): New function.
131	* aarch64-opc.c (fields): Add new SVE fields.
132	(operand_general_constraint_met_p): Handle new SVE operands.
133	(aarch64_print_operand): Likewise.
134	* aarch64-opc-2.c: Regenerate.
135
1362017-02-27  Richard Sandiford  <richard.sandiford@arm.com>
137
138	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
139	(aarch64_feature_compnum): ...this.
140	(SIMD_V8_3): Replace with...
141	(COMPNUM): ...this.
142	(CNUM_INSN): New macro.
143	(aarch64_opcode_table): Use it for the complex number instructions.
144
1452017-02-27  Richard Sandiford  <richard.sandiford@arm.com>
146
147	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
148	(aarch64_sys_reg_supported_p): Handle them.
149
1502017-02-27  Szabolcs Nagy  <szabolcs.nagy@arm.com>
151
152	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
153	(aarch64_opcode_table): Use RCPC_INSN.
154
1552017-02-11  Stafford Horne  <shorne@gmail.com>
156	    Alan Modra  <amodra@gmail.com>
157
158	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
159	Use insn_bytes_value and insn_int_value directly instead.  Don't
160	free allocated memory until function exit.
161
1622017-02-10  Nicholas Piggin  <npiggin@gmail.com>
163
164	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
165
1662017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
167
168	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
169	* i386-dis-evex.h (evex_table): Updated.
170	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
171	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
172	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
173	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
174	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
175	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
176	* i386-init.h: Regenerate.
177	* i386-tbl.h: Ditto.
178
1792017-01-02  Alan Modra  <amodra@gmail.com>
180
181	Update year range in copyright notice of all files.
182
183For older changes see ChangeLog-2016
184
185Copyright (C) 2017 Free Software Foundation, Inc.
186
187Copying and distribution of this file, with or without modification,
188are permitted in any medium without royalty provided the copyright
189notice and this notice are preserved.
190
191Local Variables:
192mode: change-log
193left-margin: 8
194fill-column: 74
195version-control: never
196End:
197