12016-12-28 Alan Modra <amodra@gmail.com> 2 3 * configure.ac: Revert 2016-12-23. 4 * Makefile.am: Likewise. 5 (MIPS_DEFS): Define. 6 (mips-dis.lo): Add rule. 7 * Makefile.in: Regenerate. 8 * aclocal.m4: Regenerate. 9 * config.in: Regenerate. 10 * configure: Regenerate. 11 122016-12-23 Maciej W. Rozycki <macro@imgtec.com> 13 14 * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', 15 `4' and `s' operand codes. 16 (mips16_opcodes): Add "asmacro" entry. 17 182016-12-23 Maciej W. Rozycki <macro@imgtec.com> 19 20 * mips-dis.c (print_mips16_insn_arg): Simplify processing of 21 extended operands. 22 * mips16-opc.c (decode_mips16_operand): Switch the extended 23 form of the `<' operand type to LSB position 22. 24 252016-12-23 Maciej W. Rozycki <macro@imgtec.com> 26 27 * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' 28 operand codes with `.' and `F' respectively. 29 (mips16_opcodes): Likewise. 30 312016-12-23 Maciej W. Rozycki <macro@imgtec.com> 32 33 * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix 34 matching for INSN2_SHORT_ONLY opcode table entries. 35 * mips16-opc.c (SH): New macro. 36 (mips16_opcodes): Set SH in `pinfo2' for non-extensible 37 instruction entries: "nop", "addu", "and", "break", "cmp", 38 "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", 39 "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", 40 "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", 41 "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", 42 "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", 43 "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", 44 "seh", "sew", "zeb", "zeh", "zew" and "extend". 45 462016-12-23 Maciej W. Rozycki <macro@imgtec.com> 47 48 * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended 49 encoding support. 50 512016-12-23 Maciej W. Rozycki <macro@imgtec.com> 52 53 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for 54 "extend". 55 562016-12-23 Maciej W. Rozycki <macro@imgtec.com> 57 58 * mips-dis.c (set_default_mips_dis_options): Use 59 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the 60 call to `bfd_mips_elf_get_abiflags'. 61 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD. 62 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'. 63 * aclocal.m4: Regenerate. 64 * configure: Regenerate. 65 * config.in: Regenerate. 66 * Makefile.in: Regenerate. 67 682016-12-23 Tristan Gingold <gingold@adacore.com> 69 70 * configure: Regenerate. 71 722016-12-23 Tristan Gingold <gingold@adacore.com> 73 74 * po/opcodes.pot: Regenerate. 75 762016-12-21 Andrew Waterman <andrew@sifive.com> 77 78 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries. 79 802016-12-20 Maciej W. Rozycki <macro@imgtec.com> 81 82 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than 83 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. 84 (print_insn_mips16): Check opcode entries for validity against 85 the ISA level and ASE set selected. 86 872016-12-20 Maciej W. Rozycki <macro@imgtec.com> 88 89 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and 90 `insn' together, with `extend' as the high-order 16 bits. 91 (match_kind): New enum. 92 (print_insn_mips16): Rework for 32-bit instruction matching. 93 Do not dump EXTEND prefixes here. 94 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. 95 Recode `match' and `mask' fields as 32-bit in absolute "jal" and 96 "jalx" entries. 97 982016-12-20 Maciej W. Rozycki <macro@imgtec.com> 99 100 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather 101 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" 102 INSN_MACRO entries. 103 1042016-12-20 Maciej W. Rozycki <macro@imgtec.com> 105 106 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather 107 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor 108 opcode). 109 1102016-12-20 Andrew Waterman <andrew@sifive.com> 111 112 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to 113 "*.aqrl". 114 1152016-12-20 Andrew Waterman <andrew@sifive.com> 116 117 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as 118 INSN_ALIAS. 119 1202016-12-20 Andrew Waterman <andrew@sifive.com> 121 122 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" 123 format. 124 1252016-12-20 Andrew Waterman <andrew@sifive.com> 126 127 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's 128 XLEN when none is provided. 129 1302016-12-20 Andrew Waterman <andrew@sifive.com> 131 132 * riscv-opc.c: Formatting fixes. 133 1342016-12-20 Alan Modra <amodra@gmail.com> 135 136 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files. 137 * Makefile.in: Regenerate. 138 * po/POTFILES.in: Regenerate. 139 1402016-12-19 Maciej W. Rozycki <macro@imgtec.com> 141 142 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]: 143 Only examine ELF file structures here. 144 1452016-12-19 Maciej W. Rozycki <macro@imgtec.com> 146 147 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call 148 `bfd_mips_elf_get_abiflags' here. 149 1502016-12-16 Nick Clifton <nickc@redhat.com> 151 152 * arm-dis.c (print_insn_thumb32): Fix compile time warning 153 computing value_in_comment. 154 1552016-12-14 Maciej W. Rozycki <macro@imgtec.com> 156 157 * mips-dis.c (mips_convert_abiflags_ases): New function. 158 (set_default_mips_dis_options): Also infer ASE flags from ELF 159 file structures. 160 1612016-12-14 Maciej W. Rozycki <macro@imgtec.com> 162 163 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file 164 header flag interpretation code. 165 1662016-12-14 Maciej W. Rozycki <macro@imgtec.com> 167 168 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in 169 `pinfo2' with SP-relative "sd" entries. 170 1712016-12-14 Maciej W. Rozycki <macro@imgtec.com> 172 173 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e 174 compact jumps. 175 1762016-12-13 Renlin Li <renlin.li@arm.com> 177 178 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range 179 qualifier. 180 (operand_general_constraint_met_p): Remove case for CP_REG. 181 (aarch64_print_operand): Print CRn, CRm operand using imm field. 182 * aarch64-tbl.h (QL_SYS): Use CR qualifier. 183 (QL_SYSL): Likewise. 184 (aarch64_opcode_table): Change CRn, CRm operand class and type. 185 * aarch64-opc-2.c : Regenerate. 186 * aarch64-asm-2.c : Likewise. 187 * aarch64-dis-2.c : Likewise. 188 1892016-12-12 Yao Qi <yao.qi@linaro.org> 190 191 * rx-dis.c: Include <setjmp.h> 192 (struct private): New. 193 (rx_get_byte): Check return value of read_memory_func, and 194 call memory_error_func and OPCODES_SIGLONGJMP on error. 195 (print_insn_rx): Call OPCODES_SIGSETJMP. 196 1972016-12-12 Yao Qi <yao.qi@linaro.org> 198 199 * rl78-dis.c: Include <setjmp.h>. 200 (struct private): New. 201 (rl78_get_byte): Check return value of read_memory_func, and 202 call memory_error_func and OPCODES_SIGLONGJMP on error. 203 (print_insn_rl78_common): Call OPCODES_SIGJMP. 204 2052016-12-09 Maciej W. Rozycki <macro@imgtec.com> 206 207 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases. 208 2092016-12-09 Maciej W. Rozycki <macro@imgtec.com> 210 211 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather 212 than UINT. 213 2142016-12-09 Maciej W. Rozycki <macro@imgtec.com> 215 216 * mips-dis.c (print_insn_mips16): Use a tab rather than a space 217 to separate `extend' and its uninterpreted argument output. 218 Separate hexadecimal halves of undecoded extended instructions 219 output. 220 2212016-12-08 Maciej W. Rozycki <macro@imgtec.com> 222 223 * mips-dis.c (print_mips16_insn_arg): Remove extraneous 224 indentation space across. 225 2262016-12-08 Maciej W. Rozycki <macro@imgtec.com> 227 228 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot 229 adjustment for PC-relative operations following MIPS16e compact 230 jumps or undefined RR/J(AL)R(C) encodings. 231 2322016-12-08 Maciej W. Rozycki <macro@imgtec.com> 233 234 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local 235 variable to `reglane_index'. 236 2372016-12-08 Luis Machado <lgustavo@codesourcery.com> 238 239 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section. 240 2412016-12-07 Maciej W. Rozycki <macro@imgtec.com> 242 243 * mips-dis.c (print_mips16_insn_arg): Fix comment typo. 244 2452016-12-07 Maciej W. Rozycki <macro@imgtec.com> 246 247 * mips16-opc.c (mips16_opcodes): Update comment naming structure 248 members. 249 2502016-12-07 Maciej W. Rozycki <macro@imgtec.com> 251 252 * mips-dis.c (print_mips_disassembler_options): Reformat output. 253 2542016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com> 255 256 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. 257 (print_insn_coprocessor): Add 'V' format for neon D or Q regs. 258 2592016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com> 260 261 * arm-dis.c (coprocessor_opcodes): Add vjcvt. 262 2632016-12-01 Nick Clifton <nickc@redhat.com> 264 265 PR binutils/20893 266 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad 267 opcode designator. 268 2692016-11-29 Claudiu Zissulescu <claziss@synopsys.com> 270 271 * arc-opc.c (insert_ra_chk): New function. 272 (insert_rb_chk): Likewise. 273 (insert_rad): Update text error message. 274 (insert_rcd): Likewise. 275 (insert_rhv2): Likewise. 276 (insert_r0): Likewise. 277 (insert_r1): Likewise. 278 (insert_r2): Likewise. 279 (insert_r3): Likewise. 280 (insert_sp): Likewise. 281 (insert_gp): Likewise. 282 (insert_pcl): Likewise. 283 (insert_blink): Likewise. 284 (insert_ilink1): Likewise. 285 (insert_ilink2): Likewise. 286 (insert_ras): Likewise. 287 (insert_rbs): Likewise. 288 (insert_rcs): Likewise. 289 (insert_simm3s): Likewise. 290 (insert_rrange): Likewise. 291 (insert_fpel): Likewise. 292 (insert_blinkel): Likewise. 293 (insert_pcel): Likewise. 294 (insert_nps_3bit_dst): Likewise. 295 (insert_nps_3bit_dst_short): Likewise. 296 (insert_nps_3bit_src2_short): Likewise. 297 (insert_nps_bitop_size_2b): Likewise. 298 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. 299 (RA_CHK): Define. 300 (RB): Adjust. 301 (RB_CHK): Define. 302 (RC): Adjust. 303 * arc-dis.c (print_insn_arc): Add LOAD and STORE class. 304 * arc-tbl.h (div, divu): All instructions are DIVREM class. 305 Change first insn argument to check for LP_COUNT usage. 306 (rem): Likewise. 307 (ld, ldd): All instructions are LOAD class. Change first insn 308 argument to check for LP_COUNT usage. 309 (st, std): All instructions are STORE class. 310 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. 311 Change first insn argument to check for LP_COUNT usage. 312 (mov): All instructions are MOVE class. Change first insn 313 argument to check for LP_COUNT usage. 314 3152016-11-29 Claudiu Zissulescu <claziss@synopsys.com> 316 317 * arc-dis.c (is_compatible_p): Remove function. 318 (skip_this_opcode): Don't add any decoding class to decode list. 319 Remove warning. 320 (find_format_from_table): Go through all opcodes, and warn if we 321 use a guessed mnemonic. 322 3232016-11-28 Ramiro Polla <ramiro@hex-rays.com> 324 Amit Pawar <amit.pawar@amd.com> 325 326 PR binutils/20637 327 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP 328 instructions. 329 3302016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com> 331 332 * configure: Regenerate. 333 3342016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com> 335 336 * sparc-opc.c (HWS_V8): Definition moved from 337 gas/config/tc-sparc.c. 338 (HWS_V9): Likewise. 339 (HWS_VA): Likewise. 340 (HWS_VB): Likewise. 341 (HWS_VC): Likewise. 342 (HWS_VD): Likewise. 343 (HWS_VE): Likewise. 344 (HWS_VV): Likewise. 345 (HWS_VM): Likewise. 346 (HWS2_VM): Likewise. 347 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of 348 existing entries. 349 3502016-11-22 Claudiu Zissulescu <claziss@synopsys.com> 351 352 * arc-tbl.h: Reorder conditional flags with delay flags for 'b' 353 instructions. 354 3552016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> 356 357 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. 358 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. 359 (aarch64_opcode_table): Add fcmla and fcadd. 360 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. 361 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. 362 * aarch64-asm.c (aarch64_ins_imm_rotate): Define. 363 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. 364 * aarch64-dis.c (aarch64_ext_imm_rotate): Define. 365 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. 366 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. 367 (operand_general_constraint_met_p): Rotate and index range check. 368 (aarch64_print_operand): Handle rotate operand. 369 * aarch64-asm-2.c: Regenerate. 370 * aarch64-dis-2.c: Likewise. 371 * aarch64-opc-2.c: Likewise. 372 3732016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> 374 375 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr. 376 * aarch64-asm-2.c: Regenerate. 377 * aarch64-dis-2.c: Regenerate. 378 * aarch64-opc-2.c: Regenerate. 379 3802016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> 381 382 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs. 383 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define. 384 * aarch64-asm-2.c: Regenerate. 385 * aarch64-dis-2.c: Regenerate. 386 * aarch64-opc-2.c: Regenerate. 387 3882016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> 389 390 * aarch64-tbl.h (QL_X1NIL): New. 391 (arch64_opcode_table): Add ldraa, ldrab. 392 (AARCH64_OPERANDS): Add "ADDR_SIMM10". 393 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. 394 * aarch64-asm.c (aarch64_ins_addr_simm10): Define. 395 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. 396 * aarch64-dis.c (aarch64_ext_addr_simm10): Define. 397 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. 398 * aarch64-opc.c (fields): Add data for FLD_S_simm10. 399 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. 400 (aarch64_print_operand): Likewise. 401 * aarch64-asm-2.c: Regenerate. 402 * aarch64-dis-2.c: Regenerate. 403 * aarch64-opc-2.c: Regenerate. 404 4052016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 406 407 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz, 408 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab. 409 * aarch64-asm-2.c: Regenerate. 410 * aarch64-dis-2.c: Regenerate. 411 * aarch64-opc-2.c: Regenerate. 412 4132016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 414 415 * aarch64-tbl.h (arch64_opcode_table): Add pacga. 416 (AARCH64_OPERANDS): Add Rm_SP. 417 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP. 418 * aarch64-asm-2.c: Regenerate. 419 * aarch64-dis-2.c: Regenerate. 420 * aarch64-opc-2.c: Regenerate. 421 4222016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 423 424 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia, 425 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza, 426 autdzb, xpaci, xpacd. 427 * aarch64-asm-2.c: Regenerate. 428 * aarch64-dis-2.c: Regenerate. 429 * aarch64-opc-2.c: Regenerate. 430 4312016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 432 433 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1, 434 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1, 435 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1. 436 (aarch64_sys_reg_supported_p): Add feature test for new registers. 437 4382016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 439 440 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New. 441 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716, 442 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz, 443 autibsp. 444 * aarch64-asm-2.c: Regenerate. 445 * aarch64-dis-2.c: Regenerate. 446 4472016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> 448 449 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32. 450 4512016-11-09 H.J. Lu <hongjiu.lu@intel.com> 452 453 PR binutils/20799 454 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw. 455 * i386-dis.c (EdqwS): Removed. 456 (dqw_swap_mode): Likewise. 457 (intel_operand_size): Don't check dqw_swap_mode. 458 (OP_E_register): Likewise. 459 (OP_E_memory): Likewise. 460 (OP_G): Likewise. 461 (OP_EX): Likewise. 462 * i386-opc.tbl: Remove "S" from EVEX vpextrw. 463 * i386-tbl.h: Regerated. 464 4652016-11-09 H.J. Lu <hongjiu.lu@intel.com> 466 467 * i386-opc.tbl: Merge AVX512F vmovq. 468 * i386-tbl.h: Regerated. 469 4702016-11-08 H.J. Lu <hongjiu.lu@intel.com> 471 472 PR binutils/20701 473 * i386-dis.c (THREE_BYTE_0F7A): Removed. 474 (dis386_twobyte): Don't use THREE_BYTE_0F7A. 475 (three_byte_table): Remove THREE_BYTE_0F7A. 476 4772016-11-07 H.J. Lu <hongjiu.lu@intel.com> 478 479 PR binutils/20775 480 * i386-dis.c (FGRPd9_2): Replace 0 with 1. 481 (FGRPd9_4): Replace 1 with 2. 482 (FGRPd9_5): Replace 2 with 3. 483 (FGRPd9_6): Replace 3 with 4. 484 (FGRPd9_7): Replace 4 with 5. 485 (FGRPda_5): Replace 5 with 6. 486 (FGRPdb_4): Replace 6 with 7. 487 (FGRPde_3): Replace 7 with 8. 488 (FGRPdf_4): Replace 8 with 9. 489 (fgrps): Add an entry for Bad_Opcode. 490 4912016-11-04 Andrew Burgess <andrew.burgess@embecosm.com> 492 493 * arc-opc.c (arc_flag_operands): Add F_DI14. 494 (arc_flag_classes): Add C_DI14. 495 * arc-nps400-tbl.h: Add new exc instructions. 496 4972016-11-03 Graham Markall <graham.markall@embecosm.com> 498 499 * arc-dis.c (arc_insn_length): Return length 8 for instructions with 500 major opcode 0xa. 501 * arc-nps-400-tbl.h: Add dcmac instruction. 502 * arc-opc.c (arc_operands): Added operands for dcmac instruction. 503 (insert_nps_rbdouble_64): Added. 504 (extract_nps_rbdouble_64): Added. 505 (insert_nps_proto_size): Added. 506 (extract_nps_proto_size): Added. 507 5082016-11-03 Andrew Burgess <andrew.burgess@embecosm.com> 509 510 * arc-dis.c (struct arc_operand_iterator): Remove all fields 511 relating to long instruction processing, add new limm field. 512 (OPCODE): Rename to... 513 (OPCODE_32BIT_INSN): ...this. 514 (OPCODE_AC): Delete. 515 (skip_this_opcode): Handle different instruction lengths, update 516 macro name. 517 (special_flag_p): Update parameter type. 518 (find_format_from_table): Update for more instruction lengths. 519 (find_format_long_instructions): Delete. 520 (find_format): Update for more instruction lengths. 521 (arc_insn_length): Likewise. 522 (extract_operand_value): Update for more instruction lengths. 523 (operand_iterator_next): Remove code relating to long 524 instructions. 525 (arc_opcode_to_insn_type): New function. 526 (print_insn_arc):Update for more instructions lengths. 527 * arc-ext.c (extInstruction_t): Change argument type. 528 * arc-ext.h (extInstruction_t): Change argument type. 529 * arc-fxi.h: Change type unsigned to unsigned long long 530 extensively throughout. 531 * arc-nps400-tbl.h: Add long instructions taken from 532 arc_long_opcodes table in arc-opc.c. 533 * arc-opc.c: Update parameter types on insert/extract handlers. 534 (arc_long_opcodes): Delete. 535 (arc_num_long_opcodes): Delete. 536 (arc_opcode_len): Update for more instruction lengths. 537 5382016-11-03 Graham Markall <graham.markall@embecosm.com> 539 540 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte. 541 5422016-11-03 Graham Markall <graham.markall@embecosm.com> 543 544 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT 545 with arc_opcode_len. 546 (find_format_long_instructions): Likewise. 547 * arc-opc.c (arc_opcode_len): New function. 548 5492016-11-03 Andrew Burgess <andrew.burgess@embecosm.com> 550 551 * arc-nps400-tbl.h: Fix some instruction masks. 552 5532016-11-03 H.J. Lu <hongjiu.lu@intel.com> 554 555 * i386-dis.c (REG_82): Removed. 556 (X86_64_82_REG_0): Likewise. 557 (X86_64_82_REG_1): Likewise. 558 (X86_64_82_REG_2): Likewise. 559 (X86_64_82_REG_3): Likewise. 560 (X86_64_82_REG_4): Likewise. 561 (X86_64_82_REG_5): Likewise. 562 (X86_64_82_REG_6): Likewise. 563 (X86_64_82_REG_7): Likewise. 564 (X86_64_82): New. 565 (dis386): Use X86_64_82 instead of REG_82. 566 (reg_table): Remove REG_82. 567 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0, 568 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, 569 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and 570 X86_64_82_REG_7. 571 5722016-11-03 H.J. Lu <hongjiu.lu@intel.com> 573 574 PR binutils/20754 575 * i386-dis.c (REG_82): New. 576 (X86_64_82_REG_0): Likewise. 577 (X86_64_82_REG_1): Likewise. 578 (X86_64_82_REG_2): Likewise. 579 (X86_64_82_REG_3): Likewise. 580 (X86_64_82_REG_4): Likewise. 581 (X86_64_82_REG_5): Likewise. 582 (X86_64_82_REG_6): Likewise. 583 (X86_64_82_REG_7): Likewise. 584 (dis386): Use REG_82. 585 (reg_table): Add REG_82. 586 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1, 587 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, 588 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7. 589 5902016-11-03 H.J. Lu <hongjiu.lu@intel.com> 591 592 * i386-dis.c (REG_82): Renamed to ... 593 (REG_83): This. 594 (dis386): Updated. 595 (reg_table): Likewise. 596 5972016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com> 598 599 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. 600 * i386-dis-evex.h (evex_table): Updated. 601 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, 602 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. 603 (cpu_flags): Add CpuAVX512_4VNNIW. 604 * i386-opc.h (enum): (AVX512_4VNNIW): New. 605 (i386_cpu_flags): Add cpuavx512_4vnniw. 606 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. 607 * i386-init.h: Regenerate. 608 * i386-tbl.h: Ditto. 609 6102016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com> 611 612 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A, 613 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB. 614 * i386-dis-evex.h (evex_table): Updated. 615 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS, 616 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS. 617 (cpu_flags): Add CpuAVX512_4FMAPS. 618 (opcode_modifiers): Add ImplicitQuadGroup modifier. 619 * i386-opc.h (AVX512_4FMAP): New. 620 (i386_cpu_flags): Add cpuavx512_4fmaps. 621 (ImplicitQuadGroup): New. 622 (i386_opcode_modifier): Add implicitquadgroup. 623 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions. 624 * i386-init.h: Regenerate. 625 * i386-tbl.h: Ditto. 626 6272016-11-01 Palmer Dabbelt <palmer@dabbelt.com> 628 Andrew Waterman <andrew@sifive.com> 629 630 Add support for RISC-V architecture. 631 * configure.ac: Add entry for bfd_riscv_arch. 632 * configure: Regenerate. 633 * disassemble.c (disassembler): Add support for riscv. 634 (disassembler_usage): Likewise. 635 * riscv-dis.c: New file. 636 * riscv-opc.c: New file. 637 6382016-10-21 H.J. Lu <hongjiu.lu@intel.com> 639 640 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. 641 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry. 642 (rm_table): Update the RM_0FAE_REG_7 entry. 643 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS. 644 (cpu_flags): Remove CpuPCOMMIT. 645 * i386-opc.h (CpuPCOMMIT): Removed. 646 (i386_cpu_flags): Remove cpupcommit. 647 * i386-opc.tbl: Remove pcommit. 648 * i386-init.h: Regenerated. 649 * i386-tbl.h: Likewise. 650 6512016-10-20 H.J. Lu <hongjiu.lu@intel.com> 652 653 PR binutis/20705 654 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and 655 the highest bit in VEX.vvvv for the 3-byte VEX prefix in 656 32-bit mode. Don't check vex.register_specifier in 32-bit 657 mode. 658 (OP_VEX): Check for invalid mask registers. 659 6602016-10-18 H.J. Lu <hongjiu.lu@intel.com> 661 662 PR binutis/20699 663 * i386-dis.c (OP_E_memory): Check addr32flag in stead of 664 sizeflag. 665 6662016-10-18 H.J. Lu <hongjiu.lu@intel.com> 667 668 PR binutis/20704 669 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support. 670 6712016-10-18 Maciej W. Rozycki <macro@imgtec.com> 672 673 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index' 674 local variable to `index_regno'. 675 6762016-10-17 Cupertino Miranda <cmiranda@synopsys.com> 677 678 * arc-tbl.h: Removed any "inv.+" instructions from the table. 679 6802016-10-14 Claudiu Zissulescu <claziss@synopsys.com> 681 682 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator 683 usage on ISA basis. 684 6852016-10-11 Jiong Wang <jiong.wang@arm.com> 686 687 PR target/20666 688 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index. 689 6902016-10-07 Jiong Wang <jiong.wang@arm.com> 691 692 PR target/20667 693 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's 694 available. 695 6962016-10-07 Alan Modra <amodra@gmail.com> 697 698 * sh-opc.h (sh_merge_bfd_arch): Delete prototype. 699 7002016-10-06 Alan Modra <amodra@gmail.com> 701 702 * aarch64-opc.c: Spell fall through comments consistently. 703 * i386-dis.c: Likewise. 704 * aarch64-dis.c: Add missing fall through comments. 705 * aarch64-opc.c: Likewise. 706 * arc-dis.c: Likewise. 707 * arm-dis.c: Likewise. 708 * i386-dis.c: Likewise. 709 * m68k-dis.c: Likewise. 710 * mep-asm.c: Likewise. 711 * ns32k-dis.c: Likewise. 712 * sh-dis.c: Likewise. 713 * tic4x-dis.c: Likewise. 714 * tic6x-dis.c: Likewise. 715 * vax-dis.c: Likewise. 716 7172016-10-06 Alan Modra <amodra@gmail.com> 718 719 * arc-ext.c (create_map): Add missing break. 720 * msp430-decode.opc (encode_as): Likewise. 721 * msp430-decode.c: Regenerate. 722 7232016-10-06 Alan Modra <amodra@gmail.com> 724 725 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic. 726 * crx-dis.c (print_insn_crx): Likewise. 727 7282016-09-30 H.J. Lu <hongjiu.lu@intel.com> 729 730 PR binutils/20657 731 * i386-dis.c (putop): Don't assign alt twice. 732 7332016-09-29 Jiong Wang <jiong.wang@arm.com> 734 735 PR target/20553 736 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field. 737 7382016-09-29 Alan Modra <amodra@gmail.com> 739 740 * ppc-opc.c (L): Make compulsory. 741 (LOPT): New, optional form of L. 742 (HTM_R): Define as LOPT. 743 (L0, L1): Delete. 744 (L32OPT): New, optional for 32-bit L. 745 (L2OPT): New, 2-bit L for dcbf. 746 (SVC_LEC): Update. 747 (L2): Define. 748 (insert_l0, extract_l0, insert_l1, extract_l2): Delete. 749 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT. 750 <dcbf>: Use L2OPT. 751 <tlbiel, tlbie>: Use LOPT. 752 <wclr, wclrall>: Use L2. 753 7542016-09-26 Vlad Zakharov <vzakhar@synopsys.com> 755 756 * Makefile.in: Regenerate. 757 * configure: Likewise. 758 7592016-09-26 Claudiu Zissulescu <claziss@synopsys.com> 760 761 * arc-ext-tbl.h (EXTINSN2OPF): Define. 762 (EXTINSN2OP): Use EXTINSN2OPF. 763 (bspeekm, bspop, modapp): New extension instructions. 764 * arc-opc.c (F_DNZ_ND): Define. 765 (F_DNZ_D): Likewise. 766 (F_SIZEB1): Changed. 767 (C_DNZ_D): Define. 768 (C_HARD): Changed. 769 * arc-tbl.h (dbnz): New instruction. 770 (prealloc): Allow it for ARC EM. 771 (xbfu): Likewise. 772 7732016-09-21 Richard Sandiford <richard.sandiford@arm.com> 774 775 * aarch64-opc.c (print_immediate_offset_address): Print spaces 776 after commas in addresses. 777 (aarch64_print_operand): Likewise. 778 7792016-09-21 Richard Sandiford <richard.sandiford@arm.com> 780 781 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be" 782 rather than "should be" or "expected to be" in error messages. 783 7842016-09-21 Richard Sandiford <richard.sandiford@arm.com> 785 786 * aarch64-dis.c (remove_dot_suffix): New function, split out from... 787 (print_mnemonic_name): ...here. 788 (print_comment): New function. 789 (print_aarch64_insn): Call it. 790 * aarch64-opc.c (aarch64_conds): Add SVE names. 791 (aarch64_print_operand): Print alternative condition names in 792 a comment. 793 7942016-09-21 Richard Sandiford <richard.sandiford@arm.com> 795 796 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) 797 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) 798 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) 799 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) 800 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) 801 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) 802 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) 803 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) 804 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) 805 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) 806 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) 807 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) 808 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) 809 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) 810 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) 811 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) 812 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) 813 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) 814 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) 815 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) 816 (OP_SVE_XWU, OP_SVE_XXU): New macros. 817 (aarch64_feature_sve): New variable. 818 (SVE): New macro. 819 (_SVE_INSN): Likewise. 820 (aarch64_opcode_table): Add SVE instructions. 821 * aarch64-opc.h (extract_fields): Declare. 822 * aarch64-opc-2.c: Regenerate. 823 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. 824 * aarch64-asm-2.c: Regenerate. 825 * aarch64-dis.c (extract_fields): Make global. 826 (do_misc_decoding): Handle the new SVE aarch64_ops. 827 * aarch64-dis-2.c: Regenerate. 828 8292016-09-21 Richard Sandiford <richard.sandiford@arm.com> 830 831 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) 832 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New 833 aarch64_field_kinds. 834 * aarch64-opc.c (fields): Add corresponding entries. 835 * aarch64-asm.c (aarch64_get_variant): New function. 836 (aarch64_encode_variant_using_iclass): Likewise. 837 (aarch64_opcode_encode): Call it. 838 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. 839 (aarch64_opcode_decode): Call it. 840 8412016-09-21 Richard Sandiford <richard.sandiford@arm.com> 842 843 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core 844 and FP register operands. 845 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) 846 (FLD_SVE_Vn): New aarch64_field_kinds. 847 * aarch64-opc.c (fields): Add corresponding entries. 848 (aarch64_print_operand): Handle the new SVE core and FP register 849 operands. 850 * aarch64-opc-2.c: Regenerate. 851 * aarch64-asm-2.c: Likewise. 852 * aarch64-dis-2.c: Likewise. 853 8542016-09-21 Richard Sandiford <richard.sandiford@arm.com> 855 856 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP 857 immediate operands. 858 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. 859 * aarch64-opc.c (fields): Add corresponding entry. 860 (operand_general_constraint_met_p): Handle the new SVE FP immediate 861 operands. 862 (aarch64_print_operand): Likewise. 863 * aarch64-opc-2.c: Regenerate. 864 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) 865 (ins_sve_float_zero_one): New inserters. 866 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. 867 (aarch64_ins_sve_float_half_two): Likewise. 868 (aarch64_ins_sve_float_zero_one): Likewise. 869 * aarch64-asm-2.c: Regenerate. 870 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) 871 (ext_sve_float_zero_one): New extractors. 872 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. 873 (aarch64_ext_sve_float_half_two): Likewise. 874 (aarch64_ext_sve_float_zero_one): Likewise. 875 * aarch64-dis-2.c: Regenerate. 876 8772016-09-21 Richard Sandiford <richard.sandiford@arm.com> 878 879 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE 880 integer immediate operands. 881 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) 882 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) 883 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. 884 * aarch64-opc.c (fields): Add corresponding entries. 885 (operand_general_constraint_met_p): Handle the new SVE integer 886 immediate operands. 887 (aarch64_print_operand): Likewise. 888 (aarch64_sve_dupm_mov_immediate_p): New function. 889 * aarch64-opc-2.c: Regenerate. 890 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) 891 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. 892 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... 893 (aarch64_ins_limm): ...here. 894 (aarch64_ins_inv_limm): New function. 895 (aarch64_ins_sve_aimm): Likewise. 896 (aarch64_ins_sve_asimm): Likewise. 897 (aarch64_ins_sve_limm_mov): Likewise. 898 (aarch64_ins_sve_shlimm): Likewise. 899 (aarch64_ins_sve_shrimm): Likewise. 900 * aarch64-asm-2.c: Regenerate. 901 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) 902 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. 903 * aarch64-dis.c (decode_limm): New function, split out from... 904 (aarch64_ext_limm): ...here. 905 (aarch64_ext_inv_limm): New function. 906 (decode_sve_aimm): Likewise. 907 (aarch64_ext_sve_aimm): Likewise. 908 (aarch64_ext_sve_asimm): Likewise. 909 (aarch64_ext_sve_limm_mov): Likewise. 910 (aarch64_top_bit): Likewise. 911 (aarch64_ext_sve_shlimm): Likewise. 912 (aarch64_ext_sve_shrimm): Likewise. 913 * aarch64-dis-2.c: Regenerate. 914 9152016-09-21 Richard Sandiford <richard.sandiford@arm.com> 916 917 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL 918 operands. 919 * aarch64-opc.c (aarch64_operand_modifiers): Initialize 920 the AARCH64_MOD_MUL_VL entry. 921 (value_aligned_p): Cope with non-power-of-two alignments. 922 (operand_general_constraint_met_p): Handle the new MUL VL addresses. 923 (print_immediate_offset_address): Likewise. 924 (aarch64_print_operand): Likewise. 925 * aarch64-opc-2.c: Regenerate. 926 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) 927 (ins_sve_addr_ri_s9xvl): New inserters. 928 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. 929 (aarch64_ins_sve_addr_ri_s6xvl): Likewise. 930 (aarch64_ins_sve_addr_ri_s9xvl): Likewise. 931 * aarch64-asm-2.c: Regenerate. 932 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) 933 (ext_sve_addr_ri_s9xvl): New extractors. 934 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. 935 (aarch64_ext_sve_addr_ri_s4xvl): Likewise. 936 (aarch64_ext_sve_addr_ri_s6xvl): Likewise. 937 (aarch64_ext_sve_addr_ri_s9xvl): Likewise. 938 * aarch64-dis-2.c: Regenerate. 939 9402016-09-21 Richard Sandiford <richard.sandiford@arm.com> 941 942 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE 943 address operands. 944 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) 945 (FLD_SVE_xs_22): New aarch64_field_kinds. 946 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. 947 (get_operand_specific_data): New function. 948 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, 949 FLD_SVE_xs_14 and FLD_SVE_xs_22. 950 (operand_general_constraint_met_p): Handle the new SVE address 951 operands. 952 (sve_reg): New array. 953 (get_addr_sve_reg_name): New function. 954 (aarch64_print_operand): Handle the new SVE address operands. 955 * aarch64-opc-2.c: Regenerate. 956 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) 957 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) 958 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. 959 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. 960 (aarch64_ins_sve_addr_rr_lsl): Likewise. 961 (aarch64_ins_sve_addr_rz_xtw): Likewise. 962 (aarch64_ins_sve_addr_zi_u5): Likewise. 963 (aarch64_ins_sve_addr_zz): Likewise. 964 (aarch64_ins_sve_addr_zz_lsl): Likewise. 965 (aarch64_ins_sve_addr_zz_sxtw): Likewise. 966 (aarch64_ins_sve_addr_zz_uxtw): Likewise. 967 * aarch64-asm-2.c: Regenerate. 968 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) 969 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) 970 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. 971 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. 972 (aarch64_ext_sve_addr_ri_u6): Likewise. 973 (aarch64_ext_sve_addr_rr_lsl): Likewise. 974 (aarch64_ext_sve_addr_rz_xtw): Likewise. 975 (aarch64_ext_sve_addr_zi_u5): Likewise. 976 (aarch64_ext_sve_addr_zz): Likewise. 977 (aarch64_ext_sve_addr_zz_lsl): Likewise. 978 (aarch64_ext_sve_addr_zz_sxtw): Likewise. 979 (aarch64_ext_sve_addr_zz_uxtw): Likewise. 980 * aarch64-dis-2.c: Regenerate. 981 9822016-09-21 Richard Sandiford <richard.sandiford@arm.com> 983 984 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for 985 AARCH64_OPND_SVE_PATTERN_SCALED. 986 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. 987 * aarch64-opc.c (fields): Add a corresponding entry. 988 (set_multiplier_out_of_range_error): New function. 989 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. 990 (operand_general_constraint_met_p): Handle 991 AARCH64_OPND_SVE_PATTERN_SCALED. 992 (print_register_offset_address): Use PRIi64 to print the 993 shift amount. 994 (aarch64_print_operand): Likewise. Handle 995 AARCH64_OPND_SVE_PATTERN_SCALED. 996 * aarch64-opc-2.c: Regenerate. 997 * aarch64-asm.h (ins_sve_scale): New inserter. 998 * aarch64-asm.c (aarch64_ins_sve_scale): New function. 999 * aarch64-asm-2.c: Regenerate. 1000 * aarch64-dis.h (ext_sve_scale): New inserter. 1001 * aarch64-dis.c (aarch64_ext_sve_scale): New function. 1002 * aarch64-dis-2.c: Regenerate. 1003 10042016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1005 1006 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for 1007 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. 1008 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. 1009 (FLD_SVE_prfop): Likewise. 1010 * aarch64-opc.c: Include libiberty.h. 1011 (aarch64_sve_pattern_array): New variable. 1012 (aarch64_sve_prfop_array): Likewise. 1013 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. 1014 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and 1015 AARCH64_OPND_SVE_PRFOP. 1016 * aarch64-asm-2.c: Regenerate. 1017 * aarch64-dis-2.c: Likewise. 1018 * aarch64-opc-2.c: Likewise. 1019 10202016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1021 1022 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for 1023 AARCH64_OPND_QLF_P_[ZM]. 1024 (aarch64_print_operand): Print /z and /m where appropriate. 1025 10262016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1027 1028 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. 1029 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) 1030 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) 1031 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) 1032 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. 1033 * aarch64-opc.c (fields): Add corresponding entries here. 1034 (operand_general_constraint_met_p): Check that SVE register lists 1035 have the correct length. Check the ranges of SVE index registers. 1036 Check for cases where p8-p15 are used in 3-bit predicate fields. 1037 (aarch64_print_operand): Handle the new SVE operands. 1038 * aarch64-opc-2.c: Regenerate. 1039 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. 1040 * aarch64-asm.c (aarch64_ins_sve_index): New function. 1041 (aarch64_ins_sve_reglist): Likewise. 1042 * aarch64-asm-2.c: Regenerate. 1043 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. 1044 * aarch64-dis.c (aarch64_ext_sve_index): New function. 1045 (aarch64_ext_sve_reglist): Likewise. 1046 * aarch64-dis-2.c: Regenerate. 1047 10482016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1049 1050 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) 1051 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) 1052 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. 1053 * aarch64-opc.c (aarch64_match_operands_constraint): Check for 1054 tied operands. 1055 10562016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1057 1058 * aarch64-opc.c (get_offset_int_reg_name): New function. 1059 (print_immediate_offset_address): Likewise. 1060 (print_register_offset_address): Take the base and offset 1061 registers as parameters. 1062 (aarch64_print_operand): Update caller accordingly. Use 1063 print_immediate_offset_address. 1064 10652016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1066 1067 * aarch64-opc.c (BANK): New macro. 1068 (R32, R64): Take a register number as argument 1069 (int_reg): Use BANK. 1070 10712016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1072 1073 * aarch64-opc.c (print_register_list): Add a prefix parameter. 1074 (aarch64_print_operand): Update accordingly. 1075 10762016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1077 1078 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm 1079 for FPIMM. 1080 * aarch64-asm.h (ins_fpimm): New inserter. 1081 * aarch64-asm.c (aarch64_ins_fpimm): New function. 1082 * aarch64-asm-2.c: Regenerate. 1083 * aarch64-dis.h (ext_fpimm): New extractor. 1084 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. 1085 (aarch64_ext_fpimm): New function. 1086 * aarch64-dis-2.c: Regenerate. 1087 10882016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1089 1090 * aarch64-asm.c: Include libiberty.h. 1091 (insert_fields): New function. 1092 (aarch64_ins_imm): Use it. 1093 * aarch64-dis.c (extract_fields): New function. 1094 (aarch64_ext_imm): Use it. 1095 10962016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1097 1098 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 1099 with an esize parameter. 1100 (operand_general_constraint_met_p): Update accordingly. 1101 Fix misindented code. 1102 * aarch64-asm.c (aarch64_ins_limm): Update call to 1103 aarch64_logical_immediate_p. 1104 11052016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1106 1107 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. 1108 11092016-09-21 Richard Sandiford <richard.sandiford@arm.com> 1110 1111 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit. 1112 11132016-09-15 Claudiu Zissulescu <claziss@synopsys.com> 1114 1115 * arc-dis.c (find_format): Walk the linked list pointed by einsn. 1116 11172016-09-14 Peter Bergner <bergner@vnet.ibm.com> 1118 1119 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. 1120 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, 1121 xor3>: Delete mnemonics. 1122 <cp_abort>: Rename mnemonic from ... 1123 <cpabort>: ...to this. 1124 <setb>: Change to a X form instruction. 1125 <sync>: Change to 1 operand form. 1126 <copy>: Delete mnemonic. 1127 <copy_first>: Rename mnemonic from ... 1128 <copy>: ...to this. 1129 <paste, paste.>: Delete mnemonics. 1130 <paste_last>: Rename mnemonic from ... 1131 <paste.>: ...to this. 1132 11332016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com> 1134 1135 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully. 1136 11372016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 1138 1139 * s390-mkopc.c (main): Support alternate arch strings. 1140 11412016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com> 1142 1143 * s390-opc.txt: Fix kmctr instruction type. 1144 11452016-09-07 H.J. Lu <hongjiu.lu@intel.com> 1146 1147 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS. 1148 * i386-init.h: Regenerated. 1149 11502016-08-30 Cupertino Miranda <cmiranda@synopsys.com> 1151 1152 * opcodes/arc-dis.c (print_insn_arc): Changed. 1153 11542016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com> 1155 1156 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi -> 1157 camellia_fl. 1158 11592016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> 1160 1161 * arm-dis.c (psr_name): Use hex as case labels. Add detection for 1162 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, 1163 FAULTMASK_NS, CONTROL_NS and SP_NS special registers. 1164 11652016-08-24 H.J. Lu <hongjiu.lu@intel.com> 1166 1167 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. 1168 (PREFIX_MOD_3_0FAE_REG_4): Likewise. 1169 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and 1170 PREFIX_MOD_3_0FAE_REG_4. 1171 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and 1172 PREFIX_MOD_3_0FAE_REG_4. 1173 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. 1174 (cpu_flags): Add CpuPTWRITE. 1175 * i386-opc.h (CpuPTWRITE): New. 1176 (i386_cpu_flags): Add cpuptwrite. 1177 * i386-opc.tbl: Add ptwrite instruction. 1178 * i386-init.h: Regenerated. 1179 * i386-tbl.h: Likewise. 1180 11812016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com> 1182 1183 * arc-dis.h: Wrap around in extern "C". 1184 11852016-08-23 Richard Sandiford <richard.sandiford@arm.com> 1186 1187 * aarch64-tbl.h (V8_2_INSN): New macro. 1188 (aarch64_opcode_table): Use it. 1189 11902016-08-23 Richard Sandiford <richard.sandiford@arm.com> 1191 1192 * aarch64-tbl.h (aarch64_opcode_table): Make more use of 1193 CORE_INSN, __FP_INSN and SIMD_INSN. 1194 11952016-08-23 Richard Sandiford <richard.sandiford@arm.com> 1196 1197 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter. 1198 (aarch64_opcode_table): Update uses accordingly. 1199 12002016-07-25 Andrew Jenner <andrew@codesourcery.com> 1201 Kwok Cheung Yeung <kcy@codesourcery.com> 1202 1203 opcodes/ 1204 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and 1205 'e_cmplwi' to 'e_cmpli' instead. 1206 (OPVUPRT, OPVUPRT_MASK): Define. 1207 (powerpc_opcodes): Add E200Z4 insns. 1208 (vle_opcodes): Add context save/restore insns. 1209 12102016-07-27 Maciej W. Rozycki <macro@imgtec.com> 1211 1212 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", 1213 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to 1214 "j". 1215 12162016-07-27 Graham Markall <graham.markall@embecosm.com> 1217 1218 * arc-nps400-tbl.h: Change block comments to GNU format. 1219 * arc-dis.c: Add new globals addrtypenames, 1220 addrtypenames_max, and addtypeunknown. 1221 (get_addrtype): New function. 1222 (print_insn_arc): Print colons and address types when 1223 required. 1224 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to 1225 define insert and extract functions for all address types. 1226 (arc_operands): Add operands for colon and all address 1227 types. 1228 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. 1229 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, 1230 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. 1231 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. 1232 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, 1233 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. 1234 12352016-07-21 H.J. Lu <hongjiu.lu@intel.com> 1236 1237 * configure: Regenerated. 1238 12392016-07-20 Claudiu Zissulescu <claziss@synopsys.com> 1240 1241 * arc-dis.c (skipclass): New structure. 1242 (decodelist): New variable. 1243 (is_compatible_p): New function. 1244 (new_element): Likewise. 1245 (skip_class_p): Likewise. 1246 (find_format_from_table): Use skip_class_p function. 1247 (find_format): Decode first the extension instructions. 1248 (print_insn_arc): Select either ARCEM or ARCHS based on elf 1249 e_flags. 1250 (parse_option): New function. 1251 (parse_disassembler_options): Likewise. 1252 (print_arc_disassembler_options): Likewise. 1253 (print_insn_arc): Use parse_disassembler_options function. Proper 1254 select ARCv2 cpu variant. 1255 * disassemble.c (disassembler_usage): Add ARC disassembler 1256 options. 1257 12582016-07-13 Maciej W. Rozycki <macro@imgtec.com> 1259 1260 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS 1261 annotation from the "nal" entry and reorder it beyond "bltzal". 1262 12632016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com> 1264 1265 * sparc-opc.c (ldtxa): New macro. 1266 (sparc_opcodes): Use the macro defined above to add entries for 1267 the LDTXA instructions. 1268 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA 1269 instruction. 1270 12712016-07-07 James Bowman <james.bowman@ftdichip.com> 1272 1273 * ft32-opc.c (ft32_opc_info): Correct mask for "callc" 1274 and "jmpc". 1275 12762016-07-01 Jan Beulich <jbeulich@suse.com> 1277 1278 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove. 1279 (movzb): Adjust to cover all permitted suffixes. 1280 (movzw): New. 1281 * i386-tbl.h: Re-generate. 1282 12832016-07-01 Jan Beulich <jbeulich@suse.com> 1284 1285 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant. 1286 (lgdt): Remove Tbyte from non-64-bit variant. 1287 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64, 1288 xsaves64, xsavec64): Remove Disp16. 1289 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd): 1290 Remove Disp32S from non-64-bit variants. Remove Disp16 from 1291 64-bit variants. 1292 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd, 1293 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi, 1294 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from 1295 64-bit variants. 1296 * i386-tbl.h: Re-generate. 1297 12982016-07-01 Jan Beulich <jbeulich@suse.com> 1299 1300 * i386-opc.tbl (xlat): Remove RepPrefixOk. 1301 * i386-tbl.h: Re-generate. 1302 13032016-06-30 Yao Qi <yao.qi@linaro.org> 1304 1305 * arm-dis.c (print_insn): Fix typo in comment. 1306 13072016-06-28 Richard Sandiford <richard.sandiford@arm.com> 1308 1309 * aarch64-opc.c (operand_general_constraint_met_p): Check the 1310 range of ldst_elemlist operands. 1311 (print_register_list): Use PRIi64 to print the index. 1312 (aarch64_print_operand): Likewise. 1313 13142016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 1315 1316 * mcore-opc.h: Remove sentinal. 1317 * mcore-dis.c (print_insn_mcore): Adjust. 1318 13192016-06-23 Graham Markall <graham.markall@embecosm.com> 1320 1321 * arc-opc.c: Correct description of availability of NPS400 1322 features. 1323 13242016-06-22 Peter Bergner <bergner@vnet.ibm.com> 1325 1326 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. 1327 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, 1328 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, 1329 xor3>: New mnemonics. 1330 <setb>: Change to a VX form instruction. 1331 (insert_sh6): Add support for rldixor. 1332 (extract_sh6): Likewise. 1333 13342016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 1335 1336 * arc-ext.h: Wrap in extern C. 1337 13382016-06-21 Graham Markall <graham.markall@embecosm.com> 1339 1340 * arc-dis.c (arc_insn_length): Add comment on instruction length. 1341 Use same method for determining instruction length on ARC700 and 1342 NPS-400. 1343 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. 1344 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions 1345 with the NPS400 subclass. 1346 * arc-opc.c: Likewise. 1347 13482016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> 1349 1350 * sparc-opc.c (rdasr): New macro. 1351 (wrasr): Likewise. 1352 (rdpr): Likewise. 1353 (wrpr): Likewise. 1354 (rdhpr): Likewise. 1355 (wrhpr): Likewise. 1356 (sparc_opcodes): Use the macros above to fix and expand the 1357 definition of read/write instructions from/to 1358 asr/privileged/hyperprivileged instructions. 1359 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and 1360 %hva_mask_nz. Prefer softint_set and softint_clear over 1361 set_softint and clear_softint. 1362 (print_insn_sparc): Support %ver in Rd. 1363 13642016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> 1365 1366 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode 1367 architecture according to the hardware capabilities they require. 1368 13692016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> 1370 1371 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. 1372 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and 1373 bfd_mach_sparc_v9{c,d,e,v,m}. 1374 * sparc-opc.c (MASK_V9C): Define. 1375 (MASK_V9D): Likewise. 1376 (MASK_V9E): Likewise. 1377 (MASK_V9V): Likewise. 1378 (MASK_V9M): Likewise. 1379 (v6): Add MASK_V9{C,D,E,V,M}. 1380 (v6notlet): Likewise. 1381 (v7): Likewise. 1382 (v8): Likewise. 1383 (v9): Likewise. 1384 (v9andleon): Likewise. 1385 (v9a): Likewise. 1386 (v9b): Likewise. 1387 (v9c): Define. 1388 (v9d): Likewise. 1389 (v9e): Likewise. 1390 (v9v): Likewise. 1391 (v9m): Likewise. 1392 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}. 1393 13942016-06-15 Nick Clifton <nickc@redhat.com> 1395 1396 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer 1397 constants to match expected behaviour. 1398 (nds32_parse_opcode): Likewise. Also for whitespace. 1399 14002016-06-15 Andrew Burgess <andrew.burgess@embecosm.com> 1401 1402 * arc-opc.c (extract_rhv1): Extract value from insn. 1403 14042016-06-14 Graham Markall <graham.markall@embecosm.com> 1405 1406 * arc-nps400-tbl.h: Add ldbit instruction. 1407 * arc-opc.c: Add flag classes required for ldbit. 1408 14092016-06-14 Graham Markall <graham.markall@embecosm.com> 1410 1411 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf 1412 * arc-opc.c: Add flag classes, insert/extract functions, and operands to 1413 support the above instructions. 1414 14152016-06-14 Graham Markall <graham.markall@embecosm.com> 1416 1417 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb, 1418 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms, 1419 csma, cbba, zncv, and hofs. 1420 * arc-opc.c: Add flag classes, insert/extract functions, and operands to 1421 support the above instructions. 1422 14232016-06-06 Graham Markall <graham.markall@embecosm.com> 1424 1425 * arc-nps400-tbl.h: Add andab and orab instructions. 1426 14272016-06-06 Graham Markall <graham.markall@embecosm.com> 1428 1429 * arc-nps400-tbl.h: Add addl-like instructions. 1430 14312016-06-06 Graham Markall <graham.markall@embecosm.com> 1432 1433 * arc-nps400-tbl.h: Add mxb and imxb instructions. 1434 14352016-06-06 Graham Markall <graham.markall@embecosm.com> 1436 1437 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey 1438 instructions. 1439 14402016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 1441 1442 * s390-dis.c (option_use_insn_len_bits_p): New file scope 1443 variable. 1444 (init_disasm): Handle new command line option "insnlength". 1445 (print_s390_disassembler_options): Mention new option in help 1446 output. 1447 (print_insn_s390): Use the encoded insn length when dumping 1448 unknown instructions. 1449 14502016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com> 1451 1452 * avr-dis.c (avr_operand): Add default data address space origin (0x800000) 1453 to the address and set as symbol address for LDS/ STS immediate operands. 1454 14552016-06-07 Alan Modra <amodra@gmail.com> 1456 1457 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default 1458 cpu for "vle" to e500. 1459 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. 1460 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. 1461 (PPCNONE): Delete, substitute throughout. 1462 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" 1463 except for major opcode 4 and 31. 1464 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. 1465 14662016-06-07 Matthew Wahab <matthew.wahab@arm.com> 1467 1468 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with 1469 ARM_EXT_RAS in relevant entries. 1470 14712016-06-03 Peter Bergner <bergner@vnet.ibm.com> 1472 1473 PR binutils/20196 1474 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable 1475 opcodes for E6500. 1476 14772016-06-03 H.J. Lu <hongjiu.lu@intel.com> 1478 1479 PR binutis/18386 1480 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. 1481 (indir_v_mode): New. 1482 Add comments for '&'. 1483 (reg_table): Replace "{T|}" with "{&|}" on call and jmp. 1484 (putop): Handle '&'. 1485 (intel_operand_size): Handle indir_v_mode. 1486 (OP_E_register): Likewise. 1487 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 1488 64-bit indirect call/jmp for AMD64. 1489 * i386-tbl.h: Regenerated 1490 14912016-06-02 Andrew Burgess <andrew.burgess@embecosm.com> 1492 1493 * arc-dis.c (struct arc_operand_iterator): New structure. 1494 (find_format_from_table): All the old content from find_format, 1495 with some minor adjustments, and parameter renaming. 1496 (find_format_long_instructions): New function. 1497 (find_format): Rewritten. 1498 (arc_insn_length): Add LSB parameter. 1499 (extract_operand_value): New function. 1500 (operand_iterator_next): New function. 1501 (print_insn_arc): Use new functions to find opcode, and iterator 1502 over operands. 1503 * arc-opc.c (insert_nps_3bit_dst_short): New function. 1504 (extract_nps_3bit_dst_short): New function. 1505 (insert_nps_3bit_src2_short): New function. 1506 (extract_nps_3bit_src2_short): New function. 1507 (insert_nps_bitop1_size): New function. 1508 (extract_nps_bitop1_size): New function. 1509 (insert_nps_bitop2_size): New function. 1510 (extract_nps_bitop2_size): New function. 1511 (insert_nps_bitop_mod4_msb): New function. 1512 (extract_nps_bitop_mod4_msb): New function. 1513 (insert_nps_bitop_mod4_lsb): New function. 1514 (extract_nps_bitop_mod4_lsb): New function. 1515 (insert_nps_bitop_dst_pos3_pos4): New function. 1516 (extract_nps_bitop_dst_pos3_pos4): New function. 1517 (insert_nps_bitop_ins_ext): New function. 1518 (extract_nps_bitop_ins_ext): New function. 1519 (arc_operands): Add new operands. 1520 (arc_long_opcodes): New global array. 1521 (arc_num_long_opcodes): New global. 1522 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. 1523 15242016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 1525 1526 * nds32-asm.h: Add extern "C". 1527 * sh-opc.h: Likewise. 1528 15292016-06-01 Graham Markall <graham.markall@embecosm.com> 1530 1531 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and 1532 0,b,limm to the rflt instruction. 1533 15342016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 1535 1536 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned 1537 constant. 1538 15392016-05-29 H.J. Lu <hongjiu.lu@intel.com> 1540 1541 PR gas/20145 1542 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, 1543 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, 1544 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, 1545 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, 1546 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. 1547 * i386-init.h: Regenerated. 1548 15492016-05-27 H.J. Lu <hongjiu.lu@intel.com> 1550 1551 PR gas/20145 1552 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove 1553 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from 1554 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. 1555 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and 1556 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from 1557 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, 1558 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. 1559 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, 1560 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, 1561 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, 1562 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX 1563 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable 1564 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and 1565 CpuRegMask for AVX512. 1566 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM 1567 and CpuRegMask. 1568 (set_bitfield_from_cpu_flag_init): New function. 1569 (set_bitfield): Remove const on f. Call 1570 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. 1571 * i386-opc.h (CpuRegMMX): New. 1572 (CpuRegXMM): Likewise. 1573 (CpuRegYMM): Likewise. 1574 (CpuRegZMM): Likewise. 1575 (CpuRegMask): Likewise. 1576 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm 1577 and cpuregmask. 1578 * i386-init.h: Regenerated. 1579 * i386-tbl.h: Likewise. 1580 15812016-05-27 H.J. Lu <hongjiu.lu@intel.com> 1582 1583 PR gas/20154 1584 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. 1585 (opcode_modifiers): Add AMD64 and Intel64. 1586 (main): Properly verify CpuMax. 1587 * i386-opc.h (CpuAMD64): Removed. 1588 (CpuIntel64): Likewise. 1589 (CpuMax): Set to CpuNo64. 1590 (i386_cpu_flags): Remove cpuamd64 and cpuintel64. 1591 (AMD64): New. 1592 (Intel64): Likewise. 1593 (i386_opcode_modifier): Add amd64 and intel64. 1594 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 1595 on call and jmp. 1596 * i386-init.h: Regenerated. 1597 * i386-tbl.h: Likewise. 1598 15992016-05-27 H.J. Lu <hongjiu.lu@intel.com> 1600 1601 PR gas/20154 1602 * i386-gen.c (main): Fail if CpuMax is incorrect. 1603 * i386-opc.h (CpuMax): Set to CpuIntel64. 1604 * i386-tbl.h: Regenerated. 1605 16062016-05-27 Nick Clifton <nickc@redhat.com> 1607 1608 PR target/20150 1609 * msp430-dis.c (msp430dis_read_two_bytes): New function. 1610 (msp430dis_opcode_unsigned): New function. 1611 (msp430dis_opcode_signed): New function. 1612 (msp430_singleoperand): Use the new opcode reading functions. 1613 Only disassenmble bytes if they were successfully read. 1614 (msp430_doubleoperand): Likewise. 1615 (msp430_branchinstr): Likewise. 1616 (msp430x_callx_instr): Likewise. 1617 (print_insn_msp430): Check that it is safe to read bytes before 1618 attempting disassembly. Use the new opcode reading functions. 1619 16202016-05-26 Peter Bergner <bergner@vnet.ibm.com> 1621 1622 * ppc-opc.c (CY): New define. Document it. 1623 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics. 1624 16252016-05-25 H.J. Lu <hongjiu.lu@intel.com> 1626 1627 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, 1628 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS 1629 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, 1630 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to 1631 CPU_ANY_AVX_FLAGS. 1632 * i386-init.h: Regenerated. 1633 16342016-05-25 H.J. Lu <hongjiu.lu@intel.com> 1635 1636 PR gas/20141 1637 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, 1638 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. 1639 * i386-init.h: Regenerated. 1640 16412016-05-25 H.J. Lu <hongjiu.lu@intel.com> 1642 1643 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to 1644 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. 1645 * i386-init.h: Regenerated. 1646 16472016-05-23 Claudiu Zissulescu <claziss@synopsys.com> 1648 1649 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type 1650 information. 1651 (print_insn_arc): Set insn_type information. 1652 * arc-opc.c (C_CC): Add F_CLASS_COND. 1653 * arc-tbl.h (bbit0, bbit1): Update subclass to COND. 1654 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. 1655 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. 1656 (breq, breq_s, brge, brhs, brlo, brlt): Likewise. 1657 (brne, brne_s, jeq_s, jne_s): Likewise. 1658 16592016-05-23 Claudiu Zissulescu <claziss@synopsys.com> 1660 1661 * arc-tbl.h (neg): New instruction variant. 1662 16632016-05-23 Cupertino Miranda <cmiranda@synopsys.com> 1664 1665 * arc-dis.c (find_format, find_format, get_auxreg) 1666 (print_insn_arc): Changed. 1667 * arc-ext.h (INSERT_XOP): Likewise. 1668 16692016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 1670 1671 * tic54x-dis.c (sprint_mmr): Adjust. 1672 * tic54x-opc.c: Likewise. 1673 16742016-05-19 Alan Modra <amodra@gmail.com> 1675 1676 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. 1677 16782016-05-19 Alan Modra <amodra@gmail.com> 1679 1680 * ppc-opc.c: Formatting. 1681 (NSISIGNOPT): Define. 1682 (powerpc_opcodes <subis>): Use NSISIGNOPT. 1683 16842016-05-18 Maciej W. Rozycki <macro@imgtec.com> 1685 1686 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, 1687 replacing references to `micromips_ase' throughout. 1688 (_print_insn_mips): Don't use file-level microMIPS annotation to 1689 determine the disassembly mode with the symbol table. 1690 16912016-05-13 Peter Bergner <bergner@vnet.ibm.com> 1692 1693 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. 1694 16952016-05-11 Andrew Bennett <andrew.bennett@imgtec.com> 1696 1697 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and 1698 mips64r6. 1699 * mips-opc.c (D34): New macro. 1700 (mips_builtin_opcodes): Define bposge32c for DSPr3. 1701 17022016-05-10 Alexander Fomin <alexander.fomin@intel.com> 1703 1704 * i386-dis.c (prefix_table): Add RDPID instruction. 1705 * i386-gen.c (cpu_flag_init): Add RDPID flag. 1706 (cpu_flags): Add RDPID bitfield. 1707 * i386-opc.h (enum): Add RDPID element. 1708 (i386_cpu_flags): Add RDPID field. 1709 * i386-opc.tbl: Add RDPID instruction. 1710 * i386-init.h: Regenerate. 1711 * i386-tbl.h: Regenerate. 1712 17132016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> 1714 1715 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get 1716 branch type of a symbol. 1717 (print_insn): Likewise. 1718 17192016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> 1720 1721 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M 1722 Mainline Security Extensions instructions. 1723 (thumb_opcodes): Add entries for narrow ARMv8-M Security 1724 Extensions instructions. 1725 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions 1726 instructions. 1727 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions 1728 special registers. 1729 17302016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com> 1731 1732 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. 1733 17342016-05-03 Claudiu Zissulescu <claziss@synopsys.com> 1735 1736 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. 1737 (arcExtMap_genOpcode): Likewise. 1738 * arc-opc.c (arg_32bit_rc): Define new variable. 1739 (arg_32bit_u6): Likewise. 1740 (arg_32bit_limm): Likewise. 1741 17422016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com> 1743 1744 * aarch64-gen.c (VERIFIER): Define. 1745 * aarch64-opc.c (VERIFIER): Define. 1746 (verify_ldpsw): Use static linkage. 1747 * aarch64-opc.h (verify_ldpsw): Remove. 1748 * aarch64-tbl.h: Use VERIFIER for verifiers. 1749 17502016-04-28 Nick Clifton <nickc@redhat.com> 1751 1752 PR target/19722 1753 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. 1754 * aarch64-opc.c (verify_ldpsw): New function. 1755 * aarch64-opc.h (verify_ldpsw): New prototype. 1756 * aarch64-tbl.h: Add initialiser for verifier field. 1757 (LDPSW): Set verifier to verify_ldpsw. 1758 17592016-04-23 H.J. Lu <hongjiu.lu@intel.com> 1760 1761 PR binutils/19983 1762 PR binutils/19984 1763 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is 1764 smaller than address size. 1765 17662016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 1767 1768 * alpha-dis.c: Regenerate. 1769 * crx-dis.c: Likewise. 1770 * disassemble.c: Likewise. 1771 * epiphany-opc.c: Likewise. 1772 * fr30-opc.c: Likewise. 1773 * frv-opc.c: Likewise. 1774 * ip2k-opc.c: Likewise. 1775 * iq2000-opc.c: Likewise. 1776 * lm32-opc.c: Likewise. 1777 * lm32-opinst.c: Likewise. 1778 * m32c-opc.c: Likewise. 1779 * m32r-opc.c: Likewise. 1780 * m32r-opinst.c: Likewise. 1781 * mep-opc.c: Likewise. 1782 * mt-opc.c: Likewise. 1783 * or1k-opc.c: Likewise. 1784 * or1k-opinst.c: Likewise. 1785 * tic80-opc.c: Likewise. 1786 * xc16x-opc.c: Likewise. 1787 * xstormy16-opc.c: Likewise. 1788 17892016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> 1790 1791 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, 1792 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp, 1793 calcsd, and calcxd instructions. 1794 * arc-opc.c (insert_nps_bitop_size): Delete. 1795 (extract_nps_bitop_size): Delete. 1796 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. 1797 (extract_nps_qcmp_m3): Define. 1798 (extract_nps_qcmp_m2): Define. 1799 (extract_nps_qcmp_m1): Define. 1800 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. 1801 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL 1802 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, 1803 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, 1804 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and 1805 NPS_QCMP_M3. 1806 18072016-04-19 Andrew Burgess <andrew.burgess@embecosm.com> 1808 1809 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions. 1810 18112016-04-15 H.J. Lu <hongjiu.lu@intel.com> 1812 1813 * Makefile.in: Regenerated with automake 1.11.6. 1814 * aclocal.m4: Likewise. 1815 18162016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> 1817 1818 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst 1819 instructions. 1820 * arc-opc.c (insert_nps_cmem_uimm16): New function. 1821 (extract_nps_cmem_uimm16): New function. 1822 (arc_operands): Add NPS_XLDST_UIMM16 operand. 1823 18242016-04-14 Andrew Burgess <andrew.burgess@embecosm.com> 1825 1826 * arc-dis.c (arc_insn_length): New function. 1827 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned. 1828 (find_format): Change insnLen parameter to unsigned. 1829 18302016-04-13 Nick Clifton <nickc@redhat.com> 1831 1832 PR target/19937 1833 * v850-opc.c (v850_opcodes): Correct masks for long versions of 1834 the LD.B and LD.BU instructions. 1835 18362016-04-12 Claudiu Zissulescu <claziss@synopsys.com> 1837 1838 * arc-dis.c (find_format): Check for extension flags. 1839 (print_flags): New function. 1840 (print_insn_arc): Update for .extCondCode, .extCoreRegister and 1841 .extAuxRegister. 1842 * arc-ext.c (arcExtMap_coreRegName): Use 1843 LAST_EXTENSION_CORE_REGISTER. 1844 (arcExtMap_coreReadWrite): Likewise. 1845 (dump_ARC_extmap): Update printing. 1846 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. 1847 (arc_aux_regs): Add cpu field. 1848 * arc-regs.h: Add cpu field, lower case name aux registers. 1849 18502016-04-12 Claudiu Zissulescu <claziss@synopsys.com> 1851 1852 * arc-tbl.h: Add rtsc, sleep with no arguments. 1853 18542016-04-12 Claudiu Zissulescu <claziss@synopsys.com> 1855 1856 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): 1857 Initialize. 1858 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) 1859 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) 1860 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) 1861 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) 1862 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) 1863 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) 1864 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) 1865 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) 1866 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. 1867 (arc_opcode arc_opcodes): Null terminate the array. 1868 (arc_num_opcodes): Remove. 1869 * arc-ext.h (INSERT_XOP): Define. 1870 (extInstruction_t): Likewise. 1871 (arcExtMap_instName): Delete. 1872 (arcExtMap_insn): New function. 1873 (arcExtMap_genOpcode): Likewise. 1874 * arc-ext.c (ExtInstruction): Remove. 1875 (create_map): Zero initialize instruction fields. 1876 (arcExtMap_instName): Remove. 1877 (arcExtMap_insn): New function. 1878 (dump_ARC_extmap): More info while debuging. 1879 (arcExtMap_genOpcode): New function. 1880 * arc-dis.c (find_format): New function. 1881 (print_insn_arc): Use find_format. 1882 (arc_get_disassembler): Enable dump_ARC_extmap only when 1883 debugging. 1884 18852016-04-11 Maciej W. Rozycki <macro@imgtec.com> 1886 1887 * mips-dis.c (print_mips16_insn_arg): Mask unused extended 1888 instruction bits out. 1889 18902016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> 1891 1892 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. 1893 * arc-opc.c (arc_flag_operands): Add new flags. 1894 (arc_flag_classes): Add new classes. 1895 18962016-04-07 Andrew Burgess <andrew.burgess@embecosm.com> 1897 1898 * arc-opc.c (arc_opcodes): Extend comment to discus table layout. 1899 19002016-04-05 Andrew Burgess <andrew.burgess@embecosm.com> 1901 1902 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, 1903 encode1, rflt, crc16, and crc32 instructions. 1904 * arc-opc.c (arc_flag_operands): Add F_NPS_R. 1905 (arc_flag_classes): Add C_NPS_R. 1906 (insert_nps_bitop_size_2b): New function. 1907 (extract_nps_bitop_size_2b): Likewise. 1908 (insert_nps_bitop_uimm8): Likewise. 1909 (extract_nps_bitop_uimm8): Likewise. 1910 (arc_operands): Add new operand entries. 1911 19122016-04-05 Claudiu Zissulescu <claziss@synopsys.com> 1913 1914 * arc-regs.h: Add a new subclass field. Add double assist 1915 accumulator register values. 1916 * arc-tbl.h: Use DPA subclass to mark the double assist 1917 instructions. Use DPX/SPX subclas to mark the FPX instructions. 1918 * arc-opc.c (RSP): Define instead of SP. 1919 (arc_aux_regs): Add the subclass field. 1920 19212016-04-05 Jiong Wang <jiong.wang@arm.com> 1922 1923 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar). 1924 19252016-03-31 Andrew Burgess <andrew.burgess@embecosm.com> 1926 1927 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and 1928 NPS_R_SRC1. 1929 19302016-03-30 Andrew Burgess <andrew.burgess@embecosm.com> 1931 1932 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace 1933 issues. No functional changes. 1934 19352016-03-30 Claudiu Zissulescu <claziss@synopsys.com> 1936 1937 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0) 1938 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1) 1939 (RTT): Remove duplicate. 1940 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*) 1941 (PCT_CONFIG*): Remove. 1942 (D1L, D1H, D2H, D2L): Define. 1943 19442016-03-29 Claudiu Zissulescu <claziss@synopsys.com> 1945 1946 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo. 1947 19482016-03-29 Claudiu Zissulescu <claziss@synopsys.com> 1949 1950 * arc-tbl.h (invld07): Remove. 1951 * arc-ext-tbl.h: New file. 1952 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. 1953 * arc-opc.c (arc_opcodes): Add ext-tbl include. 1954 19552016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com> 1956 1957 Fix -Wstack-usage warnings. 1958 * aarch64-dis.c (print_operands): Substitute size. 1959 * aarch64-opc.c (print_register_offset_address): Substitute tblen. 1960 19612016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com> 1962 1963 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order 1964 to get a proper diagnostic when an invalid ASR register is used. 1965 19662016-03-22 Nick Clifton <nickc@redhat.com> 1967 1968 * configure: Regenerate. 1969 19702016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 1971 1972 * arc-nps400-tbl.h: New file. 1973 * arc-opc.c: Add top level comment. 1974 (insert_nps_3bit_dst): New function. 1975 (extract_nps_3bit_dst): New function. 1976 (insert_nps_3bit_src2): New function. 1977 (extract_nps_3bit_src2): New function. 1978 (insert_nps_bitop_size): New function. 1979 (extract_nps_bitop_size): New function. 1980 (arc_flag_operands): Add nps400 entries. 1981 (arc_flag_classes): Add nps400 entries. 1982 (arc_operands): Add nps400 entries. 1983 (arc_opcodes): Add nps400 include. 1984 19852016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 1986 1987 * arc-opc.c (arc_flag_classes): Convert all flag classes to use 1988 the new class enum values. 1989 19902016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 1991 1992 * arc-dis.c (print_insn_arc): Handle nps400. 1993 19942016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> 1995 1996 * arc-opc.c (BASE): Delete. 1997 19982016-03-18 Nick Clifton <nickc@redhat.com> 1999 2000 PR target/19721 2001 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand 2002 of MOV insn that aliases an ORR insn. 2003 20042016-03-16 Jiong Wang <jiong.wang@arm.com> 2005 2006 * arm-dis.c (neon_opcodes): Support new FP16 instructions. 2007 20082016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> 2009 2010 * mcore-opc.h: Add const qualifiers. 2011 * microblaze-opc.h (struct op_code_struct): Likewise. 2012 * sh-opc.h: Likewise. 2013 * tic4x-dis.c (tic4x_print_indirect): Likewise. 2014 (tic4x_print_op): Likewise. 2015 20162016-03-02 Alan Modra <amodra@gmail.com> 2017 2018 * or1k-desc.h: Regenerate. 2019 * fr30-ibld.c: Regenerate. 2020 * rl78-decode.c: Regenerate. 2021 20222016-03-01 Nick Clifton <nickc@redhat.com> 2023 2024 PR target/19747 2025 * rl78-dis.c (print_insn_rl78_common): Fix typo. 2026 20272016-02-24 Renlin Li <renlin.li@arm.com> 2028 2029 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. 2030 (print_insn_coprocessor): Support fp16 instructions. 2031 20322016-02-24 Renlin Li <renlin.li@arm.com> 2033 2034 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm, 2035 vminnm, vrint(mpna). 2036 20372016-02-24 Renlin Li <renlin.li@arm.com> 2038 2039 * arm-dis.c (print_insn_coprocessor): Check co-processor number for 2040 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. 2041 20422016-02-15 H.J. Lu <hongjiu.lu@intel.com> 2043 2044 * i386-dis.c (print_insn): Parenthesize expression to prevent 2045 truncated addresses. 2046 (OP_J): Likewise. 2047 20482016-02-10 Claudiu Zissulescu <claziss@synopsys.com> 2049 Janek van Oirschot <jvanoirs@synopsys.com> 2050 2051 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New 2052 variable. 2053 20542016-02-04 Nick Clifton <nickc@redhat.com> 2055 2056 PR target/19561 2057 * msp430-dis.c (print_insn_msp430): Add a special case for 2058 decoding an RRC instruction with the ZC bit set in the extension 2059 word. 2060 20612016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> 2062 2063 * cgen-ibld.in (insert_normal): Rework calculation of shift. 2064 * epiphany-ibld.c: Regenerate. 2065 * fr30-ibld.c: Regenerate. 2066 * frv-ibld.c: Regenerate. 2067 * ip2k-ibld.c: Regenerate. 2068 * iq2000-ibld.c: Regenerate. 2069 * lm32-ibld.c: Regenerate. 2070 * m32c-ibld.c: Regenerate. 2071 * m32r-ibld.c: Regenerate. 2072 * mep-ibld.c: Regenerate. 2073 * mt-ibld.c: Regenerate. 2074 * or1k-ibld.c: Regenerate. 2075 * xc16x-ibld.c: Regenerate. 2076 * xstormy16-ibld.c: Regenerate. 2077 20782016-02-02 Andrew Burgess <andrew.burgess@embecosm.com> 2079 2080 * epiphany-dis.c: Regenerated from latest cpu files. 2081 20822016-02-01 Michael McConville <mmcco@mykolab.com> 2083 2084 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask 2085 test bit. 2086 20872016-01-25 Renlin Li <renlin.li@arm.com> 2088 2089 * arm-dis.c (mapping_symbol_for_insn): New function. 2090 (find_ifthen_state): Call mapping_symbol_for_insn(). 2091 20922016-01-20 Matthew Wahab <matthew.wahab@arm.com> 2093 2094 * aarch64-opc.c (operand_general_constraint_met_p): Check validity 2095 of MSR UAO immediate operand. 2096 20972016-01-18 Maciej W. Rozycki <macro@imgtec.com> 2098 2099 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS 2100 instruction support. 2101 21022016-01-17 Alan Modra <amodra@gmail.com> 2103 2104 * configure: Regenerate. 2105 21062016-01-14 Nick Clifton <nickc@redhat.com> 2107 2108 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw 2109 instructions that can support stack pointer operations. 2110 * rl78-decode.c: Regenerate. 2111 * rl78-dis.c: Fix display of stack pointer in MOVW based 2112 instructions. 2113 21142016-01-14 Matthew Wahab <matthew.wahab@arm.com> 2115 2116 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals 2117 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, 2118 erxtatus_el1 and erxaddr_el1. 2119 21202016-01-12 Matthew Wahab <matthew.wahab@arm.com> 2121 2122 * arm-dis.c (arm_opcodes): Add "esb". 2123 (thumb_opcodes): Likewise. 2124 21252016-01-11 Peter Bergner <bergner@vnet.ibm.com> 2126 2127 * ppc-opc.c <xscmpnedp>: Delete. 2128 <xvcmpnedp>: Likewise. 2129 <xvcmpnedp.>: Likewise. 2130 <xvcmpnesp>: Likewise. 2131 <xvcmpnesp.>: Likewise. 2132 21332016-01-08 Andreas Schwab <schwab@linux-m68k.org> 2134 2135 PR gas/13050 2136 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in 2137 addition to ISA_A. 2138 21392016-01-01 Alan Modra <amodra@gmail.com> 2140 2141 Update year range in copyright notice of all files. 2142 2143For older changes see ChangeLog-2015 2144 2145Copyright (C) 2016 Free Software Foundation, Inc. 2146 2147Copying and distribution of this file, with or without modification, 2148are permitted in any medium without royalty provided the copyright 2149notice and this notice are preserved. 2150 2151Local Variables: 2152mode: change-log 2153left-margin: 8 2154fill-column: 74 2155version-control: never 2156End: 2157