1/* tc-cr16.c -- Assembler code for the CR16 CPU core. 2 Copyright (C) 2007-2017 Free Software Foundation, Inc. 3 4 Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com> 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#include "as.h" 24#include "safe-ctype.h" 25#include "dwarf2dbg.h" 26#include "opcode/cr16.h" 27#include "elf/cr16.h" 28 29 30/* Word is considered here as a 16-bit unsigned short int. */ 31#define WORD_SHIFT 16 32 33/* Register is 2-byte size. */ 34#define REG_SIZE 2 35 36/* Maximum size of a single instruction (in words). */ 37#define INSN_MAX_SIZE 3 38 39/* Maximum bits which may be set in a `mask16' operand. */ 40#define MAX_REGS_IN_MASK16 8 41 42/* Assign a number NUM, shifted by SHIFT bytes, into a location 43 pointed by index BYTE of array 'output_opcode'. */ 44#define CR16_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT) 45 46/* Operand errors. */ 47typedef enum 48 { 49 OP_LEGAL = 0, /* Legal operand. */ 50 OP_OUT_OF_RANGE, /* Operand not within permitted range. */ 51 OP_NOT_EVEN /* Operand is Odd number, should be even. */ 52 } 53op_err; 54 55/* Opcode mnemonics hash table. */ 56static struct hash_control *cr16_inst_hash; 57/* CR16 registers hash table. */ 58static struct hash_control *reg_hash; 59/* CR16 register pair hash table. */ 60static struct hash_control *regp_hash; 61/* CR16 processor registers hash table. */ 62static struct hash_control *preg_hash; 63/* CR16 processor registers 32 bit hash table. */ 64static struct hash_control *pregp_hash; 65/* Current instruction we're assembling. */ 66const inst *instruction; 67 68 69static int code_label = 0; 70 71/* Global variables. */ 72 73/* Array to hold an instruction encoding. */ 74long output_opcode[2]; 75 76/* Nonzero means a relocatable symbol. */ 77int relocatable; 78 79/* A copy of the original instruction (used in error messages). */ 80char ins_parse[MAX_INST_LEN]; 81 82/* The current processed argument number. */ 83int cur_arg_num; 84 85/* Generic assembler global variables which must be defined by all targets. */ 86 87/* Characters which always start a comment. */ 88const char comment_chars[] = "#"; 89 90/* Characters which start a comment at the beginning of a line. */ 91const char line_comment_chars[] = "#"; 92 93/* This array holds machine specific line separator characters. */ 94const char line_separator_chars[] = ";"; 95 96/* Chars that can be used to separate mant from exp in floating point nums. */ 97const char EXP_CHARS[] = "eE"; 98 99/* Chars that mean this number is a floating point constant as in 0f12.456 */ 100const char FLT_CHARS[] = "f'"; 101 102#ifdef OBJ_ELF 103/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 104symbolS * GOT_symbol; 105#endif 106 107/* Target-specific multicharacter options, not const-declared at usage. */ 108const char *md_shortopts = ""; 109struct option md_longopts[] = 110{ 111 {NULL, no_argument, NULL, 0} 112}; 113size_t md_longopts_size = sizeof (md_longopts); 114 115static void 116l_cons (int nbytes) 117{ 118 int c; 119 expressionS exp; 120 121#ifdef md_flush_pending_output 122 md_flush_pending_output (); 123#endif 124 125 if (is_it_end_of_statement ()) 126 { 127 demand_empty_rest_of_line (); 128 return; 129 } 130 131#ifdef TC_ADDRESS_BYTES 132 if (nbytes == 0) 133 nbytes = TC_ADDRESS_BYTES (); 134#endif 135 136#ifdef md_cons_align 137 md_cons_align (nbytes); 138#endif 139 140 c = 0; 141 do 142 { 143 unsigned int bits_available = BITS_PER_CHAR * nbytes; 144 char *hold = input_line_pointer; 145 146 expression (&exp); 147 148 if (*input_line_pointer == ':') 149 { 150 /* Bitfields. */ 151 long value = 0; 152 153 for (;;) 154 { 155 unsigned long width; 156 157 if (*input_line_pointer != ':') 158 { 159 input_line_pointer = hold; 160 break; 161 } 162 if (exp.X_op == O_absent) 163 { 164 as_warn (_("using a bit field width of zero")); 165 exp.X_add_number = 0; 166 exp.X_op = O_constant; 167 } 168 169 if (exp.X_op != O_constant) 170 { 171 *input_line_pointer = '\0'; 172 as_bad (_("field width \"%s\" too complex for a bitfield"), hold); 173 *input_line_pointer = ':'; 174 demand_empty_rest_of_line (); 175 return; 176 } 177 178 if ((width = exp.X_add_number) > 179 (unsigned int)(BITS_PER_CHAR * nbytes)) 180 { 181 as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes)); 182 width = BITS_PER_CHAR * nbytes; 183 } /* Too big. */ 184 185 186 if (width > bits_available) 187 { 188 /* FIXME-SOMEDAY: backing up and reparsing is wasteful. */ 189 input_line_pointer = hold; 190 exp.X_add_number = value; 191 break; 192 } 193 194 /* Skip ':'. */ 195 hold = ++input_line_pointer; 196 197 expression (&exp); 198 if (exp.X_op != O_constant) 199 { 200 char cache = *input_line_pointer; 201 202 *input_line_pointer = '\0'; 203 as_bad (_("field value \"%s\" too complex for a bitfield"), hold); 204 *input_line_pointer = cache; 205 demand_empty_rest_of_line (); 206 return; 207 } 208 209 value |= ((~(-(1 << width)) & exp.X_add_number) 210 << ((BITS_PER_CHAR * nbytes) - bits_available)); 211 212 if ((bits_available -= width) == 0 213 || is_it_end_of_statement () 214 || *input_line_pointer != ',') 215 break; 216 217 hold = ++input_line_pointer; 218 expression (&exp); 219 } 220 221 exp.X_add_number = value; 222 exp.X_op = O_constant; 223 exp.X_unsigned = 1; 224 } 225 226 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c')) 227 code_label = 1; 228 emit_expr (&exp, (unsigned int) nbytes); 229 ++c; 230 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c')) 231 { 232 input_line_pointer +=3; 233 break; 234 } 235 } 236 while ((*input_line_pointer++ == ',')); 237 238 /* Put terminator back into stream. */ 239 input_line_pointer--; 240 241 demand_empty_rest_of_line (); 242} 243 244/* This table describes all the machine specific pseudo-ops 245 the assembler has to support. The fields are: 246 *** Pseudo-op name without dot. 247 *** Function to call to execute this pseudo-op. 248 *** Integer arg to pass to the function. */ 249 250const pseudo_typeS md_pseudo_table[] = 251{ 252 /* In CR16 machine, align is in bytes (not a ptwo boundary). */ 253 {"align", s_align_bytes, 0}, 254 {"long", l_cons, 4 }, 255 {"4byte", l_cons, 4 }, 256 {0, 0, 0} 257}; 258 259/* CR16 relaxation table. */ 260const relax_typeS md_relax_table[] = 261{ 262 /* bCC */ 263 {0x7f, -0x80, 2, 1}, /* 8 */ 264 {0xfffe, -0x10000, 4, 2}, /* 16 */ 265 {0xfffffe, -0x1000000, 6, 0}, /* 24 */ 266}; 267 268/* Return the bit size for a given operand. */ 269 270static int 271get_opbits (operand_type op) 272{ 273 if (op < MAX_OPRD) 274 return cr16_optab[op].bit_size; 275 276 return 0; 277} 278 279/* Return the argument type of a given operand. */ 280 281static argtype 282get_optype (operand_type op) 283{ 284 if (op < MAX_OPRD) 285 return cr16_optab[op].arg_type; 286 else 287 return nullargs; 288} 289 290/* Return the flags of a given operand. */ 291 292static int 293get_opflags (operand_type op) 294{ 295 if (op < MAX_OPRD) 296 return cr16_optab[op].flags; 297 298 return 0; 299} 300 301/* Get the cc code. */ 302 303static int 304get_cc (char *cc_name) 305{ 306 unsigned int i; 307 308 for (i = 0; i < cr16_num_cc; i++) 309 if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0) 310 return i; 311 312 return -1; 313} 314 315/* Get the core processor register 'reg_name'. */ 316 317static reg 318get_register (char *reg_name) 319{ 320 const reg_entry *rreg; 321 322 rreg = (const reg_entry *) hash_find (reg_hash, reg_name); 323 324 if (rreg != NULL) 325 return rreg->value.reg_val; 326 327 return nullregister; 328} 329/* Get the core processor register-pair 'reg_name'. */ 330 331static reg 332get_register_pair (char *reg_name) 333{ 334 const reg_entry *rreg; 335 char tmp_rp[16]="\0"; 336 337 /* Add '(' and ')' to the reg pair, if its not present. */ 338 if (reg_name[0] != '(') 339 { 340 tmp_rp[0] = '('; 341 strcat (tmp_rp, reg_name); 342 strcat (tmp_rp,")"); 343 rreg = (const reg_entry *) hash_find (regp_hash, tmp_rp); 344 } 345 else 346 rreg = (const reg_entry *) hash_find (regp_hash, reg_name); 347 348 if (rreg != NULL) 349 return rreg->value.reg_val; 350 351 return nullregister; 352} 353 354/* Get the index register 'reg_name'. */ 355 356static reg 357get_index_register (char *reg_name) 358{ 359 const reg_entry *rreg; 360 361 rreg = (const reg_entry *) hash_find (reg_hash, reg_name); 362 363 if ((rreg != NULL) 364 && ((rreg->value.reg_val == 12) || (rreg->value.reg_val == 13))) 365 return rreg->value.reg_val; 366 367 return nullregister; 368} 369/* Get the core processor index register-pair 'reg_name'. */ 370 371static reg 372get_index_register_pair (char *reg_name) 373{ 374 const reg_entry *rreg; 375 376 rreg = (const reg_entry *) hash_find (regp_hash, reg_name); 377 378 if (rreg != NULL) 379 { 380 if ((rreg->value.reg_val != 1) || (rreg->value.reg_val != 7) 381 || (rreg->value.reg_val != 9) || (rreg->value.reg_val > 10)) 382 return rreg->value.reg_val; 383 384 as_bad (_("Unknown register pair - index relative mode: `%d'"), rreg->value.reg_val); 385 } 386 387 return nullregister; 388} 389 390/* Get the processor register 'preg_name'. */ 391 392static preg 393get_pregister (char *preg_name) 394{ 395 const reg_entry *prreg; 396 397 prreg = (const reg_entry *) hash_find (preg_hash, preg_name); 398 399 if (prreg != NULL) 400 return prreg->value.preg_val; 401 402 return nullpregister; 403} 404 405/* Get the processor register 'preg_name 32 bit'. */ 406 407static preg 408get_pregisterp (char *preg_name) 409{ 410 const reg_entry *prreg; 411 412 prreg = (const reg_entry *) hash_find (pregp_hash, preg_name); 413 414 if (prreg != NULL) 415 return prreg->value.preg_val; 416 417 return nullpregister; 418} 419 420 421/* Round up a section size to the appropriate boundary. */ 422 423valueT 424md_section_align (segT seg, valueT val) 425{ 426 /* Round .text section to a multiple of 2. */ 427 if (seg == text_section) 428 return (val + 1) & ~1; 429 return val; 430} 431 432/* Parse an operand that is machine-specific (remove '*'). */ 433 434void 435md_operand (expressionS * exp) 436{ 437 char c = *input_line_pointer; 438 439 switch (c) 440 { 441 case '*': 442 input_line_pointer++; 443 expression (exp); 444 break; 445 default: 446 break; 447 } 448} 449 450/* Reset global variables before parsing a new instruction. */ 451 452static void 453reset_vars (char *op) 454{ 455 cur_arg_num = relocatable = 0; 456 memset (& output_opcode, '\0', sizeof (output_opcode)); 457 458 /* Save a copy of the original OP (used in error messages). */ 459 strncpy (ins_parse, op, sizeof ins_parse - 1); 460 ins_parse [sizeof ins_parse - 1] = 0; 461} 462 463/* This macro decides whether a particular reloc is an entry in a 464 switch table. It is used when relaxing, because the linker needs 465 to know about all such entries so that it can adjust them if 466 necessary. */ 467 468#define SWITCH_TABLE(fix) \ 469 ( (fix)->fx_addsy != NULL \ 470 && (fix)->fx_subsy != NULL \ 471 && S_GET_SEGMENT ((fix)->fx_addsy) == \ 472 S_GET_SEGMENT ((fix)->fx_subsy) \ 473 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \ 474 && ( (fix)->fx_r_type == BFD_RELOC_CR16_NUM8 \ 475 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16 \ 476 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32 \ 477 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a)) 478 479/* See whether we need to force a relocation into the output file. 480 This is used to force out switch and PC relative relocations when 481 relaxing. */ 482 483int 484cr16_force_relocation (fixS *fix) 485{ 486 if (generic_force_reloc (fix) || SWITCH_TABLE (fix)) 487 return 1; 488 489 return 0; 490} 491 492/* Record a fixup for a cons expression. */ 493 494void 495cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp, 496 bfd_reloc_code_real_type rtype) 497{ 498 switch (len) 499 { 500 default: rtype = BFD_RELOC_NONE; break; 501 case 1: rtype = BFD_RELOC_CR16_NUM8 ; break; 502 case 2: rtype = BFD_RELOC_CR16_NUM16; break; 503 case 4: 504 if (code_label) 505 { 506 rtype = BFD_RELOC_CR16_NUM32a; 507 code_label = 0; 508 } 509 else 510 rtype = BFD_RELOC_CR16_NUM32; 511 break; 512 } 513 514 fix_new_exp (frag, offset, len, exp, 0, rtype); 515} 516 517/* Generate a relocation entry for a fixup. */ 518 519arelent * 520tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP) 521{ 522 arelent * reloc; 523 524 /* If symbols are local and resolved, then no relocation needed. */ 525 if ( ((fixP->fx_addsy) 526 && (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section)) 527 || ((fixP->fx_subsy) 528 && (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section))) 529 return NULL; 530 531 reloc = XNEW (arelent); 532 reloc->sym_ptr_ptr = XNEW (asymbol *); 533 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 534 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; 535 reloc->addend = fixP->fx_offset; 536 537 if (fixP->fx_subsy != NULL) 538 { 539 if (SWITCH_TABLE (fixP)) 540 { 541 /* Keep the current difference in the addend. */ 542 reloc->addend = (S_GET_VALUE (fixP->fx_addsy) 543 - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset); 544 545 switch (fixP->fx_r_type) 546 { 547 case BFD_RELOC_CR16_NUM8: 548 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH8; 549 break; 550 case BFD_RELOC_CR16_NUM16: 551 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH16; 552 break; 553 case BFD_RELOC_CR16_NUM32: 554 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH32; 555 break; 556 case BFD_RELOC_CR16_NUM32a: 557 fixP->fx_r_type = BFD_RELOC_CR16_NUM32a; 558 break; 559 default: 560 abort (); 561 break; 562 } 563 } 564 else 565 { 566 /* We only resolve difference expressions in the same section. */ 567 as_bad_where (fixP->fx_file, fixP->fx_line, 568 _("can't resolve `%s' {%s section} - `%s' {%s section}"), 569 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0", 570 segment_name (fixP->fx_addsy 571 ? S_GET_SEGMENT (fixP->fx_addsy) 572 : absolute_section), 573 S_GET_NAME (fixP->fx_subsy), 574 segment_name (S_GET_SEGMENT (fixP->fx_addsy))); 575 } 576 } 577#ifdef OBJ_ELF 578 if ((fixP->fx_r_type == BFD_RELOC_CR16_GOT_REGREL20) 579 && GOT_symbol 580 && fixP->fx_addsy == GOT_symbol) 581 { 582 reloc->addend = fixP->fx_offset = reloc->address; 583 } 584 else if ((fixP->fx_r_type == BFD_RELOC_CR16_GOTC_REGREL20) 585 && GOT_symbol 586 && fixP->fx_addsy == GOT_symbol) 587 { 588 reloc->addend = fixP->fx_offset = reloc->address; 589 } 590#endif 591 592 gas_assert ((int) fixP->fx_r_type > 0); 593 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 594 595 if (reloc->howto == NULL) 596 { 597 as_bad_where (fixP->fx_file, fixP->fx_line, 598 _("internal error: reloc %d (`%s') not supported by object file format"), 599 fixP->fx_r_type, 600 bfd_get_reloc_code_name (fixP->fx_r_type)); 601 return NULL; 602 } 603 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); 604 605 return reloc; 606} 607 608/* Prepare machine-dependent frags for relaxation. */ 609 610int 611md_estimate_size_before_relax (fragS *fragp, asection *seg) 612{ 613 /* If symbol is undefined or located in a different section, 614 select the largest supported relocation. */ 615 relax_substateT subtype; 616 relax_substateT rlx_state[] = {0, 2}; 617 618 for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2) 619 { 620 if (fragp->fr_subtype == rlx_state[subtype] 621 && (!S_IS_DEFINED (fragp->fr_symbol) 622 || seg != S_GET_SEGMENT (fragp->fr_symbol))) 623 { 624 fragp->fr_subtype = rlx_state[subtype + 1]; 625 break; 626 } 627 } 628 629 if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table)) 630 abort (); 631 632 return md_relax_table[fragp->fr_subtype].rlx_length; 633} 634 635void 636md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP) 637{ 638 /* 'opcode' points to the start of the instruction, whether 639 we need to change the instruction's fixed encoding. */ 640 char *opcode = fragP->fr_literal + fragP->fr_fix; 641 bfd_reloc_code_real_type reloc; 642 643 subseg_change (sec, 0); 644 645 switch (fragP->fr_subtype) 646 { 647 case 0: 648 reloc = BFD_RELOC_CR16_DISP8; 649 break; 650 case 1: 651 /* If the subtype is not changed due to :m operand qualifier, 652 then no need to update the opcode value. */ 653 if ((int)opcode[1] != 0x18) 654 { 655 opcode[0] = (opcode[0] & 0xf0); 656 opcode[1] = 0x18; 657 } 658 reloc = BFD_RELOC_CR16_DISP16; 659 break; 660 case 2: 661 /* If the subtype is not changed due to :l operand qualifier, 662 then no need to update the opcode value. */ 663 if ((int)opcode[1] != 0) 664 { 665 opcode[2] = opcode[0]; 666 opcode[0] = opcode[1]; 667 opcode[1] = 0x0; 668 } 669 reloc = BFD_RELOC_CR16_DISP24; 670 break; 671 default: 672 abort(); 673 } 674 675 fix_new (fragP, fragP->fr_fix, 676 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)), 677 fragP->fr_symbol, fragP->fr_offset, 1, reloc); 678 fragP->fr_var = 0; 679 fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length; 680} 681 682symbolS * 683md_undefined_symbol (char *name) 684{ 685 if (*name == '_' && *(name + 1) == 'G' 686 && strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0) 687 { 688 if (!GOT_symbol) 689 { 690 if (symbol_find (name)) 691 as_bad (_("GOT already in symbol table")); 692 GOT_symbol = symbol_new (name, undefined_section, 693 (valueT) 0, &zero_address_frag); 694 } 695 return GOT_symbol; 696 } 697 return 0; 698} 699 700/* Process machine-dependent command line options. Called once for 701 each option on the command line that the machine-independent part of 702 GAS does not understand. */ 703 704int 705md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) 706{ 707 return 0; 708} 709 710/* Machine-dependent usage-output. */ 711 712void 713md_show_usage (FILE *stream ATTRIBUTE_UNUSED) 714{ 715 return; 716} 717 718const char * 719md_atof (int type, char *litP, int *sizeP) 720{ 721 return ieee_md_atof (type, litP, sizeP, target_big_endian); 722} 723 724/* Apply a fixS (fixup of an instruction or data that we didn't have 725 enough info to complete immediately) to the data in a frag. 726 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable 727 relaxation of debug sections, this function is called only when 728 fixuping relocations of debug sections. */ 729 730void 731md_apply_fix (fixS *fixP, valueT *valP, segT seg) 732{ 733 valueT val = * valP; 734 735 if (fixP->fx_addsy == NULL 736 && fixP->fx_pcrel == 0) 737 fixP->fx_done = 1; 738 else if (fixP->fx_pcrel == 1 739 && fixP->fx_addsy != NULL 740 && S_GET_SEGMENT (fixP->fx_addsy) == seg) 741 fixP->fx_done = 1; 742 else 743 fixP->fx_done = 0; 744 745 if (fixP->fx_addsy != NULL && !fixP->fx_pcrel) 746 { 747 val = fixP->fx_offset; 748 fixP->fx_done = 1; 749 } 750 751 if (fixP->fx_done) 752 { 753 char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; 754 755 fixP->fx_offset = 0; 756 757 switch (fixP->fx_r_type) 758 { 759 case BFD_RELOC_CR16_NUM8: 760 bfd_put_8 (stdoutput, (unsigned char) val, buf); 761 break; 762 case BFD_RELOC_CR16_NUM16: 763 bfd_put_16 (stdoutput, val, buf); 764 break; 765 case BFD_RELOC_CR16_NUM32: 766 bfd_put_32 (stdoutput, val, buf); 767 break; 768 case BFD_RELOC_CR16_NUM32a: 769 bfd_put_32 (stdoutput, val, buf); 770 break; 771 default: 772 /* We shouldn't ever get here because linkrelax is nonzero. */ 773 abort (); 774 break; 775 } 776 fixP->fx_done = 0; 777 } 778 else 779 fixP->fx_offset = * valP; 780} 781 782/* The location from which a PC relative jump should be calculated, 783 given a PC relative reloc. */ 784 785long 786md_pcrel_from (fixS *fixp) 787{ 788 return fixp->fx_frag->fr_address + fixp->fx_where; 789} 790 791static void 792initialise_reg_hash_table (struct hash_control ** hash_table, 793 const reg_entry * register_table, 794 const unsigned int num_entries) 795{ 796 const reg_entry * rreg; 797 const char *hashret; 798 799 if ((* hash_table = hash_new ()) == NULL) 800 as_fatal (_("Virtual memory exhausted")); 801 802 for (rreg = register_table; 803 rreg < (register_table + num_entries); 804 rreg++) 805 { 806 hashret = hash_insert (* hash_table, rreg->name, (char *) rreg); 807 if (hashret) 808 as_fatal (_("Internal Error: Can't hash %s: %s"), 809 rreg->name, hashret); 810 } 811} 812 813/* This function is called once, at assembler startup time. This should 814 set up all the tables, etc that the MD part of the assembler needs. */ 815 816void 817md_begin (void) 818{ 819 int i = 0; 820 821 /* Set up a hash table for the instructions. */ 822 if ((cr16_inst_hash = hash_new ()) == NULL) 823 as_fatal (_("Virtual memory exhausted")); 824 825 while (cr16_instruction[i].mnemonic != NULL) 826 { 827 const char *hashret; 828 const char *mnemonic = cr16_instruction[i].mnemonic; 829 830 hashret = hash_insert (cr16_inst_hash, mnemonic, 831 (char *)(cr16_instruction + i)); 832 833 if (hashret != NULL && *hashret != '\0') 834 as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic, 835 *hashret == 0 ? _("(unknown reason)") : hashret); 836 837 /* Insert unique names into hash table. The CR16 instruction set 838 has many identical opcode names that have different opcodes based 839 on the operands. This hash table then provides a quick index to 840 the first opcode with a particular name in the opcode table. */ 841 do 842 { 843 ++i; 844 } 845 while (cr16_instruction[i].mnemonic != NULL 846 && streq (cr16_instruction[i].mnemonic, mnemonic)); 847 } 848 849 /* Initialize reg_hash hash table. */ 850 initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS); 851 /* Initialize regp_hash hash table. */ 852 initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS); 853 /* Initialize preg_hash hash table. */ 854 initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS); 855 /* Initialize pregp_hash hash table. */ 856 initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS); 857 858 /* Set linkrelax here to avoid fixups in most sections. */ 859 linkrelax = 1; 860} 861 862/* Process constants (immediate/absolute) 863 and labels (jump targets/Memory locations). */ 864 865static void 866process_label_constant (char *str, ins * cr16_ins) 867{ 868 char *saved_input_line_pointer; 869 int symbol_with_at = 0; 870 int symbol_with_s = 0; 871 int symbol_with_m = 0; 872 int symbol_with_l = 0; 873 int symbol_with_at_got = 0; 874 int symbol_with_at_gotc = 0; 875 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */ 876 877 saved_input_line_pointer = input_line_pointer; 878 input_line_pointer = str; 879 880 expression (&cr16_ins->exp); 881 882 switch (cr16_ins->exp.X_op) 883 { 884 case O_big: 885 case O_absent: 886 /* Missing or bad expr becomes absolute 0. */ 887 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 888 str); 889 cr16_ins->exp.X_op = O_constant; 890 cr16_ins->exp.X_add_number = 0; 891 cr16_ins->exp.X_add_symbol = NULL; 892 cr16_ins->exp.X_op_symbol = NULL; 893 /* Fall through. */ 894 895 case O_constant: 896 cur_arg->X_op = O_constant; 897 cur_arg->constant = cr16_ins->exp.X_add_number; 898 break; 899 900 case O_symbol: 901 case O_subtract: 902 case O_add: 903 cur_arg->X_op = O_symbol; 904 cur_arg->constant = cr16_ins->exp.X_add_number; 905 cr16_ins->exp.X_add_number = 0; 906 cr16_ins->rtype = BFD_RELOC_NONE; 907 relocatable = 1; 908 909 if (strneq (input_line_pointer, "@c", 2)) 910 symbol_with_at = 1; 911 912 if (strneq (input_line_pointer, "@l", 2) 913 || strneq (input_line_pointer, ":l", 2)) 914 symbol_with_l = 1; 915 916 if (strneq (input_line_pointer, "@m", 2) 917 || strneq (input_line_pointer, ":m", 2)) 918 symbol_with_m = 1; 919 920 if (strneq (input_line_pointer, "@s", 2) 921 || strneq (input_line_pointer, ":s", 2)) 922 symbol_with_s = 1; 923 924 if (strneq (input_line_pointer, "@cGOT", 5) 925 || strneq (input_line_pointer, "@cgot", 5)) 926 { 927 if (GOT_symbol == NULL) 928 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 929 930 symbol_with_at_gotc = 1; 931 } 932 else if (strneq (input_line_pointer, "@GOT", 4) 933 || strneq (input_line_pointer, "@got", 4)) 934 { 935 if ((strneq (input_line_pointer, "+", 1)) 936 || (strneq (input_line_pointer, "-", 1))) 937 as_warn (_("GOT bad expression with %s."), input_line_pointer); 938 939 if (GOT_symbol == NULL) 940 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 941 942 symbol_with_at_got = 1; 943 } 944 945 switch (cur_arg->type) 946 { 947 case arg_cr: 948 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 949 { 950 if (symbol_with_at_got) 951 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 952 else if (symbol_with_at_gotc) 953 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 954 else if (cur_arg->size == 20) 955 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 956 else 957 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a; 958 } 959 break; 960 961 case arg_crp: 962 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 963 { 964 if (symbol_with_at_got) 965 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 966 else if (symbol_with_at_gotc) 967 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 968 } else { 969 switch (instruction->size) 970 { 971 case 1: 972 switch (cur_arg->size) 973 { 974 case 0: 975 cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; 976 break; 977 case 4: 978 if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb")) 979 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4; 980 else 981 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a; 982 break; 983 default: break; 984 } 985 break; 986 case 2: 987 cr16_ins->rtype = BFD_RELOC_CR16_REGREL16; 988 break; 989 case 3: 990 if (cur_arg->size == 20) 991 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 992 else 993 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a; 994 break; 995 default: 996 break; 997 } 998 } 999 break; 1000 1001 case arg_idxr: 1002 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 1003 { 1004 if (symbol_with_at_got) 1005 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1006 else if (symbol_with_at_gotc) 1007 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1008 else 1009 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 1010 } 1011 break; 1012 1013 case arg_idxrp: 1014 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 1015 { 1016 if (symbol_with_at_got) 1017 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1018 else if (symbol_with_at_gotc) 1019 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1020 else { 1021 switch (instruction->size) 1022 { 1023 case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break; 1024 case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break; 1025 case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break; 1026 default: break; 1027 } 1028 } 1029 } 1030 break; 1031 1032 case arg_c: 1033 if (IS_INSN_MNEMONIC ("bal")) 1034 cr16_ins->rtype = BFD_RELOC_CR16_DISP24; 1035 else if (IS_INSN_TYPE (BRANCH_INS)) 1036 { 1037 if (symbol_with_l) 1038 cr16_ins->rtype = BFD_RELOC_CR16_DISP24; 1039 else if (symbol_with_m) 1040 cr16_ins->rtype = BFD_RELOC_CR16_DISP16; 1041 else 1042 cr16_ins->rtype = BFD_RELOC_CR16_DISP8; 1043 } 1044 else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS) 1045 || IS_INSN_TYPE (CSTBIT_INS)) 1046 { 1047 if (symbol_with_s) 1048 as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str); 1049 if (symbol_with_at_got) 1050 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1051 else if (symbol_with_at_gotc) 1052 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1053 else if (symbol_with_m) 1054 cr16_ins->rtype = BFD_RELOC_CR16_ABS20; 1055 else /* Default to (symbol_with_l) */ 1056 cr16_ins->rtype = BFD_RELOC_CR16_ABS24; 1057 } 1058 else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) 1059 cr16_ins->rtype = BFD_RELOC_CR16_DISP4; 1060 break; 1061 1062 case arg_ic: 1063 if (IS_INSN_TYPE (ARITH_INS)) 1064 { 1065 if (symbol_with_at_got) 1066 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1067 else if (symbol_with_at_gotc) 1068 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1069 else if (symbol_with_s) 1070 cr16_ins->rtype = BFD_RELOC_CR16_IMM4; 1071 else if (symbol_with_m) 1072 cr16_ins->rtype = BFD_RELOC_CR16_IMM20; 1073 else if (symbol_with_at) 1074 cr16_ins->rtype = BFD_RELOC_CR16_IMM32a; 1075 else /* Default to (symbol_with_l) */ 1076 cr16_ins->rtype = BFD_RELOC_CR16_IMM32; 1077 } 1078 else if (IS_INSN_TYPE (ARITH_BYTE_INS)) 1079 { 1080 cr16_ins->rtype = BFD_RELOC_CR16_IMM16; 1081 } 1082 break; 1083 default: 1084 break; 1085 } 1086 break; 1087 1088 default: 1089 cur_arg->X_op = cr16_ins->exp.X_op; 1090 break; 1091 } 1092 1093 input_line_pointer = saved_input_line_pointer; 1094 return; 1095} 1096 1097/* Retrieve the opcode image of a given register. 1098 If the register is illegal for the current instruction, 1099 issue an error. */ 1100 1101static int 1102getreg_image (reg r) 1103{ 1104 const reg_entry *rreg; 1105 char *reg_name; 1106 int is_procreg = 0; /* Nonzero means argument should be processor reg. */ 1107 1108 /* Check whether the register is in registers table. */ 1109 if (r < MAX_REG) 1110 rreg = cr16_regtab + r; 1111 else /* Register not found. */ 1112 { 1113 as_bad (_("Unknown register: `%d'"), r); 1114 return 0; 1115 } 1116 1117 reg_name = rreg->name; 1118 1119/* Issue a error message when register is illegal. */ 1120#define IMAGE_ERR \ 1121 as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \ 1122 reg_name, ins_parse); \ 1123 break; 1124 1125 switch (rreg->type) 1126 { 1127 case CR16_R_REGTYPE: 1128 if (! is_procreg) 1129 return rreg->image; 1130 else 1131 IMAGE_ERR; 1132 1133 case CR16_P_REGTYPE: 1134 return rreg->image; 1135 break; 1136 1137 default: 1138 IMAGE_ERR; 1139 } 1140 1141 return 0; 1142} 1143 1144/* Parsing different types of operands 1145 -> constants Immediate/Absolute/Relative numbers 1146 -> Labels Relocatable symbols 1147 -> (reg pair base) Register pair base 1148 -> (rbase) Register base 1149 -> disp(rbase) Register relative 1150 -> [rinx]disp(reg pair) Register index with reg pair mode 1151 -> disp(rbase,ridx,scl) Register index mode. */ 1152 1153static void 1154set_operand (char *operand, ins * cr16_ins) 1155{ 1156 char *operandS; /* Pointer to start of sub-opearand. */ 1157 char *operandE; /* Pointer to end of sub-opearand. */ 1158 1159 argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */ 1160 1161 /* Initialize pointers. */ 1162 operandS = operandE = operand; 1163 1164 switch (cur_arg->type) 1165 { 1166 case arg_ic: /* Case $0x18. */ 1167 operandS++; 1168 /* Fall through. */ 1169 case arg_c: /* Case 0x18. */ 1170 /* Set constant. */ 1171 process_label_constant (operandS, cr16_ins); 1172 1173 if (cur_arg->type != arg_ic) 1174 cur_arg->type = arg_c; 1175 break; 1176 1177 case arg_icr: /* Case $0x18(r1). */ 1178 operandS++; 1179 case arg_cr: /* Case 0x18(r1). */ 1180 /* Set displacement constant. */ 1181 while (*operandE != '(') 1182 operandE++; 1183 *operandE = '\0'; 1184 process_label_constant (operandS, cr16_ins); 1185 operandS = operandE; 1186 /* Fall through. */ 1187 case arg_rbase: /* Case (r1) or (r1,r0). */ 1188 operandS++; 1189 /* Set register base. */ 1190 while (*operandE != ')') 1191 operandE++; 1192 *operandE = '\0'; 1193 if ((cur_arg->r = get_register (operandS)) == nullregister) 1194 as_bad (_("Illegal register `%s' in Instruction `%s'"), 1195 operandS, ins_parse); 1196 1197 /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */ 1198 if ((cur_arg->type != arg_rbase) 1199 && ((getreg_image (cur_arg->r) == 12) 1200 || (getreg_image (cur_arg->r) == 13) 1201 || (getreg_image (cur_arg->r) == 14) 1202 || (getreg_image (cur_arg->r) == 15))) 1203 { 1204 cur_arg->type = arg_crp; 1205 cur_arg->rp = cur_arg->r; 1206 } 1207 break; 1208 1209 case arg_crp: /* Case 0x18(r1,r0). */ 1210 /* Set displacement constant. */ 1211 while (*operandE != '(') 1212 operandE++; 1213 *operandE = '\0'; 1214 process_label_constant (operandS, cr16_ins); 1215 operandS = operandE; 1216 operandS++; 1217 /* Set register pair base. */ 1218 while (*operandE != ')') 1219 operandE++; 1220 *operandE = '\0'; 1221 if ((cur_arg->rp = get_register_pair (operandS)) == nullregister) 1222 as_bad (_("Illegal register pair `%s' in Instruction `%s'"), 1223 operandS, ins_parse); 1224 break; 1225 1226 case arg_idxr: 1227 /* Set register pair base. */ 1228 if ((strchr (operandS,'(') != NULL)) 1229 { 1230 while ((*operandE != '(') && (! ISSPACE (*operandE))) 1231 operandE++; 1232 if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister) 1233 as_bad (_("Illegal register pair `%s' in Instruction `%s'"), 1234 operandS, ins_parse); 1235 *operandE++ = '\0'; 1236 cur_arg->type = arg_idxrp; 1237 } 1238 else 1239 cur_arg->rp = -1; 1240 1241 operandE = operandS; 1242 /* Set displacement constant. */ 1243 while (*operandE != ']') 1244 operandE++; 1245 process_label_constant (++operandE, cr16_ins); 1246 *operandE++ = '\0'; 1247 operandE = operandS; 1248 1249 /* Set index register . */ 1250 operandS = strchr (operandE,'['); 1251 if (operandS != NULL) 1252 { /* Eliminate '[', detach from rest of operand. */ 1253 *operandS++ = '\0'; 1254 1255 operandE = strchr (operandS, ']'); 1256 1257 if (operandE == NULL) 1258 as_bad (_("unmatched '['")); 1259 else 1260 { /* Eliminate ']' and make sure it was the last thing 1261 in the string. */ 1262 *operandE = '\0'; 1263 if (*(operandE + 1) != '\0') 1264 as_bad (_("garbage after index spec ignored")); 1265 } 1266 } 1267 1268 if ((cur_arg->i_r = get_index_register (operandS)) == nullregister) 1269 as_bad (_("Illegal register `%s' in Instruction `%s'"), 1270 operandS, ins_parse); 1271 *operandE = '\0'; 1272 *operandS = '\0'; 1273 break; 1274 1275 default: 1276 break; 1277 } 1278} 1279 1280/* Parse a single operand. 1281 operand - Current operand to parse. 1282 cr16_ins - Current assembled instruction. */ 1283 1284static void 1285parse_operand (char *operand, ins * cr16_ins) 1286{ 1287 int ret_val; 1288 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */ 1289 1290 /* Initialize the type to NULL before parsing. */ 1291 cur_arg->type = nullargs; 1292 1293 /* Check whether this is a condition code . */ 1294 if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1)) 1295 { 1296 cur_arg->type = arg_cc; 1297 cur_arg->cc = ret_val; 1298 cur_arg->X_op = O_register; 1299 return; 1300 } 1301 1302 /* Check whether this is a general processor register. */ 1303 if ((ret_val = get_register (operand)) != nullregister) 1304 { 1305 cur_arg->type = arg_r; 1306 cur_arg->r = ret_val; 1307 cur_arg->X_op = 0; 1308 return; 1309 } 1310 1311 /* Check whether this is a general processor register pair. */ 1312 if ((operand[0] == '(') 1313 && ((ret_val = get_register_pair (operand)) != nullregister)) 1314 { 1315 cur_arg->type = arg_rp; 1316 cur_arg->rp = ret_val; 1317 cur_arg->X_op = O_register; 1318 return; 1319 } 1320 1321 /* Check whether the operand is a processor register. 1322 For "lprd" and "sprd" instruction, only 32 bit 1323 processor registers used. */ 1324 if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd"))) 1325 && ((ret_val = get_pregister (operand)) != nullpregister)) 1326 { 1327 cur_arg->type = arg_pr; 1328 cur_arg->pr = ret_val; 1329 cur_arg->X_op = O_register; 1330 return; 1331 } 1332 1333 /* Check whether this is a processor register - 32 bit. */ 1334 if ((ret_val = get_pregisterp (operand)) != nullpregister) 1335 { 1336 cur_arg->type = arg_prp; 1337 cur_arg->prp = ret_val; 1338 cur_arg->X_op = O_register; 1339 return; 1340 } 1341 1342 /* Deal with special characters. */ 1343 switch (operand[0]) 1344 { 1345 case '$': 1346 if (strchr (operand, '(') != NULL) 1347 cur_arg->type = arg_icr; 1348 else 1349 cur_arg->type = arg_ic; 1350 goto set_params; 1351 break; 1352 1353 case '(': 1354 cur_arg->type = arg_rbase; 1355 goto set_params; 1356 break; 1357 1358 case '[': 1359 cur_arg->type = arg_idxr; 1360 goto set_params; 1361 break; 1362 1363 default: 1364 break; 1365 } 1366 1367 if (strchr (operand, '(') != NULL) 1368 { 1369 if (strchr (operand, ',') != NULL 1370 && (strchr (operand, ',') > strchr (operand, '('))) 1371 cur_arg->type = arg_crp; 1372 else 1373 cur_arg->type = arg_cr; 1374 } 1375 else 1376 cur_arg->type = arg_c; 1377 1378/* Parse an operand according to its type. */ 1379 set_params: 1380 cur_arg->constant = 0; 1381 set_operand (operand, cr16_ins); 1382} 1383 1384/* Parse the various operands. Each operand is then analyzed to fillup 1385 the fields in the cr16_ins data structure. */ 1386 1387static void 1388parse_operands (ins * cr16_ins, char *operands) 1389{ 1390 char *operandS; /* Operands string. */ 1391 char *operandH, *operandT; /* Single operand head/tail pointers. */ 1392 int allocated = 0; /* Indicates a new operands string was allocated.*/ 1393 char *operand[MAX_OPERANDS];/* Separating the operands. */ 1394 int op_num = 0; /* Current operand number we are parsing. */ 1395 int bracket_flag = 0; /* Indicates a bracket '(' was found. */ 1396 int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */ 1397 1398 /* Preprocess the list of registers, if necessary. */ 1399 operandS = operandH = operandT = operands; 1400 1401 while (*operandT != '\0') 1402 { 1403 if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1) 1404 { 1405 *operandT++ = '\0'; 1406 operand[op_num++] = strdup (operandH); 1407 operandH = operandT; 1408 continue; 1409 } 1410 1411 if (*operandT == ' ') 1412 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse); 1413 1414 if (*operandT == '(') 1415 bracket_flag = 1; 1416 else if (*operandT == '[') 1417 sq_bracket_flag = 1; 1418 1419 if (*operandT == ')') 1420 { 1421 if (bracket_flag) 1422 bracket_flag = 0; 1423 else 1424 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1425 } 1426 else if (*operandT == ']') 1427 { 1428 if (sq_bracket_flag) 1429 sq_bracket_flag = 0; 1430 else 1431 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1432 } 1433 1434 if (bracket_flag == 1 && *operandT == ')') 1435 bracket_flag = 0; 1436 else if (sq_bracket_flag == 1 && *operandT == ']') 1437 sq_bracket_flag = 0; 1438 1439 operandT++; 1440 } 1441 1442 /* Adding the last operand. */ 1443 operand[op_num++] = strdup (operandH); 1444 cr16_ins->nargs = op_num; 1445 1446 /* Verifying correct syntax of operands (all brackets should be closed). */ 1447 if (bracket_flag || sq_bracket_flag) 1448 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1449 1450 /* Now we parse each operand separately. */ 1451 for (op_num = 0; op_num < cr16_ins->nargs; op_num++) 1452 { 1453 cur_arg_num = op_num; 1454 parse_operand (operand[op_num], cr16_ins); 1455 free (operand[op_num]); 1456 } 1457 1458 if (allocated) 1459 free (operandS); 1460} 1461 1462/* Get the trap index in dispatch table, given its name. 1463 This routine is used by assembling the 'excp' instruction. */ 1464 1465static int 1466gettrap (char *s) 1467{ 1468 const trap_entry *trap; 1469 1470 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) 1471 if (strcasecmp (trap->name, s) == 0) 1472 return trap->entry; 1473 1474 /* To make compatible with CR16 4.1 tools, the below 3-lines of 1475 * code added. Refer: Development Tracker item #123 */ 1476 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) 1477 if (trap->entry == (unsigned int) atoi (s)) 1478 return trap->entry; 1479 1480 as_bad (_("Unknown exception: `%s'"), s); 1481 return 0; 1482} 1483 1484/* Top level module where instruction parsing starts. 1485 cr16_ins - data structure holds some information. 1486 operands - holds the operands part of the whole instruction. */ 1487 1488static void 1489parse_insn (ins *insn, char *operands) 1490{ 1491 int i; 1492 1493 /* Handle instructions with no operands. */ 1494 for (i = 0; cr16_no_op_insn[i] != NULL; i++) 1495 { 1496 if (streq (cr16_no_op_insn[i], instruction->mnemonic)) 1497 { 1498 insn->nargs = 0; 1499 return; 1500 } 1501 } 1502 1503 /* Handle 'excp' instructions. */ 1504 if (IS_INSN_MNEMONIC ("excp")) 1505 { 1506 insn->nargs = 1; 1507 insn->arg[0].type = arg_ic; 1508 insn->arg[0].constant = gettrap (operands); 1509 insn->arg[0].X_op = O_constant; 1510 return; 1511 } 1512 1513 if (operands != NULL) 1514 parse_operands (insn, operands); 1515} 1516 1517/* bCC instruction requires special handling. */ 1518static char * 1519get_b_cc (char * op) 1520{ 1521 unsigned int i; 1522 char op1[5]; 1523 1524 for (i = 1; i < strlen (op); i++) 1525 op1[i-1] = op[i]; 1526 1527 op1[i-1] = '\0'; 1528 1529 for (i = 0; i < cr16_num_cc ; i++) 1530 if (streq (op1, cr16_b_cond_tab[i])) 1531 return (char *) cr16_b_cond_tab[i]; 1532 1533 return NULL; 1534} 1535 1536/* bCC instruction requires special handling. */ 1537static int 1538is_bcc_insn (char * op) 1539{ 1540 if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b") 1541 || streq (op, "beq0w") || streq (op, "bnq0w"))) 1542 if ((op[0] == 'b') && (get_b_cc (op) != NULL)) 1543 return 1; 1544 return 0; 1545} 1546 1547/* Cinv instruction requires special handling. */ 1548 1549static void 1550check_cinv_options (char * operand) 1551{ 1552 char *p = operand; 1553 1554 while (*++p != ']') 1555 { 1556 switch (*p) 1557 { 1558 case ',': 1559 case ' ': 1560 case 'i': 1561 case 'u': 1562 case 'd': 1563 break; 1564 default: 1565 as_bad (_("Illegal `cinv' parameter: `%c'"), *p); 1566 } 1567 } 1568} 1569 1570/* Retrieve the opcode image of a given register pair. 1571 If the register is illegal for the current instruction, 1572 issue an error. */ 1573 1574static int 1575getregp_image (reg r) 1576{ 1577 const reg_entry *rreg; 1578 char *reg_name; 1579 1580 /* Check whether the register is in registers table. */ 1581 if (r < MAX_REG) 1582 rreg = cr16_regptab + r; 1583 /* Register not found. */ 1584 else 1585 { 1586 as_bad (_("Unknown register pair: `%d'"), r); 1587 return 0; 1588 } 1589 1590 reg_name = rreg->name; 1591 1592/* Issue a error message when register pair is illegal. */ 1593#define RPAIR_IMAGE_ERR \ 1594 as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \ 1595 reg_name, ins_parse); \ 1596 break; 1597 1598 switch (rreg->type) 1599 { 1600 case CR16_RP_REGTYPE: 1601 return rreg->image; 1602 default: 1603 RPAIR_IMAGE_ERR; 1604 } 1605 1606 return 0; 1607} 1608 1609/* Retrieve the opcode image of a given index register pair. 1610 If the register is illegal for the current instruction, 1611 issue an error. */ 1612 1613static int 1614getidxregp_image (reg r) 1615{ 1616 const reg_entry *rreg; 1617 char *reg_name; 1618 1619 /* Check whether the register is in registers table. */ 1620 if (r < MAX_REG) 1621 rreg = cr16_regptab + r; 1622 /* Register not found. */ 1623 else 1624 { 1625 as_bad (_("Unknown register pair: `%d'"), r); 1626 return 0; 1627 } 1628 1629 reg_name = rreg->name; 1630 1631/* Issue a error message when register pair is illegal. */ 1632#define IDX_RPAIR_IMAGE_ERR \ 1633 as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \ 1634 reg_name, ins_parse); \ 1635 1636 if (rreg->type == CR16_RP_REGTYPE) 1637 { 1638 switch (rreg->image) 1639 { 1640 case 0: return 0; break; 1641 case 2: return 1; break; 1642 case 4: return 2; break; 1643 case 6: return 3; break; 1644 case 8: return 4; break; 1645 case 10: return 5; break; 1646 case 3: return 6; break; 1647 case 5: return 7; break; 1648 default: 1649 break; 1650 } 1651 } 1652 1653 IDX_RPAIR_IMAGE_ERR; 1654 return 0; 1655} 1656 1657/* Retrieve the opcode image of a given processort register. 1658 If the register is illegal for the current instruction, 1659 issue an error. */ 1660static int 1661getprocreg_image (int r) 1662{ 1663 const reg_entry *rreg; 1664 char *reg_name; 1665 1666 /* Check whether the register is in registers table. */ 1667 if (r >= MAX_REG && r < MAX_PREG) 1668 rreg = &cr16_pregtab[r - MAX_REG]; 1669 /* Register not found. */ 1670 else 1671 { 1672 as_bad (_("Unknown processor register : `%d'"), r); 1673 return 0; 1674 } 1675 1676 reg_name = rreg->name; 1677 1678/* Issue a error message when register pair is illegal. */ 1679#define PROCREG_IMAGE_ERR \ 1680 as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \ 1681 reg_name, ins_parse); \ 1682 break; 1683 1684 switch (rreg->type) 1685 { 1686 case CR16_P_REGTYPE: 1687 return rreg->image; 1688 default: 1689 PROCREG_IMAGE_ERR; 1690 } 1691 1692 return 0; 1693} 1694 1695/* Retrieve the opcode image of a given processort register. 1696 If the register is illegal for the current instruction, 1697 issue an error. */ 1698static int 1699getprocregp_image (int r) 1700{ 1701 const reg_entry *rreg; 1702 char *reg_name; 1703 int pregptab_disp = 0; 1704 1705 /* Check whether the register is in registers table. */ 1706 if (r >= MAX_REG && r < MAX_PREG) 1707 { 1708 r = r - MAX_REG; 1709 switch (r) 1710 { 1711 case 4: pregptab_disp = 1; break; 1712 case 6: pregptab_disp = 2; break; 1713 case 8: 1714 case 9: 1715 case 10: 1716 pregptab_disp = 3; break; 1717 case 12: 1718 pregptab_disp = 4; break; 1719 case 14: 1720 pregptab_disp = 5; break; 1721 default: break; 1722 } 1723 rreg = &cr16_pregptab[r - pregptab_disp]; 1724 } 1725 /* Register not found. */ 1726 else 1727 { 1728 as_bad (_("Unknown processor register (32 bit) : `%d'"), r); 1729 return 0; 1730 } 1731 1732 reg_name = rreg->name; 1733 1734/* Issue a error message when register pair is illegal. */ 1735#define PROCREGP_IMAGE_ERR \ 1736 as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\ 1737 reg_name, ins_parse); \ 1738 break; 1739 1740 switch (rreg->type) 1741 { 1742 case CR16_P_REGTYPE: 1743 return rreg->image; 1744 default: 1745 PROCREGP_IMAGE_ERR; 1746 } 1747 1748 return 0; 1749} 1750 1751/* Routine used to represent integer X using NBITS bits. */ 1752 1753static long 1754getconstant (long x, int nbits) 1755{ 1756 /* The following expression avoids overflow if 1757 'nbits' is the number of bits in 'bfd_vma'. */ 1758 return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1)); 1759} 1760 1761/* Print a constant value to 'output_opcode': 1762 ARG holds the operand's type and value. 1763 SHIFT represents the location of the operand to be print into. 1764 NBITS determines the size (in bits) of the constant. */ 1765 1766static void 1767print_constant (int nbits, int shift, argument *arg) 1768{ 1769 unsigned long mask = 0; 1770 1771 long constant = getconstant (arg->constant, nbits); 1772 1773 switch (nbits) 1774 { 1775 case 32: 1776 case 28: 1777 /* mask the upper part of the constant, that is, the bits 1778 going to the lowest byte of output_opcode[0]. 1779 The upper part of output_opcode[1] is always filled, 1780 therefore it is always masked with 0xFFFF. */ 1781 mask = (1 << (nbits - 16)) - 1; 1782 /* Divide the constant between two consecutive words : 1783 0 1 2 3 1784 +---------+---------+---------+---------+ 1785 | | X X X X | x X x X | | 1786 +---------+---------+---------+---------+ 1787 output_opcode[0] output_opcode[1] */ 1788 1789 CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0); 1790 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1791 break; 1792 1793 case 21: 1794 if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) 1795 nbits = 20; 1796 /* Fall through. */ 1797 case 24: 1798 case 22: 1799 case 20: 1800 /* mask the upper part of the constant, that is, the bits 1801 going to the lowest byte of output_opcode[0]. 1802 The upper part of output_opcode[1] is always filled, 1803 therefore it is always masked with 0xFFFF. */ 1804 mask = (1 << (nbits - 16)) - 1; 1805 /* Divide the constant between two consecutive words : 1806 0 1 2 3 1807 +---------+---------+---------+---------+ 1808 | | X X X X | - X - X | | 1809 +---------+---------+---------+---------+ 1810 output_opcode[0] output_opcode[1] */ 1811 1812 if ((instruction->size > 2) && (shift == WORD_SHIFT)) 1813 { 1814 if (arg->type == arg_idxrp) 1815 { 1816 CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0); 1817 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1818 } 1819 else 1820 { 1821 CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0); 1822 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1823 } 1824 } 1825 else 1826 CR16_PRINT (0, constant, shift); 1827 break; 1828 1829 case 14: 1830 if (arg->type == arg_idxrp) 1831 { 1832 if (instruction->size == 2) 1833 { 1834 CR16_PRINT (0, ((constant) & 0xf), shift); /* 0-3 bits. */ 1835 CR16_PRINT (0, ((constant >> 4) & 0x3), (shift + 20)); /* 4-5 bits. */ 1836 CR16_PRINT (0, ((constant >> 6) & 0x3), (shift + 14)); /* 6-7 bits. */ 1837 CR16_PRINT (0, ((constant >> 8) & 0x3f), (shift + 8)); /* 8-13 bits. */ 1838 } 1839 else 1840 CR16_PRINT (0, constant, shift); 1841 } 1842 break; 1843 1844 case 16: 1845 case 12: 1846 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is 1847 always filling the upper part of output_opcode[1]. If we mistakenly 1848 write it to output_opcode[0], the constant prefix (that is, 'match') 1849 will be overriden. 1850 0 1 2 3 1851 +---------+---------+---------+---------+ 1852 | 'match' | | X X X X | | 1853 +---------+---------+---------+---------+ 1854 output_opcode[0] output_opcode[1] */ 1855 1856 if ((instruction->size > 2) && (shift == WORD_SHIFT)) 1857 CR16_PRINT (1, constant, WORD_SHIFT); 1858 else 1859 CR16_PRINT (0, constant, shift); 1860 break; 1861 1862 case 8: 1863 CR16_PRINT (0, ((constant / 2) & 0xf), shift); 1864 CR16_PRINT (0, ((constant / 2) >> 4), (shift + 8)); 1865 break; 1866 1867 default: 1868 CR16_PRINT (0, constant, shift); 1869 break; 1870 } 1871} 1872 1873/* Print an operand to 'output_opcode', which later on will be 1874 printed to the object file: 1875 ARG holds the operand's type, size and value. 1876 SHIFT represents the printing location of operand. 1877 NBITS determines the size (in bits) of a constant operand. */ 1878 1879static void 1880print_operand (int nbits, int shift, argument *arg) 1881{ 1882 switch (arg->type) 1883 { 1884 case arg_cc: 1885 CR16_PRINT (0, arg->cc, shift); 1886 break; 1887 1888 case arg_r: 1889 CR16_PRINT (0, getreg_image (arg->r), shift); 1890 break; 1891 1892 case arg_rp: 1893 CR16_PRINT (0, getregp_image (arg->rp), shift); 1894 break; 1895 1896 case arg_pr: 1897 CR16_PRINT (0, getprocreg_image (arg->pr), shift); 1898 break; 1899 1900 case arg_prp: 1901 CR16_PRINT (0, getprocregp_image (arg->prp), shift); 1902 break; 1903 1904 case arg_idxrp: 1905 /* 16 12 8 6 0 1906 +-----------------------------+ 1907 | r_index | disp | rp_base | 1908 +-----------------------------+ */ 1909 1910 if (instruction->size == 3) 1911 { 1912 CR16_PRINT (0, getidxregp_image (arg->rp), 0); 1913 if (getreg_image (arg->i_r) == 12) 1914 CR16_PRINT (0, 0, 3); 1915 else 1916 CR16_PRINT (0, 1, 3); 1917 } 1918 else 1919 { 1920 CR16_PRINT (0, getidxregp_image (arg->rp), 16); 1921 if (getreg_image (arg->i_r) == 12) 1922 CR16_PRINT (0, 0, 19); 1923 else 1924 CR16_PRINT (0, 1, 19); 1925 } 1926 print_constant (nbits, shift, arg); 1927 break; 1928 1929 case arg_idxr: 1930 if (getreg_image (arg->i_r) == 12) 1931 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb") 1932 || IS_INSN_MNEMONIC ("tbitb")) 1933 CR16_PRINT (0, 0, 23); 1934 else CR16_PRINT (0, 0, 24); 1935 else 1936 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb") 1937 || IS_INSN_MNEMONIC ("tbitb")) 1938 CR16_PRINT (0, 1, 23); 1939 else CR16_PRINT (0, 1, 24); 1940 1941 print_constant (nbits, shift, arg); 1942 break; 1943 1944 case arg_ic: 1945 case arg_c: 1946 print_constant (nbits, shift, arg); 1947 break; 1948 1949 case arg_rbase: 1950 CR16_PRINT (0, getreg_image (arg->r), shift); 1951 break; 1952 1953 case arg_cr: 1954 print_constant (nbits, shift , arg); 1955 /* Add the register argument to the output_opcode. */ 1956 CR16_PRINT (0, getreg_image (arg->r), (shift+16)); 1957 break; 1958 1959 case arg_crp: 1960 print_constant (nbits, shift , arg); 1961 if (instruction->size > 1) 1962 CR16_PRINT (0, getregp_image (arg->rp), (shift + 16)); 1963 else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS))) 1964 { 1965 if (instruction->size == 2) 1966 CR16_PRINT (0, getregp_image (arg->rp), (shift - 8)); 1967 else if (instruction->size == 1) 1968 CR16_PRINT (0, getregp_image (arg->rp), 16); 1969 } 1970 else 1971 CR16_PRINT (0, getregp_image (arg->rp), shift); 1972 break; 1973 1974 default: 1975 break; 1976 } 1977} 1978 1979/* Retrieve the number of operands for the current assembled instruction. */ 1980 1981static int 1982get_number_of_operands (void) 1983{ 1984 int i; 1985 1986 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) 1987 ; 1988 return i; 1989} 1990 1991/* Verify that the number NUM can be represented in BITS bits (that is, 1992 within its permitted range), based on the instruction's FLAGS. 1993 If UPDATE is nonzero, update the value of NUM if necessary. 1994 Return OP_LEGAL upon success, actual error type upon failure. */ 1995 1996static op_err 1997check_range (long *num, int bits, int unsigned flags, int update) 1998{ 1999 long min, max; 2000 op_err retval = OP_LEGAL; 2001 long value = *num; 2002 2003 if (bits == 0 && value > 0) return OP_OUT_OF_RANGE; 2004 2005 /* For hosts witah longs bigger than 32-bits make sure that the top 2006 bits of a 32-bit negative value read in by the parser are set, 2007 so that the correct comparisons are made. */ 2008 if (value & 0x80000000) 2009 value |= (-1UL << 31); 2010 2011 2012 /* Verify operand value is even. */ 2013 if (flags & OP_EVEN) 2014 { 2015 if (value % 2) 2016 return OP_NOT_EVEN; 2017 } 2018 2019 if (flags & OP_DEC) 2020 { 2021 value -= 1; 2022 if (update) 2023 *num = value; 2024 } 2025 2026 if (flags & OP_SHIFT) 2027 { 2028 value >>= 1; 2029 if (update) 2030 *num = value; 2031 } 2032 else if (flags & OP_SHIFT_DEC) 2033 { 2034 value = (value >> 1) - 1; 2035 if (update) 2036 *num = value; 2037 } 2038 2039 if (flags & OP_ABS20) 2040 { 2041 if (value > 0xEFFFF) 2042 return OP_OUT_OF_RANGE; 2043 } 2044 2045 if (flags & OP_ESC) 2046 { 2047 if (value == 0xB || value == 0x9) 2048 return OP_OUT_OF_RANGE; 2049 else if (value == -1) 2050 { 2051 if (update) 2052 *num = 9; 2053 return retval; 2054 } 2055 } 2056 2057 if (flags & OP_ESC1) 2058 { 2059 if (value > 13) 2060 return OP_OUT_OF_RANGE; 2061 } 2062 2063 if (flags & OP_SIGNED) 2064 { 2065 max = (1 << (bits - 1)) - 1; 2066 min = - (1 << (bits - 1)); 2067 if ((value > max) || (value < min)) 2068 retval = OP_OUT_OF_RANGE; 2069 } 2070 else if (flags & OP_UNSIGNED) 2071 { 2072 max = ((((1 << (bits - 1)) - 1) << 1) | 1); 2073 min = 0; 2074 if (((unsigned long) value > (unsigned long) max) 2075 || ((unsigned long) value < (unsigned long) min)) 2076 retval = OP_OUT_OF_RANGE; 2077 } 2078 else if (flags & OP_NEG) 2079 { 2080 max = - 1; 2081 min = - ((1 << (bits - 1)) - 1); 2082 if ((value > max) || (value < min)) 2083 retval = OP_OUT_OF_RANGE; 2084 } 2085 return retval; 2086} 2087 2088/* Bunch of error checkings. 2089 The checks are made after a matching instruction was found. */ 2090 2091static void 2092warn_if_needed (ins *insn) 2093{ 2094 /* If the post-increment address mode is used and the load/store 2095 source register is the same as rbase, the result of the 2096 instruction is undefined. */ 2097 if (IS_INSN_TYPE (LD_STOR_INS_INC)) 2098 { 2099 /* Enough to verify that one of the arguments is a simple reg. */ 2100 if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r)) 2101 if (insn->arg[0].r == insn->arg[1].r) 2102 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r); 2103 } 2104 2105 if (IS_INSN_MNEMONIC ("pop") 2106 || IS_INSN_MNEMONIC ("push") 2107 || IS_INSN_MNEMONIC ("popret")) 2108 { 2109 unsigned int count = insn->arg[0].constant, reg_val; 2110 2111 /* Check if count operand caused to save/retrive the RA twice 2112 to generate warning message. */ 2113 if (insn->nargs > 2) 2114 { 2115 reg_val = getreg_image (insn->arg[1].r); 2116 2117 if ( ((reg_val == 9) && (count > 7)) 2118 || ((reg_val == 10) && (count > 6)) 2119 || ((reg_val == 11) && (count > 5)) 2120 || ((reg_val == 12) && (count > 4)) 2121 || ((reg_val == 13) && (count > 2)) 2122 || ((reg_val == 14) && (count > 0))) 2123 as_warn (_("RA register is saved twice.")); 2124 2125 /* Check if the third operand is "RA" or "ra" */ 2126 if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA))) 2127 as_bad (_("`%s' Illegal use of registers."), ins_parse); 2128 } 2129 2130 if (insn->nargs > 1) 2131 { 2132 reg_val = getreg_image (insn->arg[1].r); 2133 2134 /* If register is a register pair ie r12/r13/r14 in operand1, then 2135 the count constant should be validated. */ 2136 if (((reg_val == 11) && (count > 7)) 2137 || ((reg_val == 12) && (count > 6)) 2138 || ((reg_val == 13) && (count > 4)) 2139 || ((reg_val == 14) && (count > 2)) 2140 || ((reg_val == 15) && (count > 0))) 2141 as_bad (_("`%s' Illegal count-register combination."), ins_parse); 2142 } 2143 else 2144 { 2145 /* Check if the operand is "RA" or "ra" */ 2146 if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA))) 2147 as_bad (_("`%s' Illegal use of register."), ins_parse); 2148 } 2149 } 2150 2151 /* Some instruction assume the stack pointer as rptr operand. 2152 Issue an error when the register to be loaded is also SP. */ 2153 if (instruction->flags & NO_SP) 2154 { 2155 if (getreg_image (insn->arg[1].r) == getreg_image (sp)) 2156 as_bad (_("`%s' has undefined result"), ins_parse); 2157 } 2158 2159 /* If the rptr register is specified as one of the registers to be loaded, 2160 the final contents of rptr are undefined. Thus, we issue an error. */ 2161 if (instruction->flags & NO_RPTR) 2162 { 2163 if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant) 2164 as_bad (_("Same src/dest register is used (`r%d'),result is undefined"), 2165 getreg_image (insn->arg[0].r)); 2166 } 2167} 2168 2169/* In some cases, we need to adjust the instruction pointer although a 2170 match was already found. Here, we gather all these cases. 2171 Returns 1 if instruction pointer was adjusted, otherwise 0. */ 2172 2173static int 2174adjust_if_needed (ins *insn ATTRIBUTE_UNUSED) 2175{ 2176 int ret_value = 0; 2177 2178 if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS))) 2179 { 2180 if ((instruction->operands[0].op_type == abs24) 2181 && ((insn->arg[0].constant) > 0xF00000)) 2182 { 2183 insn->arg[0].constant &= 0xFFFFF; 2184 instruction--; 2185 ret_value = 1; 2186 } 2187 } 2188 2189 return ret_value; 2190} 2191 2192/* Assemble a single instruction: 2193 INSN is already parsed (that is, all operand values and types are set). 2194 For instruction to be assembled, we need to find an appropriate template in 2195 the instruction table, meeting the following conditions: 2196 1: Has the same number of operands. 2197 2: Has the same operand types. 2198 3: Each operand size is sufficient to represent the instruction's values. 2199 Returns 1 upon success, 0 upon failure. */ 2200 2201static int 2202assemble_insn (const char *mnemonic, ins *insn) 2203{ 2204 /* Type of each operand in the current template. */ 2205 argtype cur_type[MAX_OPERANDS]; 2206 /* Size (in bits) of each operand in the current template. */ 2207 unsigned int cur_size[MAX_OPERANDS]; 2208 /* Flags of each operand in the current template. */ 2209 unsigned int cur_flags[MAX_OPERANDS]; 2210 /* Instruction type to match. */ 2211 unsigned int ins_type; 2212 /* Boolean flag to mark whether a match was found. */ 2213 int match = 0; 2214 int i; 2215 /* Nonzero if an instruction with same number of operands was found. */ 2216 int found_same_number_of_operands = 0; 2217 /* Nonzero if an instruction with same argument types was found. */ 2218 int found_same_argument_types = 0; 2219 /* Nonzero if a constant was found within the required range. */ 2220 int found_const_within_range = 0; 2221 /* Argument number of an operand with invalid type. */ 2222 int invalid_optype = -1; 2223 /* Argument number of an operand with invalid constant value. */ 2224 int invalid_const = -1; 2225 /* Operand error (used for issuing various constant error messages). */ 2226 op_err op_error, const_err = OP_LEGAL; 2227 2228/* Retrieve data (based on FUNC) for each operand of a given instruction. */ 2229#define GET_CURRENT_DATA(FUNC, ARRAY) \ 2230 for (i = 0; i < insn->nargs; i++) \ 2231 ARRAY[i] = FUNC (instruction->operands[i].op_type) 2232 2233#define GET_CURRENT_TYPE GET_CURRENT_DATA (get_optype, cur_type) 2234#define GET_CURRENT_SIZE GET_CURRENT_DATA (get_opbits, cur_size) 2235#define GET_CURRENT_FLAGS GET_CURRENT_DATA (get_opflags, cur_flags) 2236 2237 /* Instruction has no operands -> only copy the constant opcode. */ 2238 if (insn->nargs == 0) 2239 { 2240 output_opcode[0] = BIN (instruction->match, instruction->match_bits); 2241 return 1; 2242 } 2243 2244 /* In some case, same mnemonic can appear with different instruction types. 2245 For example, 'storb' is supported with 3 different types : 2246 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS. 2247 We assume that when reaching this point, the instruction type was 2248 pre-determined. We need to make sure that the type stays the same 2249 during a search for matching instruction. */ 2250 ins_type = CR16_INS_TYPE (instruction->flags); 2251 2252 while (/* Check that match is still not found. */ 2253 match != 1 2254 /* Check we didn't get to end of table. */ 2255 && instruction->mnemonic != NULL 2256 /* Check that the actual mnemonic is still available. */ 2257 && IS_INSN_MNEMONIC (mnemonic) 2258 /* Check that the instruction type wasn't changed. */ 2259 && IS_INSN_TYPE (ins_type)) 2260 { 2261 /* Check whether number of arguments is legal. */ 2262 if (get_number_of_operands () != insn->nargs) 2263 goto next_insn; 2264 found_same_number_of_operands = 1; 2265 2266 /* Initialize arrays with data of each operand in current template. */ 2267 GET_CURRENT_TYPE; 2268 GET_CURRENT_SIZE; 2269 GET_CURRENT_FLAGS; 2270 2271 /* Check for type compatibility. */ 2272 for (i = 0; i < insn->nargs; i++) 2273 { 2274 if (cur_type[i] != insn->arg[i].type) 2275 { 2276 if (invalid_optype == -1) 2277 invalid_optype = i + 1; 2278 goto next_insn; 2279 } 2280 } 2281 found_same_argument_types = 1; 2282 2283 for (i = 0; i < insn->nargs; i++) 2284 { 2285 /* If 'bal' instruction size is '2' and reg operand is not 'ra' 2286 then goto next instruction. */ 2287 if (IS_INSN_MNEMONIC ("bal") && (i == 0) 2288 && (instruction->size == 2) && (insn->arg[i].rp != 14)) 2289 goto next_insn; 2290 2291 /* If 'storb' instruction with 'sp' reg and 16-bit disp of 2292 * reg-pair, leads to undifined trap, so this should use 2293 * 20-bit disp of reg-pair. */ 2294 if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2) 2295 && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp)) 2296 goto next_insn; 2297 2298 /* Only check range - don't update the constant's value, since the 2299 current instruction may not be the last we try to match. 2300 The constant's value will be updated later, right before printing 2301 it to the object file. */ 2302 if ((insn->arg[i].X_op == O_constant) 2303 && (op_error = check_range (&insn->arg[i].constant, cur_size[i], 2304 cur_flags[i], 0))) 2305 { 2306 if (invalid_const == -1) 2307 { 2308 invalid_const = i + 1; 2309 const_err = op_error; 2310 } 2311 goto next_insn; 2312 } 2313 /* For symbols, we make sure the relocation size (which was already 2314 determined) is sufficient. */ 2315 else if ((insn->arg[i].X_op == O_symbol) 2316 && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize 2317 > cur_size[i])) 2318 goto next_insn; 2319 } 2320 found_const_within_range = 1; 2321 2322 /* If we got till here -> Full match is found. */ 2323 match = 1; 2324 break; 2325 2326/* Try again with next instruction. */ 2327next_insn: 2328 instruction++; 2329 } 2330 2331 if (!match) 2332 { 2333 /* We haven't found a match - instruction can't be assembled. */ 2334 if (!found_same_number_of_operands) 2335 as_bad (_("Incorrect number of operands")); 2336 else if (!found_same_argument_types) 2337 as_bad (_("Illegal type of operand (arg %d)"), invalid_optype); 2338 else if (!found_const_within_range) 2339 { 2340 switch (const_err) 2341 { 2342 case OP_OUT_OF_RANGE: 2343 as_bad (_("Operand out of range (arg %d)"), invalid_const); 2344 break; 2345 case OP_NOT_EVEN: 2346 as_bad (_("Operand has odd displacement (arg %d)"), invalid_const); 2347 break; 2348 default: 2349 as_bad (_("Illegal operand (arg %d)"), invalid_const); 2350 break; 2351 } 2352 } 2353 2354 return 0; 2355 } 2356 else 2357 /* Full match - print the encoding to output file. */ 2358 { 2359 /* Make further checkings (such that couldn't be made earlier). 2360 Warn the user if necessary. */ 2361 warn_if_needed (insn); 2362 2363 /* Check whether we need to adjust the instruction pointer. */ 2364 if (adjust_if_needed (insn)) 2365 /* If instruction pointer was adjusted, we need to update 2366 the size of the current template operands. */ 2367 GET_CURRENT_SIZE; 2368 2369 for (i = 0; i < insn->nargs; i++) 2370 { 2371 int j = instruction->flags & REVERSE_MATCH ? 2372 i == 0 ? 1 : 2373 i == 1 ? 0 : i : 2374 i; 2375 2376 /* This time, update constant value before printing it. */ 2377 if ((insn->arg[j].X_op == O_constant) 2378 && (check_range (&insn->arg[j].constant, cur_size[j], 2379 cur_flags[j], 1) != OP_LEGAL)) 2380 as_fatal (_("Illegal operand (arg %d)"), j+1); 2381 } 2382 2383 /* First, copy the instruction's opcode. */ 2384 output_opcode[0] = BIN (instruction->match, instruction->match_bits); 2385 2386 for (i = 0; i < insn->nargs; i++) 2387 { 2388 /* For BAL (ra),disp17 instruction only. And also set the 2389 DISP24a relocation type. */ 2390 if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0) 2391 { 2392 insn->rtype = BFD_RELOC_CR16_DISP24a; 2393 continue; 2394 } 2395 cur_arg_num = i; 2396 print_operand (cur_size[i], instruction->operands[i].shift, 2397 &insn->arg[i]); 2398 } 2399 } 2400 2401 return 1; 2402} 2403 2404/* Print the instruction. 2405 Handle also cases where the instruction is relaxable/relocatable. */ 2406 2407static void 2408print_insn (ins *insn) 2409{ 2410 unsigned int i, j, insn_size; 2411 char *this_frag; 2412 unsigned short words[4]; 2413 int addr_mod; 2414 2415 /* Arrange the insn encodings in a WORD size array. */ 2416 for (i = 0, j = 0; i < 2; i++) 2417 { 2418 words[j++] = (output_opcode[i] >> 16) & 0xFFFF; 2419 words[j++] = output_opcode[i] & 0xFFFF; 2420 } 2421 2422 /* Handle relocation. */ 2423 if ((instruction->flags & RELAXABLE) && relocatable) 2424 { 2425 int relax_subtype; 2426 /* Write the maximal instruction size supported. */ 2427 insn_size = INSN_MAX_SIZE; 2428 2429 if (IS_INSN_TYPE (BRANCH_INS)) 2430 { 2431 switch (insn->rtype) 2432 { 2433 case BFD_RELOC_CR16_DISP24: 2434 relax_subtype = 2; 2435 break; 2436 case BFD_RELOC_CR16_DISP16: 2437 relax_subtype = 1; 2438 break; 2439 default: 2440 relax_subtype = 0; 2441 break; 2442 } 2443 } 2444 else 2445 abort (); 2446 2447 this_frag = frag_var (rs_machine_dependent, insn_size *2, 2448 4, relax_subtype, 2449 insn->exp.X_add_symbol, 2450 0, 2451 0); 2452 } 2453 else 2454 { 2455 insn_size = instruction->size; 2456 this_frag = frag_more (insn_size * 2); 2457 2458 if ((relocatable) && (insn->rtype != BFD_RELOC_NONE)) 2459 { 2460 reloc_howto_type *reloc_howto; 2461 int size; 2462 2463 reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype); 2464 2465 if (!reloc_howto) 2466 abort (); 2467 2468 size = bfd_get_reloc_size (reloc_howto); 2469 2470 if (size < 1 || size > 4) 2471 abort (); 2472 2473 fix_new_exp (frag_now, this_frag - frag_now->fr_literal, 2474 size, &insn->exp, reloc_howto->pc_relative, 2475 insn->rtype); 2476 } 2477 } 2478 2479 /* Verify a 2-byte code alignment. */ 2480 addr_mod = frag_now_fix () & 1; 2481 if (frag_now->has_code && frag_now->insn_addr != addr_mod) 2482 as_bad (_("instruction address is not a multiple of 2")); 2483 frag_now->insn_addr = addr_mod; 2484 frag_now->has_code = 1; 2485 2486 /* Write the instruction encoding to frag. */ 2487 for (i = 0; i < insn_size; i++) 2488 { 2489 md_number_to_chars (this_frag, (valueT) words[i], 2); 2490 this_frag += 2; 2491 } 2492} 2493 2494/* Actually assemble an instruction. */ 2495 2496static void 2497cr16_assemble (const char *op, char *param) 2498{ 2499 ins cr16_ins; 2500 2501 /* Find the instruction. */ 2502 instruction = (const inst *) hash_find (cr16_inst_hash, op); 2503 if (instruction == NULL) 2504 { 2505 as_bad (_("Unknown opcode: `%s'"), op); 2506 return; 2507 } 2508 2509 /* Tie dwarf2 debug info to the address at the start of the insn. */ 2510 dwarf2_emit_insn (0); 2511 2512 /* Parse the instruction's operands. */ 2513 parse_insn (&cr16_ins, param); 2514 2515 /* Assemble the instruction - return upon failure. */ 2516 if (assemble_insn (op, &cr16_ins) == 0) 2517 return; 2518 2519 /* Print the instruction. */ 2520 print_insn (&cr16_ins); 2521} 2522 2523/* This is the guts of the machine-dependent assembler. OP points to a 2524 machine dependent instruction. This function is supposed to emit 2525 the frags/bytes it assembles to. */ 2526 2527void 2528md_assemble (char *op) 2529{ 2530 ins cr16_ins; 2531 char *param, param1[32]; 2532 2533 /* Reset global variables for a new instruction. */ 2534 reset_vars (op); 2535 2536 /* Strip the mnemonic. */ 2537 for (param = op; *param != 0 && !ISSPACE (*param); param++) 2538 ; 2539 *param++ = '\0'; 2540 2541 /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */ 2542 if (is_bcc_insn (op)) 2543 { 2544 strcpy (param1, get_b_cc (op)); 2545 strcat (param1,","); 2546 strcat (param1, param); 2547 param = (char *) ¶m1; 2548 cr16_assemble ("b", param); 2549 return; 2550 } 2551 2552 /* Checking the cinv options and adjust the mnemonic by removing the 2553 extra white spaces. */ 2554 if (streq ("cinv", op)) 2555 { 2556 /* Validate the cinv options. */ 2557 check_cinv_options (param); 2558 strcat (op, param); 2559 } 2560 2561 /* MAPPING - SHIFT INSN, if imm4/imm16 positive values 2562 lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg 2563 as CR16 core doesn't support lsh[b/w] right shift operaions. */ 2564 if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op)) 2565 && (param [0] == '$')) 2566 { 2567 strcpy (param1, param); 2568 /* Find the instruction. */ 2569 instruction = (const inst *) hash_find (cr16_inst_hash, op); 2570 parse_operands (&cr16_ins, param1); 2571 if (((&cr16_ins)->arg[0].type == arg_ic) 2572 && ((&cr16_ins)->arg[0].constant >= 0)) 2573 { 2574 if (streq ("lshb", op)) 2575 cr16_assemble ("ashub", param); 2576 else if (streq ("lshd", op)) 2577 cr16_assemble ("ashud", param); 2578 else 2579 cr16_assemble ("ashuw", param); 2580 return; 2581 } 2582 } 2583 2584 cr16_assemble (op, param); 2585} 2586