12017-07-25 Tristan Gingold <gingold@adacore.com> 2 3 * configure: Regenerate. 4 52017-07-23 Jiong Wang <jiong.wang@arm.com> 6 7 Backport from mainline 8 2017-06-06 Jiong Wang <jiong.wang@arm.com> 9 * config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A. 10 (parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on 11 ARMv8-A. 12 (do_co_reg): Allow REG_SP for Rd on ARMv8-A. 13 (do_t_add_sub): Likewise. 14 (do_t_mov_cmp): Likewise. 15 (do_t_tb): Likewise. 16 * testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for 17 ldrsb. 18 * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test. 19 * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test. 20 * testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a. 21 * testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a". 22 * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test. 23 * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test. 24 * testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test. 25 * testsuite/gas/arm/sp-usage-thumb2-relax.s: New test. 26 * testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a. 27 282017-04-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 29 30 Backport from mainline 31 2017-04-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 32 * config/tc-arm.c (arm_regs): Add MVFR2. 33 (do_vmrs): Constraint for MVFR2 and armv8. 34 (do_vmsr): Likewise. 35 * testsuite/gas/arm/armv8-a+fp.d: Update. 36 * testsuite/gas/arm/armv8-a+fp.s: Likewise. 37 * testsuite/gas/arm/vfp-bad.s: Likewise. 38 * testsuite/gas/arm/vfp-bad.l: Likewise. 39 402017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com> 41 42 Backport from mainline 43 2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com> 44 45 * config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS. 46 Forbid MOV.W and MOVW if destination is SP or PC. 47 * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain 48 expectation of LDR not generating a MOVS for low registers and small 49 constants. Add tests of MOVW generation. 50 * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update 51 expected disassembly. 52 532017-06-05 Alan Modra <amodra@gmail.com> 54 55 Apply from master 56 2017-03-15 Nick Clifton <nickc@redhat.com> 57 * config/tc-riscv.c (riscv_pre_output_hook): Fix compile time 58 warning about discarding a const qualifier. 59 602017-04-03 Palmer Dabbelt <palmer@dabbelt.com> 61 62 * config/tc-riscv.c (riscv_clear_subsets): Cast argument to free to 63 avoid const warnings. 64 652017-03-30 Palmer Dabbelt <palmer@dabbelt.com> 66 67 * config/tc-riscv.c (riscv_clear_subsets): New function. 68 (riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to 69 clear RVC when it's been previously set. 70 712017-03-21 Palmer Dabbbelt <palmer@dabbelt.com> 72 73 * config/tc-riscv.c (md_show_usage): Remove defuct -m32, -m64, 74 -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't 75 print an invalid default ISA string. 76 * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options. 77 782017-03-14 Kito Cheng <kito.cheng@gmail.com> 79 80 * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate 81 encoding format, which can accept 0-valued immediates. 82 (riscv_ip): Likewise. 83 842017-03-02 Kuan-Lin Chen <rufus@andestech.com> 85 86 * config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define. 87 882017-03-02 Kuan-Lin Chen <rufus@andestech.com> 89 90 * config/tc-riscv.c (md_apply_fix): Set fx_frag and 91 fx_next->fx_frag for CFA_advance_loc relocations. 92 932017-03-02 Kuan-Lin Chen <rufus@andestech.com> 94 95 * config/tc-riscv.c (md_apply_fix): Compute the correct offsets 96 for CFA relocations. 97 982017-03-27 Alan Modra <amodra@gmail.com> 99 100 PR 21303 101 * testsuite/gas/ppc/pr21303.d, 102 * testsuite/gas/ppc/pr21303.s: New test 103 * testsuite/gas/ppc/ppc.exp: Run it. 104 1052017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 106 107 Backport from mainline 108 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 109 110 * config/tc-s390.c (s390_parse_cpu): Remove S390_INSTR_FLAG_VX2 111 from cpu_table. Remove vx2, and novx2 from cpu_flags. 112 1132017-03-08 Peter Bergner <bergner@vnet.ibm.com> 114 115 * testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option. 116 (objdump): Use the -Mpower8 option. 117 1182017-03-08 Peter Bergner <bergner@vnet.ibm.com> 119 120 Apply from master. 121 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> 122 * testsuite/gas/ppc/power9.d <lnia> New test. 123 * testsuite/gas/ppc/power9.s: Likewise. 124 1252017-03-02 Tristan Gingold <gingold@adacore.com> 126 127 * configure: Regenerate. 128 1292017-03-02 Tristan Gingold <gingold@adacore.com> 130 131 * configure: Regenerate. 132 1332017-02-28 Alan Modra <amodra@gmail.com> 134 135 * config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define. 136 1372017-02-28 Alan Modra <amodra@gmail.com> 138 139 * config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis. 140 (md_apply_fix): Remove fx_subsy check. Move code converting to 141 pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code 142 emiiting errors on seeing fx_pcrel set on unexpected relocs, as 143 that is done now by the generic code via.. 144 * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define. 145 (TC_VALIDATE_FIX_SUB): Define. 146 1472017-02-27 Richard Sandiford <richard.sandiford@arm.com> 148 149 * doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum. 150 * config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q 151 to be used with SVE registers. 152 (parse_operands): Handle new SVE operands. 153 (aarch64_features): Make "sve" require F16 rather than FP. Also 154 require COMPNUM. 155 * testsuite/gas/aarch64/sve.s: Add tests for new instructions. 156 Include compnum tests. 157 * testsuite/gas/aarch64/sve.d: Update accordingly. 158 * testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions. 159 * testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also 160 update expected output for new FMOV and MOV alternatives. 161 1622017-02-27 Richard Sandiford <richard.sandiford@arm.com> 163 164 * doc/c-aarch64.texi: Add a "compnum" entry. 165 * config/tc-aarch64.c (aarch64_features): Likewise, 166 * testsuite/gas/aarch64/advsimd-compnum.s: New test. 167 * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. 168 1692017-02-27 Richard Sandiford <richard.sandiford@arm.com> 170 171 * testsuite/gas/aarch64/sve-sysreg.s, 172 testsuite/gas/aarch64/sve-sysreg.d, 173 testsuite/gas/aarch64/sve-sysreg-invalid.d, 174 testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests. 175 1762017-02-27 Richard Sandiford <richard.sandiford@arm.com> 177 178 * doc/c-aarch64.texi: Fix sve entry. 179 1802017-02-27 Szabolcs Nagy <szabolcs.nagy@arm.com> 181 182 * config/tc-aarch64.c (aarch64_features): Add rcpc. 183 * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. 184 * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... 185 * testsuite/gas/aarch64/ldst-rcpc.d: This. 186 * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... 187 * testsuite/gas/aarch64/ldst-rcpc.s: This. 188 * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test. 189 1902017-02-14 Alan Modra <amodra@gmail.com> 191 192 * testsuite/gas/ppc/cell.s: Correct invalid registers. 193 * testsuite/gas/ppc/vle-simple-1.s: Likewise. 194 * testsuite/gas/ppc/vle-simple-2.s: Likewise. 195 1962017-02-10 Nicholas Piggin <npiggin@gmail.com> 197 198 * testsuite/gas/ppc/power9.d <scv, rfscv>: New tests. 199 2002017-01-30 Maciej W. Rozycki <macro@imgtec.com> 201 202 * config/tc-mips.c (mips_ignore_branch_isa): New variable. 203 (options): Add OPTION_IGNORE_BRANCH_ISA and 204 OPTION_NO_IGNORE_BRANCH_ISA enum values. 205 (md_longopts): Add "mignore-branch-isa" and 206 "mno-ignore-branch-isa" options. 207 (md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and 208 OPTION_NO_IGNORE_BRANCH_ISA. 209 (fix_bad_cross_mode_branch_p): Return FALSE if 210 `mips_ignore_branch_isa' has been set. 211 (md_show_usage): Add `-mignore-branch-isa' and 212 `-mno-ignore-branch-isa'. 213 214 * doc/as.texinfo (Target MIPS options): Add 215 `-mignore-branch-isa' and `-mno-ignore-branch-isa' options. 216 (-mignore-branch-isa, -mno-ignore-branch-isa): New options. 217 * doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and 218 `-mno-ignore-branch-isa' options. 219 220 * testsuite/gas/mips/branch-local-ignore-2.d: New test. 221 * testsuite/gas/mips/branch-local-ignore-3.d: New test. 222 * testsuite/gas/mips/branch-local-ignore-n32-2.d: New test. 223 * testsuite/gas/mips/branch-local-ignore-n32-3.d: New test. 224 * testsuite/gas/mips/branch-local-ignore-n64-2.d: New test. 225 * testsuite/gas/mips/branch-local-ignore-n64-3.d: New test. 226 * testsuite/gas/mips/mips.exp: Run the new tests. 227 2282017-01-30 Maciej W. Rozycki <macro@imgtec.com> 229 230 * testsuite/gas/mips/branch-local-2.d: New test. 231 * testsuite/gas/mips/branch-local-3.d: New test. 232 * testsuite/gas/mips/branch-local-n32-2.d: New test. 233 * testsuite/gas/mips/branch-local-n32-3.d: New test. 234 * testsuite/gas/mips/branch-local-n64-2.d: New test. 235 * testsuite/gas/mips/branch-local-n64-3.d: New test. 236 * testsuite/gas/mips/mips.exp: Fold corresponding list tests 237 into the new tests. 238 2392017-01-24 Sebastian Huber <sebastian.huber@embedded-brains.de> 240 241 * configure.tgt (riscv*-*-*): Remove em=linux. 242 2432017-01-18 Maciej W. Rozycki <macro@imgtec.com> 244 245 PR gas/20649 246 * config/tc-mips.c (pic_need_relax): Don't check for linkonce 247 symbols, remove the `segtype' parameter. 248 (mips_frob_file, md_estimate_size_before_relax): Adjust 249 accordingly. 250 (s_is_linkonce): Add an explanatory comment. 251 * testsuite/gas/mips/comdat-reloc.d: New test. 252 * testsuite/gas/mips/comdat-reloc.s: New test source. 253 * testsuite/gas/mips/mips.exp: Run the new test. 254 2552017-01-18 Bernhard Rosenkranzer <bero@lindev.ch> 256 257 PR 21059 258 * config/bfin-lex.l: Support processing with flex 2.6.3. 259 * itbl-lex.l: Likewise. 260 2612017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> 262 263 * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. 264 (cpu_noarch): Add noavx512_vpopcntdq. 265 * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. 266 * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. 267 * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. 268 * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. 269 * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. 270 * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. 271 * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. 272 * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. 273 2742017-01-09 Andrew Waterman <andrew@sifive.com> 275 276 * config/tc-riscv.c (append_insn): Don't eagerly apply relocations 277 against constants. 278 (md_apply_fix): Mark relocations against constants as "done." 279 2802017-01-09 Andrew Waterman <andrew@sifive.com> 281 282 * config/tc-riscv.c (append_insn): Don't eagerly apply relocations 283 against constants. 284 (md_apply_fix): Mark relocations against constants as "done." 285 2862017-01-09 Palmer Dabbelt <palmer@dabbelt.com> 287 Kito Cheng <kito.cheng@gmail.com> 288 289 * emulparams/elf32lriscv-defs.sh (INITIAL_READONLY_SECTIONS): 290 Removed. 291 (SDATA_START_SYMBOLS): Likewise. 292 2932017-01-09 Andrew Waterman <andrew@sifive.com> 294 295 * config/tc-riscv.c (relaxed_branch_length): Use the long 296 sequence when the target is a weak symbol. 297 2982017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> 299 300 * config/tc-aarch64.c (aarch64_features): Add rcpc. 301 * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. 302 * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... 303 * testsuite/gas/aarch64/ldst-rcpc.d: This. 304 * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... 305 * testsuite/gas/aarch64/ldst-rcpc.s: This. 306 * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test. 307 3082017-01-04 Norm Jacobs <norm.jacobs@oracle.com> 309 310 PR gas/20992 311 * configure.tgt: Treat sparcv9 as sparc64. 312 3132017-01-03 Kito Cheng <kito.cheng@gmail.com> 314 315 * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA 316 extension. 317 (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is 318 enabled and no other ABI is specified. 319 3202017-01-03 Dimitar Dimitrov <dimitar@dinux.eu> 321 322 * config/tc-pru.c (md_number_to_chars): Fix parameter to be 323 valueT, as declared in tc.h. 324 (md_apply_fix): Fix to work on 32-bit hosts. 325>>>>>>> 0115611... RISC-V/GAS: Correct branch relaxation for weak symbols. 326 3272017-01-02 Alan Modra <amodra@gmail.com> 328 329 Update year range in copyright notice of all files. 330 331For older changes see ChangeLog-2016 332 333Copyright (C) 2017 Free Software Foundation, Inc. 334 335Copying and distribution of this file, with or without modification, 336are permitted in any medium without royalty provided the copyright 337notice and this notice are preserved. 338 339Local Variables: 340mode: change-log 341left-margin: 8 342fill-column: 74 343version-control: never 344End: 345