1/* BFD back-end for Renesas H8/300 COFF binaries. 2 Copyright (C) 1990-2017 Free Software Foundation, Inc. 3 Written by Steve Chamberlain, <sac@cygnus.com>. 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22#include "sysdep.h" 23#include "bfd.h" 24#include "libbfd.h" 25#include "bfdlink.h" 26#include "genlink.h" 27#include "coff/h8300.h" 28#include "coff/internal.h" 29#include "libcoff.h" 30#include "libiberty.h" 31 32#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (1) 33 34/* We derive a hash table from the basic BFD hash table to 35 hold entries in the function vector. Aside from the 36 info stored by the basic hash table, we need the offset 37 of a particular entry within the hash table as well as 38 the offset where we'll add the next entry. */ 39 40struct funcvec_hash_entry 41 { 42 /* The basic hash table entry. */ 43 struct bfd_hash_entry root; 44 45 /* The offset within the vectors section where 46 this entry lives. */ 47 bfd_vma offset; 48 }; 49 50struct funcvec_hash_table 51 { 52 /* The basic hash table. */ 53 struct bfd_hash_table root; 54 55 bfd *abfd; 56 57 /* Offset at which we'll add the next entry. */ 58 unsigned int offset; 59 }; 60 61 62/* To lookup a value in the function vector hash table. */ 63#define funcvec_hash_lookup(table, string, create, copy) \ 64 ((struct funcvec_hash_entry *) \ 65 bfd_hash_lookup (&(table)->root, (string), (create), (copy))) 66 67/* The derived h8300 COFF linker table. Note it's derived from 68 the generic linker hash table, not the COFF backend linker hash 69 table! We use this to attach additional data structures we 70 need while linking on the h8300. */ 71struct h8300_coff_link_hash_table { 72 /* The main hash table. */ 73 struct generic_link_hash_table root; 74 75 /* Section for the vectors table. This gets attached to a 76 random input bfd, we keep it here for easy access. */ 77 asection *vectors_sec; 78 79 /* Hash table of the functions we need to enter into the function 80 vector. */ 81 struct funcvec_hash_table *funcvec_hash_table; 82}; 83 84static struct bfd_link_hash_table *h8300_coff_link_hash_table_create (bfd *); 85 86/* Get the H8/300 COFF linker hash table from a link_info structure. */ 87 88#define h8300_coff_hash_table(p) \ 89 ((struct h8300_coff_link_hash_table *) ((coff_hash_table (p)))) 90 91/* Initialize fields within a funcvec hash table entry. Called whenever 92 a new entry is added to the funcvec hash table. */ 93 94static struct bfd_hash_entry * 95funcvec_hash_newfunc (struct bfd_hash_entry *entry, 96 struct bfd_hash_table *gen_table, 97 const char *string) 98{ 99 struct funcvec_hash_entry *ret; 100 struct funcvec_hash_table *table; 101 102 ret = (struct funcvec_hash_entry *) entry; 103 table = (struct funcvec_hash_table *) gen_table; 104 105 /* Allocate the structure if it has not already been allocated by a 106 subclass. */ 107 if (ret == NULL) 108 ret = ((struct funcvec_hash_entry *) 109 bfd_hash_allocate (gen_table, 110 sizeof (struct funcvec_hash_entry))); 111 if (ret == NULL) 112 return NULL; 113 114 /* Call the allocation method of the superclass. */ 115 ret = ((struct funcvec_hash_entry *) 116 bfd_hash_newfunc ((struct bfd_hash_entry *) ret, gen_table, string)); 117 118 if (ret == NULL) 119 return NULL; 120 121 /* Note where this entry will reside in the function vector table. */ 122 ret->offset = table->offset; 123 124 /* Bump the offset at which we store entries in the function 125 vector. We'd like to bump up the size of the vectors section, 126 but it's not easily available here. */ 127 switch (bfd_get_mach (table->abfd)) 128 { 129 case bfd_mach_h8300: 130 case bfd_mach_h8300hn: 131 case bfd_mach_h8300sn: 132 table->offset += 2; 133 break; 134 case bfd_mach_h8300h: 135 case bfd_mach_h8300s: 136 table->offset += 4; 137 break; 138 default: 139 return NULL; 140 } 141 142 /* Everything went OK. */ 143 return (struct bfd_hash_entry *) ret; 144} 145 146/* Initialize the function vector hash table. */ 147 148static bfd_boolean 149funcvec_hash_table_init (struct funcvec_hash_table *table, 150 bfd *abfd, 151 struct bfd_hash_entry *(*newfunc) 152 (struct bfd_hash_entry *, 153 struct bfd_hash_table *, 154 const char *), 155 unsigned int entsize) 156{ 157 /* Initialize our local fields, then call the generic initialization 158 routine. */ 159 table->offset = 0; 160 table->abfd = abfd; 161 return (bfd_hash_table_init (&table->root, newfunc, entsize)); 162} 163 164/* Create the derived linker hash table. We use a derived hash table 165 basically to hold "static" information during an H8/300 coff link 166 without using static variables. */ 167 168static struct bfd_link_hash_table * 169h8300_coff_link_hash_table_create (bfd *abfd) 170{ 171 struct h8300_coff_link_hash_table *ret; 172 bfd_size_type amt = sizeof (struct h8300_coff_link_hash_table); 173 174 ret = (struct h8300_coff_link_hash_table *) bfd_zmalloc (amt); 175 if (ret == NULL) 176 return NULL; 177 if (!_bfd_link_hash_table_init (&ret->root.root, abfd, 178 _bfd_generic_link_hash_newfunc, 179 sizeof (struct generic_link_hash_entry))) 180 { 181 free (ret); 182 return NULL; 183 } 184 185 return &ret->root.root; 186} 187 188/* Special handling for H8/300 relocs. 189 We only come here for pcrel stuff and return normally if not an -r link. 190 When doing -r, we can't do any arithmetic for the pcrel stuff, because 191 the code in reloc.c assumes that we can manipulate the targets of 192 the pcrel branches. This isn't so, since the H8/300 can do relaxing, 193 which means that the gap after the instruction may not be enough to 194 contain the offset required for the branch, so we have to use only 195 the addend until the final link. */ 196 197static bfd_reloc_status_type 198special (bfd * abfd ATTRIBUTE_UNUSED, 199 arelent * reloc_entry ATTRIBUTE_UNUSED, 200 asymbol * symbol ATTRIBUTE_UNUSED, 201 void * data ATTRIBUTE_UNUSED, 202 asection * input_section ATTRIBUTE_UNUSED, 203 bfd * output_bfd, 204 char ** error_message ATTRIBUTE_UNUSED) 205{ 206 if (output_bfd == (bfd *) NULL) 207 return bfd_reloc_continue; 208 209 /* Adjust the reloc address to that in the output section. */ 210 reloc_entry->address += input_section->output_offset; 211 return bfd_reloc_ok; 212} 213 214static reloc_howto_type howto_table[] = 215{ 216 HOWTO (R_RELBYTE, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, special, "8", FALSE, 0x000000ff, 0x000000ff, FALSE), 217 HOWTO (R_RELWORD, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, special, "16", FALSE, 0x0000ffff, 0x0000ffff, FALSE), 218 HOWTO (R_RELLONG, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, special, "32", FALSE, 0xffffffff, 0xffffffff, FALSE), 219 HOWTO (R_PCRBYTE, 0, 0, 8, TRUE, 0, complain_overflow_signed, special, "DISP8", FALSE, 0x000000ff, 0x000000ff, TRUE), 220 HOWTO (R_PCRWORD, 0, 1, 16, TRUE, 0, complain_overflow_signed, special, "DISP16", FALSE, 0x0000ffff, 0x0000ffff, TRUE), 221 HOWTO (R_PCRLONG, 0, 2, 32, TRUE, 0, complain_overflow_signed, special, "DISP32", FALSE, 0xffffffff, 0xffffffff, TRUE), 222 HOWTO (R_MOV16B1, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, special, "relaxable mov.b:16", FALSE, 0x0000ffff, 0x0000ffff, FALSE), 223 HOWTO (R_MOV16B2, 0, 1, 8, FALSE, 0, complain_overflow_bitfield, special, "relaxed mov.b:16", FALSE, 0x000000ff, 0x000000ff, FALSE), 224 HOWTO (R_JMP1, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, special, "16/pcrel", FALSE, 0x0000ffff, 0x0000ffff, FALSE), 225 HOWTO (R_JMP2, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, special, "pcrecl/16", FALSE, 0x000000ff, 0x000000ff, FALSE), 226 HOWTO (R_JMPL1, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, special, "24/pcrell", FALSE, 0x00ffffff, 0x00ffffff, FALSE), 227 HOWTO (R_JMPL2, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, special, "pc8/24", FALSE, 0x000000ff, 0x000000ff, FALSE), 228 HOWTO (R_MOV24B1, 0, 1, 32, FALSE, 0, complain_overflow_bitfield, special, "relaxable mov.b:24", FALSE, 0xffffffff, 0xffffffff, FALSE), 229 HOWTO (R_MOV24B2, 0, 1, 8, FALSE, 0, complain_overflow_bitfield, special, "relaxed mov.b:24", FALSE, 0x0000ffff, 0x0000ffff, FALSE), 230 231 /* An indirect reference to a function. This causes the function's address 232 to be added to the function vector in lo-mem and puts the address of 233 the function vector's entry in the jsr instruction. */ 234 HOWTO (R_MEM_INDIRECT, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, special, "8/indirect", FALSE, 0x000000ff, 0x000000ff, FALSE), 235 236 /* Internal reloc for relaxing. This is created when a 16-bit pc-relative 237 branch is turned into an 8-bit pc-relative branch. */ 238 HOWTO (R_PCRWORD_B, 0, 0, 8, TRUE, 0, complain_overflow_bitfield, special, "relaxed bCC:16", FALSE, 0x000000ff, 0x000000ff, FALSE), 239 240 HOWTO (R_MOVL1, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,special, "32/24 relaxable move", FALSE, 0xffffffff, 0xffffffff, FALSE), 241 242 HOWTO (R_MOVL2, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, special, "32/24 relaxed move", FALSE, 0x0000ffff, 0x0000ffff, FALSE), 243 244 HOWTO (R_BCC_INV, 0, 0, 8, TRUE, 0, complain_overflow_signed, special, "DISP8 inverted", FALSE, 0x000000ff, 0x000000ff, TRUE), 245 246 HOWTO (R_JMP_DEL, 0, 0, 8, TRUE, 0, complain_overflow_signed, special, "Deleted jump", FALSE, 0x000000ff, 0x000000ff, TRUE), 247}; 248 249/* Turn a howto into a reloc number. */ 250 251#define SELECT_RELOC(x,howto) \ 252 { x.r_type = select_reloc (howto); } 253 254#define BADMAG(x) (H8300BADMAG (x) && H8300HBADMAG (x) && H8300SBADMAG (x) \ 255 && H8300HNBADMAG(x) && H8300SNBADMAG(x)) 256#define H8300 1 /* Customize coffcode.h */ 257#define __A_MAGIC_SET__ 258 259/* Code to swap in the reloc. */ 260#define SWAP_IN_RELOC_OFFSET H_GET_32 261#define SWAP_OUT_RELOC_OFFSET H_PUT_32 262#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \ 263 dst->r_stuff[0] = 'S'; \ 264 dst->r_stuff[1] = 'C'; 265 266static int 267select_reloc (reloc_howto_type *howto) 268{ 269 return howto->type; 270} 271 272/* Code to turn a r_type into a howto ptr, uses the above howto table. */ 273 274static void 275rtype2howto (arelent *internal, struct internal_reloc *dst) 276{ 277 switch (dst->r_type) 278 { 279 case R_RELBYTE: 280 internal->howto = howto_table + 0; 281 break; 282 case R_RELWORD: 283 internal->howto = howto_table + 1; 284 break; 285 case R_RELLONG: 286 internal->howto = howto_table + 2; 287 break; 288 case R_PCRBYTE: 289 internal->howto = howto_table + 3; 290 break; 291 case R_PCRWORD: 292 internal->howto = howto_table + 4; 293 break; 294 case R_PCRLONG: 295 internal->howto = howto_table + 5; 296 break; 297 case R_MOV16B1: 298 internal->howto = howto_table + 6; 299 break; 300 case R_MOV16B2: 301 internal->howto = howto_table + 7; 302 break; 303 case R_JMP1: 304 internal->howto = howto_table + 8; 305 break; 306 case R_JMP2: 307 internal->howto = howto_table + 9; 308 break; 309 case R_JMPL1: 310 internal->howto = howto_table + 10; 311 break; 312 case R_JMPL2: 313 internal->howto = howto_table + 11; 314 break; 315 case R_MOV24B1: 316 internal->howto = howto_table + 12; 317 break; 318 case R_MOV24B2: 319 internal->howto = howto_table + 13; 320 break; 321 case R_MEM_INDIRECT: 322 internal->howto = howto_table + 14; 323 break; 324 case R_PCRWORD_B: 325 internal->howto = howto_table + 15; 326 break; 327 case R_MOVL1: 328 internal->howto = howto_table + 16; 329 break; 330 case R_MOVL2: 331 internal->howto = howto_table + 17; 332 break; 333 case R_BCC_INV: 334 internal->howto = howto_table + 18; 335 break; 336 case R_JMP_DEL: 337 internal->howto = howto_table + 19; 338 break; 339 default: 340 internal->howto = NULL; 341 break; 342 } 343} 344 345#define RTYPE2HOWTO(internal, relocentry) rtype2howto (internal, relocentry) 346 347/* Perform any necessary magic to the addend in a reloc entry. */ 348 349#define CALC_ADDEND(abfd, symbol, ext_reloc, cache_ptr) \ 350 cache_ptr->addend = ext_reloc.r_offset; 351 352#define RELOC_PROCESSING(relent,reloc,symbols,abfd,section) \ 353 reloc_processing (relent, reloc, symbols, abfd, section) 354 355static void 356reloc_processing (arelent *relent, struct internal_reloc *reloc, 357 asymbol **symbols, bfd *abfd, asection *section) 358{ 359 relent->address = reloc->r_vaddr; 360 rtype2howto (relent, reloc); 361 362 if (((int) reloc->r_symndx) > 0) 363 relent->sym_ptr_ptr = symbols + obj_convert (abfd)[reloc->r_symndx]; 364 else 365 relent->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr; 366 367 relent->addend = reloc->r_offset; 368 relent->address -= section->vma; 369} 370 371static bfd_boolean 372h8300_symbol_address_p (bfd *abfd, asection *input_section, bfd_vma address) 373{ 374 asymbol **s; 375 376 s = _bfd_generic_link_get_symbols (abfd); 377 BFD_ASSERT (s != (asymbol **) NULL); 378 379 /* Search all the symbols for one in INPUT_SECTION with 380 address ADDRESS. */ 381 while (*s) 382 { 383 asymbol *p = *s; 384 385 if (p->section == input_section 386 && (input_section->output_section->vma 387 + input_section->output_offset 388 + p->value) == address) 389 return TRUE; 390 s++; 391 } 392 return FALSE; 393} 394 395/* If RELOC represents a relaxable instruction/reloc, change it into 396 the relaxed reloc, notify the linker that symbol addresses 397 have changed (bfd_perform_slip) and return how much the current 398 section has shrunk by. 399 400 FIXME: Much of this code has knowledge of the ordering of entries 401 in the howto table. This needs to be fixed. */ 402 403static int 404h8300_reloc16_estimate (bfd *abfd, asection *input_section, arelent *reloc, 405 unsigned int shrink, struct bfd_link_info *link_info) 406{ 407 bfd_vma value; 408 bfd_vma dot; 409 bfd_vma gap; 410 static asection *last_input_section = NULL; 411 static arelent *last_reloc = NULL; 412 413 /* The address of the thing to be relocated will have moved back by 414 the size of the shrink - but we don't change reloc->address here, 415 since we need it to know where the relocation lives in the source 416 uncooked section. */ 417 bfd_vma address = reloc->address - shrink; 418 419 if (input_section != last_input_section) 420 last_reloc = NULL; 421 422 /* Only examine the relocs which might be relaxable. */ 423 switch (reloc->howto->type) 424 { 425 /* This is the 16-/24-bit absolute branch which could become an 426 8-bit pc-relative branch. */ 427 case R_JMP1: 428 case R_JMPL1: 429 /* Get the address of the target of this branch. */ 430 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 431 432 /* Get the address of the next instruction (not the reloc). */ 433 dot = (input_section->output_section->vma 434 + input_section->output_offset + address); 435 436 /* Adjust for R_JMP1 vs R_JMPL1. */ 437 dot += (reloc->howto->type == R_JMP1 ? 1 : 2); 438 439 /* Compute the distance from this insn to the branch target. */ 440 gap = value - dot; 441 442 /* If the distance is within -128..+128 inclusive, then we can relax 443 this jump. +128 is valid since the target will move two bytes 444 closer if we do relax this branch. */ 445 if ((int) gap >= -128 && (int) gap <= 128) 446 { 447 bfd_byte code; 448 449 if (!bfd_get_section_contents (abfd, input_section, & code, 450 reloc->address, 1)) 451 break; 452 code = bfd_get_8 (abfd, & code); 453 454 /* It's possible we may be able to eliminate this branch entirely; 455 if the previous instruction is a branch around this instruction, 456 and there's no label at this instruction, then we can reverse 457 the condition on the previous branch and eliminate this jump. 458 459 original: new: 460 bCC lab1 bCC' lab2 461 jmp lab2 462 lab1: lab1: 463 464 This saves 4 bytes instead of two, and should be relatively 465 common. 466 467 Only perform this optimisation for jumps (code 0x5a) not 468 subroutine calls, as otherwise it could transform: 469 470 mov.w r0,r0 471 beq .L1 472 jsr @_bar 473 .L1: rts 474 _bar: rts 475 into: 476 mov.w r0,r0 477 bne _bar 478 rts 479 _bar: rts 480 481 which changes the call (jsr) into a branch (bne). */ 482 if (code == 0x5a 483 && gap <= 126 484 && last_reloc 485 && last_reloc->howto->type == R_PCRBYTE) 486 { 487 bfd_vma last_value; 488 last_value = bfd_coff_reloc16_get_value (last_reloc, link_info, 489 input_section) + 1; 490 491 if (last_value == dot + 2 492 && last_reloc->address + 1 == reloc->address 493 && !h8300_symbol_address_p (abfd, input_section, dot - 2)) 494 { 495 reloc->howto = howto_table + 19; 496 last_reloc->howto = howto_table + 18; 497 last_reloc->sym_ptr_ptr = reloc->sym_ptr_ptr; 498 last_reloc->addend = reloc->addend; 499 shrink += 4; 500 bfd_perform_slip (abfd, 4, input_section, address); 501 break; 502 } 503 } 504 505 /* Change the reloc type. */ 506 reloc->howto = reloc->howto + 1; 507 508 /* This shrinks this section by two bytes. */ 509 shrink += 2; 510 bfd_perform_slip (abfd, 2, input_section, address); 511 } 512 break; 513 514 /* This is the 16-bit pc-relative branch which could become an 8-bit 515 pc-relative branch. */ 516 case R_PCRWORD: 517 /* Get the address of the target of this branch, add one to the value 518 because the addend field in PCrel jumps is off by -1. */ 519 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section) + 1; 520 521 /* Get the address of the next instruction if we were to relax. */ 522 dot = input_section->output_section->vma + 523 input_section->output_offset + address; 524 525 /* Compute the distance from this insn to the branch target. */ 526 gap = value - dot; 527 528 /* If the distance is within -128..+128 inclusive, then we can relax 529 this jump. +128 is valid since the target will move two bytes 530 closer if we do relax this branch. */ 531 if ((int) gap >= -128 && (int) gap <= 128) 532 { 533 /* Change the reloc type. */ 534 reloc->howto = howto_table + 15; 535 536 /* This shrinks this section by two bytes. */ 537 shrink += 2; 538 bfd_perform_slip (abfd, 2, input_section, address); 539 } 540 break; 541 542 /* This is a 16-bit absolute address in a mov.b insn, which can 543 become an 8-bit absolute address if it's in the right range. */ 544 case R_MOV16B1: 545 /* Get the address of the data referenced by this mov.b insn. */ 546 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 547 value = bfd_h8300_pad_address (abfd, value); 548 549 /* If the address is in the top 256 bytes of the address space 550 then we can relax this instruction. */ 551 if (value >= 0xffffff00u) 552 { 553 /* Change the reloc type. */ 554 reloc->howto = reloc->howto + 1; 555 556 /* This shrinks this section by two bytes. */ 557 shrink += 2; 558 bfd_perform_slip (abfd, 2, input_section, address); 559 } 560 break; 561 562 /* Similarly for a 24-bit absolute address in a mov.b. Note that 563 if we can't relax this into an 8-bit absolute, we'll fall through 564 and try to relax it into a 16-bit absolute. */ 565 case R_MOV24B1: 566 /* Get the address of the data referenced by this mov.b insn. */ 567 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 568 value = bfd_h8300_pad_address (abfd, value); 569 570 if (value >= 0xffffff00u) 571 { 572 /* Change the reloc type. */ 573 reloc->howto = reloc->howto + 1; 574 575 /* This shrinks this section by four bytes. */ 576 shrink += 4; 577 bfd_perform_slip (abfd, 4, input_section, address); 578 579 /* Done with this reloc. */ 580 break; 581 } 582 /* Fall through. */ 583 584 /* This is a 24-/32-bit absolute address in a mov insn, which can 585 become an 16-bit absolute address if it's in the right range. */ 586 case R_MOVL1: 587 /* Get the address of the data referenced by this mov insn. */ 588 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 589 value = bfd_h8300_pad_address (abfd, value); 590 591 /* If the address is a sign-extended 16-bit value then we can 592 relax this instruction. */ 593 if (value <= 0x7fff || value >= 0xffff8000u) 594 { 595 /* Change the reloc type. */ 596 reloc->howto = howto_table + 17; 597 598 /* This shrinks this section by two bytes. */ 599 shrink += 2; 600 bfd_perform_slip (abfd, 2, input_section, address); 601 } 602 break; 603 604 /* No other reloc types represent relaxing opportunities. */ 605 default: 606 break; 607 } 608 609 last_reloc = reloc; 610 last_input_section = input_section; 611 return shrink; 612} 613 614/* Handle relocations for the H8/300, including relocs for relaxed 615 instructions. 616 617 FIXME: Not all relocations check for overflow! */ 618 619static void 620h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, 621 struct bfd_link_order *link_order, arelent *reloc, 622 bfd_byte *data, unsigned int *src_ptr, 623 unsigned int *dst_ptr) 624{ 625 unsigned int src_address = *src_ptr; 626 unsigned int dst_address = *dst_ptr; 627 asection *input_section = link_order->u.indirect.section; 628 bfd_vma value; 629 bfd_vma dot; 630 int gap, tmp; 631 unsigned char temp_code; 632 633 switch (reloc->howto->type) 634 { 635 /* Generic 8-bit pc-relative relocation. */ 636 case R_PCRBYTE: 637 /* Get the address of the target of this branch. */ 638 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 639 640 dot = (input_section->output_offset 641 + dst_address 642 + link_order->u.indirect.section->output_section->vma); 643 644 gap = value - dot; 645 646 /* Sanity check. */ 647 if (gap < -128 || gap > 126) 648 (*link_info->callbacks->reloc_overflow) 649 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 650 reloc->howto->name, reloc->addend, input_section->owner, 651 input_section, reloc->address); 652 653 /* Everything looks OK. Apply the relocation and update the 654 src/dst address appropriately. */ 655 bfd_put_8 (abfd, gap, data + dst_address); 656 dst_address++; 657 src_address++; 658 659 /* All done. */ 660 break; 661 662 /* Generic 16-bit pc-relative relocation. */ 663 case R_PCRWORD: 664 /* Get the address of the target of this branch. */ 665 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 666 667 /* Get the address of the instruction (not the reloc). */ 668 dot = (input_section->output_offset 669 + dst_address 670 + link_order->u.indirect.section->output_section->vma + 1); 671 672 gap = value - dot; 673 674 /* Sanity check. */ 675 if (gap > 32766 || gap < -32768) 676 (*link_info->callbacks->reloc_overflow) 677 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 678 reloc->howto->name, reloc->addend, input_section->owner, 679 input_section, reloc->address); 680 681 /* Everything looks OK. Apply the relocation and update the 682 src/dst address appropriately. */ 683 bfd_put_16 (abfd, (bfd_vma) gap, data + dst_address); 684 dst_address += 2; 685 src_address += 2; 686 687 /* All done. */ 688 break; 689 690 /* Generic 8-bit absolute relocation. */ 691 case R_RELBYTE: 692 /* Get the address of the object referenced by this insn. */ 693 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 694 695 bfd_put_8 (abfd, value & 0xff, data + dst_address); 696 dst_address += 1; 697 src_address += 1; 698 699 /* All done. */ 700 break; 701 702 /* Various simple 16-bit absolute relocations. */ 703 case R_MOV16B1: 704 case R_JMP1: 705 case R_RELWORD: 706 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 707 bfd_put_16 (abfd, value, data + dst_address); 708 dst_address += 2; 709 src_address += 2; 710 break; 711 712 /* Various simple 24-/32-bit absolute relocations. */ 713 case R_MOV24B1: 714 case R_MOVL1: 715 case R_RELLONG: 716 /* Get the address of the target of this branch. */ 717 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 718 bfd_put_32 (abfd, value, data + dst_address); 719 dst_address += 4; 720 src_address += 4; 721 break; 722 723 /* Another 24-/32-bit absolute relocation. */ 724 case R_JMPL1: 725 /* Get the address of the target of this branch. */ 726 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 727 728 value = ((value & 0x00ffffff) 729 | (bfd_get_32 (abfd, data + src_address) & 0xff000000)); 730 bfd_put_32 (abfd, value, data + dst_address); 731 dst_address += 4; 732 src_address += 4; 733 break; 734 735 /* This is a 24-/32-bit absolute address in one of the following 736 instructions: 737 738 "band", "bclr", "biand", "bild", "bior", "bist", "bixor", 739 "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", "ldc.w", 740 "stc.w" and "mov.[bwl]" 741 742 We may relax this into an 16-bit absolute address if it's in 743 the right range. */ 744 case R_MOVL2: 745 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 746 value = bfd_h8300_pad_address (abfd, value); 747 748 /* Sanity check. */ 749 if (value <= 0x7fff || value >= 0xffff8000u) 750 { 751 /* Insert the 16-bit value into the proper location. */ 752 bfd_put_16 (abfd, value, data + dst_address); 753 754 /* Fix the opcode. For all the instructions that belong to 755 this relaxation, we simply need to turn off bit 0x20 in 756 the previous byte. */ 757 data[dst_address - 1] &= ~0x20; 758 dst_address += 2; 759 src_address += 4; 760 } 761 else 762 (*link_info->callbacks->reloc_overflow) 763 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 764 reloc->howto->name, reloc->addend, input_section->owner, 765 input_section, reloc->address); 766 break; 767 768 /* A 16-bit absolute branch that is now an 8-bit pc-relative branch. */ 769 case R_JMP2: 770 /* Get the address of the target of this branch. */ 771 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 772 773 /* Get the address of the next instruction. */ 774 dot = (input_section->output_offset 775 + dst_address 776 + link_order->u.indirect.section->output_section->vma + 1); 777 778 gap = value - dot; 779 780 /* Sanity check. */ 781 if (gap < -128 || gap > 126) 782 (*link_info->callbacks->reloc_overflow) 783 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 784 reloc->howto->name, reloc->addend, input_section->owner, 785 input_section, reloc->address); 786 787 /* Now fix the instruction itself. */ 788 switch (data[dst_address - 1]) 789 { 790 case 0x5e: 791 /* jsr -> bsr */ 792 bfd_put_8 (abfd, 0x55, data + dst_address - 1); 793 break; 794 case 0x5a: 795 /* jmp -> bra */ 796 bfd_put_8 (abfd, 0x40, data + dst_address - 1); 797 break; 798 799 default: 800 abort (); 801 } 802 803 /* Write out the 8-bit value. */ 804 bfd_put_8 (abfd, gap, data + dst_address); 805 806 dst_address += 1; 807 src_address += 3; 808 809 break; 810 811 /* A 16-bit pc-relative branch that is now an 8-bit pc-relative branch. */ 812 case R_PCRWORD_B: 813 /* Get the address of the target of this branch. */ 814 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 815 816 /* Get the address of the instruction (not the reloc). */ 817 dot = (input_section->output_offset 818 + dst_address 819 + link_order->u.indirect.section->output_section->vma - 1); 820 821 gap = value - dot; 822 823 /* Sanity check. */ 824 if (gap < -128 || gap > 126) 825 (*link_info->callbacks->reloc_overflow) 826 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 827 reloc->howto->name, reloc->addend, input_section->owner, 828 input_section, reloc->address); 829 830 /* Now fix the instruction. */ 831 switch (data[dst_address - 2]) 832 { 833 case 0x58: 834 /* bCC:16 -> bCC:8 */ 835 /* Get the second byte of the original insn, which contains 836 the condition code. */ 837 tmp = data[dst_address - 1]; 838 839 /* Compute the fisrt byte of the relaxed instruction. The 840 original sequence 0x58 0xX0 is relaxed to 0x4X, where X 841 represents the condition code. */ 842 tmp &= 0xf0; 843 tmp >>= 4; 844 tmp |= 0x40; 845 846 /* Write it. */ 847 bfd_put_8 (abfd, tmp, data + dst_address - 2); 848 break; 849 850 case 0x5c: 851 /* bsr:16 -> bsr:8 */ 852 bfd_put_8 (abfd, 0x55, data + dst_address - 2); 853 break; 854 855 default: 856 abort (); 857 } 858 859 /* Output the target. */ 860 bfd_put_8 (abfd, gap, data + dst_address - 1); 861 862 /* We don't advance dst_address -- the 8-bit reloc is applied at 863 dst_address - 1, so the next insn should begin at dst_address. */ 864 src_address += 2; 865 866 break; 867 868 /* Similarly for a 24-bit absolute that is now 8 bits. */ 869 case R_JMPL2: 870 /* Get the address of the target of this branch. */ 871 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 872 873 /* Get the address of the instruction (not the reloc). */ 874 dot = (input_section->output_offset 875 + dst_address 876 + link_order->u.indirect.section->output_section->vma + 2); 877 878 gap = value - dot; 879 880 /* Fix the instruction. */ 881 switch (data[src_address]) 882 { 883 case 0x5e: 884 /* jsr -> bsr */ 885 bfd_put_8 (abfd, 0x55, data + dst_address); 886 break; 887 case 0x5a: 888 /* jmp ->bra */ 889 bfd_put_8 (abfd, 0x40, data + dst_address); 890 break; 891 default: 892 abort (); 893 } 894 895 bfd_put_8 (abfd, gap, data + dst_address + 1); 896 dst_address += 2; 897 src_address += 4; 898 899 break; 900 901 /* This is a 16-bit absolute address in one of the following 902 instructions: 903 904 "band", "bclr", "biand", "bild", "bior", "bist", "bixor", 905 "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and 906 "mov.b" 907 908 We may relax this into an 8-bit absolute address if it's in 909 the right range. */ 910 case R_MOV16B2: 911 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 912 913 /* All instructions with R_H8_DIR16B2 start with 0x6a. */ 914 if (data[dst_address - 2] != 0x6a) 915 abort (); 916 917 temp_code = data[src_address - 1]; 918 919 /* If this is a mov.b instruction, clear the lower nibble, which 920 contains the source/destination register number. */ 921 if ((temp_code & 0x10) != 0x10) 922 temp_code &= 0xf0; 923 924 /* Fix up the opcode. */ 925 switch (temp_code) 926 { 927 case 0x00: 928 /* This is mov.b @aa:16,Rd. */ 929 data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20; 930 break; 931 case 0x80: 932 /* This is mov.b Rs,@aa:16. */ 933 data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30; 934 break; 935 case 0x18: 936 /* This is a bit-maniputation instruction that stores one 937 bit into memory, one of "bclr", "bist", "bnot", "bset", 938 and "bst". */ 939 data[dst_address - 2] = 0x7f; 940 break; 941 case 0x10: 942 /* This is a bit-maniputation instruction that loads one bit 943 from memory, one of "band", "biand", "bild", "bior", 944 "bixor", "bld", "bor", "btst", and "bxor". */ 945 data[dst_address - 2] = 0x7e; 946 break; 947 default: 948 abort (); 949 } 950 951 bfd_put_8 (abfd, value & 0xff, data + dst_address - 1); 952 src_address += 2; 953 break; 954 955 /* This is a 24-bit absolute address in one of the following 956 instructions: 957 958 "band", "bclr", "biand", "bild", "bior", "bist", "bixor", 959 "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and 960 "mov.b" 961 962 We may relax this into an 8-bit absolute address if it's in 963 the right range. */ 964 case R_MOV24B2: 965 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 966 967 /* All instructions with R_MOV24B2 start with 0x6a. */ 968 if (data[dst_address - 2] != 0x6a) 969 abort (); 970 971 temp_code = data[src_address - 1]; 972 973 /* If this is a mov.b instruction, clear the lower nibble, which 974 contains the source/destination register number. */ 975 if ((temp_code & 0x30) != 0x30) 976 temp_code &= 0xf0; 977 978 /* Fix up the opcode. */ 979 switch (temp_code) 980 { 981 case 0x20: 982 /* This is mov.b @aa:24/32,Rd. */ 983 data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20; 984 break; 985 case 0xa0: 986 /* This is mov.b Rs,@aa:24/32. */ 987 data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30; 988 break; 989 case 0x38: 990 /* This is a bit-maniputation instruction that stores one 991 bit into memory, one of "bclr", "bist", "bnot", "bset", 992 and "bst". */ 993 data[dst_address - 2] = 0x7f; 994 break; 995 case 0x30: 996 /* This is a bit-maniputation instruction that loads one bit 997 from memory, one of "band", "biand", "bild", "bior", 998 "bixor", "bld", "bor", "btst", and "bxor". */ 999 data[dst_address - 2] = 0x7e; 1000 break; 1001 default: 1002 abort (); 1003 } 1004 1005 bfd_put_8 (abfd, value & 0xff, data + dst_address - 1); 1006 src_address += 4; 1007 break; 1008 1009 case R_BCC_INV: 1010 /* Get the address of the target of this branch. */ 1011 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 1012 1013 dot = (input_section->output_offset 1014 + dst_address 1015 + link_order->u.indirect.section->output_section->vma) + 1; 1016 1017 gap = value - dot; 1018 1019 /* Sanity check. */ 1020 if (gap < -128 || gap > 126) 1021 (*link_info->callbacks->reloc_overflow) 1022 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 1023 reloc->howto->name, reloc->addend, input_section->owner, 1024 input_section, reloc->address); 1025 1026 /* Everything looks OK. Fix the condition in the instruction, apply 1027 the relocation, and update the src/dst address appropriately. */ 1028 1029 bfd_put_8 (abfd, bfd_get_8 (abfd, data + dst_address - 1) ^ 1, 1030 data + dst_address - 1); 1031 bfd_put_8 (abfd, gap, data + dst_address); 1032 dst_address++; 1033 src_address++; 1034 1035 /* All done. */ 1036 break; 1037 1038 case R_JMP_DEL: 1039 src_address += 4; 1040 break; 1041 1042 /* An 8-bit memory indirect instruction (jmp/jsr). 1043 1044 There's several things that need to be done to handle 1045 this relocation. 1046 1047 If this is a reloc against the absolute symbol, then 1048 we should handle it just R_RELBYTE. Likewise if it's 1049 for a symbol with a value ge 0 and le 0xff. 1050 1051 Otherwise it's a jump/call through the function vector, 1052 and the linker is expected to set up the function vector 1053 and put the right value into the jump/call instruction. */ 1054 case R_MEM_INDIRECT: 1055 { 1056 /* We need to find the symbol so we can determine it's 1057 address in the function vector table. */ 1058 asymbol *symbol; 1059 const char *name; 1060 struct funcvec_hash_table *ftab; 1061 struct funcvec_hash_entry *h; 1062 struct h8300_coff_link_hash_table *htab; 1063 asection *vectors_sec; 1064 1065 if (link_info->output_bfd->xvec != abfd->xvec) 1066 { 1067 _bfd_error_handler 1068 (_("cannot handle R_MEM_INDIRECT reloc when using %s output"), 1069 link_info->output_bfd->xvec->name); 1070 1071 /* What else can we do? This function doesn't allow return 1072 of an error, and we don't want to call abort as that 1073 indicates an internal error. */ 1074#ifndef EXIT_FAILURE 1075#define EXIT_FAILURE 1 1076#endif 1077 xexit (EXIT_FAILURE); 1078 } 1079 htab = h8300_coff_hash_table (link_info); 1080 vectors_sec = htab->vectors_sec; 1081 1082 /* First see if this is a reloc against the absolute symbol 1083 or against a symbol with a nonnegative value <= 0xff. */ 1084 symbol = *(reloc->sym_ptr_ptr); 1085 value = bfd_coff_reloc16_get_value (reloc, link_info, input_section); 1086 if (symbol == bfd_abs_section_ptr->symbol 1087 || value <= 0xff) 1088 { 1089 /* This should be handled in a manner very similar to 1090 R_RELBYTES. If the value is in range, then just slam 1091 the value into the right location. Else trigger a 1092 reloc overflow callback. */ 1093 if (value <= 0xff) 1094 { 1095 bfd_put_8 (abfd, value, data + dst_address); 1096 dst_address += 1; 1097 src_address += 1; 1098 } 1099 else 1100 (*link_info->callbacks->reloc_overflow) 1101 (link_info, NULL, bfd_asymbol_name (*reloc->sym_ptr_ptr), 1102 reloc->howto->name, reloc->addend, input_section->owner, 1103 input_section, reloc->address); 1104 break; 1105 } 1106 1107 /* This is a jump/call through a function vector, and we're 1108 expected to create the function vector ourselves. 1109 1110 First look up this symbol in the linker hash table -- we need 1111 the derived linker symbol which holds this symbol's index 1112 in the function vector. */ 1113 name = symbol->name; 1114 if (symbol->flags & BSF_LOCAL) 1115 { 1116 char *new_name = bfd_malloc ((bfd_size_type) strlen (name) + 10); 1117 1118 if (new_name == NULL) 1119 abort (); 1120 1121 sprintf (new_name, "%s_%08x", name, symbol->section->id); 1122 name = new_name; 1123 } 1124 1125 ftab = htab->funcvec_hash_table; 1126 h = funcvec_hash_lookup (ftab, name, FALSE, FALSE); 1127 1128 /* This shouldn't ever happen. If it does that means we've got 1129 data corruption of some kind. Aborting seems like a reasonable 1130 thing to do here. */ 1131 if (h == NULL || vectors_sec == NULL) 1132 abort (); 1133 1134 /* Place the address of the function vector entry into the 1135 reloc's address. */ 1136 bfd_put_8 (abfd, 1137 vectors_sec->output_offset + h->offset, 1138 data + dst_address); 1139 1140 dst_address++; 1141 src_address++; 1142 1143 /* Now create an entry in the function vector itself. */ 1144 switch (bfd_get_mach (input_section->owner)) 1145 { 1146 case bfd_mach_h8300: 1147 case bfd_mach_h8300hn: 1148 case bfd_mach_h8300sn: 1149 bfd_put_16 (abfd, 1150 bfd_coff_reloc16_get_value (reloc, 1151 link_info, 1152 input_section), 1153 vectors_sec->contents + h->offset); 1154 break; 1155 case bfd_mach_h8300h: 1156 case bfd_mach_h8300s: 1157 bfd_put_32 (abfd, 1158 bfd_coff_reloc16_get_value (reloc, 1159 link_info, 1160 input_section), 1161 vectors_sec->contents + h->offset); 1162 break; 1163 default: 1164 abort (); 1165 } 1166 1167 /* Gross. We've already written the contents of the vector section 1168 before we get here... So we write it again with the new data. */ 1169 bfd_set_section_contents (vectors_sec->output_section->owner, 1170 vectors_sec->output_section, 1171 vectors_sec->contents, 1172 (file_ptr) vectors_sec->output_offset, 1173 vectors_sec->size); 1174 break; 1175 } 1176 1177 default: 1178 abort (); 1179 break; 1180 1181 } 1182 1183 *src_ptr = src_address; 1184 *dst_ptr = dst_address; 1185} 1186 1187/* Routine for the h8300 linker. 1188 1189 This routine is necessary to handle the special R_MEM_INDIRECT 1190 relocs on the h8300. It's responsible for generating a vectors 1191 section and attaching it to an input bfd as well as sizing 1192 the vectors section. It also creates our vectors hash table. 1193 1194 It uses the generic linker routines to actually add the symbols. 1195 from this BFD to the bfd linker hash table. It may add a few 1196 selected static symbols to the bfd linker hash table. */ 1197 1198static bfd_boolean 1199h8300_bfd_link_add_symbols (bfd *abfd, struct bfd_link_info *info) 1200{ 1201 asection *sec; 1202 struct funcvec_hash_table *funcvec_hash_table; 1203 bfd_size_type amt; 1204 struct h8300_coff_link_hash_table *htab; 1205 1206 /* Add the symbols using the generic code. */ 1207 _bfd_generic_link_add_symbols (abfd, info); 1208 1209 if (info->output_bfd->xvec != abfd->xvec) 1210 return TRUE; 1211 1212 htab = h8300_coff_hash_table (info); 1213 1214 /* If we haven't created a vectors section, do so now. */ 1215 if (!htab->vectors_sec) 1216 { 1217 flagword flags; 1218 1219 /* Make sure the appropriate flags are set, including SEC_IN_MEMORY. */ 1220 flags = (SEC_ALLOC | SEC_LOAD 1221 | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_READONLY); 1222 htab->vectors_sec = bfd_make_section_with_flags (abfd, ".vectors", 1223 flags); 1224 1225 /* If the section wasn't created, or we couldn't set the flags, 1226 quit quickly now, rather than dying a painful death later. */ 1227 if (!htab->vectors_sec) 1228 return FALSE; 1229 1230 /* Also create the vector hash table. */ 1231 amt = sizeof (struct funcvec_hash_table); 1232 funcvec_hash_table = (struct funcvec_hash_table *) bfd_alloc (abfd, amt); 1233 1234 if (!funcvec_hash_table) 1235 return FALSE; 1236 1237 /* And initialize the funcvec hash table. */ 1238 if (!funcvec_hash_table_init (funcvec_hash_table, abfd, 1239 funcvec_hash_newfunc, 1240 sizeof (struct funcvec_hash_entry))) 1241 { 1242 bfd_release (abfd, funcvec_hash_table); 1243 return FALSE; 1244 } 1245 1246 /* Store away a pointer to the funcvec hash table. */ 1247 htab->funcvec_hash_table = funcvec_hash_table; 1248 } 1249 1250 /* Load up the function vector hash table. */ 1251 funcvec_hash_table = htab->funcvec_hash_table; 1252 1253 /* Now scan the relocs for all the sections in this bfd; create 1254 additional space in the .vectors section as needed. */ 1255 for (sec = abfd->sections; sec; sec = sec->next) 1256 { 1257 long reloc_size, reloc_count, i; 1258 asymbol **symbols; 1259 arelent **relocs; 1260 1261 /* Suck in the relocs, symbols & canonicalize them. */ 1262 reloc_size = bfd_get_reloc_upper_bound (abfd, sec); 1263 if (reloc_size <= 0) 1264 continue; 1265 1266 relocs = (arelent **) bfd_malloc ((bfd_size_type) reloc_size); 1267 if (!relocs) 1268 return FALSE; 1269 1270 /* The symbols should have been read in by _bfd_generic link_add_symbols 1271 call abovec, so we can cheat and use the pointer to them that was 1272 saved in the above call. */ 1273 symbols = _bfd_generic_link_get_symbols(abfd); 1274 reloc_count = bfd_canonicalize_reloc (abfd, sec, relocs, symbols); 1275 if (reloc_count <= 0) 1276 { 1277 free (relocs); 1278 continue; 1279 } 1280 1281 /* Now walk through all the relocations in this section. */ 1282 for (i = 0; i < reloc_count; i++) 1283 { 1284 arelent *reloc = relocs[i]; 1285 asymbol *symbol = *(reloc->sym_ptr_ptr); 1286 const char *name; 1287 1288 /* We've got an indirect reloc. See if we need to add it 1289 to the function vector table. At this point, we have 1290 to add a new entry for each unique symbol referenced 1291 by an R_MEM_INDIRECT relocation except for a reloc 1292 against the absolute section symbol. */ 1293 if (reloc->howto->type == R_MEM_INDIRECT 1294 && symbol != bfd_abs_section_ptr->symbol) 1295 1296 { 1297 struct funcvec_hash_table *ftab; 1298 struct funcvec_hash_entry *h; 1299 1300 name = symbol->name; 1301 if (symbol->flags & BSF_LOCAL) 1302 { 1303 char *new_name; 1304 1305 new_name = bfd_malloc ((bfd_size_type) strlen (name) + 10); 1306 if (new_name == NULL) 1307 abort (); 1308 1309 sprintf (new_name, "%s_%08x", name, symbol->section->id); 1310 name = new_name; 1311 } 1312 1313 /* Look this symbol up in the function vector hash table. */ 1314 ftab = htab->funcvec_hash_table; 1315 h = funcvec_hash_lookup (ftab, name, FALSE, FALSE); 1316 1317 /* If this symbol isn't already in the hash table, add 1318 it and bump up the size of the hash table. */ 1319 if (h == NULL) 1320 { 1321 h = funcvec_hash_lookup (ftab, name, TRUE, TRUE); 1322 if (h == NULL) 1323 { 1324 free (relocs); 1325 return FALSE; 1326 } 1327 1328 /* Bump the size of the vectors section. Each vector 1329 takes 2 bytes on the h8300 and 4 bytes on the h8300h. */ 1330 switch (bfd_get_mach (abfd)) 1331 { 1332 case bfd_mach_h8300: 1333 case bfd_mach_h8300hn: 1334 case bfd_mach_h8300sn: 1335 htab->vectors_sec->size += 2; 1336 break; 1337 case bfd_mach_h8300h: 1338 case bfd_mach_h8300s: 1339 htab->vectors_sec->size += 4; 1340 break; 1341 default: 1342 abort (); 1343 } 1344 } 1345 } 1346 } 1347 1348 /* We're done with the relocations, release them. */ 1349 free (relocs); 1350 } 1351 1352 /* Now actually allocate some space for the function vector. It's 1353 wasteful to do this more than once, but this is easier. */ 1354 sec = htab->vectors_sec; 1355 if (sec->size != 0) 1356 { 1357 /* Free the old contents. */ 1358 if (sec->contents) 1359 free (sec->contents); 1360 1361 /* Allocate new contents. */ 1362 sec->contents = bfd_malloc (sec->size); 1363 } 1364 1365 return TRUE; 1366} 1367 1368#define coff_reloc16_extra_cases h8300_reloc16_extra_cases 1369#define coff_reloc16_estimate h8300_reloc16_estimate 1370#define coff_bfd_link_add_symbols h8300_bfd_link_add_symbols 1371#define coff_bfd_link_hash_table_create h8300_coff_link_hash_table_create 1372 1373#define COFF_LONG_FILENAMES 1374 1375#ifndef bfd_pe_print_pdata 1376#define bfd_pe_print_pdata NULL 1377#endif 1378 1379#include "coffcode.h" 1380 1381#undef coff_bfd_get_relocated_section_contents 1382#undef coff_bfd_relax_section 1383#define coff_bfd_get_relocated_section_contents \ 1384 bfd_coff_reloc16_get_relocated_section_contents 1385#define coff_bfd_relax_section bfd_coff_reloc16_relax_section 1386 1387CREATE_BIG_COFF_TARGET_VEC (h8300_coff_vec, "coff-h8300", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE) 1388