1/*
2 * This file is _NOT_ automatically generated.  It must agree with the
3 * Virtual Function register map definitions in t4vf_defs.h in the common
4 * code.
5 */
6struct reg_info t4vf_sge_regs[] = {
7	{ "SGE_KDOORBELL",			0x000, 0 },
8		{ "QID", 15, 17 },
9		{ "Priority", 14, 1 },
10		{ "PIDX", 0, 14 },
11	{ "SGE_GTS",				0x004, 0 },
12		{ "IngressQID", 16, 16 },
13		{ "TimerReg", 13, 3 },
14		{ "SEIntArm", 12, 1 },
15		{ "CIDXInc", 0, 12 },
16
17	{ NULL, 0, 0 }
18};
19
20struct reg_info t5vf_sge_regs[] = {
21	{ "SGE_VF_KDOORBELL",			0x000, 0 },
22		{ "QID", 15, 17 },
23		{ "Priority", 14, 1 },
24		{ "Type", 13, 1 },
25		{ "PIDX", 0, 13 },
26	{ "SGE_VF_GTS",				0x004, 0 },
27		{ "IngressQID", 16, 16 },
28		{ "TimerReg", 13, 3 },
29		{ "SEIntArm", 12, 1 },
30		{ "CIDXInc", 0, 12 },
31
32	{ NULL, 0, 0 }
33};
34
35struct reg_info t4vf_mps_regs[] = {
36	{ "MPS_VF_CTL",	0x100, 0 },
37		{ "TxEn", 1, 1 },
38		{ "RxEn", 0, 1 },
39
40	{ "MPS_VF_STAT_TX_VF_BCAST_BYTES_L",	0x180, 0 },
41	{ "MPS_VF_STAT_TX_VF_BCAST_BYTES_H",	0x184, 0 },
42	{ "MPS_VF_STAT_TX_VF_BCAST_FRAMES_L",	0x188, 0 },
43	{ "MPS_VF_STAT_TX_VF_BCAST_FRAMES_H",	0x18c, 0 },
44
45	{ "MPS_VF_STAT_TX_VF_MCAST_BYTES_L",	0x190, 0 },
46	{ "MPS_VF_STAT_TX_VF_MCAST_BYTES_H",	0x194, 0 },
47	{ "MPS_VF_STAT_TX_VF_MCAST_FRAMES_L",	0x198, 0 },
48	{ "MPS_VF_STAT_TX_VF_MCAST_FRAMES_H",	0x19c, 0 },
49
50	{ "MPS_VF_STAT_TX_VF_UCAST_BYTES_L",	0x1a0, 0 },
51	{ "MPS_VF_STAT_TX_VF_UCAST_BYTES_H",	0x1a4, 0 },
52	{ "MPS_VF_STAT_TX_VF_UCAST_FRAMES_L",	0x1a8, 0 },
53	{ "MPS_VF_STAT_TX_VF_UCAST_FRAMES_H",	0x1ac, 0 },
54
55	{ "MPS_VF_STAT_TX_VF_DROP_FRAMES_L",	0x1b0, 0 },
56	{ "MPS_VF_STAT_TX_VF_DROP_FRAMES_H",	0x1b4, 0 },
57
58	{ "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L",  0x1b8, 0 },
59	{ "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H",  0x1bc, 0 },
60	{ "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L",	0x1c0, 0 },
61	{ "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H",	0x1c4, 0 },
62
63	{ "MPS_VF_STAT_RX_VF_BCAST_BYTES_L",	0x1c8, 0 },
64	{ "MPS_VF_STAT_RX_VF_BCAST_BYTES_H",	0x1cc, 0 },
65	{ "MPS_VF_STAT_RX_VF_BCAST_FRAMES_L",	0x1d0, 0 },
66	{ "MPS_VF_STAT_RX_VF_BCAST_FRAMES_H",	0x1d4, 0 },
67
68	{ "MPS_VF_STAT_RX_VF_MCAST_BYTES_L",	0x1d8, 0 },
69	{ "MPS_VF_STAT_RX_VF_MCAST_BYTES_H",	0x1dc, 0 },
70	{ "MPS_VF_STAT_RX_VF_MCAST_FRAMES_L",	0x1e0, 0 },
71	{ "MPS_VF_STAT_RX_VF_MCAST_FRAMES_H",	0x1e4, 0 },
72
73	{ "MPS_VF_STAT_RX_VF_UCAST_BYTES_L",	0x1e8, 0 },
74	{ "MPS_VF_STAT_RX_VF_UCAST_BYTES_H",	0x1ec, 0 },
75	{ "MPS_VF_STAT_RX_VF_UCAST_FRAMES_L",	0x1f0, 0 },
76	{ "MPS_VF_STAT_RX_VF_UCAST_FRAMES_H",	0x1f4, 0 },
77
78	{ "MPS_VF_STAT_RX_VF_ERR_FRAMES_L",	0x1f8, 0 },
79	{ "MPS_VF_STAT_RX_VF_ERR_FRAMES_H",	0x1fc, 0 },
80
81	{ NULL, 0, 0 }
82};
83
84struct reg_info t4vf_pl_regs[] = {
85	{ "PL_VF_WHOAMI",			0x200, 0 },
86		{ "PortxMap", 24, 3 },
87		{ "SourceBus", 16, 2 },
88		{ "SourcePF", 8, 3 },
89		{ "IsVF", 7, 1 },
90		{ "VFID", 0, 7 },
91
92	{ NULL, 0, 0 }
93};
94
95struct reg_info t5vf_pl_regs[] = {
96	{ "PL_WHOAMI",				0x200, 0 },
97		{ "PortxMap", 24, 3 },
98		{ "SourceBus", 16, 2 },
99		{ "SourcePF", 8, 3 },
100		{ "IsVF", 7, 1 },
101		{ "VFID", 0, 7 },
102	{ "PL_VF_REV",				0x204, 0 },
103		{ "ChipID", 4, 4 },
104		{ "Rev", 0, 4 },
105	{ "PL_VF_REVISION",			0x208, 0 },
106
107	{ NULL, 0, 0 }
108};
109
110struct reg_info t6vf_pl_regs[] = {
111	{ "PL_WHOAMI",				0x200, 0 },
112		{ "PortxMap", 24, 3 },
113		{ "SourceBus", 16, 2 },
114		{ "SourcePF", 9, 3 },
115		{ "IsVF", 8, 1 },
116		{ "VFID", 0, 8 },
117	{ "PL_VF_REV",				0x204, 0 },
118		{ "ChipID", 4, 4 },
119		{ "Rev", 0, 4 },
120	{ "PL_VF_REVISION",			0x208, 0 },
121
122	{ NULL, 0, 0 }
123};
124
125struct reg_info t4vf_cim_regs[] = {
126	/*
127	 * Note: the Mailbox Control register has read side-effects so
128	 * the driver simply returns 0xffff for this register.
129	 */
130	{ "CIM_VF_EXT_MAILBOX_CTRL",		0x300, 0 },
131		{ "MBGeneric", 4, 4 },
132		{ "MBMsgValid", 3, 1 },
133		{ "MBIntReq", 2, 1 },
134		{ "MBOwner", 0, 2 },
135	{ "CIM_VF_EXT_MAILBOX_STATUS",		0x304, 0 },
136		{ "MBVFReady", 0, 1 },
137
138	{ NULL, 0, 0 }
139};
140
141struct reg_info t4vf_mbdata_regs[] = {
142	{ "CIM_VF_EXT_MAILBOX_DATA_00",		0x240, 0 },
143		{ "Return", 8, 8 },
144		{ "Length16", 0, 8 },
145	{ "CIM_VF_EXT_MAILBOX_DATA_04",		0x244, 0 },
146		{ "OpCode", 24, 8 },
147		{ "Request", 23, 1 },
148		{ "Read", 22, 1 },
149		{ "Write", 21, 1 },
150		{ "Execute", 20, 1 },
151	{ "CIM_VF_EXT_MAILBOX_DATA_08",		0x248, 0 },
152	{ "CIM_VF_EXT_MAILBOX_DATA_0c",		0x24c, 0 },
153	{ "CIM_VF_EXT_MAILBOX_DATA_10",		0x250, 0 },
154	{ "CIM_VF_EXT_MAILBOX_DATA_14",		0x254, 0 },
155	{ "CIM_VF_EXT_MAILBOX_DATA_18",		0x258, 0 },
156	{ "CIM_VF_EXT_MAILBOX_DATA_1c",		0x25c, 0 },
157	{ "CIM_VF_EXT_MAILBOX_DATA_20",		0x260, 0 },
158	{ "CIM_VF_EXT_MAILBOX_DATA_24",		0x264, 0 },
159	{ "CIM_VF_EXT_MAILBOX_DATA_28",		0x268, 0 },
160	{ "CIM_VF_EXT_MAILBOX_DATA_2c",		0x26c, 0 },
161	{ "CIM_VF_EXT_MAILBOX_DATA_30",		0x270, 0 },
162	{ "CIM_VF_EXT_MAILBOX_DATA_34",		0x274, 0 },
163	{ "CIM_VF_EXT_MAILBOX_DATA_38",		0x278, 0 },
164	{ "CIM_VF_EXT_MAILBOX_DATA_3c",		0x27c, 0 },
165
166	{ NULL, 0, 0 }
167};
168