1226584Sdim/*-
2226584Sdim * SPDX-License-Identifier: BSD-2-Clause
3226584Sdim *
4226584Sdim * Copyright (c) 2015 Nahanni Systems, Inc.
5226584Sdim * All rights reserved.
6226584Sdim *
7226584Sdim * Redistribution and use in source and binary forms, with or without
8226584Sdim * modification, are permitted provided that the following conditions
9226584Sdim * are met:
10226584Sdim * 1. Redistributions of source code must retain the above copyright
11226584Sdim *    notice, this list of conditions and the following disclaimer.
12226584Sdim * 2. Redistributions in binary form must reproduce the above copyright
13226584Sdim *    notice, this list of conditions and the following disclaimer in the
14226584Sdim *    documentation and/or other materials provided with the distribution.
15226584Sdim *
16226584Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17226584Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18234353Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19234353Sdim * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20226584Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21226584Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22226584Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23226584Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24226584Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25226584Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26226584Sdim * SUCH DAMAGE.
27226584Sdim */
28226584Sdim
29226584Sdim#include <sys/types.h>
30226584Sdim#include <sys/mman.h>
31226584Sdim
32226584Sdim#include <machine/vmm.h>
33#include <machine/vmm_snapshot.h>
34#include <vmmapi.h>
35
36#include <stdio.h>
37#include <stdlib.h>
38#include <string.h>
39
40#include <errno.h>
41#include <unistd.h>
42
43#include "bhyvegc.h"
44#include "bhyverun.h"
45#include "config.h"
46#include "debug.h"
47#include "console.h"
48#include "pci_emul.h"
49#include "rfb.h"
50#ifdef __amd64__
51#include "amd64/vga.h"
52#endif
53
54/*
55 * bhyve Framebuffer device emulation.
56 * BAR0 points to the current mode information.
57 * BAR1 is the 32-bit framebuffer address.
58 *
59 *  -s <b>,fbuf,wait,vga=on|io|off,rfb=<ip>:port,w=width,h=height
60 */
61
62static int fbuf_debug = 1;
63#define	DEBUG_INFO	1
64#define	DEBUG_VERBOSE	4
65#define	DPRINTF(level, params)  if (level <= fbuf_debug) PRINTLN params
66
67
68#define	KB	(1024UL)
69#define	MB	(1024 * 1024UL)
70
71#define	DMEMSZ	128
72
73#define	FB_SIZE		(32*MB)
74
75#define COLS_MAX	3840
76#define ROWS_MAX	2160
77
78#define COLS_DEFAULT	1024
79#define ROWS_DEFAULT	768
80
81#define COLS_MIN	640
82#define ROWS_MIN	480
83
84struct pci_fbuf_softc {
85	struct pci_devinst *fsc_pi;
86	struct {
87		uint32_t fbsize;
88		uint16_t width;
89		uint16_t height;
90		uint16_t depth;
91		uint16_t refreshrate;
92		uint8_t  reserved[116];
93	} __packed memregs;
94
95	/* rfb server */
96	char      *rfb_host;
97	char      *rfb_password;
98	int       rfb_port;
99	int       rfb_wait;
100	int       vga_enabled;
101	int	  vga_full;
102
103	uint32_t  fbaddr;
104	char      *fb_base;
105	uint16_t  gc_width;
106	uint16_t  gc_height;
107	void      *vgasc;
108	struct bhyvegc_image *gc_image;
109};
110
111static struct pci_fbuf_softc *fbuf_sc;
112
113#define	PCI_FBUF_MSI_MSGS	 4
114
115static void
116pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
117    uint64_t value)
118{
119	struct pci_fbuf_softc *sc;
120	uint8_t *p;
121
122	assert(baridx == 0);
123
124	sc = pi->pi_arg;
125
126	DPRINTF(DEBUG_VERBOSE,
127	    ("fbuf wr: offset 0x%lx, size: %d, value: 0x%lx",
128	    offset, size, value));
129
130	if (offset + size > DMEMSZ) {
131		printf("fbuf: write too large, offset %ld size %d\n",
132		       offset, size);
133		return;
134	}
135
136	p = (uint8_t *)&sc->memregs + offset;
137
138	switch (size) {
139	case 1:
140		*p = value;
141		break;
142	case 2:
143		*(uint16_t *)p = value;
144		break;
145	case 4:
146		*(uint32_t *)p = value;
147		break;
148	case 8:
149		*(uint64_t *)p = value;
150		break;
151	default:
152		printf("fbuf: write unknown size %d\n", size);
153		break;
154	}
155
156	if (!sc->gc_image->vgamode && sc->memregs.width == 0 &&
157	    sc->memregs.height == 0) {
158		DPRINTF(DEBUG_INFO, ("switching to VGA mode"));
159		sc->gc_image->vgamode = 1;
160		sc->gc_width = 0;
161		sc->gc_height = 0;
162	} else if (sc->gc_image->vgamode && sc->memregs.width != 0 &&
163	    sc->memregs.height != 0) {
164		DPRINTF(DEBUG_INFO, ("switching to VESA mode"));
165		sc->gc_image->vgamode = 0;
166	}
167}
168
169static uint64_t
170pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
171{
172	struct pci_fbuf_softc *sc;
173	uint8_t *p;
174	uint64_t value;
175
176	assert(baridx == 0);
177
178	sc = pi->pi_arg;
179
180
181	if (offset + size > DMEMSZ) {
182		printf("fbuf: read too large, offset %ld size %d\n",
183		       offset, size);
184		return (0);
185	}
186
187	p = (uint8_t *)&sc->memregs + offset;
188	value = 0;
189	switch (size) {
190	case 1:
191		value = *p;
192		break;
193	case 2:
194		value = *(uint16_t *)p;
195		break;
196	case 4:
197		value = *(uint32_t *)p;
198		break;
199	case 8:
200		value = *(uint64_t *)p;
201		break;
202	default:
203		printf("fbuf: read unknown size %d\n", size);
204		break;
205	}
206
207	DPRINTF(DEBUG_VERBOSE,
208	    ("fbuf rd: offset 0x%lx, size: %d, value: 0x%lx",
209	     offset, size, value));
210
211	return (value);
212}
213
214static void
215pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled,
216    uint64_t address)
217{
218	struct pci_fbuf_softc *sc;
219	int prot;
220
221	if (baridx != 1)
222		return;
223
224	sc = pi->pi_arg;
225	if (!enabled) {
226		if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0)
227			EPRINTLN("pci_fbuf: munmap_memseg failed");
228		sc->fbaddr = 0;
229	} else {
230		prot = PROT_READ | PROT_WRITE;
231		if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0,
232		    FB_SIZE, prot) != 0)
233			EPRINTLN("pci_fbuf: mmap_memseg failed");
234		sc->fbaddr = address;
235	}
236}
237
238
239static int
240pci_fbuf_parse_config(struct pci_fbuf_softc *sc, nvlist_t *nvl)
241{
242	const char *value;
243	char *cp;
244
245	sc->rfb_wait = get_config_bool_node_default(nvl, "wait", false);
246
247	/* Prefer "rfb" to "tcp". */
248	value = get_config_value_node(nvl, "rfb");
249	if (value == NULL)
250		value = get_config_value_node(nvl, "tcp");
251	if (value != NULL) {
252		/*
253		 * IPv4 -- host-ip:port
254		 * IPv6 -- [host-ip%zone]:port
255		 * XXX for now port is mandatory for IPv4.
256		 */
257		if (value[0] == '[') {
258			cp = strchr(value + 1, ']');
259			if (cp == NULL || cp == value + 1) {
260				EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
261				    value);
262				return (-1);
263			}
264			sc->rfb_host = strndup(value + 1, cp - (value + 1));
265			cp++;
266			if (*cp == ':') {
267				cp++;
268				if (*cp == '\0') {
269					EPRINTLN(
270					    "fbuf: Missing port number: \"%s\"",
271					    value);
272					return (-1);
273				}
274				sc->rfb_port = atoi(cp);
275			} else if (*cp != '\0') {
276				EPRINTLN("fbuf: Invalid IPv6 address: \"%s\"",
277				    value);
278				return (-1);
279			}
280		} else {
281			cp = strchr(value, ':');
282			if (cp == NULL) {
283				sc->rfb_port = atoi(value);
284			} else {
285				sc->rfb_host = strndup(value, cp - value);
286				cp++;
287				if (*cp == '\0') {
288					EPRINTLN(
289					    "fbuf: Missing port number: \"%s\"",
290					    value);
291					return (-1);
292				}
293				sc->rfb_port = atoi(cp);
294			}
295		}
296	}
297
298	value = get_config_value_node(nvl, "vga");
299	if (value != NULL) {
300		if (strcmp(value, "off") == 0) {
301			sc->vga_enabled = 0;
302		} else if (strcmp(value, "io") == 0) {
303			sc->vga_enabled = 1;
304			sc->vga_full = 0;
305		} else if (strcmp(value, "on") == 0) {
306			sc->vga_enabled = 1;
307			sc->vga_full = 1;
308		} else {
309			EPRINTLN("fbuf: Invalid vga setting: \"%s\"", value);
310			return (-1);
311		}
312	}
313
314	value = get_config_value_node(nvl, "w");
315	if (value != NULL)
316		sc->memregs.width = strtol(value, NULL, 10);
317
318	value = get_config_value_node(nvl, "h");
319	if (value != NULL)
320		sc->memregs.height = strtol(value, NULL, 10);
321
322	if (sc->memregs.width > COLS_MAX ||
323	    sc->memregs.height > ROWS_MAX) {
324		EPRINTLN("fbuf: max resolution is %ux%u", COLS_MAX, ROWS_MAX);
325		return (-1);
326	}
327	if (sc->memregs.width < COLS_MIN ||
328	    sc->memregs.height < ROWS_MIN) {
329		EPRINTLN("fbuf: minimum resolution is %ux%u",
330		    COLS_MIN, ROWS_MIN);
331		return (-1);
332	}
333
334	value = get_config_value_node(nvl, "password");
335	if (value != NULL)
336		sc->rfb_password = strdup(value);
337
338	return (0);
339}
340
341static void
342pci_fbuf_render(struct bhyvegc *gc, void *arg)
343{
344	struct pci_fbuf_softc *sc;
345
346	sc = arg;
347
348	if (sc->vga_full && sc->gc_image->vgamode) {
349		/* TODO: mode switching to vga and vesa should use the special
350		 *      EFI-bhyve protocol port.
351		 */
352		vga_render(gc, sc->vgasc);
353		return;
354	}
355	if (sc->gc_width != sc->memregs.width ||
356	    sc->gc_height != sc->memregs.height) {
357		bhyvegc_resize(gc, sc->memregs.width, sc->memregs.height);
358		sc->gc_width = sc->memregs.width;
359		sc->gc_height = sc->memregs.height;
360	}
361}
362
363static int
364pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl)
365{
366	int error;
367	struct pci_fbuf_softc *sc;
368
369	if (fbuf_sc != NULL) {
370		EPRINTLN("Only one frame buffer device is allowed.");
371		return (-1);
372	}
373
374	sc = calloc(1, sizeof(struct pci_fbuf_softc));
375
376	pi->pi_arg = sc;
377
378	/* initialize config space */
379	pci_set_cfgdata16(pi, PCIR_DEVICE, 0x40FB);
380	pci_set_cfgdata16(pi, PCIR_VENDOR, 0xFB5D);
381	pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
382	pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
383
384	sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER,
385	    "framebuffer", FB_SIZE);
386	if (sc->fb_base == MAP_FAILED) {
387		error = -1;
388		goto done;
389	}
390
391	error = pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, DMEMSZ);
392	assert(error == 0);
393
394	error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, FB_SIZE);
395	assert(error == 0);
396
397	error = pci_emul_add_msicap(pi, PCI_FBUF_MSI_MSGS);
398	assert(error == 0);
399
400	sc->memregs.fbsize = FB_SIZE;
401	sc->memregs.width  = COLS_DEFAULT;
402	sc->memregs.height = ROWS_DEFAULT;
403	sc->memregs.depth  = 32;
404
405	sc->vga_enabled = 1;
406	sc->vga_full = 0;
407
408	sc->fsc_pi = pi;
409
410	error = pci_fbuf_parse_config(sc, nvl);
411	if (error != 0)
412		goto done;
413
414	/* XXX until VGA rendering is enabled */
415	if (sc->vga_full != 0) {
416		EPRINTLN("pci_fbuf: VGA rendering not enabled");
417		goto done;
418	}
419
420	DPRINTF(DEBUG_INFO, ("fbuf frame buffer base: %p [sz %lu]",
421	        sc->fb_base, FB_SIZE));
422
423	console_init(sc->memregs.width, sc->memregs.height, sc->fb_base);
424	console_fb_register(pci_fbuf_render, sc);
425
426	if (sc->vga_enabled)
427		sc->vgasc = vga_init(!sc->vga_full);
428	sc->gc_image = console_get_image();
429
430	fbuf_sc = sc;
431
432	memset((void *)sc->fb_base, 0, FB_SIZE);
433
434	error = rfb_init(sc->rfb_host, sc->rfb_port, sc->rfb_wait, sc->rfb_password);
435done:
436	if (error)
437		free(sc);
438
439	return (error);
440}
441
442#ifdef BHYVE_SNAPSHOT
443static int
444pci_fbuf_snapshot(struct vm_snapshot_meta *meta)
445{
446	int ret;
447
448	SNAPSHOT_BUF_OR_LEAVE(fbuf_sc->fb_base, FB_SIZE, meta, ret, err);
449
450err:
451	return (ret);
452}
453#endif
454
455static const struct pci_devemu pci_fbuf = {
456	.pe_emu =	"fbuf",
457	.pe_init =	pci_fbuf_init,
458	.pe_barwrite =	pci_fbuf_write,
459	.pe_barread =	pci_fbuf_read,
460	.pe_baraddr =	pci_fbuf_baraddr,
461#ifdef BHYVE_SNAPSHOT
462	.pe_snapshot =	pci_fbuf_snapshot,
463#endif
464};
465PCI_EMUL_SET(pci_fbuf);
466