137Srgrimes/*- 247783Sandreas * SPDX-License-Identifier: BSD-2-Clause 337Srgrimes * 450472Speter * Copyright (c) 2011 NetApp, Inc. 5705Swollman * All rights reserved. 637Srgrimes * 784772Sarchie * Redistribution and use in source and binary forms, with or without 8705Swollman * modification, are permitted provided that the following conditions 937Srgrimes * are met: 1030672Sitojun * 1. Redistributions of source code must retain the above copyright 1137Srgrimes * notice, this list of conditions and the following disclaimer. 1247783Sandreas * 2. Redistributions in binary form must reproduce the above copyright 1337Srgrimes * notice, this list of conditions and the following disclaimer in the 14705Swollman * documentation and/or other materials provided with the distribution. 1547826Sandreas * 1637Srgrimes * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 1747783Sandreas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1837Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1947783Sandreas * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 2047783Sandreas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2147783Sandreas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2237Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2347783Sandreas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2447783Sandreas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2547783Sandreas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2647783Sandreas * SUCH DAMAGE. 2737Srgrimes */ 2847783Sandreas 2947783Sandreas#ifndef _PCI_EMUL_H_ 3037Srgrimes#define _PCI_EMUL_H_ 3147783Sandreas 3237Srgrimes#include <sys/types.h> 3347783Sandreas#include <sys/queue.h> 3447783Sandreas#include <sys/kernel.h> 3547783Sandreas#include <sys/nv.h> 3647783Sandreas#include <sys/pciio.h> 3737Srgrimes#include <sys/_pthreadtypes.h> 3847783Sandreas 3947783Sandreas#include <dev/pci/pcireg.h> 4047783Sandreas 4147783Sandreas#include <assert.h> 4247783Sandreas 4347783Sandreas#include "pci_irq.h" 4447783Sandreas 4547783Sandreas#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 46705Swollman#define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1) 4747783Sandreas#define PCI_ROM_IDX (PCI_BARMAX + 1) 4847783Sandreas 4947783Sandreasstruct vmctx; 5047783Sandreasstruct pci_devinst; 5130672Sitojunstruct memory_region; 5247783Sandreasstruct vm_snapshot_meta; 5330672Sitojun 5430672Sitojunstruct pci_devemu { 5547783Sandreas const char *pe_emu; /* Name of device emulation */ 5610422Swollman 5747783Sandreas /* instance creation */ 5847783Sandreas int (*pe_init)(struct pci_devinst *, nvlist_t *); 5947783Sandreas int (*pe_legacy_config)(nvlist_t *, const char *); 6030672Sitojun const char *pe_alias; 6130672Sitojun 6247783Sandreas /* ACPI DSDT enumeration */ 6347783Sandreas void (*pe_write_dsdt)(struct pci_devinst *); 6447783Sandreas 6547783Sandreas /* config space read/write callbacks */ 6647783Sandreas int (*pe_cfgwrite)(struct pci_devinst *pi, int offset, 6747783Sandreas int bytes, uint32_t val); 68126756Smlaier int (*pe_cfgread)(struct pci_devinst *pi, int offset, 6930672Sitojun int bytes, uint32_t *retval); 7030672Sitojun 7147783Sandreas /* BAR read/write callbacks */ 7247783Sandreas void (*pe_barwrite)(struct pci_devinst *pi, int baridx, 7347783Sandreas uint64_t offset, int size, uint64_t value); 7447783Sandreas uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx, 7547783Sandreas uint64_t offset, int size); 7647783Sandreas 7747783Sandreas void (*pe_baraddr)(struct pci_devinst *pi, 7896703Strhodes int baridx, int enabled, uint64_t address); 7947783Sandreas 8047783Sandreas /* Save/restore device state */ 8147783Sandreas int (*pe_snapshot)(struct vm_snapshot_meta *meta); 8247783Sandreas int (*pe_pause)(struct pci_devinst *pi); 8347783Sandreas int (*pe_resume)(struct pci_devinst *pi); 8447783Sandreas 8547783Sandreas}; 8647783Sandreas#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x) 8747783Sandreas 8847783Sandreasenum pcibar_type { 8947783Sandreas PCIBAR_NONE, 9047783Sandreas PCIBAR_IO, 91705Swollman PCIBAR_MEM32, 9247783Sandreas PCIBAR_MEM64, 9347783Sandreas PCIBAR_MEMHI64, 9447783Sandreas PCIBAR_ROM, 9547783Sandreas}; 9647783Sandreas 9747783Sandreasstruct pcibar { 9847783Sandreas enum pcibar_type type; /* io or memory */ 99705Swollman uint64_t size; 10047783Sandreas uint64_t addr; 10147783Sandreas uint8_t lobits; 10247783Sandreas}; 10347783Sandreas 104705Swollman#define PI_NAMESZ 40 10547783Sandreas 10647783Sandreasstruct msix_table_entry { 10747783Sandreas uint64_t addr; 108705Swollman uint32_t msg_data; 10947783Sandreas uint32_t vector_control; 11047783Sandreas} __packed; 11147783Sandreas 11247783Sandreas/* 11347783Sandreas * In case the structure is modified to hold extra information, use a define 11447783Sandreas * for the size that should be emulated. 11547783Sandreas */ 11647783Sandreas#define MSIX_TABLE_ENTRY_SIZE 16 11747783Sandreas#define MAX_MSIX_TABLE_ENTRIES 2048 11847783Sandreas#define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 11947783Sandreas 12047783Sandreasstruct pci_devinst { 12147783Sandreas struct pci_devemu *pi_d; 122142215Sglebius struct vmctx *pi_vmctx; 12347783Sandreas uint8_t pi_bus, pi_slot, pi_func; 12447783Sandreas char pi_name[PI_NAMESZ]; 12547783Sandreas int pi_bar_getsize; 12647783Sandreas int pi_prevcap; 12747783Sandreas int pi_capend; 12847783Sandreas 12947783Sandreas struct { 13047783Sandreas int8_t pin; 13147783Sandreas enum { 13266321Sasmodai IDLE, 13366321Sasmodai ASSERTED, 13466321Sasmodai PENDING, 13566321Sasmodai } state; 13666321Sasmodai struct pci_irq irq; 13790462Sdd pthread_mutex_t lock; 13866321Sasmodai } pi_lintr; 13966321Sasmodai 14066321Sasmodai struct { 14166321Sasmodai int enabled; 14266321Sasmodai uint64_t addr; 14366321Sasmodai uint64_t msg_data; 14466321Sasmodai int maxmsgnum; 145142215Sglebius } pi_msi; 14647783Sandreas 147107817Sfenner struct { 148 int enabled; 149 int table_bar; 150 int pba_bar; 151 uint32_t table_offset; 152 int table_count; 153 uint32_t pba_offset; 154 int pba_size; 155 int function_mask; 156 struct msix_table_entry *table; /* allocated at runtime */ 157 uint8_t *mapped_addr; 158 size_t mapped_size; 159 } pi_msix; 160 161 void *pi_arg; /* devemu-private data */ 162 163 u_char pi_cfgdata[PCI_REGMAX + 1]; 164 /* ROM is handled like a BAR */ 165 struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1]; 166 uint64_t pi_romoffset; 167}; 168 169struct msicap { 170 uint8_t capid; 171 uint8_t nextptr; 172 uint16_t msgctrl; 173 uint32_t addrlo; 174 uint32_t addrhi; 175 uint16_t msgdata; 176} __packed; 177static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 178 179struct msixcap { 180 uint8_t capid; 181 uint8_t nextptr; 182 uint16_t msgctrl; 183 uint32_t table_info; /* bar index and offset within it */ 184 uint32_t pba_info; /* bar index and offset within it */ 185} __packed; 186static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 187 188struct pciecap { 189 uint8_t capid; 190 uint8_t nextptr; 191 uint16_t pcie_capabilities; 192 193 uint32_t dev_capabilities; /* all devices */ 194 uint16_t dev_control; 195 uint16_t dev_status; 196 197 uint32_t link_capabilities; /* devices with links */ 198 uint16_t link_control; 199 uint16_t link_status; 200 201 uint32_t slot_capabilities; /* ports with slots */ 202 uint16_t slot_control; 203 uint16_t slot_status; 204 205 uint16_t root_control; /* root ports */ 206 uint16_t root_capabilities; 207 uint32_t root_status; 208 209 uint32_t dev_capabilities2; /* all devices */ 210 uint16_t dev_control2; 211 uint16_t dev_status2; 212 213 uint32_t link_capabilities2; /* devices with links */ 214 uint16_t link_control2; 215 uint16_t link_status2; 216 217 uint32_t slot_capabilities2; /* ports with slots */ 218 uint16_t slot_control2; 219 uint16_t slot_status2; 220} __packed; 221static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 222 223typedef void (*pci_lintr_cb)(int b, int s, int pin, struct pci_irq *irq, 224 void *arg); 225void pci_lintr_assert(struct pci_devinst *pi); 226void pci_lintr_deassert(struct pci_devinst *pi); 227void pci_lintr_request(struct pci_devinst *pi); 228int pci_count_lintr(int bus); 229void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 230 231int init_pci(struct vmctx *ctx); 232void pci_callback(void); 233uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl, 234 uint32_t reg, uint8_t size, uint32_t def); 235int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 236 enum pcibar_type type, uint64_t size); 237int pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 238 void **const addr); 239int pci_emul_add_boot_device(struct pci_devinst *const pi, 240 const int bootindex); 241int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 242int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 243void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 244 uint32_t val, uint8_t capoff, int capid); 245void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 246void pci_generate_msi(struct pci_devinst *pi, int msgnum); 247void pci_generate_msix(struct pci_devinst *pi, int msgnum); 248int pci_msi_enabled(struct pci_devinst *pi); 249int pci_msix_enabled(struct pci_devinst *pi); 250int pci_msix_table_bar(struct pci_devinst *pi); 251int pci_msix_pba_bar(struct pci_devinst *pi); 252int pci_msi_maxmsgnum(struct pci_devinst *pi); 253int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 254int pci_parse_slot(char *opt); 255void pci_print_supported_devices(void); 256void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 257int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 258int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 259 uint64_t value); 260uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 261void pci_write_dsdt(void); 262uint64_t pci_ecfg_base(void); 263int pci_bus_configured(int bus); 264 265#ifdef BHYVE_SNAPSHOT 266struct pci_devinst *pci_next(const struct pci_devinst *cursor); 267int pci_snapshot(struct vm_snapshot_meta *meta); 268int pci_pause(struct pci_devinst *pdi); 269int pci_resume(struct pci_devinst *pdi); 270#endif 271 272static __inline void 273pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 274{ 275 assert(offset <= PCI_REGMAX); 276 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 277} 278 279static __inline void 280pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 281{ 282 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 283 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 284} 285 286static __inline void 287pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 288{ 289 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 290 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 291} 292 293static __inline uint8_t 294pci_get_cfgdata8(struct pci_devinst *pi, int offset) 295{ 296 assert(offset <= PCI_REGMAX); 297 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 298} 299 300static __inline uint16_t 301pci_get_cfgdata16(struct pci_devinst *pi, int offset) 302{ 303 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 304 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 305} 306 307static __inline uint32_t 308pci_get_cfgdata32(struct pci_devinst *pi, int offset) 309{ 310 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 311 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 312} 313 314#endif /* _PCI_EMUL_H_ */ 315