1/*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * Copyright (c) 2014 Intel Corporation. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#if !defined(OPA_PORT_INFO_H) 36#define OPA_PORT_INFO_H 37 38#define OPA_PORT_LINK_MODE_NOP 0 /* No change */ 39#define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */ 40 41#define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */ 42#define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */ 43#define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */ 44#define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */ 45#define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */ 46 47#define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */ 48#define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */ 49#define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */ 50#define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */ 51#define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */ 52 53/* Link Down / Neighbor Link Down Reason; indicated as follows: */ 54#define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */ 55#define OPA_LINKDOWN_REASON_RCV_ERROR_0 1 56#define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2 57#define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3 58#define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4 59#define OPA_LINKDOWN_REASON_BAD_SLID 5 60#define OPA_LINKDOWN_REASON_BAD_DLID 6 61#define OPA_LINKDOWN_REASON_BAD_L2 7 62#define OPA_LINKDOWN_REASON_BAD_SC 8 63#define OPA_LINKDOWN_REASON_RCV_ERROR_8 9 64#define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10 65#define OPA_LINKDOWN_REASON_RCV_ERROR_10 11 66#define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12 67#define OPA_LINKDOWN_REASON_PREEMPT_VL15 13 68#define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14 69#define OPA_LINKDOWN_REASON_RCV_ERROR_14 15 70#define OPA_LINKDOWN_REASON_RCV_ERROR_15 16 71#define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17 72#define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18 73#define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19 74#define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20 75#define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21 76#define OPA_LINKDOWN_REASON_BAD_PREEMPT 22 77#define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23 78#define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24 79#define OPA_LINKDOWN_REASON_RCV_ERROR_24 25 80#define OPA_LINKDOWN_REASON_RCV_ERROR_25 26 81#define OPA_LINKDOWN_REASON_RCV_ERROR_26 27 82#define OPA_LINKDOWN_REASON_RCV_ERROR_27 28 83#define OPA_LINKDOWN_REASON_RCV_ERROR_28 29 84#define OPA_LINKDOWN_REASON_RCV_ERROR_29 30 85#define OPA_LINKDOWN_REASON_RCV_ERROR_30 31 86#define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32 87#define OPA_LINKDOWN_REASON_UNKNOWN 33 88/* 34 -reserved */ 89#define OPA_LINKDOWN_REASON_REBOOT 35 90#define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36 91/* 37-38 reserved */ 92#define OPA_LINKDOWN_REASON_FM_BOUNCE 39 93#define OPA_LINKDOWN_REASON_SPEED_POLICY 40 94#define OPA_LINKDOWN_REASON_WIDTH_POLICY 41 95/* 42-48 reserved */ 96#define OPA_LINKDOWN_REASON_DISCONNECTED 49 97#define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50 98#define OPA_LINKDOWN_REASON_NOT_INSTALLED 51 99#define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52 100/* 53 reserved */ 101#define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54 102/* 55 reserved */ 103#define OPA_LINKDOWN_REASON_POWER_POLICY 56 104#define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57 105#define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58 106/* 59 reserved */ 107#define OPA_LINKDOWN_REASON_SWITCH_MGMT 60 108#define OPA_LINKDOWN_REASON_SMA_DISABLED 61 109/* 62 reserved */ 110#define OPA_LINKDOWN_REASON_TRANSIENT 63 111/* 64-255 reserved */ 112 113/* OPA Link Init reason; indicated as follows: */ 114/* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */ 115#define OPA_LINKINIT_REASON_NOP 0 116#define OPA_LINKINIT_REASON_LINKUP (1 << 4) 117#define OPA_LINKINIT_REASON_FLAPPING (2 << 4) 118#define OPA_LINKINIT_REASON_CLEAR (8 << 4) 119#define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4) 120#define OPA_LINKINIT_QUARANTINED (9 << 4) 121#define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4) 122 123#define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ 124#define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ 125#define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ 126 127#define OPA_LINK_WIDTH_1X 0x0001 128#define OPA_LINK_WIDTH_2X 0x0002 129#define OPA_LINK_WIDTH_3X 0x0004 130#define OPA_LINK_WIDTH_4X 0x0008 131 132#define OPA_CAP_MASK3_IsSnoopSupported (1 << 7) 133#define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) 134#define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5) 135#define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4) 136#define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3) 137/* reserved (1 << 2) */ 138#define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1) 139#define OPA_CAP_MASK3_IsVLrSupported (1 << 0) 140 141/** 142 * new MTU values 143 */ 144enum { 145 OPA_MTU_8192 = 6, 146 OPA_MTU_10240 = 7, 147}; 148 149enum { 150 OPA_PORT_PHYS_CONF_DISCONNECTED = 0, 151 OPA_PORT_PHYS_CONF_STANDARD = 1, 152 OPA_PORT_PHYS_CONF_FIXED = 2, 153 OPA_PORT_PHYS_CONF_VARIABLE = 3, 154 OPA_PORT_PHYS_CONF_SI_PHOTO = 4 155}; 156 157enum port_info_field_masks { 158 /* vl.cap */ 159 OPA_PI_MASK_VL_CAP = 0x1F, 160 /* port_states.ledenable_offlinereason */ 161 OPA_PI_MASK_OFFLINE_REASON = 0x0F, 162 OPA_PI_MASK_LED_ENABLE = 0x40, 163 /* port_states.unsleepstate_downdefstate */ 164 OPA_PI_MASK_UNSLEEP_STATE = 0xF0, 165 OPA_PI_MASK_DOWNDEF_STATE = 0x0F, 166 /* port_states.portphysstate_portstate */ 167 OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0, 168 OPA_PI_MASK_PORT_STATE = 0x0F, 169 /* port_phys_conf */ 170 OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F, 171 /* collectivemask_multicastmask */ 172 OPA_PI_MASK_COLLECT_MASK = 0x38, 173 OPA_PI_MASK_MULTICAST_MASK = 0x07, 174 /* mkeyprotect_lmc */ 175 OPA_PI_MASK_MKEY_PROT_BIT = 0xC0, 176 OPA_PI_MASK_LMC = 0x0F, 177 /* smsl */ 178 OPA_PI_MASK_SMSL = 0x1F, 179 /* partenforce_filterraw */ 180 /* Filter Raw In/Out bits 1 and 2 were removed */ 181 OPA_PI_MASK_LINKINIT_REASON = 0xF0, 182 OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08, 183 OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04, 184 /* operational_vls */ 185 OPA_PI_MASK_OPERATIONAL_VL = 0x1F, 186 /* sa_qp */ 187 OPA_PI_MASK_SA_QP = 0x00FFFFFF, 188 /* sm_trap_qp */ 189 OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF, 190 /* localphy_overrun_errors */ 191 OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0, 192 OPA_PI_MASK_OVERRUN_ERRORS = 0x0F, 193 /* clientrereg_subnettimeout */ 194 OPA_PI_MASK_CLIENT_REREGISTER = 0x80, 195 OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F, 196 /* port_link_mode */ 197 OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10), 198 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5), 199 OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0), 200 /* port_link_crc_mode */ 201 OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00, 202 OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0, 203 OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F, 204 /* port_mode */ 205 OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001, 206 OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002, 207 OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004, 208 OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008, 209 OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010, 210 OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020, 211 OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040, 212 /* flit_control.interleave */ 213 OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12), 214 OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10), 215 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5), 216 OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0), 217 218 /* port_error_action */ 219 OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000, 220 /* 7 bits reserved */ 221 OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000, 222 OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000, 223 OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000, 224 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000, 225 OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000, 226 OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000, 227 OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000, 228 OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000, 229 /* 2 bits reserved */ 230 OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000, 231 OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000, 232 OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800, 233 /* 1 bit reserved */ 234 OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200, 235 /* 1 bit reserved */ 236 OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080, 237 OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040, 238 OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020, 239 OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010, 240 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008, 241 OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004, 242 OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002, 243 OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001, 244 245 /* pass_through.res_drctl */ 246 OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01, 247 248 /* buffer_units */ 249 OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11), 250 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6), 251 OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3), 252 OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0), 253 254 /* neigh_mtu.pvlx_to_mtu */ 255 OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0, 256 OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F, 257 258 /* neigh_mtu.vlstall_hoq_life */ 259 OPA_PI_MASK_VL_STALL = (0x03 << 5), 260 OPA_PI_MASK_HOQ_LIFE = (0x1F << 0), 261 262 /* port_neigh_mode */ 263 OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3), 264 OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2), 265 OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0), 266 267 /* resptime_value */ 268 OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F, 269 270 /* mtucap */ 271 OPA_PI_MASK_MTU_CAP = 0x0F, 272}; 273 274struct opa_port_states { 275 u8 reserved; 276 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */ 277 u8 reserved2; 278 u8 portphysstate_portstate; /* 4 bits, 4 bits */ 279}; 280 281struct opa_port_state_info { 282 struct opa_port_states port_states; 283 __be16 link_width_downgrade_tx_active; 284 __be16 link_width_downgrade_rx_active; 285}; 286 287struct opa_port_info { 288 __be32 lid; 289 __be32 flow_control_mask; 290 291 struct { 292 u8 res; /* was inittype */ 293 u8 cap; /* 3 res, 5 bits */ 294 __be16 high_limit; 295 __be16 preempt_limit; 296 u8 arb_high_cap; 297 u8 arb_low_cap; 298 } vl; 299 300 struct opa_port_states port_states; 301 u8 port_phys_conf; /* 4 res, 4 bits */ 302 u8 collectivemask_multicastmask; /* 2 res, 3, 3 */ 303 u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */ 304 u8 smsl; /* 3 res, 5 bits */ 305 306 u8 partenforce_filterraw; /* bit fields */ 307 u8 operational_vls; /* 3 res, 5 bits */ 308 __be16 pkey_8b; 309 __be16 pkey_10b; 310 __be16 mkey_violations; 311 312 __be16 pkey_violations; 313 __be16 qkey_violations; 314 __be32 sm_trap_qp; /* 8 bits, 24 bits */ 315 316 __be32 sa_qp; /* 8 bits, 24 bits */ 317 u8 neigh_port_num; 318 u8 link_down_reason; 319 u8 neigh_link_down_reason; 320 u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */ 321 322 struct { 323 __be16 supported; 324 __be16 enabled; 325 __be16 active; 326 } link_speed; 327 struct { 328 __be16 supported; 329 __be16 enabled; 330 __be16 active; 331 } link_width; 332 struct { 333 __be16 supported; 334 __be16 enabled; 335 __be16 tx_active; 336 __be16 rx_active; 337 } link_width_downgrade; 338 __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */ 339 __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */ 340 341 __be16 port_mode; /* 9 res, bit fields */ 342 struct { 343 __be16 supported; 344 __be16 enabled; 345 } port_packet_format; 346 struct { 347 __be16 interleave; /* 2 res, 2,2,5,5 */ 348 struct { 349 __be16 min_initial; 350 __be16 min_tail; 351 u8 large_pkt_limit; 352 u8 small_pkt_limit; 353 u8 max_small_pkt_limit; 354 u8 preemption_limit; 355 } preemption; 356 } flit_control; 357 358 __be32 reserved4; 359 __be32 port_error_action; /* bit field */ 360 361 struct { 362 u8 egress_port; 363 u8 res_drctl; /* 7 res, 1 */ 364 } pass_through; 365 __be16 mkey_lease_period; 366 __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */ 367 368 __be32 reserved5; 369 __be32 sm_lid; 370 371 __be64 mkey; 372 373 __be64 subnet_prefix; 374 375 struct { 376 u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */ 377 } neigh_mtu; 378 379 struct { 380 u8 vlstall_hoqlife; /* 3 bits, 5 bits */ 381 } xmit_q[OPA_MAX_VLS]; 382 383 struct { 384 u8 addr[16]; 385 } ipaddr_ipv6; 386 387 struct { 388 u8 addr[4]; 389 } ipaddr_ipv4; 390 391 u32 reserved6; 392 u32 reserved7; 393 u32 reserved8; 394 395 __be64 neigh_node_guid; 396 397 __be32 ib_cap_mask; 398 __be16 reserved9; /* was ib_cap_mask2 */ 399 __be16 opa_cap_mask; 400 401 __be32 reserved10; /* was link_roundtrip_latency */ 402 __be16 overall_buffer_space; 403 __be16 reserved11; /* was max_credit_hint */ 404 405 __be16 diag_code; 406 struct { 407 u8 buffer; 408 u8 wire; 409 } replay_depth; 410 u8 port_neigh_mode; 411 u8 mtucap; /* 4 res, 4 bits */ 412 413 u8 resptimevalue; /* 3 res, 5 bits */ 414 u8 local_port_num; 415 u8 reserved12; 416 u8 reserved13; /* was guid_cap */ 417} __attribute__ ((packed)); 418 419#endif /* OPA_PORT_INFO_H */ 420