12SN/A/*- 26SN/A * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 32SN/A * 42SN/A * Permission to use, copy, modify, and distribute this software for any 52SN/A * purpose with or without fee is hereby granted, provided that the above 62SN/A * copyright notice and this permission notice appear in all copies. 72SN/A * 82SN/A * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 92SN/A * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 102SN/A * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 112SN/A * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 122SN/A * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 132SN/A * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 142SN/A * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 152SN/A */ 162SN/A 172SN/A#include <sys/cdefs.h> 182SN/A#include "opt_wlan.h" 192SN/A 202SN/A#include <sys/param.h> 212SN/A#include <sys/sockio.h> 222SN/A#include <sys/sysctl.h> 232SN/A#include <sys/lock.h> 242SN/A#include <sys/mutex.h> 252SN/A#include <sys/mbuf.h> 261239Ssundar#include <sys/kernel.h> 272SN/A#include <sys/socket.h> 28664SN/A#include <sys/systm.h> 29664SN/A#include <sys/malloc.h> 301239Ssundar#include <sys/module.h> 311239Ssundar#include <sys/bus.h> 32664SN/A#include <sys/endian.h> 331088SN/A#include <sys/kdb.h> 342SN/A 352SN/A#include <net/if.h> 362SN/A#include <net/if_var.h> 372SN/A#include <net/if_arp.h> 382SN/A#include <net/ethernet.h> 392SN/A#include <net/if_dl.h> 402SN/A#include <net/if_media.h> 412SN/A#include <net/if_types.h> 422SN/A 432SN/A#ifdef INET 442SN/A#include <netinet/in.h> 452SN/A#include <netinet/in_systm.h> 462SN/A#include <netinet/in_var.h> 472SN/A#include <netinet/if_ether.h> 482SN/A#include <netinet/ip.h> 492SN/A#endif 502SN/A 512SN/A#include <net80211/ieee80211_var.h> 522SN/A#include <net80211/ieee80211_regdomain.h> 532SN/A#include <net80211/ieee80211_radiotap.h> 542SN/A 552SN/A#include <dev/usb/usb.h> 562SN/A#include <dev/usb/usbdi.h> 572SN/A#include "usbdevs.h" 582SN/A 592SN/A#include <dev/usb/wlan/if_urtwreg.h> 602SN/A#include <dev/usb/wlan/if_urtwvar.h> 612SN/A 622SN/A/* copy some rate indices from if_rtwn_ridx.h */ 632SN/A#define URTW_RIDX_CCK5 2 642SN/A#define URTW_RIDX_CCK11 3 652SN/A#define URTW_RIDX_OFDM6 4 662SN/A#define URTW_RIDX_OFDM24 8 672SN/A 682SN/Astatic SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 692SN/A "USB Realtek 8187L"); 702SN/A#ifdef URTW_DEBUG 712SN/Aint urtw_debug = 0; 72664SN/ASYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 73664SN/A "control debugging printfs"); 74664SN/Aenum { 75664SN/A URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 76664SN/A URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 77664SN/A URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 78664SN/A URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 79664SN/A URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 80664SN/A URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 81664SN/A URTW_DEBUG_STAT = 0x00000040, /* statistic */ 82664SN/A URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 83664SN/A URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 84664SN/A URTW_DEBUG_ANY = 0xffffffff 85664SN/A}; 86664SN/A#define DPRINTF(sc, m, fmt, ...) do { \ 87664SN/A if (sc->sc_debug & (m)) \ 882SN/A printf(fmt, __VA_ARGS__); \ 89} while (0) 90#else 91#define DPRINTF(sc, m, fmt, ...) do { \ 92 (void) sc; \ 93} while (0) 94#endif 95static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 96SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 97 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 98 99/* recognized device vendors/products */ 100#define urtw_lookup(v, p) \ 101 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 102#define URTW_DEV_B(v,p) \ 103 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 104#define URTW_DEV_L(v,p) \ 105 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 106#define URTW_REV_RTL8187B 0 107#define URTW_REV_RTL8187L 1 108static const STRUCT_USB_HOST_ID urtw_devs[] = { 109 URTW_DEV_B(NETGEAR, WG111V3), 110 URTW_DEV_B(REALTEK, RTL8187B_0), 111 URTW_DEV_B(REALTEK, RTL8187B_1), 112 URTW_DEV_B(REALTEK, RTL8187B_2), 113 URTW_DEV_B(SITECOMEU, WL168V4), 114 URTW_DEV_L(ASUS, P5B_WIFI), 115 URTW_DEV_L(BELKIN, F5D7050E), 116 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 117 URTW_DEV_L(NETGEAR, WG111V2), 118 URTW_DEV_L(REALTEK, RTL8187), 119 URTW_DEV_L(SITECOMEU, WL168V1), 120 URTW_DEV_L(SURECOM, EP9001G2A), 121 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 122 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 124 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 125 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 126 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 127 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 128#undef URTW_DEV_L 129#undef URTW_DEV_B 130}; 131 132#define urtw_read8_m(sc, val, data) do { \ 133 error = urtw_read8_c(sc, val, data); \ 134 if (error != 0) \ 135 goto fail; \ 136} while (0) 137#define urtw_write8_m(sc, val, data) do { \ 138 error = urtw_write8_c(sc, val, data); \ 139 if (error != 0) \ 140 goto fail; \ 141} while (0) 142#define urtw_read16_m(sc, val, data) do { \ 143 error = urtw_read16_c(sc, val, data); \ 144 if (error != 0) \ 145 goto fail; \ 146} while (0) 147#define urtw_write16_m(sc, val, data) do { \ 148 error = urtw_write16_c(sc, val, data); \ 149 if (error != 0) \ 150 goto fail; \ 151} while (0) 152#define urtw_read32_m(sc, val, data) do { \ 153 error = urtw_read32_c(sc, val, data); \ 154 if (error != 0) \ 155 goto fail; \ 156} while (0) 157#define urtw_write32_m(sc, val, data) do { \ 158 error = urtw_write32_c(sc, val, data); \ 159 if (error != 0) \ 160 goto fail; \ 161} while (0) 162#define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 163 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 164 if (error != 0) \ 165 goto fail; \ 166} while (0) 167#define urtw_8187_write_phy_cck(sc, val, data) do { \ 168 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 169 if (error != 0) \ 170 goto fail; \ 171} while (0) 172#define urtw_8225_write(sc, val, data) do { \ 173 error = urtw_8225_write_c(sc, val, data); \ 174 if (error != 0) \ 175 goto fail; \ 176} while (0) 177 178struct urtw_pair { 179 uint32_t reg; 180 uint32_t val; 181}; 182 183static uint8_t urtw_8225_agc[] = { 184 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 185 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 186 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 187 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 188 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 189 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 190 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 191 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 192 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 193 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 194 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 195 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 196}; 197 198static uint8_t urtw_8225z2_agc[] = { 199 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 200 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 201 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 202 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 203 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 204 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 205 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 206 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 207 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 208 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 209 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 210 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 211}; 212 213static uint32_t urtw_8225_channel[] = { 214 0x0000, /* dummy channel 0 */ 215 0x085c, /* 1 */ 216 0x08dc, /* 2 */ 217 0x095c, /* 3 */ 218 0x09dc, /* 4 */ 219 0x0a5c, /* 5 */ 220 0x0adc, /* 6 */ 221 0x0b5c, /* 7 */ 222 0x0bdc, /* 8 */ 223 0x0c5c, /* 9 */ 224 0x0cdc, /* 10 */ 225 0x0d5c, /* 11 */ 226 0x0ddc, /* 12 */ 227 0x0e5c, /* 13 */ 228 0x0f72, /* 14 */ 229}; 230 231static uint8_t urtw_8225_gain[] = { 232 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 233 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 234 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 235 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 236 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 237 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 238 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 239}; 240 241static struct urtw_pair urtw_8225_rf_part1[] = { 242 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 243 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 244 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 245 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 246}; 247 248static struct urtw_pair urtw_8225_rf_part2[] = { 249 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 250 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 251 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 252 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 253 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 254 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 255 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 256 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 257 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 258 { 0x27, 0x88 } 259}; 260 261static struct urtw_pair urtw_8225_rf_part3[] = { 262 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 263 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 264 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 265 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 266 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 267 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 268 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 269}; 270 271static uint16_t urtw_8225_rxgain[] = { 272 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 273 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 274 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 275 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 276 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 277 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 278 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 279 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 280 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 281 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 282 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 283 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 284}; 285 286static uint8_t urtw_8225_threshold[] = { 287 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 288}; 289 290static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 291 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 292}; 293 294static uint8_t urtw_8225_txpwr_cck[] = { 295 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 296 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 297 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 298 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 299 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 300 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 301}; 302 303static uint8_t urtw_8225_txpwr_cck_ch14[] = { 304 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 305 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 306 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 307 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 308 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 309 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 310}; 311 312static uint8_t urtw_8225_txpwr_ofdm[]={ 313 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 314}; 315 316static uint8_t urtw_8225v2_gain_bg[]={ 317 0x23, 0x15, 0xa5, /* -82-1dbm */ 318 0x23, 0x15, 0xb5, /* -82-2dbm */ 319 0x23, 0x15, 0xc5, /* -82-3dbm */ 320 0x33, 0x15, 0xc5, /* -78dbm */ 321 0x43, 0x15, 0xc5, /* -74dbm */ 322 0x53, 0x15, 0xc5, /* -70dbm */ 323 0x63, 0x15, 0xc5, /* -66dbm */ 324}; 325 326static struct urtw_pair urtw_8225v2_rf_part1[] = { 327 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 328 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 329 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 330 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 331}; 332 333static struct urtw_pair urtw_8225v2b_rf_part0[] = { 334 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 335 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 336 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 337 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 338}; 339 340static struct urtw_pair urtw_8225v2b_rf_part1[] = { 341 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 342 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 343 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 344 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 345 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 346 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 347 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 348 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 349 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 350 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 351 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 352 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 353 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 354 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 355 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 356 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 357 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 358 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 359 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 360 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 361 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 362 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 363 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 364 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 365 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 366 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 367 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 368 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 369 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 370 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 371 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 372}; 373 374static struct urtw_pair urtw_8225v2_rf_part2[] = { 375 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 376 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 377 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 378 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 379 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 380 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 381 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 382 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 383 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 384 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 385}; 386 387static struct urtw_pair urtw_8225v2b_rf_part2[] = { 388 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 389 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 390 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 391 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 392 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 393 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 394 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 395 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 396 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 397 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 398 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 399 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 400 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 401 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 402 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 403}; 404 405static struct urtw_pair urtw_8225v2_rf_part3[] = { 406 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 407 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 408 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 409 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 410 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 411 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 412 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 413 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 414}; 415 416static uint16_t urtw_8225v2_rxgain[] = { 417 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 418 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 419 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 420 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 421 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 422 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 423 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 424 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 425 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 426 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 427 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 428 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 429}; 430 431static uint16_t urtw_8225v2b_rxgain[] = { 432 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 433 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 434 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 435 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 436 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 437 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 438 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 439 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 440 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 441 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 442 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 443 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 444}; 445 446static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 447 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 448 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 449 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 450 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 451 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 452 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 453}; 454 455static uint8_t urtw_8225v2_txpwr_cck[] = { 456 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 457}; 458 459static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 460 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 461}; 462 463static uint8_t urtw_8225v2b_txpwr_cck[] = { 464 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 465 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 466 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 467 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 468}; 469 470static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 471 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 472 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 474 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 475}; 476 477static struct urtw_pair urtw_ratetable[] = { 478 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 479 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 480 { 96, 10 }, { 108, 11 } 481}; 482 483#if 0 484static const uint8_t urtw_8187b_reg_table[][3] = { 485 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 486 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 487 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 488 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 489 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 490 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 491 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 492 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 493 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 494 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 495 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 496 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 497 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 498 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 499 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 500 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 501 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 502 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 503 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 504 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 505 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 506 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 507 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 508 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 509 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 510 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 511 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 512 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 513 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 514 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 515 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 516}; 517#endif 518 519static usb_callback_t urtw_bulk_rx_callback; 520static usb_callback_t urtw_bulk_tx_callback; 521static usb_callback_t urtw_bulk_tx_status_callback; 522 523static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 524 [URTW_8187B_BULK_RX] = { 525 .type = UE_BULK, 526 .endpoint = 0x83, 527 .direction = UE_DIR_IN, 528 .bufsize = MCLBYTES, 529 .flags = { 530 .ext_buffer = 1, 531 .pipe_bof = 1, 532 .short_xfer_ok = 1 533 }, 534 .callback = urtw_bulk_rx_callback 535 }, 536 [URTW_8187B_BULK_TX_STATUS] = { 537 .type = UE_BULK, 538 .endpoint = 0x89, 539 .direction = UE_DIR_IN, 540 .bufsize = sizeof(uint64_t), 541 .flags = { 542 .pipe_bof = 1, 543 .short_xfer_ok = 1 544 }, 545 .callback = urtw_bulk_tx_status_callback 546 }, 547 [URTW_8187B_BULK_TX_BE] = { 548 .type = UE_BULK, 549 .endpoint = URTW_8187B_TXPIPE_BE, 550 .direction = UE_DIR_OUT, 551 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 552 .flags = { 553 .force_short_xfer = 1, 554 .pipe_bof = 1, 555 }, 556 .callback = urtw_bulk_tx_callback, 557 .timeout = URTW_DATA_TIMEOUT 558 }, 559 [URTW_8187B_BULK_TX_BK] = { 560 .type = UE_BULK, 561 .endpoint = URTW_8187B_TXPIPE_BK, 562 .direction = UE_DIR_OUT, 563 .bufsize = URTW_TX_MAXSIZE, 564 .flags = { 565 .ext_buffer = 1, 566 .force_short_xfer = 1, 567 .pipe_bof = 1, 568 }, 569 .callback = urtw_bulk_tx_callback, 570 .timeout = URTW_DATA_TIMEOUT 571 }, 572 [URTW_8187B_BULK_TX_VI] = { 573 .type = UE_BULK, 574 .endpoint = URTW_8187B_TXPIPE_VI, 575 .direction = UE_DIR_OUT, 576 .bufsize = URTW_TX_MAXSIZE, 577 .flags = { 578 .ext_buffer = 1, 579 .force_short_xfer = 1, 580 .pipe_bof = 1, 581 }, 582 .callback = urtw_bulk_tx_callback, 583 .timeout = URTW_DATA_TIMEOUT 584 }, 585 [URTW_8187B_BULK_TX_VO] = { 586 .type = UE_BULK, 587 .endpoint = URTW_8187B_TXPIPE_VO, 588 .direction = UE_DIR_OUT, 589 .bufsize = URTW_TX_MAXSIZE, 590 .flags = { 591 .ext_buffer = 1, 592 .force_short_xfer = 1, 593 .pipe_bof = 1, 594 }, 595 .callback = urtw_bulk_tx_callback, 596 .timeout = URTW_DATA_TIMEOUT 597 }, 598 [URTW_8187B_BULK_TX_EP12] = { 599 .type = UE_BULK, 600 .endpoint = 0xc, 601 .direction = UE_DIR_OUT, 602 .bufsize = URTW_TX_MAXSIZE, 603 .flags = { 604 .ext_buffer = 1, 605 .force_short_xfer = 1, 606 .pipe_bof = 1, 607 }, 608 .callback = urtw_bulk_tx_callback, 609 .timeout = URTW_DATA_TIMEOUT 610 } 611}; 612 613static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 614 [URTW_8187L_BULK_RX] = { 615 .type = UE_BULK, 616 .endpoint = 0x81, 617 .direction = UE_DIR_IN, 618 .bufsize = MCLBYTES, 619 .flags = { 620 .ext_buffer = 1, 621 .pipe_bof = 1, 622 .short_xfer_ok = 1 623 }, 624 .callback = urtw_bulk_rx_callback 625 }, 626 [URTW_8187L_BULK_TX_LOW] = { 627 .type = UE_BULK, 628 .endpoint = 0x2, 629 .direction = UE_DIR_OUT, 630 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 631 .flags = { 632 .force_short_xfer = 1, 633 .pipe_bof = 1, 634 }, 635 .callback = urtw_bulk_tx_callback, 636 .timeout = URTW_DATA_TIMEOUT 637 }, 638 [URTW_8187L_BULK_TX_NORMAL] = { 639 .type = UE_BULK, 640 .endpoint = 0x3, 641 .direction = UE_DIR_OUT, 642 .bufsize = URTW_TX_MAXSIZE, 643 .flags = { 644 .ext_buffer = 1, 645 .force_short_xfer = 1, 646 .pipe_bof = 1, 647 }, 648 .callback = urtw_bulk_tx_callback, 649 .timeout = URTW_DATA_TIMEOUT 650 }, 651}; 652 653static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 654 const char [IFNAMSIZ], int, enum ieee80211_opmode, 655 int, const uint8_t [IEEE80211_ADDR_LEN], 656 const uint8_t [IEEE80211_ADDR_LEN]); 657static void urtw_vap_delete(struct ieee80211vap *); 658static void urtw_init(struct urtw_softc *); 659static void urtw_stop(struct urtw_softc *); 660static void urtw_parent(struct ieee80211com *); 661static int urtw_transmit(struct ieee80211com *, struct mbuf *); 662static void urtw_start(struct urtw_softc *); 663static int urtw_alloc_rx_data_list(struct urtw_softc *); 664static int urtw_alloc_tx_data_list(struct urtw_softc *); 665static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 666 const struct ieee80211_bpf_params *); 667static void urtw_scan_start(struct ieee80211com *); 668static void urtw_scan_end(struct ieee80211com *); 669static void urtw_getradiocaps(struct ieee80211com *, int, int *, 670 struct ieee80211_channel[]); 671static void urtw_set_channel(struct ieee80211com *); 672static void urtw_update_promisc(struct ieee80211com *); 673static void urtw_update_mcast(struct ieee80211com *); 674static int urtw_tx_start(struct urtw_softc *, 675 struct ieee80211_node *, struct mbuf *, 676 struct urtw_data *, int); 677static int urtw_newstate(struct ieee80211vap *, 678 enum ieee80211_state, int); 679static void urtw_led_ch(void *); 680static void urtw_ledtask(void *, int); 681static void urtw_watchdog(void *); 682static void urtw_set_multi(void *); 683static int urtw_isbmode(uint16_t); 684static uint16_t urtw_rtl2rate(uint32_t); 685static usb_error_t urtw_set_rate(struct urtw_softc *); 686static usb_error_t urtw_update_msr(struct urtw_softc *); 687static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 688static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 689static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 690static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 691static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 692static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 693static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 694static usb_error_t urtw_eprom_ck(struct urtw_softc *); 695static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 696 int); 697static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 698 uint32_t *); 699static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 700static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 701static usb_error_t urtw_get_macaddr(struct urtw_softc *); 702static usb_error_t urtw_get_txpwr(struct urtw_softc *); 703static usb_error_t urtw_get_rfchip(struct urtw_softc *); 704static usb_error_t urtw_led_init(struct urtw_softc *); 705static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 706static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 707static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 708 uint32_t); 709static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 710 uint8_t, uint32_t); 711static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 712 uint32_t); 713static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 714static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 715static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 716 uint16_t); 717static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 718 uint16_t *); 719static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 720 uint32_t *); 721static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 722static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 723static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 724static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 725static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 726static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 727static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 728static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 729static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 730static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 731static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 732static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 733static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 734static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 735static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 736static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 737static usb_error_t urtw_intr_enable(struct urtw_softc *); 738static usb_error_t urtw_intr_disable(struct urtw_softc *); 739static usb_error_t urtw_reset(struct urtw_softc *); 740static usb_error_t urtw_led_on(struct urtw_softc *, int); 741static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 742static usb_error_t urtw_led_blink(struct urtw_softc *); 743static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 744static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 745static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 746static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 747static usb_error_t urtw_rx_setconf(struct urtw_softc *); 748static usb_error_t urtw_rx_enable(struct urtw_softc *); 749static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 750static void urtw_free_tx_data_list(struct urtw_softc *); 751static void urtw_free_rx_data_list(struct urtw_softc *); 752static void urtw_free_data_list(struct urtw_softc *, 753 struct urtw_data data[], int, int); 754static usb_error_t urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 755static usb_error_t urtw_adapter_start(struct urtw_softc *); 756static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 757static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 758static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 759static usb_error_t urtw_do_request(struct urtw_softc *, 760 struct usb_device_request *, void *); 761static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 762static usb_error_t urtw_led_off(struct urtw_softc *, int); 763static void urtw_abort_xfers(struct urtw_softc *); 764static struct urtw_data * 765 urtw_getbuf(struct urtw_softc *sc); 766static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 767 uint8_t); 768static void urtw_updateslot(struct ieee80211com *); 769static void urtw_updateslottask(void *, int); 770static void urtw_sysctl_node(struct urtw_softc *); 771 772static int 773urtw_match(device_t dev) 774{ 775 struct usb_attach_arg *uaa = device_get_ivars(dev); 776 777 if (uaa->usb_mode != USB_MODE_HOST) 778 return (ENXIO); 779 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 780 return (ENXIO); 781 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 782 return (ENXIO); 783 784 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 785} 786 787static int 788urtw_attach(device_t dev) 789{ 790 const struct usb_config *setup_start; 791 int ret = ENXIO; 792 struct urtw_softc *sc = device_get_softc(dev); 793 struct usb_attach_arg *uaa = device_get_ivars(dev); 794 struct ieee80211com *ic = &sc->sc_ic; 795 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 796 uint16_t n_setup; 797 uint32_t data; 798 usb_error_t error; 799 800 device_set_usb_desc(dev); 801 802 sc->sc_dev = dev; 803 sc->sc_udev = uaa->device; 804 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 805 sc->sc_flags |= URTW_RTL8187B; 806#ifdef URTW_DEBUG 807 sc->sc_debug = urtw_debug; 808#endif 809 810 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 811 MTX_DEF); 812 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 813 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 814 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 815 callout_init(&sc->sc_watchdog_ch, 0); 816 mbufq_init(&sc->sc_snd, ifqmaxlen); 817 818 if (sc->sc_flags & URTW_RTL8187B) { 819 setup_start = urtw_8187b_usbconfig; 820 n_setup = URTW_8187B_N_XFERS; 821 } else { 822 setup_start = urtw_8187l_usbconfig; 823 n_setup = URTW_8187L_N_XFERS; 824 } 825 826 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 827 setup_start, n_setup, sc, &sc->sc_mtx); 828 if (error) { 829 device_printf(dev, "could not allocate USB transfers, " 830 "err=%s\n", usbd_errstr(error)); 831 ret = ENXIO; 832 goto fail0; 833 } 834 835 if (sc->sc_flags & URTW_RTL8187B) { 836 sc->sc_tx_dma_buf = 837 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 838 URTW_8187B_BULK_TX_BE], 0); 839 } else { 840 sc->sc_tx_dma_buf = 841 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 842 URTW_8187L_BULK_TX_LOW], 0); 843 } 844 845 URTW_LOCK(sc); 846 847 urtw_read32_m(sc, URTW_RX, &data); 848 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 849 URTW_EEPROM_93C46; 850 851 error = urtw_get_rfchip(sc); 852 if (error != 0) 853 goto fail; 854 error = urtw_get_macaddr(sc); 855 if (error != 0) 856 goto fail; 857 error = urtw_get_txpwr(sc); 858 if (error != 0) 859 goto fail; 860 error = urtw_led_init(sc); 861 if (error != 0) 862 goto fail; 863 864 URTW_UNLOCK(sc); 865 866 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 867 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 868 sc->sc_currate = URTW_RIDX_CCK11; 869 sc->sc_preamble_mode = urtw_preamble_mode; 870 871 ic->ic_softc = sc; 872 ic->ic_name = device_get_nameunit(dev); 873 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 874 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 875 876 /* set device capabilities */ 877 ic->ic_caps = 878 IEEE80211_C_STA | /* station mode */ 879 IEEE80211_C_MONITOR | /* monitor mode supported */ 880 IEEE80211_C_TXPMGT | /* tx power management */ 881 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 882 IEEE80211_C_SHSLOT | /* short slot time supported */ 883 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 884 IEEE80211_C_WPA; /* 802.11i */ 885 886 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/ 887 888 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 889 ic->ic_channels); 890 891 ieee80211_ifattach(ic); 892 ic->ic_raw_xmit = urtw_raw_xmit; 893 ic->ic_scan_start = urtw_scan_start; 894 ic->ic_scan_end = urtw_scan_end; 895 ic->ic_getradiocaps = urtw_getradiocaps; 896 ic->ic_set_channel = urtw_set_channel; 897 ic->ic_updateslot = urtw_updateslot; 898 ic->ic_vap_create = urtw_vap_create; 899 ic->ic_vap_delete = urtw_vap_delete; 900 ic->ic_update_promisc = urtw_update_promisc; 901 ic->ic_update_mcast = urtw_update_mcast; 902 ic->ic_parent = urtw_parent; 903 ic->ic_transmit = urtw_transmit; 904 905 ieee80211_radiotap_attach(ic, 906 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 907 URTW_TX_RADIOTAP_PRESENT, 908 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 909 URTW_RX_RADIOTAP_PRESENT); 910 911 urtw_sysctl_node(sc); 912 913 if (bootverbose) 914 ieee80211_announce(ic); 915 return (0); 916 917fail: 918 URTW_UNLOCK(sc); 919 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 920 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 921fail0: 922 return (ret); 923} 924 925static int 926urtw_detach(device_t dev) 927{ 928 struct urtw_softc *sc = device_get_softc(dev); 929 struct ieee80211com *ic = &sc->sc_ic; 930 unsigned x; 931 unsigned n_xfers; 932 933 /* Prevent further ioctls */ 934 URTW_LOCK(sc); 935 sc->sc_flags |= URTW_DETACHED; 936 urtw_stop(sc); 937 URTW_UNLOCK(sc); 938 939 ieee80211_draintask(ic, &sc->sc_updateslot_task); 940 ieee80211_draintask(ic, &sc->sc_led_task); 941 942 usb_callout_drain(&sc->sc_led_ch); 943 callout_drain(&sc->sc_watchdog_ch); 944 945 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 946 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 947 948 /* prevent further allocations from RX/TX data lists */ 949 URTW_LOCK(sc); 950 STAILQ_INIT(&sc->sc_tx_active); 951 STAILQ_INIT(&sc->sc_tx_inactive); 952 STAILQ_INIT(&sc->sc_tx_pending); 953 954 STAILQ_INIT(&sc->sc_rx_active); 955 STAILQ_INIT(&sc->sc_rx_inactive); 956 URTW_UNLOCK(sc); 957 958 /* drain USB transfers */ 959 for (x = 0; x != n_xfers; x++) 960 usbd_transfer_drain(sc->sc_xfer[x]); 961 962 /* free data buffers */ 963 URTW_LOCK(sc); 964 urtw_free_tx_data_list(sc); 965 urtw_free_rx_data_list(sc); 966 URTW_UNLOCK(sc); 967 968 /* free USB transfers and some data buffers */ 969 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 970 971 ieee80211_ifdetach(ic); 972 mbufq_drain(&sc->sc_snd); 973 mtx_destroy(&sc->sc_mtx); 974 return (0); 975} 976 977static void 978urtw_free_tx_data_list(struct urtw_softc *sc) 979{ 980 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 981} 982 983static void 984urtw_free_rx_data_list(struct urtw_softc *sc) 985{ 986 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 987} 988 989static void 990urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 991 int fillmbuf) 992{ 993 int i; 994 995 for (i = 0; i < ndata; i++) { 996 struct urtw_data *dp = &data[i]; 997 998 if (fillmbuf == 1) { 999 if (dp->m != NULL) { 1000 m_freem(dp->m); 1001 dp->m = NULL; 1002 dp->buf = NULL; 1003 } 1004 } else { 1005 dp->buf = NULL; 1006 } 1007 if (dp->ni != NULL) { 1008 ieee80211_free_node(dp->ni); 1009 dp->ni = NULL; 1010 } 1011 } 1012} 1013 1014static struct ieee80211vap * 1015urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1016 enum ieee80211_opmode opmode, int flags, 1017 const uint8_t bssid[IEEE80211_ADDR_LEN], 1018 const uint8_t mac[IEEE80211_ADDR_LEN]) 1019{ 1020 struct urtw_vap *uvp; 1021 struct ieee80211vap *vap; 1022 1023 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1024 return (NULL); 1025 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1026 vap = &uvp->vap; 1027 /* enable s/w bmiss handling for sta mode */ 1028 1029 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1030 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1031 /* out of memory */ 1032 free(uvp, M_80211_VAP); 1033 return (NULL); 1034 } 1035 1036 /* override state transition machine */ 1037 uvp->newstate = vap->iv_newstate; 1038 vap->iv_newstate = urtw_newstate; 1039 1040 /* complete setup */ 1041 ieee80211_vap_attach(vap, ieee80211_media_change, 1042 ieee80211_media_status, mac); 1043 ic->ic_opmode = opmode; 1044 return (vap); 1045} 1046 1047static void 1048urtw_vap_delete(struct ieee80211vap *vap) 1049{ 1050 struct urtw_vap *uvp = URTW_VAP(vap); 1051 1052 ieee80211_vap_detach(vap); 1053 free(uvp, M_80211_VAP); 1054} 1055 1056static void 1057urtw_init(struct urtw_softc *sc) 1058{ 1059 usb_error_t error; 1060 int ret; 1061 1062 URTW_ASSERT_LOCKED(sc); 1063 1064 if (sc->sc_flags & URTW_RUNNING) 1065 urtw_stop(sc); 1066 1067 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1068 urtw_adapter_start(sc); 1069 if (error != 0) 1070 goto fail; 1071 1072 /* reset softc variables */ 1073 sc->sc_txtimer = 0; 1074 1075 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1076 ret = urtw_alloc_rx_data_list(sc); 1077 if (ret != 0) 1078 goto fail; 1079 ret = urtw_alloc_tx_data_list(sc); 1080 if (ret != 0) 1081 goto fail; 1082 sc->sc_flags |= URTW_INIT_ONCE; 1083 } 1084 1085 error = urtw_rx_enable(sc); 1086 if (error != 0) 1087 goto fail; 1088 error = urtw_tx_enable(sc); 1089 if (error != 0) 1090 goto fail; 1091 1092 if (sc->sc_flags & URTW_RTL8187B) 1093 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1094 1095 sc->sc_flags |= URTW_RUNNING; 1096 1097 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1098fail: 1099 return; 1100} 1101 1102static usb_error_t 1103urtw_adapter_start_b(struct urtw_softc *sc) 1104{ 1105 uint8_t data8; 1106 usb_error_t error; 1107 1108 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1109 if (error) 1110 goto fail; 1111 1112 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1113 urtw_write8_m(sc, URTW_CONFIG3, 1114 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1115 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1116 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1117 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1118 1119 urtw_write8_m(sc, 0x61, 0x10); 1120 urtw_read8_m(sc, 0x62, &data8); 1121 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1122 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1123 1124 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1125 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1126 urtw_write8_m(sc, URTW_CONFIG3, data8); 1127 1128 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1129 if (error) 1130 goto fail; 1131 1132 error = urtw_8187b_cmd_reset(sc); 1133 if (error) 1134 goto fail; 1135 1136 error = sc->sc_rf_init(sc); 1137 if (error != 0) 1138 goto fail; 1139 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1140 1141 /* fix RTL8187B RX stall */ 1142 error = urtw_intr_enable(sc); 1143 if (error) 1144 goto fail; 1145 1146 error = urtw_write8e(sc, 0x41, 0xf4); 1147 if (error) 1148 goto fail; 1149 error = urtw_write8e(sc, 0x40, 0x00); 1150 if (error) 1151 goto fail; 1152 error = urtw_write8e(sc, 0x42, 0x00); 1153 if (error) 1154 goto fail; 1155 error = urtw_write8e(sc, 0x42, 0x01); 1156 if (error) 1157 goto fail; 1158 error = urtw_write8e(sc, 0x40, 0x0f); 1159 if (error) 1160 goto fail; 1161 error = urtw_write8e(sc, 0x42, 0x00); 1162 if (error) 1163 goto fail; 1164 error = urtw_write8e(sc, 0x42, 0x01); 1165 if (error) 1166 goto fail; 1167 1168 urtw_read8_m(sc, 0xdb, &data8); 1169 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1170 urtw_write16_m(sc, 0x372, 0x59fa); 1171 urtw_write16_m(sc, 0x374, 0x59d2); 1172 urtw_write16_m(sc, 0x376, 0x59d2); 1173 urtw_write16_m(sc, 0x378, 0x19fa); 1174 urtw_write16_m(sc, 0x37a, 0x19fa); 1175 urtw_write16_m(sc, 0x37c, 0x00d0); 1176 urtw_write8_m(sc, 0x61, 0); 1177 1178 urtw_write8_m(sc, 0x180, 0x0f); 1179 urtw_write8_m(sc, 0x183, 0x03); 1180 urtw_write8_m(sc, 0xda, 0x10); 1181 urtw_write8_m(sc, 0x24d, 0x08); 1182 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1183 1184 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1185fail: 1186 return (error); 1187} 1188 1189static usb_error_t 1190urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *macaddr) 1191{ 1192 usb_error_t error; 1193 1194 urtw_write32_m(sc, URTW_MAC0, ((const uint32_t *)macaddr)[0]); 1195 urtw_write16_m(sc, URTW_MAC4, ((const uint32_t *)macaddr)[1] & 0xffff); 1196 1197fail: 1198 return (error); 1199} 1200 1201static usb_error_t 1202urtw_adapter_start(struct urtw_softc *sc) 1203{ 1204 struct ieee80211com *ic = &sc->sc_ic; 1205 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1206 const uint8_t *macaddr; 1207 usb_error_t error; 1208 1209 error = urtw_reset(sc); 1210 if (error) 1211 goto fail; 1212 1213 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1214 urtw_write8_m(sc, URTW_GPIO, 0); 1215 1216 /* for led */ 1217 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1218 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1219 if (error != 0) 1220 goto fail; 1221 1222 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1223 if (error) 1224 goto fail; 1225 /* applying MAC address again. */ 1226 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 1227 urtw_set_macaddr(sc, macaddr); 1228 if (error) 1229 goto fail; 1230 1231 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1232 if (error) 1233 goto fail; 1234 1235 error = urtw_update_msr(sc); 1236 if (error) 1237 goto fail; 1238 1239 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1240 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1241 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1242 error = urtw_set_rate(sc); 1243 if (error != 0) 1244 goto fail; 1245 1246 error = sc->sc_rf_init(sc); 1247 if (error != 0) 1248 goto fail; 1249 if (sc->sc_rf_set_sens != NULL) 1250 sc->sc_rf_set_sens(sc, sc->sc_sens); 1251 1252 /* XXX correct? to call write16 */ 1253 urtw_write16_m(sc, URTW_PSR, 1); 1254 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1255 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1256 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1257 /* XXX correct? to call write16 */ 1258 urtw_write16_m(sc, URTW_PSR, 0); 1259 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1260 1261 error = urtw_intr_enable(sc); 1262 if (error != 0) 1263 goto fail; 1264 1265fail: 1266 return (error); 1267} 1268 1269static usb_error_t 1270urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1271{ 1272 uint8_t data; 1273 usb_error_t error; 1274 1275 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1276 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1277 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1278 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1279fail: 1280 return (error); 1281} 1282 1283static void 1284urtw_pause_ms(struct urtw_softc *sc, int delay) 1285{ 1286 usb_pause_mtx(&sc->sc_mtx, USB_MS_TO_TICKS(delay)); 1287} 1288 1289static usb_error_t 1290urtw_8187b_cmd_reset(struct urtw_softc *sc) 1291{ 1292 int i; 1293 uint8_t data8; 1294 usb_error_t error; 1295 1296 /* XXX the code can be duplicate with urtw_reset(). */ 1297 urtw_read8_m(sc, URTW_CMD, &data8); 1298 data8 = (data8 & 0x2) | URTW_CMD_RST; 1299 urtw_write8_m(sc, URTW_CMD, data8); 1300 1301 for (i = 0; i < 20; i++) { 1302 urtw_pause_ms(sc, 2); 1303 urtw_read8_m(sc, URTW_CMD, &data8); 1304 if (!(data8 & URTW_CMD_RST)) 1305 break; 1306 } 1307 if (i >= 20) { 1308 device_printf(sc->sc_dev, "reset timeout\n"); 1309 goto fail; 1310 } 1311fail: 1312 return (error); 1313} 1314 1315static usb_error_t 1316urtw_do_request(struct urtw_softc *sc, 1317 struct usb_device_request *req, void *data) 1318{ 1319 usb_error_t err; 1320 int ntries = 10; 1321 1322 URTW_ASSERT_LOCKED(sc); 1323 1324 while (ntries--) { 1325 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1326 req, data, 0, NULL, 250 /* ms */); 1327 if (err == 0) 1328 break; 1329 1330 DPRINTF(sc, URTW_DEBUG_INIT, 1331 "Control request failed, %s (retrying)\n", 1332 usbd_errstr(err)); 1333 urtw_pause_ms(sc, 10); 1334 } 1335 return (err); 1336} 1337 1338static void 1339urtw_stop(struct urtw_softc *sc) 1340{ 1341 uint8_t data8; 1342 usb_error_t error; 1343 1344 URTW_ASSERT_LOCKED(sc); 1345 1346 sc->sc_flags &= ~URTW_RUNNING; 1347 1348 error = urtw_intr_disable(sc); 1349 if (error) 1350 goto fail; 1351 urtw_read8_m(sc, URTW_CMD, &data8); 1352 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1353 urtw_write8_m(sc, URTW_CMD, data8); 1354 1355 error = sc->sc_rf_stop(sc); 1356 if (error != 0) 1357 goto fail; 1358 1359 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1360 if (error) 1361 goto fail; 1362 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1363 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1364 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1365 if (error) 1366 goto fail; 1367fail: 1368 if (error) 1369 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1370 usbd_errstr(error)); 1371 1372 usb_callout_stop(&sc->sc_led_ch); 1373 callout_stop(&sc->sc_watchdog_ch); 1374 1375 urtw_abort_xfers(sc); 1376} 1377 1378static void 1379urtw_abort_xfers(struct urtw_softc *sc) 1380{ 1381 int i, max; 1382 1383 URTW_ASSERT_LOCKED(sc); 1384 1385 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1386 URTW_8187L_N_XFERS; 1387 1388 /* abort any pending transfers */ 1389 for (i = 0; i < max; i++) 1390 usbd_transfer_stop(sc->sc_xfer[i]); 1391} 1392 1393static void 1394urtw_parent(struct ieee80211com *ic) 1395{ 1396 struct urtw_softc *sc = ic->ic_softc; 1397 int startall = 0; 1398 1399 URTW_LOCK(sc); 1400 if (sc->sc_flags & URTW_DETACHED) { 1401 URTW_UNLOCK(sc); 1402 return; 1403 } 1404 1405 if (ic->ic_nrunning > 0) { 1406 if (sc->sc_flags & URTW_RUNNING) { 1407 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1408 urtw_set_multi(sc); 1409 } else { 1410 urtw_init(sc); 1411 startall = 1; 1412 } 1413 } else if (sc->sc_flags & URTW_RUNNING) 1414 urtw_stop(sc); 1415 URTW_UNLOCK(sc); 1416 if (startall) 1417 ieee80211_start_all(ic); 1418} 1419 1420static int 1421urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1422{ 1423 struct urtw_softc *sc = ic->ic_softc; 1424 int error; 1425 1426 URTW_LOCK(sc); 1427 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1428 URTW_UNLOCK(sc); 1429 return (ENXIO); 1430 } 1431 error = mbufq_enqueue(&sc->sc_snd, m); 1432 if (error) { 1433 URTW_UNLOCK(sc); 1434 return (error); 1435 } 1436 urtw_start(sc); 1437 URTW_UNLOCK(sc); 1438 1439 return (0); 1440} 1441 1442static void 1443urtw_start(struct urtw_softc *sc) 1444{ 1445 struct urtw_data *bf; 1446 struct ieee80211_node *ni; 1447 struct mbuf *m; 1448 1449 URTW_ASSERT_LOCKED(sc); 1450 1451 if ((sc->sc_flags & URTW_RUNNING) == 0) 1452 return; 1453 1454 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1455 bf = urtw_getbuf(sc); 1456 if (bf == NULL) { 1457 mbufq_prepend(&sc->sc_snd, m); 1458 break; 1459 } 1460 1461 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1462 m->m_pkthdr.rcvif = NULL; 1463 1464 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1465 if_inc_counter(ni->ni_vap->iv_ifp, 1466 IFCOUNTER_OERRORS, 1); 1467 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1468 ieee80211_free_node(ni); 1469 break; 1470 } 1471 1472 sc->sc_txtimer = 5; 1473 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1474 } 1475} 1476 1477static int 1478urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1479 int ndata, int maxsz, void *dma_buf) 1480{ 1481 int i, error; 1482 1483 for (i = 0; i < ndata; i++) { 1484 struct urtw_data *dp = &data[i]; 1485 1486 dp->sc = sc; 1487 if (dma_buf == NULL) { 1488 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1489 if (dp->m == NULL) { 1490 device_printf(sc->sc_dev, 1491 "could not allocate rx mbuf\n"); 1492 error = ENOMEM; 1493 goto fail; 1494 } 1495 dp->buf = mtod(dp->m, uint8_t *); 1496 } else { 1497 dp->m = NULL; 1498 dp->buf = ((uint8_t *)dma_buf) + 1499 (i * maxsz); 1500 } 1501 dp->ni = NULL; 1502 } 1503 return (0); 1504 1505fail: urtw_free_data_list(sc, data, ndata, 1); 1506 return (error); 1507} 1508 1509static int 1510urtw_alloc_rx_data_list(struct urtw_softc *sc) 1511{ 1512 int error, i; 1513 1514 error = urtw_alloc_data_list(sc, 1515 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1516 MCLBYTES, NULL /* mbufs */); 1517 if (error != 0) 1518 return (error); 1519 1520 STAILQ_INIT(&sc->sc_rx_active); 1521 STAILQ_INIT(&sc->sc_rx_inactive); 1522 1523 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1524 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1525 1526 return (0); 1527} 1528 1529static int 1530urtw_alloc_tx_data_list(struct urtw_softc *sc) 1531{ 1532 int error, i; 1533 1534 error = urtw_alloc_data_list(sc, 1535 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1536 sc->sc_tx_dma_buf /* no mbufs */); 1537 if (error != 0) 1538 return (error); 1539 1540 STAILQ_INIT(&sc->sc_tx_active); 1541 STAILQ_INIT(&sc->sc_tx_inactive); 1542 STAILQ_INIT(&sc->sc_tx_pending); 1543 1544 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1545 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1546 next); 1547 1548 return (0); 1549} 1550 1551static int 1552urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1553 const struct ieee80211_bpf_params *params) 1554{ 1555 struct ieee80211com *ic = ni->ni_ic; 1556 struct urtw_softc *sc = ic->ic_softc; 1557 struct urtw_data *bf; 1558 1559 /* prevent management frames from being sent if we're not ready */ 1560 if (!(sc->sc_flags & URTW_RUNNING)) { 1561 m_freem(m); 1562 return ENETDOWN; 1563 } 1564 URTW_LOCK(sc); 1565 bf = urtw_getbuf(sc); 1566 if (bf == NULL) { 1567 m_freem(m); 1568 URTW_UNLOCK(sc); 1569 return (ENOBUFS); /* XXX */ 1570 } 1571 1572 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1573 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1574 URTW_UNLOCK(sc); 1575 return (EIO); 1576 } 1577 URTW_UNLOCK(sc); 1578 1579 sc->sc_txtimer = 5; 1580 return (0); 1581} 1582 1583static void 1584urtw_scan_start(struct ieee80211com *ic) 1585{ 1586 1587 /* XXX do nothing? */ 1588} 1589 1590static void 1591urtw_scan_end(struct ieee80211com *ic) 1592{ 1593 1594 /* XXX do nothing? */ 1595} 1596 1597static void 1598urtw_getradiocaps(struct ieee80211com *ic, 1599 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1600{ 1601 uint8_t bands[IEEE80211_MODE_BYTES]; 1602 1603 memset(bands, 0, sizeof(bands)); 1604 setbit(bands, IEEE80211_MODE_11B); 1605 setbit(bands, IEEE80211_MODE_11G); 1606 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1607} 1608 1609static void 1610urtw_set_channel(struct ieee80211com *ic) 1611{ 1612 struct urtw_softc *sc = ic->ic_softc; 1613 uint32_t data, orig; 1614 usb_error_t error; 1615 1616 /* 1617 * if the user set a channel explicitly using ifconfig(8) this function 1618 * can be called earlier than we're expected that in some cases the 1619 * initialization would be failed if setting a channel is called before 1620 * the init have done. 1621 */ 1622 if (!(sc->sc_flags & URTW_RUNNING)) 1623 return; 1624 1625 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1626 return; 1627 1628 URTW_LOCK(sc); 1629 1630 /* 1631 * during changing th channel we need to temporarily be disable 1632 * TX. 1633 */ 1634 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1635 data = orig & ~URTW_TX_LOOPBACK_MASK; 1636 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1637 1638 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1639 if (error != 0) 1640 goto fail; 1641 urtw_pause_ms(sc, 10); 1642 urtw_write32_m(sc, URTW_TX_CONF, orig); 1643 1644 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1645 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1646 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1647 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1648 1649fail: 1650 URTW_UNLOCK(sc); 1651 1652 sc->sc_curchan = ic->ic_curchan; 1653 1654 if (error != 0) 1655 device_printf(sc->sc_dev, "could not change the channel\n"); 1656} 1657 1658static void 1659urtw_update_promisc(struct ieee80211com *ic) 1660{ 1661 struct urtw_softc *sc = ic->ic_softc; 1662 1663 URTW_LOCK(sc); 1664 if (sc->sc_flags & URTW_RUNNING) 1665 urtw_rx_setconf(sc); 1666 URTW_UNLOCK(sc); 1667} 1668 1669static void 1670urtw_update_mcast(struct ieee80211com *ic) 1671{ 1672 1673 /* XXX do nothing? */ 1674} 1675 1676static int 1677urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1678 struct urtw_data *data, int prior) 1679{ 1680 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1681 struct ieee80211_key *k; 1682 const struct ieee80211_txparam *tp = ni->ni_txparms; 1683 struct ieee80211com *ic = &sc->sc_ic; 1684 struct ieee80211vap *vap = ni->ni_vap; 1685 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1686 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1687 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1688 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1689 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1690 }; 1691 struct usb_xfer *xfer; 1692 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type, 1693 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast; 1694 uint16_t acktime, rtstime, ctstime; 1695 uint32_t flags; 1696 usb_error_t error; 1697 1698 URTW_ASSERT_LOCKED(sc); 1699 1700 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1701 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1702 1703 /* 1704 * Software crypto. 1705 */ 1706 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1707 k = ieee80211_crypto_encap(ni, m0); 1708 if (k == NULL) { 1709 device_printf(sc->sc_dev, 1710 "ieee80211_crypto_encap returns NULL.\n"); 1711 /* XXX we don't expect the fragmented frames */ 1712 m_freem(m0); 1713 return (ENOBUFS); 1714 } 1715 1716 /* in case packet header moved, reset pointer */ 1717 wh = mtod(m0, struct ieee80211_frame *); 1718 } 1719 1720 if (ieee80211_radiotap_active_vap(vap)) { 1721 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1722 1723 tap->wt_flags = 0; 1724 ieee80211_radiotap_tx(vap, m0); 1725 } 1726 1727 if (type == IEEE80211_FC0_TYPE_MGT || 1728 type == IEEE80211_FC0_TYPE_CTL || 1729 (m0->m_flags & M_EAPOL) != 0) { 1730 rate = tp->mgmtrate; 1731 } else { 1732 /* for data frames */ 1733 if (ismcast) 1734 rate = tp->mcastrate; 1735 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1736 rate = tp->ucastrate; 1737 else 1738 rate = urtw_rtl2rate(sc->sc_currate); 1739 } 1740 1741 sc->sc_stats.txrates[sc->sc_currate]++; 1742 1743 if (ismcast) 1744 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1745 IEEE80211_CRC_LEN, rate, 0, 0); 1746 else { 1747 acktime = urtw_compute_txtime(14, 2,0, 0); 1748 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1749 rtsenable = 1; 1750 ctsenable = 0; 1751 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1752 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1753 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1754 IEEE80211_CRC_LEN, rate, 0, isshort); 1755 rtsdur = ctstime + pkttime + acktime + 1756 3 * URTW_ASIFS_TIME; 1757 txdur = rtstime + rtsdur; 1758 } else { 1759 rtsenable = ctsenable = rtsdur = 0; 1760 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1761 IEEE80211_CRC_LEN, rate, 0, isshort); 1762 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1763 } 1764 1765 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1766 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1767 IEEE80211_CRC_LEN, rate, 0, isshort) + 1768 3 * URTW_ASIFS_TIME + 1769 2 * acktime; 1770 else 1771 dur = URTW_ASIFS_TIME + acktime; 1772 } 1773 USETW(wh->i_dur, dur); 1774 1775 xferlen = m0->m_pkthdr.len; 1776 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1777 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1778 xferlen += 1; 1779 1780 memset(data->buf, 0, URTW_TX_MAXSIZE); 1781 flags = m0->m_pkthdr.len & 0xfff; 1782 flags |= URTW_TX_FLAG_NO_ENC; 1783 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1784 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1785 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1786 (sc->sc_currate != 0)) 1787 flags |= URTW_TX_FLAG_SPLCP; 1788 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1789 flags |= URTW_TX_FLAG_MOREFRAG; 1790 1791 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1792 1793 if (sc->sc_flags & URTW_RTL8187B) { 1794 struct urtw_8187b_txhdr *tx; 1795 1796 tx = (struct urtw_8187b_txhdr *)data->buf; 1797 if (ctsenable) 1798 flags |= URTW_TX_FLAG_CTS; 1799 if (rtsenable) { 1800 flags |= URTW_TX_FLAG_RTS; 1801 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1802 tx->rtsdur = rtsdur; 1803 } 1804 tx->flag = htole32(flags); 1805 tx->txdur = txdur; 1806 if (type == IEEE80211_FC0_TYPE_MGT && 1807 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1808 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1809 tx->retry = 1; 1810 else 1811 tx->retry = URTW_TX_MAXRETRY; 1812 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1813 } else { 1814 struct urtw_8187l_txhdr *tx; 1815 1816 tx = (struct urtw_8187l_txhdr *)data->buf; 1817 if (rtsenable) { 1818 flags |= URTW_TX_FLAG_RTS; 1819 tx->rtsdur = rtsdur; 1820 } 1821 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1822 tx->flag = htole32(flags); 1823 tx->retry = 3; /* CW minimum */ 1824 tx->retry |= 7 << 4; /* CW maximum */ 1825 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */ 1826 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1827 } 1828 1829 data->buflen = xferlen; 1830 data->ni = ni; 1831 data->m = m0; 1832 1833 if (sc->sc_flags & URTW_RTL8187B) { 1834 switch (type) { 1835 case IEEE80211_FC0_TYPE_CTL: 1836 case IEEE80211_FC0_TYPE_MGT: 1837 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1838 break; 1839 default: 1840 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1841 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1842 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1843 break; 1844 } 1845 } else 1846 xfer = (prior == URTW_PRIORITY_LOW) ? 1847 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1848 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1849 1850 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1851 usbd_transfer_start(xfer); 1852 1853 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1854 if (error != 0) 1855 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1856 error); 1857 return (0); 1858} 1859 1860static int 1861urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1862{ 1863 struct ieee80211com *ic = vap->iv_ic; 1864 struct urtw_softc *sc = ic->ic_softc; 1865 struct urtw_vap *uvp = URTW_VAP(vap); 1866 struct ieee80211_node *ni; 1867 usb_error_t error = 0; 1868 1869 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1870 ieee80211_state_name[vap->iv_state], 1871 ieee80211_state_name[nstate]); 1872 1873 sc->sc_state = nstate; 1874 1875 IEEE80211_UNLOCK(ic); 1876 URTW_LOCK(sc); 1877 usb_callout_stop(&sc->sc_led_ch); 1878 callout_stop(&sc->sc_watchdog_ch); 1879 1880 switch (nstate) { 1881 case IEEE80211_S_INIT: 1882 case IEEE80211_S_SCAN: 1883 case IEEE80211_S_AUTH: 1884 case IEEE80211_S_ASSOC: 1885 break; 1886 case IEEE80211_S_RUN: 1887 ni = ieee80211_ref_node(vap->iv_bss); 1888 /* setting bssid. */ 1889 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1890 urtw_write16_m(sc, URTW_BSSID + 4, 1891 ((uint16_t *)ni->ni_bssid)[2]); 1892 urtw_update_msr(sc); 1893 /* XXX maybe the below would be incorrect. */ 1894 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1895 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1896 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1897 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1898 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1899 if (error != 0) 1900 device_printf(sc->sc_dev, 1901 "could not control LED (%d)\n", error); 1902 ieee80211_free_node(ni); 1903 break; 1904 default: 1905 break; 1906 } 1907fail: 1908 URTW_UNLOCK(sc); 1909 IEEE80211_LOCK(ic); 1910 return (uvp->newstate(vap, nstate, arg)); 1911} 1912 1913static void 1914urtw_watchdog(void *arg) 1915{ 1916 struct urtw_softc *sc = arg; 1917 struct ieee80211com *ic = &sc->sc_ic; 1918 1919 if (sc->sc_txtimer > 0) { 1920 if (--sc->sc_txtimer == 0) { 1921 device_printf(sc->sc_dev, "device timeout\n"); 1922 counter_u64_add(ic->ic_oerrors, 1); 1923 ieee80211_restart_all(ic); 1924 return; 1925 } 1926 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1927 } 1928} 1929 1930static void 1931urtw_set_multi(void *arg) 1932{ 1933 /* XXX don't know how to set a device. Lack of docs. */ 1934} 1935 1936static usb_error_t 1937urtw_set_rate(struct urtw_softc *sc) 1938{ 1939 int i, basic_rate, min_rr_rate, max_rr_rate; 1940 uint16_t data; 1941 usb_error_t error; 1942 1943 basic_rate = URTW_RIDX_OFDM24; 1944 min_rr_rate = URTW_RIDX_OFDM6; 1945 max_rr_rate = URTW_RIDX_OFDM24; 1946 1947 urtw_write8_m(sc, URTW_RESP_RATE, 1948 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1949 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1950 1951 urtw_read16_m(sc, URTW_BRSR, &data); 1952 data &= ~URTW_BRSR_MBR_8185; 1953 1954 for (i = 0; i <= basic_rate; i++) 1955 data |= (1 << i); 1956 1957 urtw_write16_m(sc, URTW_BRSR, data); 1958fail: 1959 return (error); 1960} 1961 1962static uint16_t 1963urtw_rtl2rate(uint32_t rate) 1964{ 1965 unsigned i; 1966 1967 for (i = 0; i < nitems(urtw_ratetable); i++) { 1968 if (rate == urtw_ratetable[i].val) 1969 return urtw_ratetable[i].reg; 1970 } 1971 1972 return (0); 1973} 1974 1975static usb_error_t 1976urtw_update_msr(struct urtw_softc *sc) 1977{ 1978 struct ieee80211com *ic = &sc->sc_ic; 1979 uint8_t data; 1980 usb_error_t error; 1981 1982 urtw_read8_m(sc, URTW_MSR, &data); 1983 data &= ~URTW_MSR_LINK_MASK; 1984 1985 if (sc->sc_state == IEEE80211_S_RUN) { 1986 switch (ic->ic_opmode) { 1987 case IEEE80211_M_STA: 1988 case IEEE80211_M_MONITOR: 1989 data |= URTW_MSR_LINK_STA; 1990 if (sc->sc_flags & URTW_RTL8187B) 1991 data |= URTW_MSR_LINK_ENEDCA; 1992 break; 1993 case IEEE80211_M_IBSS: 1994 data |= URTW_MSR_LINK_ADHOC; 1995 break; 1996 case IEEE80211_M_HOSTAP: 1997 data |= URTW_MSR_LINK_HOSTAP; 1998 break; 1999 default: 2000 DPRINTF(sc, URTW_DEBUG_STATE, 2001 "unsupported operation mode 0x%x\n", 2002 ic->ic_opmode); 2003 error = USB_ERR_INVAL; 2004 goto fail; 2005 } 2006 } else 2007 data |= URTW_MSR_LINK_NONE; 2008 2009 urtw_write8_m(sc, URTW_MSR, data); 2010fail: 2011 return (error); 2012} 2013 2014static usb_error_t 2015urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 2016{ 2017 struct usb_device_request req; 2018 usb_error_t error; 2019 2020 URTW_ASSERT_LOCKED(sc); 2021 2022 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2023 req.bRequest = URTW_8187_GETREGS_REQ; 2024 USETW(req.wValue, (val & 0xff) | 0xff00); 2025 USETW(req.wIndex, (val >> 8) & 0x3); 2026 USETW(req.wLength, sizeof(uint8_t)); 2027 2028 error = urtw_do_request(sc, &req, data); 2029 return (error); 2030} 2031 2032static usb_error_t 2033urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 2034{ 2035 struct usb_device_request req; 2036 usb_error_t error; 2037 2038 URTW_ASSERT_LOCKED(sc); 2039 2040 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2041 req.bRequest = URTW_8187_GETREGS_REQ; 2042 USETW(req.wValue, (val & 0xff) | 0xff00); 2043 USETW(req.wIndex, (val >> 8) & 0x3); 2044 USETW(req.wLength, sizeof(uint16_t)); 2045 2046 error = urtw_do_request(sc, &req, data); 2047 return (error); 2048} 2049 2050static usb_error_t 2051urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2052{ 2053 struct usb_device_request req; 2054 usb_error_t error; 2055 2056 URTW_ASSERT_LOCKED(sc); 2057 2058 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2059 req.bRequest = URTW_8187_GETREGS_REQ; 2060 USETW(req.wValue, (val & 0xff) | 0xff00); 2061 USETW(req.wIndex, (val >> 8) & 0x3); 2062 USETW(req.wLength, sizeof(uint32_t)); 2063 2064 error = urtw_do_request(sc, &req, data); 2065 return (error); 2066} 2067 2068static usb_error_t 2069urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2070{ 2071 struct usb_device_request req; 2072 2073 URTW_ASSERT_LOCKED(sc); 2074 2075 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2076 req.bRequest = URTW_8187_SETREGS_REQ; 2077 USETW(req.wValue, (val & 0xff) | 0xff00); 2078 USETW(req.wIndex, (val >> 8) & 0x3); 2079 USETW(req.wLength, sizeof(uint8_t)); 2080 2081 return (urtw_do_request(sc, &req, &data)); 2082} 2083 2084static usb_error_t 2085urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2086{ 2087 struct usb_device_request req; 2088 2089 URTW_ASSERT_LOCKED(sc); 2090 2091 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2092 req.bRequest = URTW_8187_SETREGS_REQ; 2093 USETW(req.wValue, (val & 0xff) | 0xff00); 2094 USETW(req.wIndex, (val >> 8) & 0x3); 2095 USETW(req.wLength, sizeof(uint16_t)); 2096 2097 return (urtw_do_request(sc, &req, &data)); 2098} 2099 2100static usb_error_t 2101urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2102{ 2103 struct usb_device_request req; 2104 2105 URTW_ASSERT_LOCKED(sc); 2106 2107 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2108 req.bRequest = URTW_8187_SETREGS_REQ; 2109 USETW(req.wValue, (val & 0xff) | 0xff00); 2110 USETW(req.wIndex, (val >> 8) & 0x3); 2111 USETW(req.wLength, sizeof(uint32_t)); 2112 2113 return (urtw_do_request(sc, &req, &data)); 2114} 2115 2116static usb_error_t 2117urtw_get_macaddr(struct urtw_softc *sc) 2118{ 2119 struct ieee80211com *ic = &sc->sc_ic; 2120 uint32_t data; 2121 usb_error_t error; 2122 2123 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2124 if (error != 0) 2125 goto fail; 2126 ic->ic_macaddr[0] = data & 0xff; 2127 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2128 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2129 if (error != 0) 2130 goto fail; 2131 ic->ic_macaddr[2] = data & 0xff; 2132 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2133 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2134 if (error != 0) 2135 goto fail; 2136 ic->ic_macaddr[4] = data & 0xff; 2137 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2138fail: 2139 return (error); 2140} 2141 2142static usb_error_t 2143urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2144{ 2145#define URTW_READCMD_LEN 3 2146 int addrlen, i; 2147 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2148 usb_error_t error; 2149 2150 /* NB: make sure the buffer is initialized */ 2151 *data = 0; 2152 2153 /* enable EPROM programming */ 2154 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2155 DELAY(URTW_EPROM_DELAY); 2156 2157 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2158 if (error != 0) 2159 goto fail; 2160 error = urtw_eprom_ck(sc); 2161 if (error != 0) 2162 goto fail; 2163 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2164 if (error != 0) 2165 goto fail; 2166 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2167 addrlen = 8; 2168 addrstr[0] = addr & (1 << 7); 2169 addrstr[1] = addr & (1 << 6); 2170 addrstr[2] = addr & (1 << 5); 2171 addrstr[3] = addr & (1 << 4); 2172 addrstr[4] = addr & (1 << 3); 2173 addrstr[5] = addr & (1 << 2); 2174 addrstr[6] = addr & (1 << 1); 2175 addrstr[7] = addr & (1 << 0); 2176 } else { 2177 addrlen=6; 2178 addrstr[0] = addr & (1 << 5); 2179 addrstr[1] = addr & (1 << 4); 2180 addrstr[2] = addr & (1 << 3); 2181 addrstr[3] = addr & (1 << 2); 2182 addrstr[4] = addr & (1 << 1); 2183 addrstr[5] = addr & (1 << 0); 2184 } 2185 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2186 if (error != 0) 2187 goto fail; 2188 2189 error = urtw_eprom_writebit(sc, 0); 2190 if (error != 0) 2191 goto fail; 2192 2193 for (i = 0; i < 16; i++) { 2194 error = urtw_eprom_ck(sc); 2195 if (error != 0) 2196 goto fail; 2197 error = urtw_eprom_readbit(sc, &data16); 2198 if (error != 0) 2199 goto fail; 2200 2201 (*data) |= (data16 << (15 - i)); 2202 } 2203 2204 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2205 if (error != 0) 2206 goto fail; 2207 error = urtw_eprom_ck(sc); 2208 if (error != 0) 2209 goto fail; 2210 2211 /* now disable EPROM programming */ 2212 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2213fail: 2214 return (error); 2215#undef URTW_READCMD_LEN 2216} 2217 2218static usb_error_t 2219urtw_eprom_cs(struct urtw_softc *sc, int able) 2220{ 2221 uint8_t data; 2222 usb_error_t error; 2223 2224 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2225 if (able == URTW_EPROM_ENABLE) 2226 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2227 else 2228 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2229 DELAY(URTW_EPROM_DELAY); 2230fail: 2231 return (error); 2232} 2233 2234static usb_error_t 2235urtw_eprom_ck(struct urtw_softc *sc) 2236{ 2237 uint8_t data; 2238 usb_error_t error; 2239 2240 /* masking */ 2241 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2242 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2243 DELAY(URTW_EPROM_DELAY); 2244 /* unmasking */ 2245 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2246 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2247 DELAY(URTW_EPROM_DELAY); 2248fail: 2249 return (error); 2250} 2251 2252static usb_error_t 2253urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2254{ 2255 uint8_t data8; 2256 usb_error_t error; 2257 2258 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2259 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2260 DELAY(URTW_EPROM_DELAY); 2261 2262fail: 2263 return (error); 2264} 2265 2266static usb_error_t 2267urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2268{ 2269 uint8_t data; 2270 usb_error_t error; 2271 2272 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2273 if (bit != 0) 2274 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2275 else 2276 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2277 DELAY(URTW_EPROM_DELAY); 2278fail: 2279 return (error); 2280} 2281 2282static usb_error_t 2283urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2284{ 2285 int i = 0; 2286 usb_error_t error = 0; 2287 2288 for (i = 0; i < buflen; i++) { 2289 error = urtw_eprom_writebit(sc, buf[i]); 2290 if (error != 0) 2291 goto fail; 2292 error = urtw_eprom_ck(sc); 2293 if (error != 0) 2294 goto fail; 2295 } 2296fail: 2297 return (error); 2298} 2299 2300static usb_error_t 2301urtw_get_txpwr(struct urtw_softc *sc) 2302{ 2303 int i, j; 2304 uint32_t data; 2305 usb_error_t error; 2306 2307 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2308 if (error != 0) 2309 goto fail; 2310 sc->sc_txpwr_cck_base = data & 0xf; 2311 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2312 2313 for (i = 1, j = 0; i < 6; i += 2, j++) { 2314 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2315 if (error != 0) 2316 goto fail; 2317 sc->sc_txpwr_cck[i] = data & 0xf; 2318 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2319 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2320 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2321 } 2322 for (i = 1, j = 0; i < 4; i += 2, j++) { 2323 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2324 if (error != 0) 2325 goto fail; 2326 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2327 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2328 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2329 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2330 } 2331 if (sc->sc_flags & URTW_RTL8187B) { 2332 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2333 if (error != 0) 2334 goto fail; 2335 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2336 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2337 error = urtw_eprom_read32(sc, 0x0a, &data); 2338 if (error != 0) 2339 goto fail; 2340 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2341 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2342 error = urtw_eprom_read32(sc, 0x1c, &data); 2343 if (error != 0) 2344 goto fail; 2345 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2346 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2347 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2348 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2349 } else { 2350 for (i = 1, j = 0; i < 4; i += 2, j++) { 2351 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2352 &data); 2353 if (error != 0) 2354 goto fail; 2355 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2356 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2357 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2358 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2359 } 2360 } 2361fail: 2362 return (error); 2363} 2364 2365static usb_error_t 2366urtw_get_rfchip(struct urtw_softc *sc) 2367{ 2368 int ret; 2369 uint8_t data8; 2370 uint32_t data; 2371 usb_error_t error; 2372 2373 if (sc->sc_flags & URTW_RTL8187B) { 2374 urtw_read8_m(sc, 0xe1, &data8); 2375 switch (data8) { 2376 case 0: 2377 sc->sc_flags |= URTW_RTL8187B_REV_B; 2378 break; 2379 case 1: 2380 sc->sc_flags |= URTW_RTL8187B_REV_D; 2381 break; 2382 case 2: 2383 sc->sc_flags |= URTW_RTL8187B_REV_E; 2384 break; 2385 default: 2386 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2387 sc->sc_flags |= URTW_RTL8187B_REV_B; 2388 break; 2389 } 2390 } else { 2391 urtw_read32_m(sc, URTW_TX_CONF, &data); 2392 switch (data & URTW_TX_HWMASK) { 2393 case URTW_TX_R8187vD_B: 2394 sc->sc_flags |= URTW_RTL8187B; 2395 break; 2396 case URTW_TX_R8187vD: 2397 break; 2398 default: 2399 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2400 data & URTW_TX_HWMASK); 2401 break; 2402 } 2403 } 2404 2405 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2406 if (error != 0) 2407 goto fail; 2408 switch (data & 0xff) { 2409 case URTW_EPROM_RFCHIPID_RTL8225U: 2410 error = urtw_8225_isv2(sc, &ret); 2411 if (error != 0) 2412 goto fail; 2413 if (ret == 0) { 2414 sc->sc_rf_init = urtw_8225_rf_init; 2415 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2416 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2417 sc->sc_rf_stop = urtw_8225_rf_stop; 2418 } else { 2419 sc->sc_rf_init = urtw_8225v2_rf_init; 2420 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2421 sc->sc_rf_stop = urtw_8225_rf_stop; 2422 } 2423 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2424 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2425 break; 2426 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2427 sc->sc_rf_init = urtw_8225v2b_rf_init; 2428 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2429 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2430 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2431 sc->sc_rf_stop = urtw_8225_rf_stop; 2432 break; 2433 default: 2434 DPRINTF(sc, URTW_DEBUG_STATE, 2435 "unsupported RF chip %d\n", data & 0xff); 2436 error = USB_ERR_INVAL; 2437 goto fail; 2438 } 2439 2440 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2441 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2442 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2443 "rtl8225z2", 2444 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2445 (data8 == 1) ? "d" : "e") : "none"); 2446 2447fail: 2448 return (error); 2449} 2450 2451static usb_error_t 2452urtw_led_init(struct urtw_softc *sc) 2453{ 2454 uint32_t rev; 2455 usb_error_t error; 2456 2457 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2458 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2459 if (error != 0) 2460 goto fail; 2461 2462 switch (rev & URTW_EPROM_CID_MASK) { 2463 case URTW_EPROM_CID_ALPHA0: 2464 sc->sc_strategy = URTW_SW_LED_MODE1; 2465 break; 2466 case URTW_EPROM_CID_SERCOMM_PS: 2467 sc->sc_strategy = URTW_SW_LED_MODE3; 2468 break; 2469 case URTW_EPROM_CID_HW_LED: 2470 sc->sc_strategy = URTW_HW_LED; 2471 break; 2472 case URTW_EPROM_CID_RSVD0: 2473 case URTW_EPROM_CID_RSVD1: 2474 default: 2475 sc->sc_strategy = URTW_SW_LED_MODE0; 2476 break; 2477 } 2478 2479 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2480 2481fail: 2482 return (error); 2483} 2484 2485static usb_error_t 2486urtw_8225_rf_init(struct urtw_softc *sc) 2487{ 2488 unsigned i; 2489 uint16_t data; 2490 usb_error_t error; 2491 2492 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2493 if (error) 2494 goto fail; 2495 2496 error = urtw_8225_usb_init(sc); 2497 if (error) 2498 goto fail; 2499 2500 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2501 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2502 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2503 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2504 2505 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2506 if (error) 2507 goto fail; 2508 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2509 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2510 if (error) 2511 goto fail; 2512 2513 error = urtw_8185_rf_pins_enable(sc); 2514 if (error) 2515 goto fail; 2516 urtw_pause_ms(sc, 1000); 2517 2518 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2519 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2520 urtw_8225_rf_part1[i].val); 2521 urtw_pause_ms(sc, 1); 2522 } 2523 urtw_pause_ms(sc, 100); 2524 urtw_8225_write(sc, 2525 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2526 urtw_pause_ms(sc, 200); 2527 urtw_8225_write(sc, 2528 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2529 urtw_pause_ms(sc, 200); 2530 urtw_8225_write(sc, 2531 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2532 2533 for (i = 0; i < 95; i++) { 2534 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2535 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2536 } 2537 2538 urtw_8225_write(sc, 2539 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2540 urtw_8225_write(sc, 2541 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2542 2543 for (i = 0; i < 128; i++) { 2544 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2545 urtw_pause_ms(sc, 1); 2546 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2547 urtw_pause_ms(sc, 1); 2548 } 2549 2550 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2551 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2552 urtw_8225_rf_part2[i].val); 2553 urtw_pause_ms(sc, 1); 2554 } 2555 2556 error = urtw_8225_setgain(sc, 4); 2557 if (error) 2558 goto fail; 2559 2560 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2561 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2562 urtw_8225_rf_part3[i].val); 2563 urtw_pause_ms(sc, 1); 2564 } 2565 2566 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2567 2568 error = urtw_8225_set_txpwrlvl(sc, 1); 2569 if (error) 2570 goto fail; 2571 2572 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2573 urtw_pause_ms(sc, 1); 2574 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2575 urtw_pause_ms(sc, 1); 2576 2577 /* TX ant A, 0x0 for B */ 2578 error = urtw_8185_tx_antenna(sc, 0x3); 2579 if (error) 2580 goto fail; 2581 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2582 2583 error = urtw_8225_rf_set_chan(sc, 1); 2584fail: 2585 return (error); 2586} 2587 2588static usb_error_t 2589urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2590{ 2591 usb_error_t error = 0; 2592 2593 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2594fail: 2595 return (error); 2596} 2597 2598static usb_error_t 2599urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2600{ 2601 usb_error_t error; 2602 2603 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2604 urtw_pause_ms(sc, 1); 2605fail: 2606 return (error); 2607} 2608 2609static usb_error_t 2610urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2611{ 2612 2613 data = data & 0xff; 2614 return urtw_8187_write_phy(sc, addr, data); 2615} 2616 2617static usb_error_t 2618urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2619{ 2620 2621 data = data & 0xff; 2622 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2623} 2624 2625static usb_error_t 2626urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2627{ 2628 uint32_t phyw; 2629 usb_error_t error; 2630 2631 phyw = ((data << 8) | (addr | 0x80)); 2632 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2633 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2634 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2635 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2636 urtw_pause_ms(sc, 1); 2637fail: 2638 return (error); 2639} 2640 2641static usb_error_t 2642urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2643{ 2644 usb_error_t error; 2645 2646 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2647 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2648 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2649 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2650fail: 2651 return (error); 2652} 2653 2654static usb_error_t 2655urtw_8225_usb_init(struct urtw_softc *sc) 2656{ 2657 uint8_t data; 2658 usb_error_t error; 2659 2660 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2661 urtw_write8_m(sc, URTW_GPIO, 0); 2662 error = urtw_read8e(sc, 0x53, &data); 2663 if (error) 2664 goto fail; 2665 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2666 if (error) 2667 goto fail; 2668 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2669 urtw_write8_m(sc, URTW_GPIO, 0x20); 2670 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2671 2672 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2673 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2674 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2675 2676 urtw_pause_ms(sc, 500); 2677fail: 2678 return (error); 2679} 2680 2681static usb_error_t 2682urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2683{ 2684 uint16_t d80, d82, d84; 2685 usb_error_t error; 2686 2687 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2688 d80 &= URTW_RF_PINS_MAGIC1; 2689 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2690 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2691 d84 &= URTW_RF_PINS_MAGIC2; 2692 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2693 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2694 DELAY(10); 2695 2696 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2697 DELAY(2); 2698 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2699 DELAY(10); 2700 2701 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2702 if (error != 0) 2703 goto fail; 2704 2705 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2706 DELAY(10); 2707 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2708 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2709 urtw_pause_ms(sc, 2); 2710fail: 2711 return (error); 2712} 2713 2714static usb_error_t 2715urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2716 uint16_t *data) 2717{ 2718 uint8_t buf[2]; 2719 uint16_t data16; 2720 struct usb_device_request req; 2721 usb_error_t error = 0; 2722 2723 data16 = *data; 2724 2725 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2726 req.bRequest = URTW_8187_SETREGS_REQ; 2727 USETW(req.wValue, addr); 2728 USETW(req.wIndex, index); 2729 USETW(req.wLength, sizeof(uint16_t)); 2730 buf[0] = (data16 & 0x00ff); 2731 buf[1] = (data16 & 0xff00) >> 8; 2732 2733 error = urtw_do_request(sc, &req, buf); 2734 2735 return (error); 2736} 2737 2738static usb_error_t 2739urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2740{ 2741 usb_error_t error; 2742 2743 error = urtw_8225_set_txpwrlvl(sc, chan); 2744 if (error) 2745 goto fail; 2746 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2747 urtw_pause_ms(sc, 10); 2748fail: 2749 return (error); 2750} 2751 2752static usb_error_t 2753urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2754{ 2755 usb_error_t error; 2756 2757 if (sens < 0 || sens > 6) 2758 return -1; 2759 2760 if (sens > 4) 2761 urtw_8225_write(sc, 2762 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2763 else 2764 urtw_8225_write(sc, 2765 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2766 2767 sens = 6 - sens; 2768 error = urtw_8225_setgain(sc, sens); 2769 if (error) 2770 goto fail; 2771 2772 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2773 2774fail: 2775 return (error); 2776} 2777 2778static usb_error_t 2779urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2780{ 2781 int i, idx, set; 2782 uint8_t *cck_pwltable; 2783 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2784 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2785 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2786 usb_error_t error; 2787 2788 cck_pwrlvl_max = 11; 2789 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2790 ofdm_pwrlvl_min = 10; 2791 2792 /* CCK power setting */ 2793 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2794 idx = cck_pwrlvl % 6; 2795 set = cck_pwrlvl / 6; 2796 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2797 urtw_8225_txpwr_cck; 2798 2799 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2800 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2801 for (i = 0; i < 8; i++) { 2802 urtw_8187_write_phy_cck(sc, 0x44 + i, 2803 cck_pwltable[idx * 8 + i]); 2804 } 2805 urtw_pause_ms(sc, 1); 2806 2807 /* OFDM power setting */ 2808 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2809 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2810 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2811 2812 idx = ofdm_pwrlvl % 6; 2813 set = ofdm_pwrlvl / 6; 2814 2815 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2816 if (error) 2817 goto fail; 2818 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2819 urtw_8187_write_phy_ofdm(sc, 6, 0); 2820 urtw_8187_write_phy_ofdm(sc, 8, 0); 2821 2822 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2823 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2824 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2825 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2826 urtw_pause_ms(sc, 1); 2827fail: 2828 return (error); 2829} 2830 2831static usb_error_t 2832urtw_8225_rf_stop(struct urtw_softc *sc) 2833{ 2834 uint8_t data; 2835 usb_error_t error; 2836 2837 urtw_8225_write(sc, 0x4, 0x1f); 2838 2839 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2840 if (error) 2841 goto fail; 2842 2843 urtw_read8_m(sc, URTW_CONFIG3, &data); 2844 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2845 if (sc->sc_flags & URTW_RTL8187B) { 2846 urtw_write32_m(sc, URTW_ANAPARAM2, 2847 URTW_8187B_8225_ANAPARAM2_OFF); 2848 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2849 urtw_write32_m(sc, URTW_ANAPARAM3, 2850 URTW_8187B_8225_ANAPARAM3_OFF); 2851 } else { 2852 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2853 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2854 } 2855 2856 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2857 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2858 if (error) 2859 goto fail; 2860 2861fail: 2862 return (error); 2863} 2864 2865static usb_error_t 2866urtw_8225v2_rf_init(struct urtw_softc *sc) 2867{ 2868 unsigned i; 2869 uint16_t data; 2870 uint32_t data32; 2871 usb_error_t error; 2872 2873 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2874 if (error) 2875 goto fail; 2876 2877 error = urtw_8225_usb_init(sc); 2878 if (error) 2879 goto fail; 2880 2881 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2882 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2883 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2884 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2885 2886 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2887 if (error) 2888 goto fail; 2889 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2890 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2891 if (error) 2892 goto fail; 2893 2894 error = urtw_8185_rf_pins_enable(sc); 2895 if (error) 2896 goto fail; 2897 2898 urtw_pause_ms(sc, 500); 2899 2900 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2901 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2902 urtw_8225v2_rf_part1[i].val); 2903 } 2904 urtw_pause_ms(sc, 50); 2905 2906 urtw_8225_write(sc, 2907 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2908 2909 for (i = 0; i < 95; i++) { 2910 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2911 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2912 urtw_8225v2_rxgain[i]); 2913 } 2914 2915 urtw_8225_write(sc, 2916 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2917 urtw_8225_write(sc, 2918 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2919 urtw_8225_write(sc, 2920 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2921 urtw_8225_write(sc, 2922 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2923 urtw_pause_ms(sc, 100); 2924 urtw_8225_write(sc, 2925 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2926 urtw_pause_ms(sc, 100); 2927 2928 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2929 if (error != 0) 2930 goto fail; 2931 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2932 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2933 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2934 urtw_8225_write(sc, 2935 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2936 urtw_pause_ms(sc, 100); 2937 urtw_8225_write(sc, 2938 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2939 urtw_pause_ms(sc, 50); 2940 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2941 if (error != 0) 2942 goto fail; 2943 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2944 device_printf(sc->sc_dev, "RF calibration failed\n"); 2945 } 2946 urtw_pause_ms(sc, 100); 2947 2948 urtw_8225_write(sc, 2949 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2950 for (i = 0; i < 128; i++) { 2951 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2952 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2953 } 2954 2955 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2956 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2957 urtw_8225v2_rf_part2[i].val); 2958 } 2959 2960 error = urtw_8225v2_setgain(sc, 4); 2961 if (error) 2962 goto fail; 2963 2964 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2965 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2966 urtw_8225v2_rf_part3[i].val); 2967 } 2968 2969 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2970 2971 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2972 if (error) 2973 goto fail; 2974 2975 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2976 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2977 2978 /* TX ant A, 0x0 for B */ 2979 error = urtw_8185_tx_antenna(sc, 0x3); 2980 if (error) 2981 goto fail; 2982 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2983 2984 error = urtw_8225_rf_set_chan(sc, 1); 2985fail: 2986 return (error); 2987} 2988 2989static usb_error_t 2990urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2991{ 2992 usb_error_t error; 2993 2994 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2995 if (error) 2996 goto fail; 2997 2998 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2999 urtw_pause_ms(sc, 10); 3000fail: 3001 return (error); 3002} 3003 3004static usb_error_t 3005urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 3006{ 3007 int i; 3008 int16_t bit; 3009 uint8_t rlen = 12, wlen = 6; 3010 uint16_t o1, o2, o3, tmp; 3011 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 3012 uint32_t mask = 0x80000000, value = 0; 3013 usb_error_t error; 3014 3015 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 3016 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 3017 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 3018 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 3019 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 3020 o1 &= ~URTW_RF_PINS_MAGIC4; 3021 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 3022 DELAY(5); 3023 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 3024 DELAY(5); 3025 3026 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 3027 bit = ((d2w & mask) != 0) ? 1 : 0; 3028 3029 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3030 DELAY(2); 3031 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3032 URTW_BB_HOST_BANG_CLK); 3033 DELAY(2); 3034 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3035 URTW_BB_HOST_BANG_CLK); 3036 DELAY(2); 3037 mask = mask >> 1; 3038 if (i == 2) 3039 break; 3040 bit = ((d2w & mask) != 0) ? 1 : 0; 3041 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3042 URTW_BB_HOST_BANG_CLK); 3043 DELAY(2); 3044 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3045 URTW_BB_HOST_BANG_CLK); 3046 DELAY(2); 3047 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3048 DELAY(1); 3049 } 3050 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3051 URTW_BB_HOST_BANG_CLK); 3052 DELAY(2); 3053 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3054 DELAY(2); 3055 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3056 DELAY(2); 3057 3058 mask = 0x800; 3059 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3060 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3061 o1 | URTW_BB_HOST_BANG_RW); 3062 DELAY(2); 3063 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3064 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3065 DELAY(2); 3066 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3067 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3068 DELAY(2); 3069 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3070 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3071 DELAY(2); 3072 3073 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3074 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3075 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3076 o1 | URTW_BB_HOST_BANG_RW); 3077 DELAY(2); 3078 } 3079 3080 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3081 URTW_BB_HOST_BANG_RW); 3082 DELAY(2); 3083 3084 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3085 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3086 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3087 3088 if (data != NULL) 3089 *data = value; 3090fail: 3091 return (error); 3092} 3093 3094static usb_error_t 3095urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3096{ 3097 int i; 3098 uint8_t *cck_pwrtable; 3099 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3100 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3101 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3102 usb_error_t error; 3103 3104 /* CCK power setting */ 3105 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3106 cck_pwrlvl += sc->sc_txpwr_cck_base; 3107 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3108 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3109 urtw_8225v2_txpwr_cck; 3110 3111 for (i = 0; i < 8; i++) 3112 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3113 3114 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3115 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3116 urtw_pause_ms(sc, 1); 3117 3118 /* OFDM power setting */ 3119 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3120 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3121 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3122 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3123 3124 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3125 if (error) 3126 goto fail; 3127 3128 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3129 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3130 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3131 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3132 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3133 3134 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3135 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3136 urtw_pause_ms(sc, 1); 3137fail: 3138 return (error); 3139} 3140 3141static usb_error_t 3142urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3143{ 3144 uint8_t *gainp; 3145 usb_error_t error; 3146 3147 /* XXX for A? */ 3148 gainp = urtw_8225v2_gain_bg; 3149 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3150 urtw_pause_ms(sc, 1); 3151 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3152 urtw_pause_ms(sc, 1); 3153 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3154 urtw_pause_ms(sc, 1); 3155 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3156 urtw_pause_ms(sc, 1); 3157fail: 3158 return (error); 3159} 3160 3161static usb_error_t 3162urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3163{ 3164 uint32_t data; 3165 usb_error_t error; 3166 3167 *ret = 1; 3168 3169 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3170 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3171 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3172 urtw_pause_ms(sc, 500); 3173 3174 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3175 URTW_8225_ADDR_0_DATA_MAGIC1); 3176 3177 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3178 if (error != 0) 3179 goto fail; 3180 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3181 *ret = 0; 3182 else { 3183 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3184 if (error != 0) 3185 goto fail; 3186 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3187 *ret = 0; 3188 } 3189 3190 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3191 URTW_8225_ADDR_0_DATA_MAGIC2); 3192fail: 3193 return (error); 3194} 3195 3196static usb_error_t 3197urtw_8225v2b_rf_init(struct urtw_softc *sc) 3198{ 3199 struct ieee80211com *ic = &sc->sc_ic; 3200 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3201 const uint8_t *macaddr; 3202 unsigned i; 3203 uint8_t data8; 3204 usb_error_t error; 3205 3206 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3207 if (error) 3208 goto fail; 3209 3210 /* 3211 * initialize extra registers on 8187 3212 */ 3213 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3214 3215 /* retry limit */ 3216 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3217 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3218 urtw_write8_m(sc, URTW_CW_CONF, data8); 3219 3220 /* TX AGC */ 3221 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3222 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3223 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3224 3225 /* Auto Rate Fallback Control */ 3226#define URTW_ARFR 0x1e0 3227 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3228 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3229 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3230 data8 | URTW_RATE_FALLBACK_ENABLE); 3231 3232 urtw_read8_m(sc, URTW_MSR, &data8); 3233 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3234 urtw_read8_m(sc, URTW_MSR, &data8); 3235 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3236 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3237 3238 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3239 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3240#define URTW_FEMR_FOR_8187B 0x1d4 3241 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3242 3243 /* led type */ 3244 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3245 data8 = (data8 & 0x3f) | 0x80; 3246 urtw_write8_m(sc, URTW_CONFIG1, data8); 3247 3248 /* applying MAC address again. */ 3249 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 3250 error = urtw_set_macaddr(sc, macaddr); 3251 if (error) 3252 goto fail; 3253 3254 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3255 if (error) 3256 goto fail; 3257 3258 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3259 3260 /* 3261 * MAC configuration 3262 */ 3263 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3264 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3265 urtw_8225v2b_rf_part1[i].val); 3266 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3267 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3268 urtw_write32_m(sc, 0x1f0, 0); 3269 urtw_write32_m(sc, 0x1f4, 0); 3270 urtw_write8_m(sc, 0x1f8, 0); 3271 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3272 3273#define URTW_RFSW_CTRL 0x272 3274 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3275 3276 /* 3277 * initialize PHY 3278 */ 3279 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3280 if (error) 3281 goto fail; 3282 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3283 urtw_write8_m(sc, URTW_CONFIG3, 3284 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3285 3286 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3287 if (error) 3288 goto fail; 3289 3290 /* setup RFE initial timing */ 3291 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3292 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3293 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3294 urtw_pause_ms(sc, 1100); 3295 3296 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3297 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3298 urtw_8225v2b_rf_part0[i].val); 3299 urtw_pause_ms(sc, 1); 3300 } 3301 urtw_8225_write(sc, 0x00, 0x01b7); 3302 3303 for (i = 0; i < 95; i++) { 3304 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3305 urtw_pause_ms(sc, 1); 3306 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3307 urtw_8225v2b_rxgain[i]); 3308 urtw_pause_ms(sc, 1); 3309 } 3310 3311 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3312 urtw_pause_ms(sc, 1); 3313 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3314 urtw_pause_ms(sc, 1); 3315 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3316 urtw_pause_ms(sc, 1); 3317 urtw_pause_ms(sc, 3000); 3318 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3319 urtw_pause_ms(sc, 2000); 3320 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3321 urtw_pause_ms(sc, 1); 3322 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3323 urtw_pause_ms(sc, 1); 3324 3325 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3326 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3327 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3328 3329 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3330 for (i = 0; i < 128; i++) { 3331 uint32_t addr, data; 3332 3333 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3334 addr = ((i + 0x80) << 8) | 0x0000008e; 3335 3336 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3337 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3338 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3339 } 3340 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3341 3342 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3343 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3344 3345 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3346 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3347 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3348 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3349 3350 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3351 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3352 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3353 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3354 3355fail: 3356 return (error); 3357} 3358 3359static usb_error_t 3360urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3361{ 3362 usb_error_t error; 3363 3364 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3365 if (error) 3366 goto fail; 3367 3368 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3369 urtw_pause_ms(sc, 10); 3370fail: 3371 return (error); 3372} 3373 3374static usb_error_t 3375urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3376{ 3377 int i; 3378 uint8_t *cck_pwrtable; 3379 uint8_t cck_pwrlvl_max = 15; 3380 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3381 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3382 usb_error_t error; 3383 3384 /* CCK power setting */ 3385 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3386 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3387 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3388 cck_pwrlvl += sc->sc_txpwr_cck_base; 3389 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3390 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3391 urtw_8225v2b_txpwr_cck; 3392 3393 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3394 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3395 ((cck_pwrlvl <= 11) ? 8 : 16); 3396 else 3397 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3398 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3399 3400 for (i = 0; i < 8; i++) 3401 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3402 3403 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3404 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3405 urtw_pause_ms(sc, 1); 3406 3407 /* OFDM power setting */ 3408 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3409 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3410 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3411 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3412 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3413 3414 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3415 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3416 3417 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3418 if (ofdm_pwrlvl <= 11) { 3419 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3420 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3421 } else { 3422 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3423 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3424 } 3425 } else { 3426 if (ofdm_pwrlvl <= 11) { 3427 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3428 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3429 } else if (ofdm_pwrlvl <= 17) { 3430 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3431 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3432 } else { 3433 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3434 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3435 } 3436 } 3437 urtw_pause_ms(sc, 1); 3438fail: 3439 return (error); 3440} 3441 3442static usb_error_t 3443urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3444{ 3445 struct usb_device_request req; 3446 usb_error_t error; 3447 3448 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3449 req.bRequest = URTW_8187_GETREGS_REQ; 3450 USETW(req.wValue, val | 0xfe00); 3451 USETW(req.wIndex, 0); 3452 USETW(req.wLength, sizeof(uint8_t)); 3453 3454 error = urtw_do_request(sc, &req, data); 3455 return (error); 3456} 3457 3458static usb_error_t 3459urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3460{ 3461 struct usb_device_request req; 3462 3463 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3464 req.bRequest = URTW_8187_SETREGS_REQ; 3465 USETW(req.wValue, val | 0xfe00); 3466 USETW(req.wIndex, 0); 3467 USETW(req.wLength, sizeof(uint8_t)); 3468 3469 return (urtw_do_request(sc, &req, &data)); 3470} 3471 3472static usb_error_t 3473urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3474{ 3475 uint8_t data; 3476 usb_error_t error; 3477 3478 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3479 if (error) 3480 goto fail; 3481 3482 urtw_read8_m(sc, URTW_CONFIG3, &data); 3483 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3484 urtw_write32_m(sc, URTW_ANAPARAM, val); 3485 urtw_read8_m(sc, URTW_CONFIG3, &data); 3486 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3487 3488 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3489 if (error) 3490 goto fail; 3491fail: 3492 return (error); 3493} 3494 3495static usb_error_t 3496urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3497{ 3498 uint8_t data; 3499 usb_error_t error; 3500 3501 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3502 if (error) 3503 goto fail; 3504 3505 urtw_read8_m(sc, URTW_CONFIG3, &data); 3506 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3507 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3508 urtw_read8_m(sc, URTW_CONFIG3, &data); 3509 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3510 3511 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3512 if (error) 3513 goto fail; 3514fail: 3515 return (error); 3516} 3517 3518static usb_error_t 3519urtw_intr_enable(struct urtw_softc *sc) 3520{ 3521 usb_error_t error; 3522 3523 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3524fail: 3525 return (error); 3526} 3527 3528static usb_error_t 3529urtw_intr_disable(struct urtw_softc *sc) 3530{ 3531 usb_error_t error; 3532 3533 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3534fail: 3535 return (error); 3536} 3537 3538static usb_error_t 3539urtw_reset(struct urtw_softc *sc) 3540{ 3541 uint8_t data; 3542 usb_error_t error; 3543 3544 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3545 if (error) 3546 goto fail; 3547 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3548 if (error) 3549 goto fail; 3550 3551 error = urtw_intr_disable(sc); 3552 if (error) 3553 goto fail; 3554 urtw_pause_ms(sc, 100); 3555 3556 error = urtw_write8e(sc, 0x18, 0x10); 3557 if (error != 0) 3558 goto fail; 3559 error = urtw_write8e(sc, 0x18, 0x11); 3560 if (error != 0) 3561 goto fail; 3562 error = urtw_write8e(sc, 0x18, 0x00); 3563 if (error != 0) 3564 goto fail; 3565 urtw_pause_ms(sc, 100); 3566 3567 urtw_read8_m(sc, URTW_CMD, &data); 3568 data = (data & 0x2) | URTW_CMD_RST; 3569 urtw_write8_m(sc, URTW_CMD, data); 3570 urtw_pause_ms(sc, 100); 3571 3572 urtw_read8_m(sc, URTW_CMD, &data); 3573 if (data & URTW_CMD_RST) { 3574 device_printf(sc->sc_dev, "reset timeout\n"); 3575 goto fail; 3576 } 3577 3578 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3579 if (error) 3580 goto fail; 3581 urtw_pause_ms(sc, 100); 3582 3583 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3584 if (error) 3585 goto fail; 3586 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3587 if (error) 3588 goto fail; 3589fail: 3590 return (error); 3591} 3592 3593static usb_error_t 3594urtw_led_ctl(struct urtw_softc *sc, int mode) 3595{ 3596 usb_error_t error = 0; 3597 3598 switch (sc->sc_strategy) { 3599 case URTW_SW_LED_MODE0: 3600 error = urtw_led_mode0(sc, mode); 3601 break; 3602 case URTW_SW_LED_MODE1: 3603 error = urtw_led_mode1(sc, mode); 3604 break; 3605 case URTW_SW_LED_MODE2: 3606 error = urtw_led_mode2(sc, mode); 3607 break; 3608 case URTW_SW_LED_MODE3: 3609 error = urtw_led_mode3(sc, mode); 3610 break; 3611 default: 3612 DPRINTF(sc, URTW_DEBUG_STATE, 3613 "unsupported LED mode %d\n", sc->sc_strategy); 3614 error = USB_ERR_INVAL; 3615 break; 3616 } 3617 3618 return (error); 3619} 3620 3621static usb_error_t 3622urtw_led_mode0(struct urtw_softc *sc, int mode) 3623{ 3624 3625 switch (mode) { 3626 case URTW_LED_CTL_POWER_ON: 3627 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3628 break; 3629 case URTW_LED_CTL_TX: 3630 if (sc->sc_gpio_ledinprogress == 1) 3631 return (0); 3632 3633 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3634 sc->sc_gpio_blinktime = 2; 3635 break; 3636 case URTW_LED_CTL_LINK: 3637 sc->sc_gpio_ledstate = URTW_LED_ON; 3638 break; 3639 default: 3640 DPRINTF(sc, URTW_DEBUG_STATE, 3641 "unsupported LED mode 0x%x", mode); 3642 return (USB_ERR_INVAL); 3643 } 3644 3645 switch (sc->sc_gpio_ledstate) { 3646 case URTW_LED_ON: 3647 if (sc->sc_gpio_ledinprogress != 0) 3648 break; 3649 urtw_led_on(sc, URTW_LED_GPIO); 3650 break; 3651 case URTW_LED_BLINK_NORMAL: 3652 if (sc->sc_gpio_ledinprogress != 0) 3653 break; 3654 sc->sc_gpio_ledinprogress = 1; 3655 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3656 URTW_LED_OFF : URTW_LED_ON; 3657 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3658 break; 3659 case URTW_LED_POWER_ON_BLINK: 3660 urtw_led_on(sc, URTW_LED_GPIO); 3661 urtw_pause_ms(sc, 100); 3662 urtw_led_off(sc, URTW_LED_GPIO); 3663 break; 3664 default: 3665 DPRINTF(sc, URTW_DEBUG_STATE, 3666 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3667 return (USB_ERR_INVAL); 3668 } 3669 return (0); 3670} 3671 3672static usb_error_t 3673urtw_led_mode1(struct urtw_softc *sc, int mode) 3674{ 3675 return (USB_ERR_INVAL); 3676} 3677 3678static usb_error_t 3679urtw_led_mode2(struct urtw_softc *sc, int mode) 3680{ 3681 return (USB_ERR_INVAL); 3682} 3683 3684static usb_error_t 3685urtw_led_mode3(struct urtw_softc *sc, int mode) 3686{ 3687 return (USB_ERR_INVAL); 3688} 3689 3690static usb_error_t 3691urtw_led_on(struct urtw_softc *sc, int type) 3692{ 3693 usb_error_t error; 3694 3695 if (type == URTW_LED_GPIO) { 3696 switch (sc->sc_gpio_ledpin) { 3697 case URTW_LED_PIN_GPIO0: 3698 urtw_write8_m(sc, URTW_GPIO, 0x01); 3699 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3700 break; 3701 default: 3702 DPRINTF(sc, URTW_DEBUG_STATE, 3703 "unsupported LED PIN type 0x%x", 3704 sc->sc_gpio_ledpin); 3705 error = USB_ERR_INVAL; 3706 goto fail; 3707 } 3708 } else { 3709 DPRINTF(sc, URTW_DEBUG_STATE, 3710 "unsupported LED type 0x%x", type); 3711 error = USB_ERR_INVAL; 3712 goto fail; 3713 } 3714 3715 sc->sc_gpio_ledon = 1; 3716fail: 3717 return (error); 3718} 3719 3720static usb_error_t 3721urtw_led_off(struct urtw_softc *sc, int type) 3722{ 3723 usb_error_t error; 3724 3725 if (type == URTW_LED_GPIO) { 3726 switch (sc->sc_gpio_ledpin) { 3727 case URTW_LED_PIN_GPIO0: 3728 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3729 urtw_write8_m(sc, 3730 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3731 break; 3732 default: 3733 DPRINTF(sc, URTW_DEBUG_STATE, 3734 "unsupported LED PIN type 0x%x", 3735 sc->sc_gpio_ledpin); 3736 error = USB_ERR_INVAL; 3737 goto fail; 3738 } 3739 } else { 3740 DPRINTF(sc, URTW_DEBUG_STATE, 3741 "unsupported LED type 0x%x", type); 3742 error = USB_ERR_INVAL; 3743 goto fail; 3744 } 3745 3746 sc->sc_gpio_ledon = 0; 3747 3748fail: 3749 return (error); 3750} 3751 3752static void 3753urtw_led_ch(void *arg) 3754{ 3755 struct urtw_softc *sc = arg; 3756 struct ieee80211com *ic = &sc->sc_ic; 3757 3758 ieee80211_runtask(ic, &sc->sc_led_task); 3759} 3760 3761static void 3762urtw_ledtask(void *arg, int pending) 3763{ 3764 struct urtw_softc *sc = arg; 3765 3766 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3767 DPRINTF(sc, URTW_DEBUG_STATE, 3768 "could not process a LED strategy 0x%x", 3769 sc->sc_strategy); 3770 return; 3771 } 3772 3773 URTW_LOCK(sc); 3774 urtw_led_blink(sc); 3775 URTW_UNLOCK(sc); 3776} 3777 3778static usb_error_t 3779urtw_led_blink(struct urtw_softc *sc) 3780{ 3781 uint8_t ing = 0; 3782 3783 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3784 urtw_led_on(sc, URTW_LED_GPIO); 3785 else 3786 urtw_led_off(sc, URTW_LED_GPIO); 3787 sc->sc_gpio_blinktime--; 3788 if (sc->sc_gpio_blinktime == 0) 3789 ing = 1; 3790 else { 3791 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3792 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3793 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3794 ing = 1; 3795 } 3796 if (ing == 1) { 3797 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3798 sc->sc_gpio_ledon == 0) 3799 urtw_led_on(sc, URTW_LED_GPIO); 3800 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3801 sc->sc_gpio_ledon == 1) 3802 urtw_led_off(sc, URTW_LED_GPIO); 3803 3804 sc->sc_gpio_blinktime = 0; 3805 sc->sc_gpio_ledinprogress = 0; 3806 return (0); 3807 } 3808 3809 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3810 URTW_LED_ON : URTW_LED_OFF; 3811 3812 switch (sc->sc_gpio_ledstate) { 3813 case URTW_LED_BLINK_NORMAL: 3814 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3815 break; 3816 default: 3817 DPRINTF(sc, URTW_DEBUG_STATE, 3818 "unknown LED status 0x%x", 3819 sc->sc_gpio_ledstate); 3820 return (USB_ERR_INVAL); 3821 } 3822 return (0); 3823} 3824 3825static usb_error_t 3826urtw_rx_enable(struct urtw_softc *sc) 3827{ 3828 uint8_t data; 3829 usb_error_t error; 3830 3831 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3832 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3833 3834 error = urtw_rx_setconf(sc); 3835 if (error != 0) 3836 goto fail; 3837 3838 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3839 urtw_read8_m(sc, URTW_CMD, &data); 3840 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3841 } 3842fail: 3843 return (error); 3844} 3845 3846static usb_error_t 3847urtw_tx_enable(struct urtw_softc *sc) 3848{ 3849 uint8_t data8; 3850 uint32_t data; 3851 usb_error_t error; 3852 3853 if (sc->sc_flags & URTW_RTL8187B) { 3854 urtw_read32_m(sc, URTW_TX_CONF, &data); 3855 data &= ~URTW_TX_LOOPBACK_MASK; 3856 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3857 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3858 data &= ~URTW_TX_SWPLCPLEN; 3859 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3860 (7 << 8) | /* short retry limit */ 3861 (7 << 0) | /* long retry limit */ 3862 (7 << 21); /* MAX TX DMA */ 3863 urtw_write32_m(sc, URTW_TX_CONF, data); 3864 3865 urtw_read8_m(sc, URTW_MSR, &data8); 3866 data8 |= URTW_MSR_LINK_ENEDCA; 3867 urtw_write8_m(sc, URTW_MSR, data8); 3868 return (error); 3869 } 3870 3871 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3872 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3873 urtw_write8_m(sc, URTW_CW_CONF, data8); 3874 3875 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3876 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3877 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3878 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3879 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3880 3881 urtw_read32_m(sc, URTW_TX_CONF, &data); 3882 data &= ~URTW_TX_LOOPBACK_MASK; 3883 data |= URTW_TX_LOOPBACK_NONE; 3884 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3885 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3886 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3887 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3888 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3889 data &= ~URTW_TX_SWPLCPLEN; 3890 data |= URTW_TX_NOICV; 3891 urtw_write32_m(sc, URTW_TX_CONF, data); 3892 3893 urtw_read8_m(sc, URTW_CMD, &data8); 3894 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3895fail: 3896 return (error); 3897} 3898 3899static usb_error_t 3900urtw_rx_setconf(struct urtw_softc *sc) 3901{ 3902 struct ieee80211com *ic = &sc->sc_ic; 3903 uint32_t data; 3904 usb_error_t error; 3905 3906 urtw_read32_m(sc, URTW_RX, &data); 3907 data = data &~ URTW_RX_FILTER_MASK; 3908 if (sc->sc_flags & URTW_RTL8187B) { 3909 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3910 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3911 URTW_RX_FIFO_THRESHOLD_NONE | 3912 URTW_MAX_RX_DMA_2048 | 3913 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3914 } else { 3915 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3916 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3917 3918 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3919 data = data | URTW_RX_FILTER_ICVERR; 3920 data = data | URTW_RX_FILTER_PWR; 3921 } 3922 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3923 data = data | URTW_RX_FILTER_CRCERR; 3924 3925 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3926 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3927 URTW_RX_AUTORESETPHY; 3928 data = data &~ URTW_MAX_RX_DMA_MASK; 3929 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3930 } 3931 3932 /* XXX allmulti should not be checked here... */ 3933 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3934 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3935 data = data | URTW_RX_FILTER_CTL; 3936 data = data | URTW_RX_FILTER_ALLMAC; 3937 } else { 3938 data = data | URTW_RX_FILTER_NICMAC; 3939 data = data | URTW_RX_CHECK_BSSID; 3940 } 3941 3942 urtw_write32_m(sc, URTW_RX, data); 3943fail: 3944 return (error); 3945} 3946 3947static struct mbuf * 3948urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3949 int8_t *nf_p) 3950{ 3951 int actlen, flen, rssi; 3952 struct ieee80211_frame *wh; 3953 struct mbuf *m, *mnew; 3954 struct urtw_softc *sc = data->sc; 3955 struct ieee80211com *ic = &sc->sc_ic; 3956 uint8_t noise = 0, rate; 3957 uint64_t mactime; 3958 3959 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3960 3961 if (sc->sc_flags & URTW_RTL8187B) { 3962 struct urtw_8187b_rxhdr *rx; 3963 3964 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3965 goto fail; 3966 3967 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3968 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3969 flen = le32toh(rx->flag) & 0xfff; 3970 if (flen > actlen - sizeof(*rx)) 3971 goto fail; 3972 3973 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3974 /* XXX correct? */ 3975 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3976 noise = rx->noise; 3977 3978 if (ieee80211_radiotap_active(ic)) 3979 mactime = rx->mactime; 3980 } else { 3981 struct urtw_8187l_rxhdr *rx; 3982 3983 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3984 goto fail; 3985 3986 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3987 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3988 flen = le32toh(rx->flag) & 0xfff; 3989 if (flen > actlen - sizeof(*rx)) 3990 goto fail; 3991 3992 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3993 /* XXX correct? */ 3994 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3995 noise = rx->noise; 3996 3997 if (ieee80211_radiotap_active(ic)) 3998 mactime = rx->mactime; 3999 } 4000 4001 if (flen < IEEE80211_ACK_LEN) 4002 goto fail; 4003 4004 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 4005 if (mnew == NULL) 4006 goto fail; 4007 4008 m = data->m; 4009 data->m = mnew; 4010 data->buf = mtod(mnew, uint8_t *); 4011 4012 /* finalize mbuf */ 4013 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 4014 4015 if (ieee80211_radiotap_active(ic)) { 4016 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 4017 4018 tap->wr_tsf = mactime; 4019 tap->wr_flags = 0; 4020 tap->wr_dbm_antsignal = (int8_t)rssi; 4021 } 4022 4023 wh = mtod(m, struct ieee80211_frame *); 4024 if (IEEE80211_IS_DATA(wh)) 4025 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 4026 4027 *rssi_p = rssi; 4028 *nf_p = noise; /* XXX correct? */ 4029 4030 return (m); 4031 4032fail: 4033 counter_u64_add(ic->ic_ierrors, 1); 4034 return (NULL); 4035} 4036 4037static void 4038urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 4039{ 4040 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4041 struct ieee80211com *ic = &sc->sc_ic; 4042 struct ieee80211_node *ni; 4043 struct mbuf *m = NULL; 4044 struct urtw_data *data; 4045 int8_t nf = -95; 4046 int rssi = 1; 4047 4048 URTW_ASSERT_LOCKED(sc); 4049 4050 switch (USB_GET_STATE(xfer)) { 4051 case USB_ST_TRANSFERRED: 4052 data = STAILQ_FIRST(&sc->sc_rx_active); 4053 if (data == NULL) 4054 goto setup; 4055 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4056 m = urtw_rxeof(xfer, data, &rssi, &nf); 4057 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4058 /* FALLTHROUGH */ 4059 case USB_ST_SETUP: 4060setup: 4061 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4062 if (data == NULL) { 4063 KASSERT(m == NULL, ("mbuf isn't NULL")); 4064 return; 4065 } 4066 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4067 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4068 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4069 usbd_xfer_max_len(xfer)); 4070 usbd_transfer_submit(xfer); 4071 4072 /* 4073 * To avoid LOR we should unlock our private mutex here to call 4074 * ieee80211_input() because here is at the end of a USB 4075 * callback and safe to unlock. 4076 */ 4077 URTW_UNLOCK(sc); 4078 if (m != NULL) { 4079 if (m->m_pkthdr.len >= 4080 sizeof(struct ieee80211_frame_min)) { 4081 ni = ieee80211_find_rxnode(ic, 4082 mtod(m, struct ieee80211_frame_min *)); 4083 } else 4084 ni = NULL; 4085 4086 if (ni != NULL) { 4087 (void) ieee80211_input(ni, m, rssi, nf); 4088 /* node is no longer needed */ 4089 ieee80211_free_node(ni); 4090 } else 4091 (void) ieee80211_input_all(ic, m, rssi, nf); 4092 m = NULL; 4093 } 4094 URTW_LOCK(sc); 4095 break; 4096 default: 4097 /* needs it to the inactive queue due to a error. */ 4098 data = STAILQ_FIRST(&sc->sc_rx_active); 4099 if (data != NULL) { 4100 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4101 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4102 } 4103 if (error != USB_ERR_CANCELLED) { 4104 usbd_xfer_set_stall(xfer); 4105 counter_u64_add(ic->ic_ierrors, 1); 4106 goto setup; 4107 } 4108 break; 4109 } 4110} 4111 4112#define URTW_STATUS_TYPE_TXCLOSE 1 4113#define URTW_STATUS_TYPE_BEACON_INTR 0 4114 4115static void 4116urtw_txstatus_eof(struct usb_xfer *xfer) 4117{ 4118 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4119 struct ieee80211com *ic = &sc->sc_ic; 4120 int actlen, type, pktretry; 4121 uint64_t val; 4122 4123 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4124 4125 if (actlen != sizeof(uint64_t)) 4126 return; 4127 4128 val = le64toh(sc->sc_txstatus); 4129 type = (val >> 30) & 0x3; 4130 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4131 pktretry = val & 0xff; 4132 if (pktretry == URTW_TX_MAXRETRY) 4133 counter_u64_add(ic->ic_oerrors, 1); 4134 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4135 pktretry, (val >> 16) & 0xff); 4136 } 4137} 4138 4139static void 4140urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4141{ 4142 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4143 struct ieee80211com *ic = &sc->sc_ic; 4144 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4145 4146 URTW_ASSERT_LOCKED(sc); 4147 4148 switch (USB_GET_STATE(xfer)) { 4149 case USB_ST_TRANSFERRED: 4150 urtw_txstatus_eof(xfer); 4151 /* FALLTHROUGH */ 4152 case USB_ST_SETUP: 4153setup: 4154 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4155 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4156 usbd_transfer_submit(xfer); 4157 break; 4158 default: 4159 if (error != USB_ERR_CANCELLED) { 4160 usbd_xfer_set_stall(xfer); 4161 counter_u64_add(ic->ic_ierrors, 1); 4162 goto setup; 4163 } 4164 break; 4165 } 4166} 4167 4168static void 4169urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4170{ 4171 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4172 4173 URTW_ASSERT_LOCKED(sc); 4174 4175 if (data->m) { 4176 /* XXX status? */ 4177 ieee80211_tx_complete(data->ni, data->m, 0); 4178 data->m = NULL; 4179 data->ni = NULL; 4180 } 4181 sc->sc_txtimer = 0; 4182} 4183 4184static void 4185urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4186{ 4187 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4188 struct urtw_data *data; 4189 4190 URTW_ASSERT_LOCKED(sc); 4191 4192 switch (USB_GET_STATE(xfer)) { 4193 case USB_ST_TRANSFERRED: 4194 data = STAILQ_FIRST(&sc->sc_tx_active); 4195 if (data == NULL) 4196 goto setup; 4197 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4198 urtw_txeof(xfer, data); 4199 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4200 /* FALLTHROUGH */ 4201 case USB_ST_SETUP: 4202setup: 4203 data = STAILQ_FIRST(&sc->sc_tx_pending); 4204 if (data == NULL) { 4205 DPRINTF(sc, URTW_DEBUG_XMIT, 4206 "%s: empty pending queue\n", __func__); 4207 return; 4208 } 4209 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4210 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4211 4212 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4213 usbd_transfer_submit(xfer); 4214 4215 urtw_start(sc); 4216 break; 4217 default: 4218 data = STAILQ_FIRST(&sc->sc_tx_active); 4219 if (data == NULL) 4220 goto setup; 4221 if (data->ni != NULL) { 4222 if_inc_counter(data->ni->ni_vap->iv_ifp, 4223 IFCOUNTER_OERRORS, 1); 4224 ieee80211_free_node(data->ni); 4225 data->ni = NULL; 4226 } 4227 if (error != USB_ERR_CANCELLED) { 4228 usbd_xfer_set_stall(xfer); 4229 goto setup; 4230 } 4231 break; 4232 } 4233} 4234 4235static struct urtw_data * 4236_urtw_getbuf(struct urtw_softc *sc) 4237{ 4238 struct urtw_data *bf; 4239 4240 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4241 if (bf != NULL) 4242 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4243 else 4244 bf = NULL; 4245 if (bf == NULL) 4246 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4247 "out of xmit buffers"); 4248 return (bf); 4249} 4250 4251static struct urtw_data * 4252urtw_getbuf(struct urtw_softc *sc) 4253{ 4254 struct urtw_data *bf; 4255 4256 URTW_ASSERT_LOCKED(sc); 4257 4258 bf = _urtw_getbuf(sc); 4259 if (bf == NULL) 4260 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4261 return (bf); 4262} 4263 4264static int 4265urtw_isbmode(uint16_t rate) 4266{ 4267 4268 return ((rate <= 22 && rate != 12 && rate != 18) || 4269 rate == 44) ? (1) : (0); 4270} 4271 4272static uint16_t 4273urtw_rate2dbps(uint16_t rate) 4274{ 4275 4276 switch(rate) { 4277 case 12: 4278 case 18: 4279 case 24: 4280 case 36: 4281 case 48: 4282 case 72: 4283 case 96: 4284 case 108: 4285 return (rate * 2); 4286 default: 4287 break; 4288 } 4289 return (24); 4290} 4291 4292static int 4293urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4294 uint8_t ismgt, uint8_t isshort) 4295{ 4296 uint16_t ceiling, frametime, n_dbps; 4297 4298 if (urtw_isbmode(rate)) { 4299 if (ismgt || !isshort || rate == 2) 4300 frametime = (uint16_t)(144 + 48 + 4301 (framelen * 8 / (rate / 2))); 4302 else 4303 frametime = (uint16_t)(72 + 24 + 4304 (framelen * 8 / (rate / 2))); 4305 if ((framelen * 8 % (rate / 2)) != 0) 4306 frametime++; 4307 } else { 4308 n_dbps = urtw_rate2dbps(rate); 4309 ceiling = (16 + 8 * framelen + 6) / n_dbps 4310 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4311 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4312 } 4313 return (frametime); 4314} 4315 4316/* 4317 * Callback from the 802.11 layer to update the 4318 * slot time based on the current setting. 4319 */ 4320static void 4321urtw_updateslot(struct ieee80211com *ic) 4322{ 4323 struct urtw_softc *sc = ic->ic_softc; 4324 4325 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4326} 4327 4328static void 4329urtw_updateslottask(void *arg, int pending) 4330{ 4331 struct urtw_softc *sc = arg; 4332 struct ieee80211com *ic = &sc->sc_ic; 4333 int error; 4334 4335 URTW_LOCK(sc); 4336 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4337 URTW_UNLOCK(sc); 4338 return; 4339 } 4340 if (sc->sc_flags & URTW_RTL8187B) { 4341 urtw_write8_m(sc, URTW_SIFS, 0x22); 4342 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4343 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4344 else 4345 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4346 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4347 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4348 } else { 4349 urtw_write8_m(sc, URTW_SIFS, 0x22); 4350 if (sc->sc_state == IEEE80211_S_ASSOC && 4351 ic->ic_flags & IEEE80211_F_SHSLOT) 4352 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4353 else 4354 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4355 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4356 urtw_write8_m(sc, URTW_DIFS, 0x14); 4357 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4358 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4359 } else { 4360 urtw_write8_m(sc, URTW_DIFS, 0x24); 4361 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4362 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4363 } 4364 } 4365fail: 4366 URTW_UNLOCK(sc); 4367} 4368 4369static void 4370urtw_sysctl_node(struct urtw_softc *sc) 4371{ 4372#define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4373 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4374 struct sysctl_ctx_list *ctx; 4375 struct sysctl_oid_list *child, *parent; 4376 struct sysctl_oid *tree; 4377 struct urtw_stats *stats = &sc->sc_stats; 4378 4379 ctx = device_get_sysctl_ctx(sc->sc_dev); 4380 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4381 4382 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4383 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "URTW statistics"); 4384 parent = SYSCTL_CHILDREN(tree); 4385 4386 /* Tx statistics. */ 4387 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 4388 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 4389 child = SYSCTL_CHILDREN(tree); 4390 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4391 "1 Mbit/s"); 4392 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4393 "2 Mbit/s"); 4394 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4395 "5.5 Mbit/s"); 4396 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4397 "6 Mbit/s"); 4398 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4399 "9 Mbit/s"); 4400 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4401 "11 Mbit/s"); 4402 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4403 "12 Mbit/s"); 4404 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4405 "18 Mbit/s"); 4406 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4407 "24 Mbit/s"); 4408 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4409 "36 Mbit/s"); 4410 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4411 "48 Mbit/s"); 4412 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4413 "54 Mbit/s"); 4414#undef URTW_SYSCTL_STAT_ADD32 4415} 4416 4417static device_method_t urtw_methods[] = { 4418 DEVMETHOD(device_probe, urtw_match), 4419 DEVMETHOD(device_attach, urtw_attach), 4420 DEVMETHOD(device_detach, urtw_detach), 4421 DEVMETHOD_END 4422}; 4423 4424static driver_t urtw_driver = { 4425 .name = "urtw", 4426 .methods = urtw_methods, 4427 .size = sizeof(struct urtw_softc) 4428}; 4429 4430DRIVER_MODULE(urtw, uhub, urtw_driver, NULL, NULL); 4431MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4432MODULE_DEPEND(urtw, usb, 1, 1, 1); 4433MODULE_VERSION(urtw, 1); 4434USB_PNP_HOST_INFO(urtw_devs); 4435