1/* $OpenBSD: if_uathreg.h,v 1.2 2006/09/18 16:34:23 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2006 Sam Leffler, Errno Consulting 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#define UATH_CONFIG_INDEX 0 22#define UATH_IFACE_INDEX 0 23 24/* all fields are big endian */ 25struct uath_fwblock { 26 uint32_t flags; 27#define UATH_WRITE_BLOCK (1 << 4) 28 29 uint32_t len; 30#define UATH_MAX_FWBLOCK_SIZE 2048 31 32 uint32_t total; 33 uint32_t remain; 34 uint32_t rxtotal; 35 uint32_t pad[123]; 36} __packed; 37 38#define UATH_MAX_CMDSZ 512 39 40/* 41 * Messages are passed in Target Endianness. All fixed-size 42 * fields of a WDS Control Message are treated as 32-bit 43 * values and Control Msgs are guaranteed to be 32-bit aligned. 44 * 45 * The format of a WDS Control Message is as follows: 46 * Message Length 32 bits 47 * Message Opcode 32 bits 48 * Message ID 32 bits 49 * parameter 1 50 * parameter 2 51 * ... 52 * 53 * A variable-length parameter, or a parameter that is larger than 54 * 32 bits is passed as <length, data> pair, where length is a 55 * 32-bit quantity and data is padded to 32 bits. 56 */ 57struct uath_cmd_hdr { 58 uint32_t len; /* msg length including header */ 59 uint32_t code; /* operation code */ 60/* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ 61/* messages from Host -> Target */ 62#define WDCMSG_HOST_AVAILABLE 0x01 63#define WDCMSG_BIND 0x02 64#define WDCMSG_TARGET_RESET 0x03 65#define WDCMSG_TARGET_GET_CAPABILITY 0x04 66#define WDCMSG_TARGET_SET_CONFIG 0x05 67#define WDCMSG_TARGET_GET_STATUS 0x06 68#define WDCMSG_TARGET_GET_STATS 0x07 69#define WDCMSG_TARGET_START 0x08 70#define WDCMSG_TARGET_STOP 0x09 71#define WDCMSG_TARGET_ENABLE 0x0a 72#define WDCMSG_TARGET_DISABLE 0x0b 73#define WDCMSG_CREATE_CONNECTION 0x0c 74#define WDCMSG_UPDATE_CONNECT_ATTR 0x0d 75#define WDCMSG_DELETE_CONNECT 0x0e 76#define WDCMSG_SEND 0x0f 77#define WDCMSG_FLUSH 0x10 78/* messages from Target -> Host */ 79#define WDCMSG_STATS_UPDATE 0x11 80#define WDCMSG_BMISS 0x12 81#define WDCMSG_DEVICE_AVAIL 0x13 82#define WDCMSG_SEND_COMPLETE 0x14 83#define WDCMSG_DATA_AVAIL 0x15 84#define WDCMSG_SET_PWR_MODE 0x16 85#define WDCMSG_BMISS_ACK 0x17 86#define WDCMSG_SET_LED_STEADY 0x18 87#define WDCMSG_SET_LED_BLINK 0x19 88/* more messages */ 89#define WDCMSG_SETUP_BEACON_DESC 0x1a 90#define WDCMSG_BEACON_INIT 0x1b 91#define WDCMSG_RESET_KEY_CACHE 0x1c 92#define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d 93#define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e 94#define WDCMSG_SET_DECOMP_MASK 0x1f 95#define WDCMSG_SET_REGULATORY_DOMAIN 0x20 96#define WDCMSG_SET_LED_STATE 0x21 97#define WDCMSG_WRITE_ASSOCID 0x22 98#define WDCMSG_SET_STA_BEACON_TIMERS 0x23 99#define WDCMSG_GET_TSF 0x24 100#define WDCMSG_RESET_TSF 0x25 101#define WDCMSG_SET_ADHOC_MODE 0x26 102#define WDCMSG_SET_BASIC_RATE 0x27 103#define WDCMSG_MIB_CONTROL 0x28 104#define WDCMSG_GET_CHANNEL_DATA 0x29 105#define WDCMSG_GET_CUR_RSSI 0x2a 106#define WDCMSG_SET_ANTENNA_SWITCH 0x2b 107#define WDCMSG_USE_SHORT_SLOT_TIME 0x2f 108#define WDCMSG_SET_POWER_MODE 0x30 109#define WDCMSG_SETUP_PSPOLL_DESC 0x31 110#define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 111#define WDCMSG_RX_FILTER 0x33 112#define WDCMSG_PER_CALIBRATION 0x34 113#define WDCMSG_RESET 0x35 114#define WDCMSG_DISABLE 0x36 115#define WDCMSG_PHY_DISABLE 0x37 116#define WDCMSG_SET_TX_POWER_LIMIT 0x38 117#define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 118#define WDCMSG_SETUP_TX_QUEUE 0x3a 119#define WDCMSG_RELEASE_TX_QUEUE 0x3b 120#define WDCMSG_SET_DEFAULT_KEY 0x43 121 uint32_t msgid; /* msg id (supplied by host) */ 122 uint32_t magic; /* response desired/target status */ 123 uint32_t debug[4]; /* debug data area */ 124 /* msg data follows */ 125} __packed; 126 127struct uath_chunk { 128 uint8_t seqnum; /* sequence number for ordering */ 129 uint8_t flags; 130#define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ 131#define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ 132#define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ 133 uint16_t length; /* chunk size in bytes */ 134 /* chunk data follows */ 135} __packed; 136 137#define UATH_RX_DUMMYSIZE 4 138 139/* 140 * Message format for a WDCMSG_DATA_AVAIL message from Target to Host. 141 */ 142struct uath_rx_desc { 143 uint32_t len; /* msg length including header */ 144 uint32_t code; /* WDCMSG_DATA_AVAIL */ 145 uint32_t gennum; /* generation number */ 146 uint32_t status; /* start of RECEIVE_INFO */ 147#define UATH_STATUS_OK 0 148#define UATH_STATUS_STOP_IN_PROGRESS 1 149#define UATH_STATUS_CRC_ERR 2 150#define UATH_STATUS_PHY_ERR 3 151#define UATH_STATUS_DECRYPT_CRC_ERR 4 152#define UATH_STATUS_DECRYPT_MIC_ERR 5 153#define UATH_STATUS_DECOMP_ERR 6 154#define UATH_STATUS_KEY_ERR 7 155#define UATH_STATUS_ERR 8 156 uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */ 157 uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */ 158 uint32_t framelen; /* frame length */ 159 uint32_t rate; /* rx rate code */ 160 uint32_t antenna; 161 int32_t rssi; 162 uint32_t channel; 163 uint32_t phyerror; 164 uint32_t connix; /* key table ix for bss traffic */ 165 uint32_t decrypterror; 166 uint32_t keycachemiss; 167 uint32_t pad; /* XXX? */ 168} __packed; 169 170struct uath_tx_desc { 171 uint32_t msglen; 172 uint32_t msgid; /* msg id (supplied by host) */ 173 uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ 174 uint32_t txqid; /* tx queue id and flags */ 175#define UATH_TXQID_MASK 0x0f 176#define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ 177#define UATH_TXQID_FF 0x20 /* content is fast frame */ 178 uint32_t connid; /* tx connection id */ 179#define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ 180 uint32_t flags; /* non-zero if response desired */ 181#define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ 182 uint32_t buflen; /* payload length */ 183} __packed; 184 185struct uath_cmd_host_available { 186 uint32_t sw_ver_major; 187 uint32_t sw_ver_minor; 188 uint32_t sw_ver_patch; 189 uint32_t sw_ver_build; 190} __packed; 191#define ATH_SW_VER_MAJOR 1 192#define ATH_SW_VER_MINOR 5 193#define ATH_SW_VER_PATCH 0 194#define ATH_SW_VER_BUILD 9999 195 196struct uath_cmd_bind { 197 uint32_t targethandle; 198 uint32_t hostapiversion; 199} __packed; 200 201/* structure for command WDCMSG_RESET */ 202struct uath_cmd_reset { 203 uint32_t flags; /* channel flags */ 204#define UATH_CHAN_TURBO 0x0100 205#define UATH_CHAN_CCK 0x0200 206#define UATH_CHAN_OFDM 0x0400 207#define UATH_CHAN_2GHZ 0x1000 208#define UATH_CHAN_5GHZ 0x2000 209 uint32_t freq; /* channel frequency */ 210 uint32_t maxrdpower; 211 uint32_t cfgctl; 212 uint32_t twiceantennareduction; 213 uint32_t channelchange; 214 uint32_t keeprccontent; 215} __packed; 216 217/* structure for commands UATH_CMD_READ_MAC and UATH_CMD_READ_EEPROM */ 218struct uath_read_mac { 219 uint32_t len; 220 uint8_t data[32]; 221} __packed; 222 223/* structure for command UATH_CMD_WRITE_MAC */ 224struct uath_write_mac { 225 uint32_t reg; 226 uint32_t len; 227 uint8_t data[32]; 228} __packed; 229 230/* structure for command UATH_CMD_STA_JOIN */ 231struct uath_cmd_join_bss { 232 uint32_t bssid; /* NB: use zero */ 233 uint32_t bssmac[2]; /* bssid mac address */ 234 uint32_t bsstype; 235 uint32_t wlanmode; 236 uint32_t beaconinterval; 237 uint32_t dtiminterval; 238 uint32_t cfpinterval; 239 uint32_t atimwindow; 240 uint32_t defaultrateix; 241 uint32_t shortslottime11g; 242 uint32_t sleepduration; 243 uint32_t bmissthreshold; 244 uint32_t tcppowerlimit; 245 uint32_t quietduration; 246 uint32_t quietoffset; 247 uint32_t quietackctsallow; 248 uint32_t bssdefaultkey; /* XXX? */ 249} __packed; 250 251struct uath_cmd_assoc_bss { 252 uint32_t bssid; 253 uint32_t associd; 254} __packed; 255 256struct uath_cmd_start_bss { 257 uint32_t bssid; 258} __packed; 259 260/* structure for command UATH_CMD_0C */ 261struct uath_cmd_0c { 262 uint32_t magic1; 263 uint32_t magic2; 264 uint32_t magic3; 265} __packed; 266 267struct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ 268 uint32_t lednum; 269#define UATH_LED_LINK 0 270#define UATH_LED_ACTIVITY 1 271 uint32_t ledmode; 272#define UATH_LED_OFF 0 273#define UATH_LED_ON 1 274} __packed; 275 276struct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ 277 uint32_t lednum; 278 uint32_t ledmode; 279 uint32_t blinkrate; 280 uint32_t slowmode; 281} __packed; 282 283struct uath_cmd_ledstate { /* WDCMSG_SET_LED_STATE */ 284 uint32_t connected; 285} __packed; 286 287struct uath_connkey_rec { 288 uint8_t bssid[IEEE80211_ADDR_LEN]; 289 uint32_t keyiv; 290 uint32_t extkeyiv; 291 uint16_t keyflags; 292 uint16_t keylen; 293 uint16_t keytype; /* WEP, TKIP or AES */ 294 /* As far as I know, MIPS 4Kp is 32-bit processor */ 295 uint32_t priv; 296 uint8_t keyval[32]; 297 uint16_t aes_keylen; 298 uint8_t aes_keyval[16]; 299 uint8_t mic_txkeyval[8]; 300 uint8_t mic_rxkeyval[8]; 301 int64_t keyrsc[17]; 302 int32_t keytsc[17]; 303 int32_t keyexttsc[17]; 304} __packed; 305 306/* structure for command UATH_CMD_CRYPTO */ 307struct uath_cmd_crypto { 308 uint32_t keyidx; 309#define UATH_DEFAULT_KEY 6 310 uint32_t xorkey; 311 uint32_t size; 312 struct uath_connkey_rec rec; 313} __packed; 314 315struct uath_cmd_rateset { 316 uint8_t length; 317#define UATH_MAX_NRATES 32 318 uint8_t set[UATH_MAX_NRATES]; 319}; 320 321/* structure for command WDCMSG_SET_BASIC_RATE */ 322struct uath_cmd_rates { 323 uint32_t connid; 324 uint32_t keeprccontent; 325 uint32_t size; 326 struct uath_cmd_rateset rateset; 327} __packed; 328 329enum { 330 WLAN_MODE_NONE = 0, 331 WLAN_MODE_11b, 332 WLAN_MODE_11a, 333 WLAN_MODE_11g, 334 WLAN_MODE_11a_TURBO, 335 WLAN_MODE_11g_TURBO, 336 WLAN_MODE_11a_TURBO_PRIME, 337 WLAN_MODE_11g_TURBO_PRIME, 338 WLAN_MODE_11a_XR, 339 WLAN_MODE_11g_XR, 340}; 341 342struct uath_cmd_connection_attr { 343 uint32_t longpreambleonly; 344 struct uath_cmd_rateset rateset; 345 uint32_t wlanmode; 346} __packed; 347 348/* structure for command WDCMSG_CREATE_CONNECTION */ 349struct uath_cmd_create_connection { 350 uint32_t connid; 351 uint32_t bssid; 352 uint32_t size; 353 struct uath_cmd_connection_attr connattr; 354} __packed; 355 356struct uath_cmd_txq_setparams { /* WDCMSG_SET_TX_QUEUE_PARAMS */ 357 uint32_t qnum; 358 uint32_t aifs; 359 uint32_t logcwmin; 360 uint32_t logcwmax; 361 uint32_t bursttime; 362 uint32_t qflags; 363} __packed; 364 365struct uath_cmd_txq_attr { 366 uint32_t priority; 367 uint32_t aifs; 368 uint32_t logcwmin; 369 uint32_t logcwmax; 370 uint32_t bursttime; 371 uint32_t mode; 372 uint32_t qflags; 373} __packed; 374 375struct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ 376 uint32_t qid; 377 uint32_t len; 378 struct uath_cmd_txq_attr attr; 379} __packed; 380 381struct uath_cmd_stoptxdma { /* WDCMSG_STOP_TX_DMA */ 382 uint32_t qnum; 383 uint32_t msec; 384} __packed; 385 386/* structure for command UATH_CMD_31 */ 387struct uath_cmd_31 { 388 uint32_t magic1; 389 uint32_t magic2; 390} __packed; 391 392struct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */ 393 uint32_t bits; 394#define UATH_FILTER_RX_UCAST 0x00000001 395#define UATH_FILTER_RX_MCAST 0x00000002 396#define UATH_FILTER_RX_BCAST 0x00000004 397#define UATH_FILTER_RX_CONTROL 0x00000008 398#define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ 399#define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ 400#define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ 401#define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ 402#define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ 403#define UATH_FILTER_RX_PROBE_REQ 0x00000800 404 uint32_t op; 405#define UATH_FILTER_OP_INIT 0x0 406#define UATH_FILTER_OP_SET 0x1 407#define UATH_FILTER_OP_CLEAR 0x2 408#define UATH_FILTER_OP_TEMP 0x3 409#define UATH_FILTER_OP_RESTORE 0x4 410} __packed; 411 412struct uath_cmd_rx_mcast_filter { /* WDCMSG_SET_RX_MCAST_FILTER */ 413 uint32_t filter0; 414 uint32_t filter1; 415} __packed; 416 417struct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */ 418 uint32_t defaultrateix; 419 uint32_t associd; 420 uint32_t timoffset; 421 uint32_t turboprime; 422 uint32_t bssid[2]; 423} __packed; 424 425struct uath_cmd_set_stabeacon_timers { /* WDCMSG_SET_STA_BEACON_TIMERS */ 426 uint32_t nexttbtt; 427 uint32_t nextdtim; 428 uint32_t nextcfp; 429 uint32_t beaconperiod; 430 uint32_t dtimperiod; 431 uint32_t cfpperiod; 432 uint32_t cfpduration; 433 uint32_t sleepduration; 434 uint32_t bsmissthreshold; 435} __packed; 436 437enum { 438 CFG_NONE, /* Sentinal to indicate "no config" */ 439 CFG_REG_DOMAIN, /* Regulatory Domain */ 440 CFG_RATE_CONTROL_ENABLE, 441 CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ 442 CFG_HW_TX_RETRIES, 443 CFG_SW_TX_RETRIES, 444 CFG_SLOW_CLOCK_ENABLE, 445 CFG_COMP_PROC, 446 CFG_USER_RTS_THRESHOLD, 447 CFG_XR2NORM_RATE_THRESHOLD, 448 CFG_XRMODE_SWITCH_COUNT, 449 CFG_PROTECTION_TYPE, 450 CFG_BURST_SEQ_THRESHOLD, 451 CFG_ABOLT, 452 CFG_IQ_LOG_COUNT_MAX, 453 CFG_MODE_CTS, 454 CFG_WME_ENABLED, 455 CFG_GPRS_CBR_PERIOD, 456 CFG_SERVICE_TYPE, 457 /* MAC Address to use. Overrides EEPROM */ 458 CFG_MAC_ADDR, 459 CFG_DEBUG_EAR, 460 CFG_INIT_REGS, 461 /* An ID for use in error & debug messages */ 462 CFG_DEBUG_ID, 463 CFG_COMP_WIN_SZ, 464 CFG_DIVERSITY_CTL, 465 CFG_TP_SCALE, 466 CFG_TPC_HALF_DBM5, 467 CFG_TPC_HALF_DBM2, 468 CFG_OVERRD_TX_POWER, 469 CFG_USE_32KHZ_CLOCK, 470 CFG_GMODE_PROTECTION, 471 CFG_GMODE_PROTECT_RATE_INDEX, 472 CFG_GMODE_NON_ERP_PREAMBLE, 473 CFG_WDC_TRANSPORT_CHUNK_SIZE, 474}; 475 476enum { 477 /* Sentinal to indicate "no capability" */ 478 CAP_NONE, 479 CAP_ALL, /* ALL capabilities */ 480 CAP_TARGET_VERSION, 481 CAP_TARGET_REVISION, 482 CAP_MAC_VERSION, 483 CAP_MAC_REVISION, 484 CAP_PHY_REVISION, 485 CAP_ANALOG_5GHz_REVISION, 486 CAP_ANALOG_2GHz_REVISION, 487 /* Target supports WDC message debug features */ 488 CAP_DEBUG_WDCMSG_SUPPORT, 489 490 CAP_REG_DOMAIN, 491 CAP_COUNTRY_CODE, 492 CAP_REG_CAP_BITS, 493 494 CAP_WIRELESS_MODES, 495 CAP_CHAN_SPREAD_SUPPORT, 496 CAP_SLEEP_AFTER_BEACON_BROKEN, 497 CAP_COMPRESS_SUPPORT, 498 CAP_BURST_SUPPORT, 499 CAP_FAST_FRAMES_SUPPORT, 500 CAP_CHAP_TUNING_SUPPORT, 501 CAP_TURBOG_SUPPORT, 502 CAP_TURBO_PRIME_SUPPORT, 503 CAP_DEVICE_TYPE, 504 CAP_XR_SUPPORT, 505 CAP_WME_SUPPORT, 506 CAP_TOTAL_QUEUES, 507 CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ 508 509 CAP_LOW_5GHZ_CHAN, 510 CAP_HIGH_5GHZ_CHAN, 511 CAP_LOW_2GHZ_CHAN, 512 CAP_HIGH_2GHZ_CHAN, 513 514 CAP_MIC_AES_CCM, 515 CAP_MIC_CKIP, 516 CAP_MIC_TKIP, 517 CAP_MIC_TKIP_WME, 518 CAP_CIPHER_AES_CCM, 519 CAP_CIPHER_CKIP, 520 CAP_CIPHER_TKIP, 521 522 CAP_TWICE_ANTENNAGAIN_5G, 523 CAP_TWICE_ANTENNAGAIN_2G, 524}; 525 526enum { 527 ST_NONE, /* Sentinal to indicate "no status" */ 528 ST_ALL, 529 ST_SERVICE_TYPE, 530 ST_WLAN_MODE, 531 ST_FREQ, 532 ST_BAND, 533 ST_LAST_RSSI, 534 ST_PS_FRAMES_DROPPED, 535 ST_CACHED_DEF_ANT, 536 ST_COUNT_OTHER_RX_ANT, 537 ST_USE_FAST_DIVERSITY, 538 ST_MAC_ADDR, 539 ST_RX_GENERATION_NUM, 540 ST_TX_QUEUE_DEPTH, 541 ST_SERIAL_NUMBER, 542 ST_WDC_TRANSPORT_CHUNK_SIZE, 543}; 544 545enum { 546 BSS_ATTR_BEACON_INTERVAL, 547 BSS_ATTR_DTIM_INTERVAL, 548 BSS_ATTR_CFP_INTERVAL, 549 BSS_ATTR_CFP_MAX_DURATION, 550 BSS_ATTR_ATIM_WINDOW, 551 BSS_ATTR_DEFAULT_RATE_INDEX, 552 BSS_ATTR_SHORT_SLOT_TIME_11g, 553 BSS_ATTR_SLEEP_DURATION, 554 BSS_ATTR_BMISS_THRESHOLD, 555 BSS_ATTR_TPC_POWER_LIMIT, 556 BSS_ATTR_BSS_KEY_UPDATE, 557}; 558 559struct uath_cmd_update_bss_attribute { 560 uint32_t bssid; 561 uint32_t attribute; /* BSS_ATTR_BEACON_INTERVAL, et al. */ 562 uint32_t cfgsize; /* should be zero 0 */ 563 uint32_t cfgdata; 564}; 565 566struct uath_cmd_update_bss_attribute_key { 567 uint32_t bssid; 568 uint32_t attribute; /* BSS_ATTR_BSS_KEY_UPDATE */ 569 uint32_t cfgsize; /* size of remaining data */ 570 uint32_t bsskeyix; 571 uint32_t isdefaultkey; 572 uint32_t keyiv; /* IV generation control */ 573 uint32_t extkeyiv; /* extended IV for TKIP & CCM */ 574 uint32_t keyflags; 575 uint32_t keytype; 576 uint32_t initvalue; /* XXX */ 577 uint32_t keyval[4]; 578 uint32_t mictxkeyval[2]; 579 uint32_t micrxkeyval[2]; 580 uint32_t keyrsc[2]; 581}; 582 583enum { 584 TARGET_DEVICE_AWAKE, 585 TARGET_DEVICE_SLEEP, 586 TARGET_DEVICE_PWRDN, 587 TARGET_DEVICE_PWRSAVE, 588 TARGET_DEVICE_SUSPEND, 589 TARGET_DEVICE_RESUME, 590}; 591 592#define UATH_MAX_TXBUFSZ \ 593 (sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc) + \ 594 IEEE80211_MAX_LEN) 595 596/* 597 * it's not easy to measure how the chunk is passed into the host if the target 598 * passed the multi-chunks so just we check a minimal size we can imagine. 599 */ 600#define UATH_MIN_RXBUFSZ (sizeof(struct uath_chunk)) 601