1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37#include <sys/param.h> 38#include <sys/module.h> 39#include <sys/systm.h> /* For FreeBSD 11 */ 40#include <sys/types.h> /* For FreeBSD 11 */ 41#include <sys/errno.h> 42#include <sys/kernel.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <machine/bus.h> 46#include <sys/mutex.h> 47#include <sys/malloc.h> 48#include <sys/rman.h> 49#include <sys/queue.h> 50#include <sys/taskqueue.h> 51#include <sys/sysctl.h> 52#include <dev/pci/pcivar.h> 53#include <dev/pci/pcireg.h> 54#include <dev/mmc/bridge.h> 55#include <dev/mmc/mmcreg.h> 56#include <dev/mmc/mmcbrvar.h> 57#include <machine/_inttypes.h> 58 59#include "opt_mmccam.h" 60 61#ifdef MMCCAM 62#include <cam/cam.h> 63#include <cam/cam_ccb.h> 64#include <cam/cam_debug.h> 65#include <cam/cam_sim.h> 66#include <cam/cam_xpt_sim.h> 67#include <cam/mmc/mmc_sim.h> 68#include "mmc_sim_if.h" 69#endif /* MMCCAM */ 70 71#include "rtsxreg.h" 72 73/* The softc holds our per-instance data. */ 74struct rtsx_softc { 75 struct mtx rtsx_mtx; /* device mutex */ 76 device_t rtsx_dev; /* device */ 77 uint16_t rtsx_flags; /* device flags */ 78 uint16_t rtsx_device_id; /* device ID */ 79 device_t rtsx_mmc_dev; /* device of mmc bus */ 80 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 81 uint32_t rtsx_intr_status; /* soft interrupt status */ 82 int rtsx_irq_res_id; /* bus IRQ resource id */ 83 struct resource *rtsx_irq_res; /* bus IRQ resource */ 84 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 85 struct callout rtsx_timeout_callout; /* callout for timeout */ 86 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 87 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 88 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 89 /* function to call if transfer succeed */ 90 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 91 /* function to call if transfer fail */ 92 93 struct timeout_task 94 rtsx_card_insert_task; /* card insert delayed task */ 95 struct task rtsx_card_remove_task; /* card remove task */ 96 97 int rtsx_mem_res_id; /* bus memory resource id */ 98 struct resource *rtsx_mem_res; /* bus memory resource */ 99 bus_space_tag_t rtsx_mem_btag; /* host register set tag */ 100 bus_space_handle_t rtsx_mem_bhandle; /* host register set handle */ 101 102 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 103 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 104 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 105 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 106 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 107 108 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 109 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 110 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 111 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 112 113#ifdef MMCCAM 114 union ccb *rtsx_ccb; /* CAM control block */ 115 struct mmc_sim rtsx_mmc_sim; /* CAM generic sim */ 116 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 117#endif /* MMCCAM */ 118 119 struct mmc_request *rtsx_req; /* MMC request */ 120 struct mmc_host rtsx_host; /* host parameters */ 121 int rtsx_pcie_cap; /* PCIe capability offset */ 122 int8_t rtsx_bus_busy; /* bus busy status */ 123 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 124 int32_t rtsx_ios_clock; /* current host.ios.clock */ 125 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 126 int8_t rtsx_ios_timing; /* current host.ios.timing */ 127 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 128 uint8_t rtsx_read_only; /* card read only status */ 129 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 130 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 131 uint8_t rtsx_debug_mask; /* debugging mask */ 132#define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */ 133#define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */ 134#define RTSX_DEBUG_TUNING 0x04 /* debug tuning */ 135#ifdef MMCCAM 136 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 137#endif /* MMCCAM */ 138 uint64_t rtsx_read_count; /* count of read operations */ 139 uint64_t rtsx_write_count; /* count of write operations */ 140 bool rtsx_discovery_mode; /* are we in discovery mode? */ 141 bool rtsx_tuning_mode; /* are we tuning */ 142 bool rtsx_double_clk; /* double clock freqency */ 143 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 144 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 145 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 146 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 147}; 148 149/* rtsx_flags values */ 150#define RTSX_F_DEFAULT 0x0000 151#define RTSX_F_CARD_PRESENT 0x0001 152#define RTSX_F_SDIO_SUPPORT 0x0002 153#define RTSX_F_VERSION_A 0x0004 154#define RTSX_F_VERSION_B 0x0008 155#define RTSX_F_VERSION_C 0x0010 156#define RTSX_F_VERSION_D 0x0020 157#define RTSX_F_8411B_QFN48 0x0040 158#define RTSX_F_REVERSE_SOCKET 0x0080 159 160#define RTSX_REALTEK 0x10ec 161#define RTSX_RTS5209 0x5209 162#define RTSX_RTS5227 0x5227 163#define RTSX_RTS5229 0x5229 164#define RTSX_RTS522A 0x522a 165#define RTSX_RTS525A 0x525a 166#define RTSX_RTS5249 0x5249 167#define RTSX_RTS5260 0x5260 168#define RTSX_RTL8402 0x5286 169#define RTSX_RTL8411 0x5289 170#define RTSX_RTL8411B 0x5287 171 172#define RTSX_VERSION "2.1g" 173 174static const struct rtsx_pciids { 175 uint16_t device_id; 176 const char *desc; 177} rtsx_ids[] = { 178 { RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe SD Card Reader" }, 179 { RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe SD Card Reader" }, 180 { RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe SD Card Reader" }, 181 { RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe SD Card Reader" }, 182 { RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe SD Card Reader" }, 183 { RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe SD Card Reader" }, 184 { RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe SD Card Reader" }, 185 { RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe SD Card Reader" }, 186 { RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe SD Card Reader" }, 187 { RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe SD Card Reader" }, 188}; 189 190/* See `kenv | grep smbios.system` */ 191static const struct rtsx_inversion_model { 192 char *maker; 193 char *family; 194 char *product; 195} rtsx_inversion_models[] = { 196 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 197 { "LENOVO", "ThinkPad X13 Gen 1", "20UF000QRT"}, 198 { NULL, NULL, NULL} 199}; 200 201static int rtsx_dma_alloc(struct rtsx_softc *sc); 202static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 203static void rtsx_dma_free(struct rtsx_softc *sc); 204static void rtsx_intr(void *arg); 205static void rtsx_handle_card_present(struct rtsx_softc *sc); 206static void rtsx_card_task(void *arg, int pending __unused); 207static bool rtsx_is_card_present(struct rtsx_softc *sc); 208static int rtsx_init(struct rtsx_softc *sc); 209static int rtsx_map_sd_drive(int index); 210static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 211static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 212static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc); 213static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 214static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 215static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 216static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 217static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 218static int rtsx_bus_power_off(struct rtsx_softc *sc); 219static int rtsx_bus_power_on(struct rtsx_softc *sc); 220static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 221static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 222static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 223static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 224static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 225#ifndef MMCCAM 226static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 227static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 228static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 229static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 230static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 231static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 232static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 233static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 234static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 235#endif /* !MMCCAM */ 236#if 0 /* For led */ 237static int rtsx_led_enable(struct rtsx_softc *sc); 238static int rtsx_led_disable(struct rtsx_softc *sc); 239#endif /* For led */ 240static uint8_t rtsx_response_type(uint16_t mmc_rsp); 241static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 242static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 243 uint8_t mask, uint8_t data); 244static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 245static void rtsx_send_cmd(struct rtsx_softc *sc); 246static void rtsx_ret_resp(struct rtsx_softc *sc); 247static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 248static void rtsx_stop_cmd(struct rtsx_softc *sc); 249static void rtsx_clear_error(struct rtsx_softc *sc); 250static void rtsx_req_done(struct rtsx_softc *sc); 251static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 252static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 253static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 254static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 255static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 256static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 257static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 258static void rtsx_write_ppbuf(struct rtsx_softc *sc); 259static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 260static void rtsx_xfer_begin(struct rtsx_softc *sc); 261static void rtsx_xfer_start(struct rtsx_softc *sc); 262static void rtsx_xfer_finish(struct rtsx_softc *sc); 263static void rtsx_timeout(void *arg); 264 265#ifdef MMCCAM 266static int rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 267static int rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 268static int rtsx_cam_request(device_t dev, union ccb *ccb); 269#endif /* MMCCAM */ 270 271static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 272static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 273 274static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 275static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 276static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 277#ifndef MMCCAM 278static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 279static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 280static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 281static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 282static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 283#endif /* !MMCCAM */ 284 285static int rtsx_probe(device_t dev); 286static int rtsx_attach(device_t dev); 287static int rtsx_detach(device_t dev); 288static int rtsx_shutdown(device_t dev); 289static int rtsx_suspend(device_t dev); 290static int rtsx_resume(device_t dev); 291 292#define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 293 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 294#define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 295#define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 296#define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 297 298#define RTSX_SDCLK_OFF 0 299#define RTSX_SDCLK_250KHZ 250000 300#define RTSX_SDCLK_400KHZ 400000 301#define RTSX_SDCLK_25MHZ 25000000 302#define RTSX_SDCLK_50MHZ 50000000 303#define RTSX_SDCLK_100MHZ 100000000 304#define RTSX_SDCLK_208MHZ 208000000 305 306#define RTSX_MIN_DIV_N 80 307#define RTSX_MAX_DIV_N 208 308 309#define RTSX_MAX_DATA_BLKLEN 512 310 311#define RTSX_DMA_ALIGN 4 312#define RTSX_HOSTCMD_MAX 256 313#define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 314#define RTSX_DMA_DATA_BUFSIZE maxphys 315 316#define ISSET(t, f) ((t) & (f)) 317 318#define READ4(sc, reg) \ 319 (bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg))) 320#define WRITE4(sc, reg, val) \ 321 (bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val))) 322 323#define RTSX_READ(sc, reg, val) \ 324 do { \ 325 int err = rtsx_read((sc), (reg), (val)); \ 326 if (err) \ 327 return (err); \ 328 } while (0) 329 330#define RTSX_WRITE(sc, reg, val) \ 331 do { \ 332 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 333 if (err) \ 334 return (err); \ 335 } while (0) 336#define RTSX_CLR(sc, reg, bits) \ 337 do { \ 338 int err = rtsx_write((sc), (reg), (bits), 0); \ 339 if (err) \ 340 return (err); \ 341 } while (0) 342 343#define RTSX_SET(sc, reg, bits) \ 344 do { \ 345 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 346 if (err) \ 347 return (err); \ 348 } while (0) 349 350#define RTSX_BITOP(sc, reg, mask, bits) \ 351 do { \ 352 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 353 if (err) \ 354 return (err); \ 355 } while (0) 356 357/* 358 * We use two DMA buffers: a command buffer and a data buffer. 359 * 360 * The command buffer contains a command queue for the host controller, 361 * which describes SD/MMC commands to run, and other parameters. The chip 362 * runs the command queue when a special bit in the RTSX_HCBAR register is 363 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 364 * Each command is encoded as a 4 byte sequence containing command number 365 * (read, write, or check a host controller register), a register address, 366 * and a data bit-mask and value. 367 * SD/MMC commands which do not transfer any data from/to the card only use 368 * the command buffer. 369 * 370 * The data buffer is used for transfer longer than 512. Data transfer is 371 * controlled via the RTSX_HDBAR register and completion is signalled by 372 * the RTSX_TRANS_OK_INT interrupt. 373 * 374 * The chip is unable to perform DMA above 4GB. 375 */ 376 377/* 378 * Main commands in the usual seqence used: 379 * 380 * CMD0 Go idle state 381 * CMD8 Send interface condition 382 * CMD55 Application Command for next ACMD 383 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 384 * CMD2 Send Card Identification (CID) Register 385 * CMD3 Send relative address 386 * CMD9 Send Card Specific Data (CSD) 387 * CMD13 Send status (32 bits - bit 25: card password protected) 388 * CMD7 Select card (before Get card SCR) 389 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 390 * CMD6 SD switch function 391 * ACMD13 Send SD status (512 bits) 392 * ACMD42 Set/Clear card detect 393 * ACMD6 Set bus width 394 * CMD19 Send tuning block 395 * CMD12 Stop transmission 396 * 397 * CMD17 Read single block (<=512) 398 * CMD18 Read multiple blocks (>512) 399 * CMD24 Write single block (<=512) 400 * CMD25 Write multiple blocks (>512) 401 * 402 * CMD52 IO R/W direct 403 * CMD5 Send Operation Conditions 404 */ 405 406static int 407rtsx_dma_alloc(struct rtsx_softc *sc) 408{ 409 int error = 0; 410 411 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 412 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 413 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 414 BUS_SPACE_MAXADDR, /* highaddr */ 415 NULL, NULL, /* filter, filterarg */ 416 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 417 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 418 0, /* flags */ 419 NULL, NULL, /* lockfunc, lockarg */ 420 &sc->rtsx_cmd_dma_tag); 421 if (error) { 422 device_printf(sc->rtsx_dev, 423 "Can't create cmd parent DMA tag\n"); 424 return (error); 425 } 426 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 427 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 428 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 429 &sc->rtsx_cmd_dmamap); /* DMA map */ 430 if (error) { 431 device_printf(sc->rtsx_dev, 432 "Can't create DMA map for command transfer\n"); 433 goto destroy_cmd_dma_tag; 434 435 } 436 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 437 sc->rtsx_cmd_dmamap, /* DMA map */ 438 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 439 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 440 rtsx_dmamap_cb, /* callback */ 441 &sc->rtsx_cmd_buffer, /* first arg of callback */ 442 0); /* flags */ 443 if (error || sc->rtsx_cmd_buffer == 0) { 444 device_printf(sc->rtsx_dev, 445 "Can't load DMA memory for command transfer\n"); 446 error = (error) ? error : EFAULT; 447 goto destroy_cmd_dmamem_alloc; 448 } 449 450 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 451 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 452 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 453 BUS_SPACE_MAXADDR, /* highaddr */ 454 NULL, NULL, /* filter, filterarg */ 455 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 456 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 457 0, /* flags */ 458 NULL, NULL, /* lockfunc, lockarg */ 459 &sc->rtsx_data_dma_tag); 460 if (error) { 461 device_printf(sc->rtsx_dev, 462 "Can't create data parent DMA tag\n"); 463 goto destroy_cmd_dmamap_load; 464 } 465 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 466 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 467 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 468 &sc->rtsx_data_dmamap); /* DMA map */ 469 if (error) { 470 device_printf(sc->rtsx_dev, 471 "Can't create DMA map for data transfer\n"); 472 goto destroy_data_dma_tag; 473 } 474 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 475 sc->rtsx_data_dmamap, /* DMA map */ 476 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 477 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 478 rtsx_dmamap_cb, /* callback */ 479 &sc->rtsx_data_buffer, /* first arg of callback */ 480 0); /* flags */ 481 if (error || sc->rtsx_data_buffer == 0) { 482 device_printf(sc->rtsx_dev, 483 "Can't load DMA memory for data transfer\n"); 484 error = (error) ? error : EFAULT; 485 goto destroy_data_dmamem_alloc; 486 } 487 return (error); 488 489 destroy_data_dmamem_alloc: 490 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 491 destroy_data_dma_tag: 492 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 493 destroy_cmd_dmamap_load: 494 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 495 destroy_cmd_dmamem_alloc: 496 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 497 destroy_cmd_dma_tag: 498 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 499 500 return (error); 501} 502 503static void 504rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 505{ 506 if (error) { 507 printf("rtsx_dmamap_cb: error %d\n", error); 508 return; 509 } 510 *(bus_addr_t *)arg = segs[0].ds_addr; 511} 512 513static void 514rtsx_dma_free(struct rtsx_softc *sc) 515{ 516 if (sc->rtsx_cmd_dma_tag != NULL) { 517 if (sc->rtsx_cmd_dmamap != NULL) 518 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 519 sc->rtsx_cmd_dmamap); 520 if (sc->rtsx_cmd_dmamem != NULL) 521 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 522 sc->rtsx_cmd_dmamem, 523 sc->rtsx_cmd_dmamap); 524 sc->rtsx_cmd_dmamap = NULL; 525 sc->rtsx_cmd_dmamem = NULL; 526 sc->rtsx_cmd_buffer = 0; 527 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 528 sc->rtsx_cmd_dma_tag = NULL; 529 } 530 if (sc->rtsx_data_dma_tag != NULL) { 531 if (sc->rtsx_data_dmamap != NULL) 532 bus_dmamap_unload(sc->rtsx_data_dma_tag, 533 sc->rtsx_data_dmamap); 534 if (sc->rtsx_data_dmamem != NULL) 535 bus_dmamem_free(sc->rtsx_data_dma_tag, 536 sc->rtsx_data_dmamem, 537 sc->rtsx_data_dmamap); 538 sc->rtsx_data_dmamap = NULL; 539 sc->rtsx_data_dmamem = NULL; 540 sc->rtsx_data_buffer = 0; 541 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 542 sc->rtsx_data_dma_tag = NULL; 543 } 544} 545 546static void 547rtsx_intr(void *arg) 548{ 549 struct rtsx_softc *sc = arg; 550 uint32_t enabled; 551 uint32_t status; 552 553 RTSX_LOCK(sc); 554 555 enabled = sc->rtsx_intr_enabled; 556 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 557 sc->rtsx_intr_status = status; 558 559 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 560 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 561 562 /* Ack interrupts. */ 563 WRITE4(sc, RTSX_BIPR, status); 564 565 if (((enabled & status) == 0) || status == 0xffffffff) { 566 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 567 RTSX_UNLOCK(sc); 568 return; 569 } 570 571 /* Detect write protect. */ 572 if (status & RTSX_SD_WRITE_PROTECT) 573 sc->rtsx_read_only = 1; 574 else 575 sc->rtsx_read_only = 0; 576 577 /* Start task to handle SD card status change (from dwmmc.c). */ 578 if (status & RTSX_SD_INT) { 579 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 580 rtsx_handle_card_present(sc); 581 } 582 583 if (sc->rtsx_req == NULL) { 584 RTSX_UNLOCK(sc); 585 return; 586 } 587 588 if (status & RTSX_TRANS_OK_INT) { 589 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 590 if (sc->rtsx_intr_trans_ok != NULL) 591 sc->rtsx_intr_trans_ok(sc); 592 } else if (status & RTSX_TRANS_FAIL_INT) { 593 uint8_t stat1; 594 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 595 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 596 (stat1 & RTSX_SD_CRC_ERR)) { 597 device_printf(sc->rtsx_dev, "CRC error\n"); 598 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 599 } 600 if (!sc->rtsx_tuning_mode) 601 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 602 rtsx_stop_cmd(sc); 603 if (sc->rtsx_intr_trans_ko != NULL) 604 sc->rtsx_intr_trans_ko(sc); 605 } 606 607 RTSX_UNLOCK(sc); 608} 609 610/* 611 * Function called from the IRQ handler (from dwmmc.c). 612 */ 613static void 614rtsx_handle_card_present(struct rtsx_softc *sc) 615{ 616 bool was_present; 617 bool is_present; 618 619#ifdef MMCCAM 620 was_present = sc->rtsx_cam_status; 621#else /* !MMCCAM */ 622 was_present = sc->rtsx_mmc_dev != NULL; 623#endif /* MMCCAM */ 624 is_present = rtsx_is_card_present(sc); 625 if (is_present) 626 device_printf(sc->rtsx_dev, "Card present\n"); 627 else 628 device_printf(sc->rtsx_dev, "Card absent\n"); 629 630 if (!was_present && is_present) { 631 /* 632 * The delay is to debounce the card insert 633 * (sometimes the card detect pin stabilizes 634 * before the other pins have made good contact). 635 */ 636 taskqueue_enqueue_timeout(taskqueue_swi_giant, 637 &sc->rtsx_card_insert_task, -hz); 638 } else if (was_present && !is_present) { 639 taskqueue_enqueue(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 640 } 641} 642 643/* 644 * This function is called at startup. 645 */ 646static void 647rtsx_card_task(void *arg, int pending __unused) 648{ 649 struct rtsx_softc *sc = arg; 650 651 if (rtsx_is_card_present(sc)) { 652 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 653 /* Card is present, attach if necessary. */ 654#ifdef MMCCAM 655 if (sc->rtsx_cam_status == 0) { 656#else /* !MMCCAM */ 657 if (sc->rtsx_mmc_dev == NULL) { 658#endif /* MMCCAM */ 659 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 660 device_printf(sc->rtsx_dev, "Card inserted\n"); 661 662 sc->rtsx_read_count = sc->rtsx_write_count = 0; 663#ifdef MMCCAM 664 sc->rtsx_cam_status = 1; 665 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 666#else /* !MMCCAM */ 667 RTSX_LOCK(sc); 668 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", -1); 669 RTSX_UNLOCK(sc); 670 if (sc->rtsx_mmc_dev == NULL) { 671 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 672 } else { 673 device_set_ivars(sc->rtsx_mmc_dev, sc); 674 device_probe_and_attach(sc->rtsx_mmc_dev); 675 } 676#endif /* MMCCAM */ 677 } 678 } else { 679 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 680 /* Card isn't present, detach if necessary. */ 681#ifdef MMCCAM 682 if (sc->rtsx_cam_status != 0) { 683#else /* !MMCCAM */ 684 if (sc->rtsx_mmc_dev != NULL) { 685#endif /* MMCCAM */ 686 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 687 device_printf(sc->rtsx_dev, "Card removed\n"); 688 689 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 690 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 691 sc->rtsx_read_count, sc->rtsx_write_count); 692#ifdef MMCCAM 693 sc->rtsx_cam_status = 0; 694 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 695#else /* !MMCCAM */ 696 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 697 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 698 sc->rtsx_mmc_dev = NULL; 699#endif /* MMCCAM */ 700 } 701 } 702} 703 704static bool 705rtsx_is_card_present(struct rtsx_softc *sc) 706{ 707 uint32_t status; 708 709 status = READ4(sc, RTSX_BIPR); 710 if (sc->rtsx_inversion == 0) 711 return (status & RTSX_SD_EXIST); 712 else 713 return !(status & RTSX_SD_EXIST); 714} 715 716static int 717rtsx_init(struct rtsx_softc *sc) 718{ 719 uint8_t version; 720 uint8_t val; 721 int error; 722 723 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 724 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 725 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 726 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 727 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 728 729 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 730 if (sc->rtsx_device_id == RTSX_RTS5209) 731 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 732 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 733 734 /* 735 * Check IC version. 736 */ 737 switch (sc->rtsx_device_id) { 738 case RTSX_RTS5229: 739 /* Read IC version from dummy register. */ 740 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 741 if ((version & 0x0F) == RTSX_IC_VERSION_C) 742 sc->rtsx_flags |= RTSX_F_VERSION_C; 743 break; 744 case RTSX_RTS522A: 745 /* Read IC version from dummy register. */ 746 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 747 if ((version & 0x0F) == RTSX_IC_VERSION_A) 748 sc->rtsx_flags |= RTSX_F_VERSION_A; 749 break; 750 case RTSX_RTS525A: 751 /* Read IC version from dummy register. */ 752 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 753 if ((version & 0x0F) == RTSX_IC_VERSION_A) 754 sc->rtsx_flags |= RTSX_F_VERSION_A; 755 break; 756 case RTSX_RTL8411B: 757 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 758 if (version & RTSX_RTL8411B_QFN48) 759 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 760 break; 761 } 762 763 /* 764 * Fetch vendor settings. 765 */ 766 /* 767 * Normally OEMs will set vendor setting to the config space 768 * of Realtek card reader in BIOS stage. This statement reads 769 * the setting and configure the internal registers according 770 * to it, to improve card reader's compatibility condition. 771 */ 772 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 773 switch (sc->rtsx_device_id) { 774 uint32_t reg; 775 uint32_t reg1; 776 uint8_t reg3; 777 case RTSX_RTS5209: 778 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 779 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 780 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 781 if (!(reg & 0x80)) { 782 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 783 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 784 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 785 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 786 } 787 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 788 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 789 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 790 break; 791 case RTSX_RTS5227: 792 case RTSX_RTS522A: 793 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 794 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 795 if (!(reg & 0x1000000)) { 796 sc->rtsx_card_drive_sel &= 0x3F; 797 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 798 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 799 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 800 if (reg & 0x4000) 801 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 802 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 803 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 804 } 805 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 806 device_printf(sc->rtsx_dev, 807 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 808 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 809 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 810 break; 811 case RTSX_RTS5229: 812 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 813 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 814 if (!(reg & 0x1000000)) { 815 sc->rtsx_card_drive_sel &= 0x3F; 816 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 817 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 818 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 819 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 820 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 821 } 822 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 823 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 824 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 825 break; 826 case RTSX_RTS525A: 827 case RTSX_RTS5249: 828 case RTSX_RTS5260: 829 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 830 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 831 if ((reg & 0x1000000)) { 832 sc->rtsx_card_drive_sel &= 0x3F; 833 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 834 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 835 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 836 if (reg & 0x4000) 837 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 838 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 839 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 840 } 841 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 842 device_printf(sc->rtsx_dev, 843 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 844 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 845 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 846 break; 847 case RTSX_RTL8402: 848 case RTSX_RTL8411: 849 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 850 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 851 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 852 if (reg1 & 0x1000000) { 853 sc->rtsx_card_drive_sel &= 0x3F; 854 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 855 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 856 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 857 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 858 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 859 } 860 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 861 device_printf(sc->rtsx_dev, 862 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 863 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 864 break; 865 case RTSX_RTL8411B: 866 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 867 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 868 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 869 if (!(reg & 0x1000000)) { 870 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 871 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 872 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 873 } 874 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 875 device_printf(sc->rtsx_dev, 876 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 877 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 878 break; 879 } 880 881 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 882 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 883 884 /* Enable interrupts. */ 885 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN; 886 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 887 888 /* Power on SSC clock. */ 889 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 890 /* Wait SSC power stable. */ 891 DELAY(200); 892 893 /* Disable ASPM */ 894 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 895 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 896 897 /* 898 * Optimize phy. 899 */ 900 switch (sc->rtsx_device_id) { 901 case RTSX_RTS5209: 902 /* Some magic numbers from Linux driver. */ 903 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 904 return (error); 905 break; 906 case RTSX_RTS5227: 907 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 908 909 /* Optimize RX sensitivity. */ 910 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 911 return (error); 912 break; 913 case RTSX_RTS5229: 914 /* Optimize RX sensitivity. */ 915 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 916 return (error); 917 break; 918 case RTSX_RTS522A: 919 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 920 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 921 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 922 return (error); 923 } 924 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 925 return (error); 926 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 927 return (error); 928 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 929 return (error); 930 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 931 return (error); 932 break; 933 case RTSX_RTS525A: 934 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 935 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 936 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 937 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 938 return (error); 939 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 940 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 941 RTSX__PHY_CMU_DEBUG_EN))) 942 return (error); 943 if (sc->rtsx_flags & RTSX_F_VERSION_A) 944 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 945 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 946 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 947 return (error); 948 break; 949 case RTSX_RTS5249: 950 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 951 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 952 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 953 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 954 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 955 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 956 RTSX_PHY_REV_STOP_CLKWR))) 957 return (error); 958 DELAY(1000); 959 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 960 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 961 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 962 return (error); 963 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 964 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 965 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 966 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 967 return (error); 968 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 969 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 970 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 971 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 972 return (error); 973 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 974 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 975 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 976 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 977 RTSX_PHY_FLD4_BER_CHK_EN))) 978 return (error); 979 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 980 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 981 return (error); 982 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 983 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 984 return (error); 985 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 986 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 987 RTSX_PHY_FLD3_RXDELINK))) 988 return (error); 989 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 990 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 991 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 992 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 993 return (error); 994 break; 995 } 996 997 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 998 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 999 1000 /* Disable sleep mode. */ 1001 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1002 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1003 1004 /* Disable card clock. */ 1005 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1006 1007 /* Reset delink mode. */ 1008 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1009 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1010 1011 /* Card driving select. */ 1012 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1013 1014 /* Enable SSC clock. */ 1015 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1016 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1017 1018 /* Disable cd_pwr_save. */ 1019 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1020 1021 /* Clear Link Ready Interrupt. */ 1022 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1023 1024 /* Enlarge the estimation window of PERST# glitch 1025 * to reduce the chance of invalid card interrupt. */ 1026 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1027 1028 /* Set RC oscillator to 400K. */ 1029 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1030 1031 /* Enable interrupt write-clear (default is read-clear). */ 1032 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1033 1034 switch (sc->rtsx_device_id) { 1035 case RTSX_RTS525A: 1036 case RTSX_RTS5260: 1037 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1038 break; 1039 } 1040 1041 /* OC power down. */ 1042 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1043 1044 /* Enable clk_request_n to enable clock power management */ 1045 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1046 1047 /* Enter L1 when host tx idle */ 1048 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1049 1050 /* 1051 * Specific extra init. 1052 */ 1053 switch (sc->rtsx_device_id) { 1054 uint16_t cap; 1055 case RTSX_RTS5209: 1056 /* Turn off LED. */ 1057 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1058 /* Reset ASPM state to default value. */ 1059 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1060 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1061 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1062 /* Configure GPIO as output. */ 1063 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1064 /* Configure driving. */ 1065 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1066 break; 1067 case RTSX_RTS5227: 1068 /* Configure GPIO as output. */ 1069 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1070 /* Reset ASPM state to default value. */ 1071 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1072 /* Switch LDO3318 source from DV33 to 3V3. */ 1073 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1074 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1075 /* Set default OLT blink period. */ 1076 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1077 /* Configure LTR. */ 1078 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1079 if (cap & PCIEM_CTL2_LTR_ENABLE) 1080 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1081 /* Configure OBFF. */ 1082 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1083 /* Configure driving. */ 1084 if ((error = rtsx_rts5227_fill_driving(sc))) 1085 return (error); 1086 /* Configure force_clock_req. */ 1087 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1088 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1089 else 1090 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1091 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1092 /*!!! Added for reboot after Windows. */ 1093 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1094 break; 1095 case RTSX_RTS5229: 1096 /* Configure GPIO as output. */ 1097 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1098 /* Reset ASPM state to default value. */ 1099 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1100//!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1101 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1102 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1103 /* Switch LDO3318 source from DV33 to card_3v3. */ 1104 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1105 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1106 /* Set default OLT blink period. */ 1107 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1108 /* Configure driving. */ 1109 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1110 break; 1111 case RTSX_RTS522A: 1112 /* Add specific init from RTS5227. */ 1113 /* Configure GPIO as output. */ 1114 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1115 /* Reset ASPM state to default value. */ 1116 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1117 /* Switch LDO3318 source from DV33 to 3V3. */ 1118 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1119 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1120 /* Set default OLT blink period. */ 1121 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1122 /* Configure LTR. */ 1123 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1124 if (cap & PCIEM_CTL2_LTR_ENABLE) 1125 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1126 /* Configure OBFF. */ 1127 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1128 /* Configure driving. */ 1129 if ((error = rtsx_rts5227_fill_driving(sc))) 1130 return (error); 1131 /* Configure force_clock_req. */ 1132 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1133 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1134 else 1135 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1136 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1137 1138 /* specific for RTS522A. */ 1139 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1140 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1141 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1142 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1143 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1144 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1145 break; 1146 case RTSX_RTS525A: 1147 /* Add specific init from RTS5249. */ 1148 /* Rest L1SUB Config. */ 1149 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1150 /* Configure GPIO as output. */ 1151 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1152 /* Reset ASPM state to default value. */ 1153 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1154 /* Switch LDO3318 source from DV33 to 3V3. */ 1155 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1156 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1157 /* Set default OLT blink period. */ 1158 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1159 /* Configure driving. */ 1160 if ((error = rtsx_rts5249_fill_driving(sc))) 1161 return (error); 1162 /* Configure force_clock_req. */ 1163 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1164 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1165 else 1166 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1167 1168 /* Specifc for RTS525A. */ 1169 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1170 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1171 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1172 RTSX_BITOP(sc, RTSX_RREF_CFG, 1173 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1174 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1175 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1176 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1177 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1178 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1179 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1180 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1181 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1182 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1183 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1184 } 1185 break; 1186 case RTSX_RTS5249: 1187 /* Rest L1SUB Config. */ 1188 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1189 /* Configure GPIO as output. */ 1190 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1191 /* Reset ASPM state to default value. */ 1192 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1193 /* Switch LDO3318 source from DV33 to 3V3. */ 1194 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1195 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1196 /* Set default OLT blink period. */ 1197 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1198 /* Configure driving. */ 1199 if ((error = rtsx_rts5249_fill_driving(sc))) 1200 return (error); 1201 /* Configure force_clock_req. */ 1202 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1203 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1204 else 1205 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1206 break; 1207 case RTSX_RTS5260: 1208 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1209 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1210 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D); 1211 /* Force no MDIO */ 1212 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE); 1213 /* Modify SDVCC Tune Default Parameters! */ 1214 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1215 1216 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1217 1218 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE); 1219 /* Rest L1SUB Config */ 1220 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF); 1221 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN); 1222 RTSX_WRITE(sc, RTSX_PWD_SUSPEND_EN, 0xFF); 1223 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN); 1224 RTSX_BITOP(sc, RTSX_REG_VREF, RTSX_PWD_SUSPND_EN, RTSX_PWD_SUSPND_EN); 1225 RTSX_BITOP(sc, RTSX_RBCTL, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE); 1226 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1227 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1228 else 1229 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1230 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE); 1231 1232 RTSX_CLR(sc, RTSX_RTS5260_DVCC_CTRL, RTSX_RTS5260_DVCC_OCP_EN | RTSX_RTS5260_DVCC_OCP_CL_EN); 1233 1234 /* CLKREQ# PIN will be forced to drive low. */ 1235 RTSX_BITOP(sc, RTSX_PETXCFG, RTSX_FORCE_CLKREQ_DELINK_MASK, RTSX_FORCE_CLKREQ_LOW); 1236 1237 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1238 break; 1239 case RTSX_RTL8402: 1240 case RTSX_RTL8411: 1241 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1242 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1243 RTSX_CD_ENABLE); 1244 break; 1245 case RTSX_RTL8411B: 1246 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1247 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1248 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1249 /* Enable SD interrupt. */ 1250 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1251 RTSX_CD_ENABLE); 1252 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1253 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1254 break; 1255 } 1256 1257 /*!!! Added for reboot after Windows. */ 1258 rtsx_bus_power_off(sc); 1259 rtsx_set_sd_timing(sc, bus_timing_normal); 1260 rtsx_set_sd_clock(sc, 0); 1261 /*!!! Added for reboot after Windows. */ 1262 1263 return (0); 1264} 1265 1266static int 1267rtsx_map_sd_drive(int index) 1268{ 1269 uint8_t sd_drive[4] = 1270 { 1271 0x01, /* Type D */ 1272 0x02, /* Type C */ 1273 0x05, /* Type A */ 1274 0x03 /* Type B */ 1275 }; 1276 return (sd_drive[index]); 1277} 1278 1279/* For voltage 3v3. */ 1280static int 1281rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1282{ 1283 u_char driving_3v3[4][3] = { 1284 {0x13, 0x13, 0x13}, 1285 {0x96, 0x96, 0x96}, 1286 {0x7F, 0x7F, 0x7F}, 1287 {0x96, 0x96, 0x96}, 1288 }; 1289 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1290 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1291 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1292 1293 return (0); 1294} 1295 1296/* For voltage 3v3. */ 1297static int 1298rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1299{ 1300 u_char driving_3v3[4][3] = { 1301 {0x11, 0x11, 0x18}, 1302 {0x55, 0x55, 0x5C}, 1303 {0xFF, 0xFF, 0xFF}, 1304 {0x96, 0x96, 0x96}, 1305 }; 1306 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1307 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1308 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1309 1310 return (0); 1311} 1312 1313static int 1314rtsx_rts5260_fill_driving(struct rtsx_softc *sc) 1315{ 1316 u_char driving_3v3[4][3] = { 1317 {0x11, 0x11, 0x11}, 1318 {0x22, 0x22, 0x22}, 1319 {0x55, 0x55, 0x55}, 1320 {0x33, 0x33, 0x33}, 1321 }; 1322 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1323 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1324 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1325 1326 return (0); 1327} 1328 1329static int 1330rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1331{ 1332 int tries = 1024; 1333 uint32_t arg; 1334 uint32_t reg; 1335 1336 arg = RTSX_HAIMR_BUSY | (uint32_t)((addr & 0x3FFF) << 16); 1337 WRITE4(sc, RTSX_HAIMR, arg); 1338 1339 while (tries--) { 1340 reg = READ4(sc, RTSX_HAIMR); 1341 if (!(reg & RTSX_HAIMR_BUSY)) 1342 break; 1343 } 1344 *val = (reg & 0xff); 1345 1346 if (tries > 0) { 1347 return (0); 1348 } else { 1349 device_printf(sc->rtsx_dev, "rtsx_read(0x%x) timeout\n", arg); 1350 return (ETIMEDOUT); 1351 } 1352} 1353 1354static int 1355rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1356{ 1357 int tries = 1024; 1358 uint8_t data0, data1, data2, data3, rwctl; 1359 1360 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1361 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1362 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1363 1364 while (tries--) { 1365 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1366 if (!(rwctl & RTSX_CFG_BUSY)) 1367 break; 1368 } 1369 1370 if (tries == 0) 1371 return (ETIMEDOUT); 1372 1373 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1374 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1375 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1376 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1377 1378 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1379 1380 return (0); 1381} 1382 1383static int 1384rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1385{ 1386 int tries = 1024; 1387 uint32_t arg; 1388 uint32_t reg; 1389 1390 arg = RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1391 (uint32_t)(((addr & 0x3FFF) << 16) | 1392 (mask << 8) | val); 1393 WRITE4(sc, RTSX_HAIMR, arg); 1394 1395 while (tries--) { 1396 reg = READ4(sc, RTSX_HAIMR); 1397 if (!(reg & RTSX_HAIMR_BUSY)) { 1398 if (val != (reg & 0xff)) { 1399 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg); 1400 return (EIO); 1401 } 1402 return (0); 1403 } 1404 } 1405 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) timeout\n", arg); 1406 1407 return (ETIMEDOUT); 1408} 1409 1410static int 1411rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1412{ 1413 int tries = 100000; 1414 uint8_t data0, data1, rwctl; 1415 1416 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1417 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1418 1419 while (tries--) { 1420 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1421 if (!(rwctl & RTSX_PHY_BUSY)) 1422 break; 1423 } 1424 if (tries == 0) 1425 return (ETIMEDOUT); 1426 1427 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1428 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1429 *val = data1 << 8 | data0; 1430 1431 return (0); 1432} 1433 1434static int 1435rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1436{ 1437 int tries = 100000; 1438 uint8_t rwctl; 1439 1440 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1441 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1442 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1443 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1444 1445 while (tries--) { 1446 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1447 if (!(rwctl & RTSX_PHY_BUSY)) 1448 break; 1449 } 1450 1451 return ((tries == 0) ? ETIMEDOUT : 0); 1452} 1453 1454/* 1455 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1456 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1457 * it is a mask of *enabled* gates. 1458 */ 1459static int 1460rtsx_bus_power_off(struct rtsx_softc *sc) 1461{ 1462 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1463 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1464 1465 /* Disable SD clock. */ 1466 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1467 1468 /* Disable SD output. */ 1469 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1470 1471 /* Turn off power. */ 1472 switch (sc->rtsx_device_id) { 1473 case RTSX_RTS5209: 1474 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1475 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1476 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1477 break; 1478 case RTSX_RTS5227: 1479 case RTSX_RTS5229: 1480 case RTSX_RTS522A: 1481 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1482 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1483 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1484 break; 1485 case RTSX_RTS5260: 1486 rtsx_stop_cmd(sc); 1487 /* Switch vccq to 330 */ 1488 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1489 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 1490 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 1491 rtsx_rts5260_fill_driving(sc); 1492 1493 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF); 1494 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF); 1495 break; 1496 case RTSX_RTL8402: 1497 case RTSX_RTL8411: 1498 case RTSX_RTL8411B: 1499 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1500 RTSX_BPP_POWER_OFF); 1501 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1502 RTSX_BPP_LDO_SUSPEND); 1503 break; 1504 default: 1505 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1506 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1507 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1508 break; 1509 } 1510 1511 /* Disable pull control. */ 1512 switch (sc->rtsx_device_id) { 1513 case RTSX_RTS5209: 1514 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1515 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1516 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1517 break; 1518 case RTSX_RTS5227: 1519 case RTSX_RTS522A: 1520 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1521 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1522 break; 1523 case RTSX_RTS5229: 1524 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1525 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1526 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1527 else 1528 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1529 break; 1530 case RTSX_RTS525A: 1531 case RTSX_RTS5249: 1532 case RTSX_RTS5260: 1533 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1534 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1535 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1536 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1537 break; 1538 case RTSX_RTL8402: 1539 case RTSX_RTL8411: 1540 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1541 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1542 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1543 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1544 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1545 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1546 break; 1547 case RTSX_RTL8411B: 1548 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1549 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1550 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1551 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1552 } else { 1553 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1554 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1555 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1556 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1557 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1558 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1559 } 1560 break; 1561 } 1562 1563 return (0); 1564} 1565 1566static int 1567rtsx_bus_power_on(struct rtsx_softc *sc) 1568{ 1569 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1570 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1571 1572 /* Select SD card. */ 1573 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1574 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1575 1576 /* Enable SD clock. */ 1577 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1578 1579 /* Enable pull control. */ 1580 switch (sc->rtsx_device_id) { 1581 case RTSX_RTS5209: 1582 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1583 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1584 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1585 break; 1586 case RTSX_RTS5227: 1587 case RTSX_RTS522A: 1588 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1589 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1590 break; 1591 case RTSX_RTS5229: 1592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1593 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1594 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1595 else 1596 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1597 break; 1598 case RTSX_RTS525A: 1599 case RTSX_RTS5249: 1600 case RTSX_RTS5260: 1601 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1602 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1603 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1604 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1605 break; 1606 case RTSX_RTL8402: 1607 case RTSX_RTL8411: 1608 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1609 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1610 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1611 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1612 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1613 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1614 break; 1615 case RTSX_RTL8411B: 1616 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1617 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1618 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1619 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1620 } else { 1621 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1622 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1623 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1624 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1625 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1626 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1627 } 1628 break; 1629 } 1630 1631 /* 1632 * To avoid a current peak, enable card power in two phases 1633 * with a delay in between. 1634 */ 1635 switch (sc->rtsx_device_id) { 1636 case RTSX_RTS5209: 1637 /* Partial power. */ 1638 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1639 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1640 1641 DELAY(200); 1642 1643 /* Full power. */ 1644 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1645 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1646 break; 1647 case RTSX_RTS5227: 1648 case RTSX_RTS522A: 1649 /* Partial power. */ 1650 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1651 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1652 1653 DELAY(20000); 1654 1655 /* Full power. */ 1656 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1657 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1658 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1659 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1660 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1661 break; 1662 case RTSX_RTS5229: 1663 /* Partial power. */ 1664 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1665 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1666 1667 DELAY(200); 1668 1669 /* Full power. */ 1670 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1671 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1672 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1673 break; 1674 case RTSX_RTS525A: 1675 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1676 case RTSX_RTS5249: 1677 /* Partial power. */ 1678 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1679 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1680 1681 DELAY(5000); 1682 1683 /* Full power. */ 1684 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1685 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1686 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1687 break; 1688 case RTSX_RTS5260: 1689 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1690 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1691 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON); 1692 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON); 1693 1694 DELAY(20000); 1695 1696 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK | RTSX_SD_ASYNC_FIFO_NOT_RST, 1697 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1698 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CLK_LOW_FREQ); 1699 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1700 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1701 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1702 1703 /* Initialize SD_CFG1 register */ 1704 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE); 1705 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE); 1706 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff); 1707 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 1708 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 1709 /* Reset SD_CFG3 register */ 1710 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN); 1711 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG, 1712 RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1); 1713 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE); 1714 break; 1715 case RTSX_RTL8402: 1716 case RTSX_RTL8411: 1717 case RTSX_RTL8411B: 1718 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1719 RTSX_BPP_POWER_5_PERCENT_ON); 1720 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1721 RTSX_BPP_LDO_SUSPEND); 1722 DELAY(150); 1723 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1724 RTSX_BPP_POWER_10_PERCENT_ON); 1725 DELAY(150); 1726 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1727 RTSX_BPP_POWER_15_PERCENT_ON); 1728 DELAY(150); 1729 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1730 RTSX_BPP_POWER_ON); 1731 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1732 RTSX_BPP_LDO_ON); 1733 break; 1734 } 1735 1736 /* Enable SD card output. */ 1737 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1738 1739 DELAY(200); 1740 1741 return (0); 1742} 1743 1744/* 1745 * Set but width. 1746 */ 1747static int 1748rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1749{ 1750 uint32_t bus_width; 1751 1752 switch (width) { 1753 case bus_width_1: 1754 bus_width = RTSX_BUS_WIDTH_1; 1755 break; 1756 case bus_width_4: 1757 bus_width = RTSX_BUS_WIDTH_4; 1758 break; 1759 case bus_width_8: 1760 bus_width = RTSX_BUS_WIDTH_8; 1761 break; 1762 default: 1763 return (MMC_ERR_INVALID); 1764 } 1765 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1766 1767 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1768 char *busw[] = { 1769 "1 bit", 1770 "4 bits", 1771 "8 bits" 1772 }; 1773 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1774 } 1775 return (0); 1776} 1777 1778static int 1779rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1780{ 1781 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1782 timing = bus_timing_uhs_sdr50; 1783 sc->rtsx_ios_timing = timing; 1784 } 1785 1786 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1787 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1788 1789 switch (timing) { 1790 case bus_timing_uhs_sdr50: 1791 case bus_timing_uhs_sdr104: 1792 sc->rtsx_double_clk = false; 1793 sc->rtsx_vpclk = true; 1794 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1795 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1796 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1797 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1798 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1799 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1800 break; 1801 case bus_timing_hs: 1802 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1803 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1804 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1805 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1806 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1807 1808 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1809 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1810 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1811 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1812 break; 1813 default: 1814 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1815 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1816 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1817 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1818 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1819 1820 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1821 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1822 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1823 break; 1824 } 1825 1826 return (0); 1827} 1828 1829/* 1830 * Set or change SDCLK frequency or disable the SD clock. 1831 * Return zero on success. 1832 */ 1833static int 1834rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1835{ 1836 uint8_t clk; 1837 uint8_t clk_divider, n, div, mcu; 1838 int error = 0; 1839 1840 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1841 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1842 1843 if (freq == RTSX_SDCLK_OFF) { 1844 error = rtsx_stop_sd_clock(sc); 1845 return error; 1846 } 1847 1848 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1849 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1850 1851 if (sc->rtsx_discovery_mode) { 1852 /* We use 250k(around) here, in discovery stage. */ 1853 clk_divider = RTSX_CLK_DIVIDE_128; 1854 freq = 30000000; 1855 } else { 1856 clk_divider = RTSX_CLK_DIVIDE_0; 1857 } 1858 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1859 1860 freq /= 1000000; 1861 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1862 clk = freq; 1863 else 1864 clk = freq * 2; 1865 1866 switch (sc->rtsx_device_id) { 1867 case RTSX_RTL8402: 1868 case RTSX_RTL8411: 1869 case RTSX_RTL8411B: 1870 n = clk * 4 / 5 - 2; 1871 break; 1872 default: 1873 n = clk - 2; 1874 break; 1875 } 1876 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1877 return (MMC_ERR_INVALID); 1878 1879 mcu = 125 / clk + 3; 1880 if (mcu > 15) 1881 mcu = 15; 1882 1883 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1884 div = RTSX_CLK_DIV_1; 1885 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1886 switch (sc->rtsx_device_id) { 1887 case RTSX_RTL8402: 1888 case RTSX_RTL8411: 1889 case RTSX_RTL8411B: 1890 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1891 break; 1892 default: 1893 n = (n + 2) * 2 - 2; 1894 break; 1895 } 1896 div++; 1897 } 1898 1899 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1900 sc->rtsx_ssc_depth -= 1; 1901 1902 if (div > RTSX_CLK_DIV_1) { 1903 if (sc->rtsx_ssc_depth > (div - 1)) 1904 sc->rtsx_ssc_depth -= (div - 1); 1905 else 1906 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1907 } 1908 1909 /* Enable SD clock. */ 1910 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1911 1912 return (error); 1913} 1914 1915static int 1916rtsx_stop_sd_clock(struct rtsx_softc *sc) 1917{ 1918 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1919 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1920 1921 return (0); 1922} 1923 1924static int 1925rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1926{ 1927 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1928 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1929 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1930 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1931 clk, n, div, mcu); 1932 } 1933 1934 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1935 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1936 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1937 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1938 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1939 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1940 if (sc->rtsx_vpclk) { 1941 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1942 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1943 } 1944 1945 /* Wait SSC clock stable. */ 1946 DELAY(200); 1947 1948 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1949 1950 return (0); 1951} 1952 1953#ifndef MMCCAM 1954static void 1955rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1956{ 1957 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1958 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1959 1960 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1961 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1962 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1963 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1964 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1965 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1966} 1967 1968static void 1969rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1970{ 1971 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 1972 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1973 1974 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1975 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1976 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1977 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1978 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1979 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1980} 1981 1982static void 1983rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1984{ 1985 uint32_t raw_phase_map = 0; 1986 int i; 1987 int error; 1988 1989 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1990 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1991 if (error == 0) 1992 raw_phase_map |= 1 << i; 1993 } 1994 if (phase_map != NULL) 1995 *phase_map = raw_phase_map; 1996} 1997 1998static int 1999rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 2000{ 2001 struct mmc_request req = {}; 2002 struct mmc_command cmd = {}; 2003 int error = 0; 2004 2005 cmd.opcode = MMC_SEND_TUNING_BLOCK; 2006 cmd.arg = 0; 2007 req.cmd = &cmd; 2008 2009 RTSX_LOCK(sc); 2010 2011 sc->rtsx_req = &req; 2012 2013 rtsx_sd_change_rx_phase(sc, sample_point); 2014 2015 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 2016 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 2017 2018 rtsx_init_cmd(sc, &cmd); 2019 rtsx_set_cmd_data_len(sc, 1, 0x40); 2020 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2021 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2022 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2023 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2024 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 2025 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2026 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2027 2028 /* Set interrupt post processing */ 2029 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 2030 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 2031 2032 /* Run the command queue. */ 2033 rtsx_send_cmd(sc); 2034 2035 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 2036 2037 if (error) { 2038 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 2039 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 2040 rtsx_sd_wait_data_idle(sc); 2041 rtsx_clear_error(sc); 2042 } 2043 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 2044 2045 sc->rtsx_req = NULL; 2046 2047 RTSX_UNLOCK(sc); 2048 2049 return (error); 2050} 2051 2052static int 2053rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 2054{ 2055 int status; 2056 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 2057 2058 status = sc->rtsx_intr_status & mask; 2059 while (status == 0) { 2060 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 2061 cmd->error = MMC_ERR_TIMEOUT; 2062 return (MMC_ERR_TIMEOUT); 2063 } 2064 status = sc->rtsx_intr_status & mask; 2065 } 2066 return (cmd->error); 2067} 2068 2069static void 2070rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 2071{ 2072 wakeup(&sc->rtsx_intr_status); 2073} 2074 2075static void 2076rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 2077{ 2078 int i; 2079 uint8_t val; 2080 2081 for (i = 0; i < 100; i++) { 2082 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 2083 if (val & RTSX_SD_DATA_IDLE) 2084 return; 2085 DELAY(100); 2086 } 2087} 2088 2089static uint8_t 2090rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 2091{ 2092 int start = 0, len = 0; 2093 int start_final = 0, len_final = 0; 2094 uint8_t final_phase = 0xff; 2095 2096 while (start < RTSX_RX_PHASE_MAX) { 2097 len = rtsx_sd_get_rx_phase_len(phase_map, start); 2098 if (len_final < len) { 2099 start_final = start; 2100 len_final = len; 2101 } 2102 start += len ? len : 1; 2103 } 2104 2105 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2106 2107 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2108 device_printf(sc->rtsx_dev, 2109 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2110 phase_map, start_final, len_final, final_phase); 2111 2112 return final_phase; 2113} 2114 2115static int 2116rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2117{ 2118 int i; 2119 2120 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2121 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2122 return i; 2123 } 2124 return RTSX_RX_PHASE_MAX; 2125} 2126#endif /* !MMCCAM */ 2127 2128#if 0 /* For led */ 2129static int 2130rtsx_led_enable(struct rtsx_softc *sc) 2131{ 2132 switch (sc->rtsx_device_id) { 2133 case RTSX_RTS5209: 2134 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2135 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2136 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2137 break; 2138 case RTSX_RTL8411B: 2139 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2140 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2141 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2142 break; 2143 default: 2144 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2145 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2146 break; 2147 } 2148 2149 return (0); 2150} 2151 2152static int 2153rtsx_led_disable(struct rtsx_softc *sc) 2154{ 2155 switch (sc->rtsx_device_id) { 2156 case RTSX_RTS5209: 2157 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2158 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2159 break; 2160 case RTSX_RTL8411B: 2161 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2162 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2163 break; 2164 default: 2165 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2166 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2167 break; 2168 } 2169 2170 return (0); 2171} 2172#endif /* For led */ 2173 2174static uint8_t 2175rtsx_response_type(uint16_t mmc_rsp) 2176{ 2177 int i; 2178 struct rsp_type { 2179 uint16_t mmc_rsp; 2180 uint8_t rtsx_rsp; 2181 } rsp_types[] = { 2182 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2183 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2184 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2185 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2186 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2187 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2188 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2189 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2190 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2191 }; 2192 2193 for (i = 0; i < nitems(rsp_types); i++) { 2194 if (mmc_rsp == rsp_types[i].mmc_rsp) 2195 return (rsp_types[i].rtsx_rsp); 2196 } 2197 2198 return (0); 2199} 2200 2201/* 2202 * Init command buffer with SD command index and argument. 2203 */ 2204static void 2205rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2206{ 2207 sc->rtsx_cmd_index = 0; 2208 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2209 0xff, RTSX_SD_CMD_START | cmd->opcode); 2210 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2211 0xff, cmd->arg >> 24); 2212 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2213 0xff, cmd->arg >> 16); 2214 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2215 0xff, cmd->arg >> 8); 2216 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2217 0xff, cmd->arg); 2218} 2219 2220/* 2221 * Append a properly encoded host command to the host command buffer. 2222 */ 2223static void 2224rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2225 uint8_t mask, uint8_t data) 2226{ 2227 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2228 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2229 2230 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2231 cmd_buffer[sc->rtsx_cmd_index++] = 2232 htole32((uint32_t)(cmd & 0x3) << 30) | 2233 ((uint32_t)(reg & 0x3fff) << 16) | 2234 ((uint32_t)(mask) << 8) | 2235 ((uint32_t)data); 2236} 2237 2238/* 2239 * Queue commands to configure data transfer size. 2240 */ 2241static void 2242rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2243{ 2244 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2245 0xff, block_cnt & 0xff); 2246 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2247 0xff, block_cnt >> 8); 2248 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2249 0xff, byte_cnt & 0xff); 2250 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2251 0xff, byte_cnt >> 8); 2252} 2253 2254/* 2255 * Run the command queue. 2256 */ 2257static void 2258rtsx_send_cmd(struct rtsx_softc *sc) 2259{ 2260 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2261 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2262 2263 sc->rtsx_intr_status = 0; 2264 2265 /* Sync command DMA buffer. */ 2266 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2267 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2268 2269 /* Tell the chip where the command buffer is and run the commands. */ 2270 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2271 WRITE4(sc, RTSX_HCBCTLR, 2272 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2273} 2274 2275/* 2276 * Stop previous command. 2277 */ 2278static void 2279rtsx_stop_cmd(struct rtsx_softc *sc) 2280{ 2281 /* Stop command transfer. */ 2282 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2283 2284 /* Stop DMA transfer. */ 2285 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2286 2287 switch (sc->rtsx_device_id) { 2288 case RTSX_RTS5260: 2289 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0, 2290 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST, 2291 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST); 2292 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2293 break; 2294 default: 2295 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2296 2297 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2298 break; 2299 } 2300} 2301 2302/* 2303 * Clear error. 2304 */ 2305static void 2306rtsx_clear_error(struct rtsx_softc *sc) 2307{ 2308 /* Clear error. */ 2309 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2310 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2311} 2312 2313/* 2314 * Signal end of request to mmc/mmcsd. 2315 */ 2316static void 2317rtsx_req_done(struct rtsx_softc *sc) 2318{ 2319#ifdef MMCCAM 2320 union ccb *ccb; 2321#endif /* MMCCAM */ 2322 struct mmc_request *req; 2323 2324 req = sc->rtsx_req; 2325 if (req->cmd->error == MMC_ERR_NONE) { 2326 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2327 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2328 sc->rtsx_read_count++; 2329 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2330 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2331 sc->rtsx_write_count++; 2332 } else { 2333 rtsx_clear_error(sc); 2334 } 2335 callout_stop(&sc->rtsx_timeout_callout); 2336 sc->rtsx_req = NULL; 2337#ifdef MMCCAM 2338 ccb = sc->rtsx_ccb; 2339 sc->rtsx_ccb = NULL; 2340 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2341 xpt_done(ccb); 2342#else /* !MMCCAM */ 2343 req->done(req); 2344#endif /* MMCCAM */ 2345} 2346 2347/* 2348 * Send request. 2349 */ 2350static int 2351rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2352{ 2353 uint8_t rsp_type; 2354 uint16_t reg; 2355 2356 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2357 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2358 2359 /* Convert response type. */ 2360 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2361 if (rsp_type == 0) { 2362 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2363 cmd->error = MMC_ERR_INVALID; 2364 return (MMC_ERR_INVALID); 2365 } 2366 2367 rtsx_init_cmd(sc, cmd); 2368 2369 /* Queue command to set response type. */ 2370 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2371 2372 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2373 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2374 0x01, RTSX_PINGPONG_BUFFER); 2375 2376 /* Queue commands to perform SD transfer. */ 2377 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2378 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2379 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2380 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2381 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2382 2383 /* If needed queue commands to read back card status response. */ 2384 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2385 /* Read data from ping-pong buffer. */ 2386 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2387 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2388 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2389 /* Read data from SD_CMDx registers. */ 2390 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2391 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2392 } 2393 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2394 2395 /* Set transfer OK function. */ 2396 if (sc->rtsx_intr_trans_ok == NULL) 2397 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2398 2399 /* Run the command queue. */ 2400 rtsx_send_cmd(sc); 2401 2402 return (0); 2403} 2404 2405/* 2406 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2407 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2408 */ 2409static void 2410rtsx_ret_resp(struct rtsx_softc *sc) 2411{ 2412 struct mmc_command *cmd; 2413 2414 cmd = sc->rtsx_req->cmd; 2415 rtsx_set_resp(sc, cmd); 2416 rtsx_req_done(sc); 2417} 2418 2419/* 2420 * Set response of previous command. 2421 */ 2422static void 2423rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2424{ 2425 uint8_t rsp_type; 2426 2427 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2428 2429 /* Sync command DMA buffer. */ 2430 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2431 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2432 2433 /* Copy card response into mmc response buffer. */ 2434 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2435 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2436 2437 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) { 2438 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2439 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2440 } 2441 2442 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2443 /* First byte is CHECK_REG_CMD return value, skip it. */ 2444 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2445 int i; 2446 2447 /* 2448 * The controller offloads the last byte {CRC-7, end bit 1} 2449 * of response type R2. Assign dummy CRC, 0, and end bit to this 2450 * byte (ptr[16], goes into the LSB of resp[3] later). 2451 */ 2452 ptr[16] = 0x01; 2453 /* The second byte is the status of response, skip it. */ 2454 for (i = 0; i < 4; i++) 2455 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2456 } else { 2457 /* 2458 * First byte is CHECK_REG_CMD return value, second 2459 * one is the command op code -- we skip those. 2460 */ 2461 cmd->resp[0] = 2462 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2463 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2464 } 2465 2466 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2467 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2468 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2469 } 2470} 2471 2472/* 2473 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2474 */ 2475static int 2476rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2477{ 2478 int read; 2479 2480 if (cmd->data == NULL || cmd->data->len == 0) { 2481 cmd->error = MMC_ERR_INVALID; 2482 return (MMC_ERR_INVALID); 2483 } 2484 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2485 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2486 2487 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2488 2489 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2490 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2491 read ? "Read" : "Write", 2492 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2493 2494 if (cmd->data->len > 512) { 2495 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2496 (unsigned long)cmd->data->len); 2497 cmd->error = MMC_ERR_INVALID; 2498 return (MMC_ERR_INVALID); 2499 } 2500 2501 if (read) { 2502 if (sc->rtsx_discovery_mode) 2503 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2504 2505 rtsx_init_cmd(sc, cmd); 2506 2507 /* Queue commands to configure data transfer size. */ 2508 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2509 2510 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2511 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2512 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2513 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2514 2515 /* Use the ping-pong buffer (cmd buffer). */ 2516 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2517 0x01, RTSX_PINGPONG_BUFFER); 2518 2519 /* Queue commands to perform SD transfer. */ 2520 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2521 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2522 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2523 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2524 2525 /* Set transfer OK function. */ 2526 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2527 2528 /* Run the command queue. */ 2529 rtsx_send_cmd(sc); 2530 } else { 2531 /* Set transfer OK function. */ 2532 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2533 2534 /* Run the command queue. */ 2535 rtsx_send_req(sc, cmd); 2536 } 2537 2538 return (0); 2539} 2540 2541/* 2542 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2543 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2544 */ 2545static void 2546rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2547{ 2548 struct mmc_command *cmd; 2549 uint16_t reg = RTSX_PPBUF_BASE2; 2550 int len; 2551 int i; 2552 2553 cmd = sc->rtsx_req->cmd; 2554 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2555 2556 sc->rtsx_cmd_index = 0; 2557 for (i = 0; i < len; i++) { 2558 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2559 } 2560 2561 /* Set transfer OK function. */ 2562 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2563 2564 /* Run the command queue. */ 2565 rtsx_send_cmd(sc); 2566} 2567 2568/* 2569 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2570 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2571 */ 2572static void 2573rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2574{ 2575 struct mmc_command *cmd; 2576 uint8_t *ptr; 2577 int len; 2578 2579 cmd = sc->rtsx_req->cmd; 2580 ptr = cmd->data->data; 2581 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2582 2583 /* Sync command DMA buffer. */ 2584 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2585 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2586 2587 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2588 2589 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2590 2591 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2592 if (len > 0) { 2593 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2594 int i; 2595 2596 sc->rtsx_cmd_index = 0; 2597 for (i = 0; i < len; i++) { 2598 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2599 } 2600 2601 /* Set transfer OK function. */ 2602 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2603 2604 /* Run the command queue. */ 2605 rtsx_send_cmd(sc); 2606 } else { 2607 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) { 2608 uint8_t *ptr = cmd->data->data; 2609 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2610 ptr[0], ptr[1], ptr[2], ptr[3], 2611 ptr[4], ptr[5], ptr[6], ptr[7]); 2612 } 2613 2614 if (sc->rtsx_discovery_mode) 2615 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2616 2617 rtsx_req_done(sc); 2618 } 2619} 2620 2621/* 2622 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2623 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2624 */ 2625static void 2626rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2627{ 2628 struct mmc_command *cmd; 2629 uint8_t *ptr; 2630 int len; 2631 2632 cmd = sc->rtsx_req->cmd; 2633 ptr = cmd->data->data; 2634 ptr += RTSX_HOSTCMD_MAX; 2635 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2636 2637 /* Sync command DMA buffer. */ 2638 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2639 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2640 2641 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2642 2643 if (sc->rtsx_discovery_mode) 2644 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2645 2646 rtsx_req_done(sc); 2647} 2648 2649/* 2650 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2651 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2652 */ 2653static void 2654rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2655{ 2656 struct mmc_command *cmd; 2657 uint16_t reg = RTSX_PPBUF_BASE2; 2658 uint8_t *ptr; 2659 int len; 2660 int i; 2661 2662 cmd = sc->rtsx_req->cmd; 2663 ptr = cmd->data->data; 2664 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2665 2666 rtsx_set_resp(sc, cmd); 2667 2668 sc->rtsx_cmd_index = 0; 2669 for (i = 0; i < len; i++) { 2670 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2671 ptr++; 2672 } 2673 2674 /* Set transfer OK function. */ 2675 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2676 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2677 else 2678 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2679 2680 /* Run the command queue. */ 2681 rtsx_send_cmd(sc); 2682} 2683 2684/* 2685 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2686 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2687 */ 2688static void 2689rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2690{ 2691 struct mmc_command *cmd; 2692 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2693 uint8_t *ptr; 2694 int len; 2695 int i; 2696 2697 cmd = sc->rtsx_req->cmd; 2698 ptr = cmd->data->data; 2699 ptr += RTSX_HOSTCMD_MAX; 2700 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2701 2702 sc->rtsx_cmd_index = 0; 2703 for (i = 0; i < len; i++) { 2704 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2705 ptr++; 2706 } 2707 2708 /* Set transfer OK function. */ 2709 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2710 2711 /* Run the command queue. */ 2712 rtsx_send_cmd(sc); 2713} 2714 2715/* 2716 * Write the data previously given via the ping-pong buffer on the card. 2717 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2718 */ 2719static void 2720rtsx_write_ppbuf(struct rtsx_softc *sc) 2721{ 2722 struct mmc_command *cmd; 2723 2724 cmd = sc->rtsx_req->cmd; 2725 2726 sc->rtsx_cmd_index = 0; 2727 2728 /* Queue commands to configure data transfer size. */ 2729 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2730 2731 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2732 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2733 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2734 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2735 2736 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2737 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2738 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2739 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2740 2741 /* Set transfer OK function. */ 2742 sc->rtsx_intr_trans_ok = rtsx_req_done; 2743 2744 /* Run the command queue. */ 2745 rtsx_send_cmd(sc); 2746} 2747 2748/* 2749 * Use the data buffer for transfer > 512 bytes. 2750 */ 2751static int 2752rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2753{ 2754 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2755 2756 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2757 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2758 2759 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2760 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2761 read ? "Read" : "Write", 2762 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2763 2764 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2765 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %ld\n", 2766 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2767 cmd->error = MMC_ERR_INVALID; 2768 return (MMC_ERR_INVALID); 2769 } 2770 2771 if (!read) { 2772 /* Set transfer OK function. */ 2773 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2774 2775 /* Run the command queue. */ 2776 rtsx_send_req(sc, cmd); 2777 } else { 2778 rtsx_xfer_start(sc); 2779 } 2780 2781 return (0); 2782} 2783 2784/* 2785 * Get request response and start dma data transfer (write command). 2786 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2787 */ 2788static void 2789rtsx_xfer_begin(struct rtsx_softc *sc) 2790{ 2791 struct mmc_command *cmd; 2792 2793 cmd = sc->rtsx_req->cmd; 2794 2795 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2796 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2797 2798 rtsx_set_resp(sc, cmd); 2799 rtsx_xfer_start(sc); 2800} 2801 2802/* 2803 * Start dma data transfer. 2804 */ 2805static void 2806rtsx_xfer_start(struct rtsx_softc *sc) 2807{ 2808 struct mmc_command *cmd; 2809 int read; 2810 uint8_t cfg2; 2811 int dma_dir; 2812 int tmode; 2813 2814 cmd = sc->rtsx_req->cmd; 2815 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2816 2817 /* Configure DMA transfer mode parameters. */ 2818 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2819 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2820 else 2821 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2822 if (read) { 2823 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2824 /* 2825 * Use transfer mode AUTO_READ1, which assume we not 2826 * already send the read command and don't need to send 2827 * CMD 12 manually after read. 2828 */ 2829 tmode = RTSX_TM_AUTO_READ1; 2830 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2831 2832 rtsx_init_cmd(sc, cmd); 2833 } else { 2834 dma_dir = RTSX_DMA_DIR_TO_CARD; 2835 /* 2836 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2837 * sent the write command and gotten the response, and will 2838 * send CMD 12 manually after writing. 2839 */ 2840 tmode = RTSX_TM_AUTO_WRITE3; 2841 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2842 2843 sc->rtsx_cmd_index = 0; 2844 } 2845 2846 /* Queue commands to configure data transfer size. */ 2847 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2848 2849 /* Configure DMA controller. */ 2850 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2851 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2852 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2853 0xff, cmd->data->len >> 24); 2854 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2855 0xff, cmd->data->len >> 16); 2856 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2857 0xff, cmd->data->len >> 8); 2858 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2859 0xff, cmd->data->len); 2860 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2861 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2862 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2863 2864 /* Use the DMA ring buffer for commands which transfer data. */ 2865 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2866 0x01, RTSX_RING_BUFFER); 2867 2868 /* Queue command to set response type. */ 2869 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2870 2871 /* Queue commands to perform SD transfer. */ 2872 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2873 0xff, tmode | RTSX_SD_TRANSFER_START); 2874 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2875 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2876 2877 /* Run the command queue. */ 2878 rtsx_send_cmd(sc); 2879 2880 if (!read) 2881 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2882 2883 /* Sync data DMA buffer. */ 2884 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2885 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2886 2887 /* Set transfer OK function. */ 2888 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2889 2890 /* Tell the chip where the data buffer is and run the transfer. */ 2891 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2892 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2893 (cmd->data->len & 0x00ffffff)); 2894} 2895 2896/* 2897 * Finish dma data transfer. 2898 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2899 */ 2900static void 2901rtsx_xfer_finish(struct rtsx_softc *sc) 2902{ 2903 struct mmc_command *cmd; 2904 int read; 2905 2906 cmd = sc->rtsx_req->cmd; 2907 2908 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2909 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2910 2911 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2912 2913 /* Sync data DMA buffer. */ 2914 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2915 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2916 2917 if (read) { 2918 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2919 rtsx_req_done(sc); 2920 } else { 2921 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2922 /* and complete request. */ 2923 sc->rtsx_intr_trans_ok = NULL; 2924 rtsx_send_req(sc, sc->rtsx_req->stop); 2925 } 2926} 2927 2928/* 2929 * Manage request timeout. 2930 */ 2931static void 2932rtsx_timeout(void *arg) 2933{ 2934 struct rtsx_softc *sc; 2935 2936 sc = (struct rtsx_softc *)arg; 2937 if (sc->rtsx_req != NULL) { 2938 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2939 sc->rtsx_req->cmd->opcode); 2940 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2941 rtsx_stop_cmd(sc); 2942 rtsx_req_done(sc); 2943 } else { 2944 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2945 } 2946} 2947 2948#ifdef MMCCAM 2949static int 2950rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2951{ 2952 struct rtsx_softc *sc; 2953 2954 sc = device_get_softc(dev); 2955 2956 cts->host_ocr = sc->rtsx_host.host_ocr; 2957 cts->host_f_min = sc->rtsx_host.f_min; 2958 cts->host_f_max = sc->rtsx_host.f_max; 2959 cts->host_caps = sc->rtsx_host.caps; 2960 cts->host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2961 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2962 2963 return (0); 2964} 2965 2966/* 2967 * Apply settings and return status accordingly. 2968*/ 2969static int 2970rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2971{ 2972 struct rtsx_softc *sc; 2973 struct mmc_ios *ios; 2974 struct mmc_ios *new_ios; 2975 2976 sc = device_get_softc(dev); 2977 2978 ios = &sc->rtsx_host.ios; 2979 new_ios = &cts->ios; 2980 2981 /* Update only requested fields */ 2982 if (cts->ios_valid & MMC_CLK) { 2983 ios->clock = new_ios->clock; 2984 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2985 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2986 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock); 2987 } 2988 if (cts->ios_valid & MMC_VDD) { 2989 ios->vdd = new_ios->vdd; 2990 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2991 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd); 2992 } 2993 if (cts->ios_valid & MMC_CS) { 2994 ios->chip_select = new_ios->chip_select; 2995 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2996 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select); 2997 } 2998 if (cts->ios_valid & MMC_BW) { 2999 ios->bus_width = new_ios->bus_width; 3000 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3001 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3002 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width); 3003 } 3004 if (cts->ios_valid & MMC_PM) { 3005 ios->power_mode = new_ios->power_mode; 3006 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3007 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3008 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode); 3009 } 3010 if (cts->ios_valid & MMC_BT) { 3011 ios->timing = new_ios->timing; 3012 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3013 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3014 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing); 3015 } 3016 if (cts->ios_valid & MMC_BM) { 3017 ios->bus_mode = new_ios->bus_mode; 3018 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3019 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 3020 } 3021#if __FreeBSD_version >= 1300000 3022 if (cts->ios_valid & MMC_VCCQ) { 3023 ios->vccq = new_ios->vccq; 3024 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3025 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3026 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq); 3027 } 3028#endif /* __FreeBSD_version >= 1300000 */ 3029 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 3030 return (CAM_REQ_CMP); 3031 else 3032 return (CAM_REQ_CMP_ERR); 3033} 3034 3035/* 3036 * Build a request and run it. 3037 */ 3038static int 3039rtsx_cam_request(device_t dev, union ccb *ccb) 3040{ 3041 struct rtsx_softc *sc; 3042 3043 sc = device_get_softc(dev); 3044 3045 RTSX_LOCK(sc); 3046 if (sc->rtsx_ccb != NULL) { 3047 RTSX_UNLOCK(sc); 3048 return (CAM_BUSY); 3049 } 3050 sc->rtsx_ccb = ccb; 3051 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 3052 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 3053 RTSX_UNLOCK(sc); 3054 3055 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 3056 return (0); 3057} 3058#endif /* MMCCAM */ 3059 3060static int 3061rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 3062{ 3063 struct rtsx_softc *sc; 3064 3065 sc = device_get_softc(bus); 3066 switch (which) { 3067 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3068 *result = sc->rtsx_host.ios.bus_mode; 3069 break; 3070 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3071 *result = sc->rtsx_host.ios.bus_width; 3072 break; 3073 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3074 *result = sc->rtsx_host.ios.chip_select; 3075 break; 3076 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3077 *result = sc->rtsx_host.ios.clock; 3078 break; 3079 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3080 *result = sc->rtsx_host.f_min; 3081 break; 3082 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3083 *result = sc->rtsx_host.f_max; 3084 break; 3085 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3086 *result = sc->rtsx_host.host_ocr; 3087 break; 3088 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3089 *result = sc->rtsx_host.mode; 3090 break; 3091 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3092 *result = sc->rtsx_host.ocr; 3093 break; 3094 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3095 *result = sc->rtsx_host.ios.power_mode; 3096 break; 3097 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3098 *result = sc->rtsx_host.ios.vdd; 3099 break; 3100 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3101 *result = sc->rtsx_host.ios.vccq; 3102 break; 3103 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3104 *result = sc->rtsx_host.caps; 3105 break; 3106 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3107 *result = sc->rtsx_host.ios.timing; 3108 break; 3109 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3110 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 3111 break; 3112 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3113 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3114 default: 3115 return (EINVAL); 3116 } 3117 3118 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3119 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3120 which, *(int *)result, *(int *)result); 3121 3122 return (0); 3123} 3124 3125static int 3126rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3127{ 3128 struct rtsx_softc *sc; 3129 3130 sc = device_get_softc(bus); 3131 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3132 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3133 which, (int)value, (int)value); 3134 3135 switch (which) { 3136 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3137 sc->rtsx_host.ios.bus_mode = value; 3138 break; 3139 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3140 sc->rtsx_host.ios.bus_width = value; 3141 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3142 break; 3143 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3144 sc->rtsx_host.ios.chip_select = value; 3145 break; 3146 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3147 sc->rtsx_host.ios.clock = value; 3148 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3149 break; 3150 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3151 sc->rtsx_host.mode = value; 3152 break; 3153 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3154 sc->rtsx_host.ocr = value; 3155 break; 3156 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3157 sc->rtsx_host.ios.power_mode = value; 3158 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3159 break; 3160 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3161 sc->rtsx_host.ios.vdd = value; 3162 break; 3163 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3164 sc->rtsx_host.ios.vccq = value; 3165 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3166 break; 3167 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3168 sc->rtsx_host.ios.timing = value; 3169 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3170 break; 3171 /* These are read-only. */ 3172 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3173 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3174 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3175 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3176 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3177 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3178 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3179 default: 3180 return (EINVAL); 3181 } 3182 3183 return (0); 3184} 3185 3186static int 3187rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3188{ 3189 struct rtsx_softc *sc; 3190 struct mmc_ios *ios; 3191 int error; 3192 3193 sc = device_get_softc(bus); 3194 ios = &sc->rtsx_host.ios; 3195 3196 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3197 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3198 3199 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3200 if (sc->rtsx_ios_bus_width < 0) { 3201 sc->rtsx_ios_bus_width = ios->bus_width; 3202 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3203 return (error); 3204 } 3205 3206 /* if MMCBR_IVAR_POWER_MODE updated. */ 3207 if (sc->rtsx_ios_power_mode < 0) { 3208 sc->rtsx_ios_power_mode = ios->power_mode; 3209 switch (ios->power_mode) { 3210 case power_off: 3211 if ((error = rtsx_bus_power_off(sc))) 3212 return (error); 3213 break; 3214 case power_up: 3215 if ((error = rtsx_bus_power_on(sc))) 3216 return (error); 3217 break; 3218 case power_on: 3219 if ((error = rtsx_bus_power_on(sc))) 3220 return (error); 3221 break; 3222 } 3223 } 3224 3225 sc->rtsx_double_clk = true; 3226 sc->rtsx_vpclk = false; 3227 3228 /* if MMCBR_IVAR_TIMING updated. */ 3229 if (sc->rtsx_ios_timing < 0) { 3230 sc->rtsx_ios_timing = ios->timing; 3231 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3232 return (error); 3233 } 3234 3235 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3236 if (sc->rtsx_ios_clock < 0) { 3237 sc->rtsx_ios_clock = ios->clock; 3238 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3239 return (error); 3240 } 3241 3242 /* if MMCCAM and vccq updated */ 3243 if (sc->rtsx_ios_vccq < 0) { 3244 sc->rtsx_ios_vccq = ios->vccq; 3245 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3246 return (error); 3247 } 3248 3249 return (0); 3250} 3251 3252/* 3253 * Set output stage logic power voltage. 3254 */ 3255static int 3256rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3257{ 3258 struct rtsx_softc *sc; 3259 int vccq = 0; 3260 int error; 3261 3262 sc = device_get_softc(bus); 3263 3264 switch (sc->rtsx_host.ios.vccq) { 3265 case vccq_120: 3266 vccq = 120; 3267 break; 3268 case vccq_180: 3269 vccq = 180; 3270 break; 3271 case vccq_330: 3272 vccq = 330; 3273 break; 3274 }; 3275 /* It seems it is always vccq_330. */ 3276 if (vccq == 330) { 3277 switch (sc->rtsx_device_id) { 3278 uint16_t val; 3279 case RTSX_RTS5227: 3280 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3281 return (error); 3282 if ((error = rtsx_rts5227_fill_driving(sc))) 3283 return (error); 3284 break; 3285 case RTSX_RTS5209: 3286 case RTSX_RTS5229: 3287 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3288 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3289 return (error); 3290 break; 3291 case RTSX_RTS522A: 3292 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3293 return (error); 3294 if ((error = rtsx_rts5227_fill_driving(sc))) 3295 return (error); 3296 break; 3297 case RTSX_RTS525A: 3298 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3299 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3300 if ((error = rtsx_rts5249_fill_driving(sc))) 3301 return (error); 3302 break; 3303 case RTSX_RTS5249: 3304 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3305 return (error); 3306 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3307 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3308 return (error); 3309 if ((error = rtsx_rts5249_fill_driving(sc))) 3310 return (error); 3311 break; 3312 case RTSX_RTS5260: 3313 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 3314 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 3315 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 3316 if ((error = rtsx_rts5260_fill_driving(sc))) 3317 return (error); 3318 break; 3319 case RTSX_RTL8402: 3320 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3321 RTSX_BITOP(sc, RTSX_LDO_CTL, 3322 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3323 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3324 break; 3325 case RTSX_RTL8411: 3326 case RTSX_RTL8411B: 3327 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3328 RTSX_BITOP(sc, RTSX_LDO_CTL, 3329 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3330 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3331 break; 3332 } 3333 DELAY(300); 3334 } 3335 3336 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD)) 3337 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3338 3339 return (0); 3340} 3341 3342#ifndef MMCCAM 3343/* 3344 * Tune card if bus_timing_uhs_sdr50. 3345 */ 3346static int 3347rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3348{ 3349 struct rtsx_softc *sc; 3350 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3351 uint32_t phase_map; 3352 uint8_t final_phase; 3353 int i; 3354 3355 sc = device_get_softc(bus); 3356 3357 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3358 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3359 (hs400) ? "true" : "false"); 3360 3361 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3362 return (0); 3363 3364 sc->rtsx_tuning_mode = true; 3365 3366 switch (sc->rtsx_device_id) { 3367 case RTSX_RTS5209: 3368 case RTSX_RTS5227: 3369 rtsx_sd_change_tx_phase(sc, 27); 3370 break; 3371 case RTSX_RTS522A: 3372 rtsx_sd_change_tx_phase(sc, 20); 3373 break; 3374 case RTSX_RTS5229: 3375 rtsx_sd_change_tx_phase(sc, 27); 3376 break; 3377 case RTSX_RTS525A: 3378 case RTSX_RTS5249: 3379 rtsx_sd_change_tx_phase(sc, 29); 3380 break; 3381 case RTSX_RTL8402: 3382 case RTSX_RTL8411: 3383 case RTSX_RTL8411B: 3384 rtsx_sd_change_tx_phase(sc, 7); 3385 break; 3386 } 3387 3388 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3389 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3390 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3391 if (raw_phase_map[i] == 0) 3392 break; 3393 } 3394 3395 phase_map = 0xffffffff; 3396 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3397 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING)) 3398 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3399 i, raw_phase_map[i]); 3400 phase_map &= raw_phase_map[i]; 3401 } 3402 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3403 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3404 3405 if (phase_map) { 3406 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3407 if (final_phase != 0xff) { 3408 rtsx_sd_change_rx_phase(sc, final_phase); 3409 } 3410 } 3411 3412 sc->rtsx_tuning_mode = false; 3413 3414 return (0); 3415} 3416 3417static int 3418rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3419{ 3420 struct rtsx_softc *sc; 3421 3422 sc = device_get_softc(bus); 3423 3424 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3425 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3426 3427 return (0); 3428} 3429#endif /* !MMCCAM */ 3430 3431static int 3432rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3433{ 3434 struct rtsx_softc *sc; 3435 struct mmc_command *cmd; 3436 int timeout; 3437 int error; 3438 3439 sc = device_get_softc(bus); 3440 3441 RTSX_LOCK(sc); 3442 if (sc->rtsx_req != NULL) { 3443 RTSX_UNLOCK(sc); 3444 return (EBUSY); 3445 } 3446 sc->rtsx_req = req; 3447 cmd = req->cmd; 3448 cmd->error = error = MMC_ERR_NONE; 3449 sc->rtsx_intr_status = 0; 3450 sc->rtsx_intr_trans_ok = NULL; 3451 sc->rtsx_intr_trans_ko = rtsx_req_done; 3452 3453 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3454 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3455 cmd->opcode, cmd->arg, cmd->flags, 3456 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3457 cmd->data != NULL ? cmd->data->flags : 0); 3458 3459 /* Check if card present. */ 3460 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3461 cmd->error = error = MMC_ERR_FAILED; 3462 goto end; 3463 } 3464 3465 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3466 if (cmd->opcode == IO_SEND_OP_COND && 3467 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3468 cmd->error = error = MMC_ERR_INVALID; 3469 goto end; 3470 } 3471 3472 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3473 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3474 cmd->error = error = MMC_ERR_TIMEOUT; 3475 goto end; 3476 } 3477 3478 /* Select SD card. */ 3479 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3480 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3481 3482 if (cmd->data == NULL) { 3483 DELAY(200); 3484 timeout = sc->rtsx_timeout_cmd; 3485 error = rtsx_send_req(sc, cmd); 3486 } else if (cmd->data->len <= 512) { 3487 timeout = sc->rtsx_timeout_io; 3488 error = rtsx_xfer_short(sc, cmd); 3489 } else { 3490 timeout = sc->rtsx_timeout_io; 3491 error = rtsx_xfer(sc, cmd); 3492 } 3493 end: 3494 if (error == MMC_ERR_NONE) { 3495 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3496 } else { 3497 rtsx_req_done(sc); 3498 } 3499 RTSX_UNLOCK(sc); 3500 3501 return (error); 3502} 3503 3504#ifndef MMCCAM 3505static int 3506rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3507{ 3508 struct rtsx_softc *sc; 3509 3510 sc = device_get_softc(bus); 3511 3512 if (sc->rtsx_inversion == 0) 3513 return (sc->rtsx_read_only); 3514 else 3515 return !(sc->rtsx_read_only); 3516} 3517 3518static int 3519rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3520{ 3521 struct rtsx_softc *sc; 3522 3523 sc = device_get_softc(bus); 3524 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3525 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3526 3527 RTSX_LOCK(sc); 3528 while (sc->rtsx_bus_busy) 3529 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3530 sc->rtsx_bus_busy++; 3531 RTSX_UNLOCK(sc); 3532 3533 return (0); 3534} 3535 3536static int 3537rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3538{ 3539 struct rtsx_softc *sc; 3540 3541 sc = device_get_softc(bus); 3542 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3543 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3544 3545 RTSX_LOCK(sc); 3546 sc->rtsx_bus_busy--; 3547 wakeup(&sc->rtsx_bus_busy); 3548 RTSX_UNLOCK(sc); 3549 3550 return (0); 3551} 3552#endif /* !MMCCAM */ 3553 3554/* 3555 * 3556 * PCI Support Functions 3557 * 3558 */ 3559 3560/* 3561 * Compare the device ID (chip) of this device against the IDs that this driver 3562 * supports. If there is a match, set the description and return success. 3563 */ 3564static int 3565rtsx_probe(device_t dev) 3566{ 3567 uint16_t vendor_id; 3568 uint16_t device_id; 3569 int i; 3570 3571 vendor_id = pci_get_vendor(dev); 3572 device_id = pci_get_device(dev); 3573 3574 if (vendor_id != RTSX_REALTEK) 3575 return (ENXIO); 3576 for (i = 0; i < nitems(rtsx_ids); i++) { 3577 if (rtsx_ids[i].device_id == device_id) { 3578 device_set_desc(dev, rtsx_ids[i].desc); 3579 return (BUS_PROBE_DEFAULT); 3580 } 3581 } 3582 return (ENXIO); 3583} 3584 3585/* 3586 * Attach function is only called if the probe is successful. 3587 */ 3588static int 3589rtsx_attach(device_t dev) 3590{ 3591 struct rtsx_softc *sc = device_get_softc(dev); 3592 uint16_t vendor_id; 3593 uint16_t device_id; 3594 struct sysctl_ctx_list *ctx; 3595 struct sysctl_oid_list *tree; 3596 int msi_count = 1; 3597 uint32_t sdio_cfg; 3598 int error; 3599 char *maker; 3600 char *family; 3601 char *product; 3602 int i; 3603 3604 vendor_id = pci_get_vendor(dev); 3605 device_id = pci_get_device(dev); 3606 if (bootverbose) 3607 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3608 vendor_id, device_id); 3609 3610 sc->rtsx_dev = dev; 3611 sc->rtsx_device_id = device_id; 3612 sc->rtsx_req = NULL; 3613 sc->rtsx_timeout_cmd = 1; 3614 sc->rtsx_timeout_io = 10; 3615 sc->rtsx_read_only = 0; 3616 sc->rtsx_inversion = 0; 3617 sc->rtsx_force_timing = 0; 3618 sc->rtsx_debug_mask = 0; 3619 sc->rtsx_read_count = 0; 3620 sc->rtsx_write_count = 0; 3621 3622 maker = kern_getenv("smbios.system.maker"); 3623 family = kern_getenv("smbios.system.family"); 3624 product = kern_getenv("smbios.system.product"); 3625 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3626 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3627 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3628 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3629 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3630 device_printf(dev, "If a card is detected without an SD card present," 3631 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3632 sc->rtsx_inversion = 1; 3633 } 3634 } 3635 3636 RTSX_LOCK_INIT(sc); 3637 3638 ctx = device_get_sysctl_ctx(dev); 3639 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3640 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3641 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3642 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3643 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3644 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3645 &sc->rtsx_read_only, 0, "Card is write protected"); 3646 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3647 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3648 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3649 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3650 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN, 3651 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)"); 3652 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS, 3653 &sc->rtsx_read_count, 0, "Count of read operations"); 3654 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS, 3655 &sc->rtsx_write_count, 0, "Count of write operations"); 3656 3657 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3658 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3659 3660 /* Allocate IRQ. */ 3661 sc->rtsx_irq_res_id = 0; 3662 if (pci_alloc_msi(dev, &msi_count) == 0) 3663 sc->rtsx_irq_res_id = 1; 3664 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3665 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3666 if (sc->rtsx_irq_res == NULL) { 3667 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3668 pci_release_msi(dev); 3669 return (ENXIO); 3670 } 3671 3672 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3673 3674 /* Allocate memory resource. */ 3675 if (sc->rtsx_device_id == RTSX_RTS525A) 3676 sc->rtsx_mem_res_id = PCIR_BAR(1); 3677 else 3678 sc->rtsx_mem_res_id = PCIR_BAR(0); 3679 sc->rtsx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_mem_res_id, RF_ACTIVE); 3680 if (sc->rtsx_mem_res == NULL) { 3681 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_mem_res_id); 3682 goto destroy_rtsx_irq_res; 3683 } 3684 3685 if (bootverbose) 3686 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_mem_res_id: %d\n", 3687 sc->rtsx_irq_res_id, sc->rtsx_mem_res_id); 3688 3689 sc->rtsx_mem_btag = rman_get_bustag(sc->rtsx_mem_res); 3690 sc->rtsx_mem_bhandle = rman_get_bushandle(sc->rtsx_mem_res); 3691 3692 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->rtsx_card_insert_task, 0, 3693 rtsx_card_task, sc); 3694 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3695 3696 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3697 error = rtsx_dma_alloc(sc); 3698 if (error) 3699 goto destroy_rtsx_irq_res; 3700 3701 /* Activate the interrupt. */ 3702 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3703 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3704 if (error) { 3705 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3706 goto destroy_rtsx_mem_res; 3707 } 3708 pci_enable_busmaster(dev); 3709 3710 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3711 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3712 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3713 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3714 } 3715 3716#ifdef MMCCAM 3717 sc->rtsx_ccb = NULL; 3718 sc->rtsx_cam_status = 0; 3719 3720 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3721 &sc->rtsx_cam_status, 0, "driver cam card present"); 3722 3723 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) { 3724 device_printf(dev, "Can't allocate CAM SIM\n"); 3725 goto destroy_rtsx_irq; 3726 } 3727#endif /* MMCCAM */ 3728 3729 /* Initialize device. */ 3730 error = rtsx_init(sc); 3731 if (error) { 3732 device_printf(dev, "Error %d during rtsx_init()\n", error); 3733 goto destroy_rtsx_irq; 3734 } 3735 3736 /* 3737 * Schedule a card detection as we won't get an interrupt 3738 * if the card is inserted when we attach. We wait a quarter 3739 * of a second to allow for a "spontaneous" interrupt which may 3740 * change the card presence state. This delay avoid a panic 3741 * on some configuration (e.g. Lenovo T540p). 3742 */ 3743 DELAY(250000); 3744 if (rtsx_is_card_present(sc)) 3745 device_printf(sc->rtsx_dev, "A card is detected\n"); 3746 else 3747 device_printf(sc->rtsx_dev, "No card is detected\n"); 3748 rtsx_card_task(sc, 0); 3749 3750 if (bootverbose) 3751 device_printf(dev, "Device attached\n"); 3752 3753 return (0); 3754 3755 destroy_rtsx_irq: 3756 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3757 destroy_rtsx_mem_res: 3758 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3759 sc->rtsx_mem_res); 3760 rtsx_dma_free(sc); 3761 destroy_rtsx_irq_res: 3762 callout_drain(&sc->rtsx_timeout_callout); 3763 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3764 sc->rtsx_irq_res); 3765 pci_release_msi(dev); 3766 RTSX_LOCK_DESTROY(sc); 3767 3768 return (ENXIO); 3769} 3770 3771static int 3772rtsx_detach(device_t dev) 3773{ 3774 struct rtsx_softc *sc = device_get_softc(dev); 3775 int error; 3776 3777 if (bootverbose) 3778 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3779 pci_get_vendor(dev), sc->rtsx_device_id); 3780 3781 /* Disable interrupts. */ 3782 sc->rtsx_intr_enabled = 0; 3783 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3784 3785 /* Stop device. */ 3786 error = device_delete_children(sc->rtsx_dev); 3787 sc->rtsx_mmc_dev = NULL; 3788 if (error) 3789 return (error); 3790 3791 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->rtsx_card_insert_task); 3792 taskqueue_drain(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 3793 3794 /* Teardown the state in our softc created in our attach routine. */ 3795 rtsx_dma_free(sc); 3796 if (sc->rtsx_mem_res != NULL) 3797 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3798 sc->rtsx_mem_res); 3799 if (sc->rtsx_irq_cookie != NULL) 3800 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3801 if (sc->rtsx_irq_res != NULL) { 3802 callout_drain(&sc->rtsx_timeout_callout); 3803 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3804 sc->rtsx_irq_res); 3805 pci_release_msi(dev); 3806 } 3807 RTSX_LOCK_DESTROY(sc); 3808#ifdef MMCCAM 3809 mmc_cam_sim_free(&sc->rtsx_mmc_sim); 3810#endif /* MMCCAM */ 3811 3812 return (0); 3813} 3814 3815static int 3816rtsx_shutdown(device_t dev) 3817{ 3818 if (bootverbose) 3819 device_printf(dev, "Shutdown\n"); 3820 3821 return (0); 3822} 3823 3824/* 3825 * Device suspend routine. 3826 */ 3827static int 3828rtsx_suspend(device_t dev) 3829{ 3830 struct rtsx_softc *sc = device_get_softc(dev); 3831 3832 device_printf(dev, "Suspend\n"); 3833 3834#ifdef MMCCAM 3835 if (sc->rtsx_ccb != NULL) { 3836 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3837 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3838 } 3839#else /* !MMCCAM */ 3840 if (sc->rtsx_req != NULL) { 3841 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3842 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3843 } 3844#endif /* MMCCAM */ 3845 3846 bus_generic_suspend(dev); 3847 3848 return (0); 3849} 3850 3851/* 3852 * Device resume routine. 3853 */ 3854static int 3855rtsx_resume(device_t dev) 3856{ 3857 device_printf(dev, "Resume\n"); 3858 3859 rtsx_init(device_get_softc(dev)); 3860 3861 bus_generic_resume(dev); 3862 3863 return (0); 3864} 3865 3866static device_method_t rtsx_methods[] = { 3867 /* Device interface */ 3868 DEVMETHOD(device_probe, rtsx_probe), 3869 DEVMETHOD(device_attach, rtsx_attach), 3870 DEVMETHOD(device_detach, rtsx_detach), 3871 DEVMETHOD(device_shutdown, rtsx_shutdown), 3872 DEVMETHOD(device_suspend, rtsx_suspend), 3873 DEVMETHOD(device_resume, rtsx_resume), 3874 3875 /* Bus interface */ 3876 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3877 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3878 3879#ifndef MMCCAM 3880 /* MMC bridge interface */ 3881 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3882 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3883 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3884 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3885 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3886 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3887 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3888 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3889#endif /* !MMCCAM */ 3890 3891#ifdef MMCCAM 3892 /* MMCCAM interface */ 3893 DEVMETHOD(mmc_sim_get_tran_settings, rtsx_get_tran_settings), 3894 DEVMETHOD(mmc_sim_set_tran_settings, rtsx_set_tran_settings), 3895 DEVMETHOD(mmc_sim_cam_request, rtsx_cam_request), 3896#endif /* MMCCAM */ 3897 3898 DEVMETHOD_END 3899}; 3900 3901DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3902DRIVER_MODULE(rtsx, pci, rtsx_driver, NULL, NULL); 3903 3904/* For Plug and Play */ 3905MODULE_PNP_INFO("U16:device;D:#;T:vendor=0x10ec", pci, rtsx, 3906 rtsx_ids, nitems(rtsx_ids)); 3907 3908#ifndef MMCCAM 3909MMC_DECLARE_BRIDGE(rtsx); 3910#endif /* !MMCCAM */ 3911