1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 1997, Stefan Esser <se@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef __PCI_PCIREG_H 30#define __PCI_PCIREG_H 31 32/* 33 * PCIM_xxx: mask to locate subfield in register 34 * PCIR_xxx: config register offset 35 * PCIC_xxx: device class 36 * PCIS_xxx: device subclass 37 * PCIP_xxx: device programming interface 38 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 39 * PCID_xxx: device ID 40 * PCIY_xxx: capability identification number 41 * PCIZ_xxx: extended capability identification number 42 */ 43 44/* some PCI bus constants */ 45#define PCI_DOMAINMAX 65535 /* highest supported domain number */ 46#define PCI_BUSMAX 255 /* highest supported bus number */ 47#define PCI_SLOTMAX 31 /* highest supported slot number */ 48#define PCI_FUNCMAX 7 /* highest supported function number */ 49#define PCI_REGMAX 255 /* highest supported config register addr. */ 50#define PCIE_REGMAX 4095 /* highest supported config register addr. */ 51#define PCI_MAXHDRTYPE 2 52 53#define PCIE_ARI_SLOTMAX 0 54#define PCIE_ARI_FUNCMAX 255 55 56#define PCI_RID_DOMAIN_SHIFT 16 57#define PCI_RID_BUS_SHIFT 8 58#define PCI_RID_SLOT_SHIFT 3 59#define PCI_RID_FUNC_SHIFT 0 60 61#define PCI_RID(bus, slot, func) \ 62 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 63 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 64 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 65 66#define PCI_ARI_RID(bus, func) \ 67 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 68 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 69 70#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 71#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 72#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 73 74#define PCIE_ARI_RID2SLOT(rid) (0) 75#define PCIE_ARI_RID2FUNC(rid) \ 76 (((rid) >> PCI_RID_FUNC_SHIFT) & PCIE_ARI_FUNCMAX) 77 78#define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 79#define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 80 81/* PCI config header registers for all devices */ 82 83#define PCIR_DEVVENDOR 0x00 84#define PCIR_VENDOR 0x00 85#define PCIR_DEVICE 0x02 86#define PCIR_COMMAND 0x04 87#define PCIM_CMD_PORTEN 0x0001 88#define PCIM_CMD_MEMEN 0x0002 89#define PCIM_CMD_BUSMASTEREN 0x0004 90#define PCIM_CMD_SPECIALEN 0x0008 91#define PCIM_CMD_MWRICEN 0x0010 92#define PCIM_CMD_PERRESPEN 0x0040 93#define PCIM_CMD_SERRESPEN 0x0100 94#define PCIM_CMD_BACKTOBACK 0x0200 95#define PCIM_CMD_INTxDIS 0x0400 96#define PCIR_STATUS 0x06 97#define PCIM_STATUS_INTxSTATE 0x0008 98#define PCIM_STATUS_CAPPRESENT 0x0010 99#define PCIM_STATUS_66CAPABLE 0x0020 100#define PCIM_STATUS_BACKTOBACK 0x0080 101#define PCIM_STATUS_MDPERR 0x0100 102#define PCIM_STATUS_SEL_FAST 0x0000 103#define PCIM_STATUS_SEL_MEDIMUM 0x0200 104#define PCIM_STATUS_SEL_SLOW 0x0400 105#define PCIM_STATUS_SEL_MASK 0x0600 106#define PCIM_STATUS_STABORT 0x0800 107#define PCIM_STATUS_RTABORT 0x1000 108#define PCIM_STATUS_RMABORT 0x2000 109#define PCIM_STATUS_SERR 0x4000 110#define PCIM_STATUS_PERR 0x8000 111#define PCIR_REVID 0x08 112#define PCIR_PROGIF 0x09 113#define PCIR_SUBCLASS 0x0a 114#define PCIR_CLASS 0x0b 115#define PCIR_CACHELNSZ 0x0c 116#define PCIR_LATTIMER 0x0d 117#define PCIR_HDRTYPE 0x0e 118#define PCIM_HDRTYPE 0x7f 119#define PCIM_HDRTYPE_NORMAL 0x00 120#define PCIM_HDRTYPE_BRIDGE 0x01 121#define PCIM_HDRTYPE_CARDBUS 0x02 122#define PCIM_MFDEV 0x80 123#define PCIR_BIST 0x0f 124 125/* PCI Spec rev 2.2: 0FFFFh is an invalid value for Vendor ID. */ 126#define PCIV_INVALID 0xffff 127 128/* Capability Register Offsets */ 129 130#define PCICAP_ID 0x0 131#define PCICAP_NEXTPTR 0x1 132 133/* Capability Identification Numbers */ 134 135#define PCIY_PMG 0x01 /* PCI Power Management */ 136#define PCIY_AGP 0x02 /* AGP */ 137#define PCIY_VPD 0x03 /* Vital Product Data */ 138#define PCIY_SLOTID 0x04 /* Slot Identification */ 139#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 140#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 141#define PCIY_PCIX 0x07 /* PCI-X */ 142#define PCIY_HT 0x08 /* HyperTransport */ 143#define PCIY_VENDOR 0x09 /* Vendor Unique */ 144#define PCIY_DEBUG 0x0a /* Debug port */ 145#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 146#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 147#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 148#define PCIY_AGP8X 0x0e /* AGP 8x */ 149#define PCIY_SECDEV 0x0f /* Secure Device */ 150#define PCIY_EXPRESS 0x10 /* PCI Express */ 151#define PCIY_MSIX 0x11 /* MSI-X */ 152#define PCIY_SATA 0x12 /* SATA */ 153#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 154#define PCIY_EA 0x14 /* PCI Extended Allocation */ 155#define PCIY_FPB 0x15 /* Flattening Portal Bridge */ 156 157/* Extended Capability Register Fields */ 158 159#define PCIR_EXTCAP 0x100 160#define PCIM_EXTCAP_ID 0x0000ffff 161#define PCIM_EXTCAP_VER 0x000f0000 162#define PCIM_EXTCAP_NEXTPTR 0xfff00000 163#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 164#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 165#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 166 167/* Extended Capability Identification Numbers */ 168 169#define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 170#define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 171#define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 172#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 173#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 174#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 175#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 176#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 177#define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 178#define PCIZ_RCRB 0x000a /* RCRB Header */ 179#define PCIZ_VENDOR 0x000b /* Vendor Unique */ 180#define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 181#define PCIZ_ACS 0x000d /* Access Control Services */ 182#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 183#define PCIZ_ATS 0x000f /* Address Translation Services */ 184#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 185#define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 186#define PCIZ_MULTICAST 0x0012 /* Multicast */ 187#define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 188#define PCIZ_AMD 0x0014 /* Reserved for AMD */ 189#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 190#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 191#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 192#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 193#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 194#define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 195#define PCIZ_PASID 0x001b /* Process Address Space ID */ 196#define PCIZ_LN_REQ 0x001c /* LN Requester */ 197#define PCIZ_DPC 0x001d /* Downstream Port Containment */ 198#define PCIZ_L1PM 0x001e /* L1 PM Substates */ 199#define PCIZ_PTM 0x001f /* Precision Time Measurement */ 200#define PCIZ_M_PCIE 0x0020 /* PCIe over M-PHY */ 201#define PCIZ_FRS 0x0021 /* FRS Queuing */ 202#define PCIZ_RTR 0x0022 /* Readiness Time Reporting */ 203#define PCIZ_DVSEC 0x0023 /* Designated Vendor-Specific */ 204#define PCIZ_VF_REBAR 0x0024 /* VF Resizable BAR */ 205#define PCIZ_DLNK 0x0025 /* Data Link Feature */ 206#define PCIZ_16GT 0x0026 /* Physical Layer 16.0 GT/s */ 207#define PCIZ_LMR 0x0027 /* Lane Margining at Receiver */ 208#define PCIZ_HIER_ID 0x0028 /* Hierarchy ID */ 209#define PCIZ_NPEM 0x0029 /* Native PCIe Enclosure Management */ 210#define PCIZ_PL32 0x002a /* Physical Layer 32.0 GT/s */ 211#define PCIZ_AP 0x002b /* Alternate Protocol */ 212#define PCIZ_SFI 0x002c /* System Firmware Intermediary */ 213 214/* config registers for header type 0 devices */ 215 216#define PCIR_BARS 0x10 217#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 218#define PCIR_MAX_BAR_0 5 219#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 220#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 221#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 222#define PCIM_BAR_SPACE 0x00000001 223#define PCIM_BAR_MEM_SPACE 0 224#define PCIM_BAR_IO_SPACE 1 225#define PCIM_BAR_MEM_TYPE 0x00000006 226#define PCIM_BAR_MEM_32 0 227#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 228#define PCIM_BAR_MEM_64 4 229#define PCIM_BAR_MEM_PREFETCH 0x00000008 230#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 231#define PCIM_BAR_IO_RESERVED 0x00000002 232#define PCIM_BAR_IO_BASE 0xfffffffc 233#define PCIR_CIS 0x28 234#define PCIM_CIS_ASI_MASK 0x00000007 235#define PCIM_CIS_ASI_CONFIG 0 236#define PCIM_CIS_ASI_BAR0 1 237#define PCIM_CIS_ASI_BAR1 2 238#define PCIM_CIS_ASI_BAR2 3 239#define PCIM_CIS_ASI_BAR3 4 240#define PCIM_CIS_ASI_BAR4 5 241#define PCIM_CIS_ASI_BAR5 6 242#define PCIM_CIS_ASI_ROM 7 243#define PCIM_CIS_ADDR_MASK 0x0ffffff8 244#define PCIM_CIS_ROM_MASK 0xf0000000 245#define PCIM_CIS_CONFIG_MASK 0xff 246#define PCIR_SUBVEND_0 0x2c 247#define PCIR_SUBDEV_0 0x2e 248#define PCIR_BIOS 0x30 249#define PCIM_BIOS_ENABLE 0x01 250#define PCIM_BIOS_ADDR_MASK 0xfffff800 251#define PCIR_CAP_PTR 0x34 252#define PCIR_INTLINE 0x3c 253#define PCIR_INTPIN 0x3d 254#define PCIR_MINGNT 0x3e 255#define PCIR_MAXLAT 0x3f 256 257/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 258 259#define PCIR_MAX_BAR_1 1 260#define PCIR_SECSTAT_1 0x1e 261 262#define PCIR_PRIBUS_1 0x18 263#define PCIR_SECBUS_1 0x19 264#define PCIR_SUBBUS_1 0x1a 265#define PCIR_SECLAT_1 0x1b 266 267#define PCIR_IOBASEL_1 0x1c 268#define PCIR_IOLIMITL_1 0x1d 269#define PCIR_IOBASEH_1 0x30 270#define PCIR_IOLIMITH_1 0x32 271#define PCIM_BRIO_16 0x0 272#define PCIM_BRIO_32 0x1 273#define PCIM_BRIO_MASK 0xf 274 275#define PCIR_MEMBASE_1 0x20 276#define PCIR_MEMLIMIT_1 0x22 277 278#define PCIR_PMBASEL_1 0x24 279#define PCIR_PMLIMITL_1 0x26 280#define PCIR_PMBASEH_1 0x28 281#define PCIR_PMLIMITH_1 0x2c 282#define PCIM_BRPM_32 0x0 283#define PCIM_BRPM_64 0x1 284#define PCIM_BRPM_MASK 0xf 285 286#define PCIR_BIOS_1 0x38 287#define PCIR_BRIDGECTL_1 0x3e 288 289#define PCI_PPBMEMBASE(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 290#define PCI_PPBMEMLIMIT(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff) 291#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 292#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 293 294/* config registers for header type 2 (CardBus) devices */ 295 296#define PCIR_MAX_BAR_2 0 297#define PCIR_CAP_PTR_2 0x14 298#define PCIR_SECSTAT_2 0x16 299 300#define PCIR_PRIBUS_2 0x18 301#define PCIR_SECBUS_2 0x19 302#define PCIR_SUBBUS_2 0x1a 303#define PCIR_SECLAT_2 0x1b 304 305#define PCIR_MEMBASE0_2 0x1c 306#define PCIR_MEMLIMIT0_2 0x20 307#define PCIR_MEMBASE1_2 0x24 308#define PCIR_MEMLIMIT1_2 0x28 309#define PCIR_IOBASE0_2 0x2c 310#define PCIR_IOLIMIT0_2 0x30 311#define PCIR_IOBASE1_2 0x34 312#define PCIR_IOLIMIT1_2 0x38 313#define PCIM_CBBIO_16 0x0 314#define PCIM_CBBIO_32 0x1 315#define PCIM_CBBIO_MASK 0x3 316 317#define PCIR_BRIDGECTL_2 0x3e 318 319#define PCIR_SUBVEND_2 0x40 320#define PCIR_SUBDEV_2 0x42 321 322#define PCIR_PCCARDIF_2 0x44 323 324#define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) 325#define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) 326#define PCI_CBBIOBASE(l) ((l) & ~0x3) 327#define PCI_CBBIOLIMIT(l) ((l) | 0x3) 328 329/* PCI device class, subclass and programming interface definitions */ 330 331#define PCIC_OLD 0x00 332#define PCIS_OLD_NONVGA 0x00 333#define PCIS_OLD_VGA 0x01 334 335#define PCIC_STORAGE 0x01 336#define PCIS_STORAGE_SCSI 0x00 337#define PCIS_STORAGE_IDE 0x01 338#define PCIP_STORAGE_IDE_MODEPRIM 0x01 339#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 340#define PCIP_STORAGE_IDE_MODESEC 0x04 341#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 342#define PCIP_STORAGE_IDE_MASTERDEV 0x80 343#define PCIS_STORAGE_FLOPPY 0x02 344#define PCIS_STORAGE_IPI 0x03 345#define PCIS_STORAGE_RAID 0x04 346#define PCIS_STORAGE_ATA_ADMA 0x05 347#define PCIS_STORAGE_SATA 0x06 348#define PCIP_STORAGE_SATA_AHCI_1_0 0x01 349#define PCIS_STORAGE_SAS 0x07 350#define PCIS_STORAGE_NVM 0x08 351#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 352#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 353#define PCIS_STORAGE_UFS 0x09 354#define PCIP_STORAGE_UFS_UFSHCI_1_0 0x01 355#define PCIS_STORAGE_OTHER 0x80 356 357#define PCIC_NETWORK 0x02 358#define PCIS_NETWORK_ETHERNET 0x00 359#define PCIS_NETWORK_TOKENRING 0x01 360#define PCIS_NETWORK_FDDI 0x02 361#define PCIS_NETWORK_ATM 0x03 362#define PCIS_NETWORK_ISDN 0x04 363#define PCIS_NETWORK_WORLDFIP 0x05 364#define PCIS_NETWORK_PICMG 0x06 365#define PCIS_NETWORK_INFINIBAND 0x07 366#define PCIS_NETWORK_HFC 0x08 367#define PCIS_NETWORK_OTHER 0x80 368 369#define PCIC_DISPLAY 0x03 370#define PCIS_DISPLAY_VGA 0x00 371#define PCIS_DISPLAY_XGA 0x01 372#define PCIS_DISPLAY_3D 0x02 373#define PCIS_DISPLAY_OTHER 0x80 374 375#define PCIC_MULTIMEDIA 0x04 376#define PCIS_MULTIMEDIA_VIDEO 0x00 377#define PCIS_MULTIMEDIA_AUDIO 0x01 378#define PCIS_MULTIMEDIA_TELE 0x02 379#define PCIS_MULTIMEDIA_HDA 0x03 380#define PCIP_MULTIMEDIA_HDA_VENDOR 0x01 381#define PCIS_MULTIMEDIA_OTHER 0x80 382 383#define PCIC_MEMORY 0x05 384#define PCIS_MEMORY_RAM 0x00 385#define PCIS_MEMORY_FLASH 0x01 386#define PCIS_MEMORY_OTHER 0x80 387 388#define PCIC_BRIDGE 0x06 389#define PCIS_BRIDGE_HOST 0x00 390#define PCIS_BRIDGE_ISA 0x01 391#define PCIS_BRIDGE_EISA 0x02 392#define PCIS_BRIDGE_MCA 0x03 393#define PCIS_BRIDGE_PCI 0x04 394#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 395#define PCIS_BRIDGE_PCMCIA 0x05 396#define PCIS_BRIDGE_NUBUS 0x06 397#define PCIS_BRIDGE_CARDBUS 0x07 398#define PCIS_BRIDGE_RACEWAY 0x08 399#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 400#define PCIS_BRIDGE_INFINIBAND 0x0a 401#define PCIS_BRIDGE_AS_PCI 0x0b 402#define PCIS_BRIDGE_AS_PCI_ASI_SIG 0x01 403#define PCIS_BRIDGE_OTHER 0x80 404 405#define PCIC_SIMPLECOMM 0x07 406#define PCIS_SIMPLECOMM_UART 0x00 407#define PCIP_SIMPLECOMM_UART_8250 0x00 408#define PCIP_SIMPLECOMM_UART_16450A 0x01 409#define PCIP_SIMPLECOMM_UART_16550A 0x02 410#define PCIP_SIMPLECOMM_UART_16650A 0x03 411#define PCIP_SIMPLECOMM_UART_16750A 0x04 412#define PCIP_SIMPLECOMM_UART_16850A 0x05 413#define PCIP_SIMPLECOMM_UART_16950A 0x06 414#define PCIS_SIMPLECOMM_PAR 0x01 415#define PCIS_SIMPLECOMM_MULSER 0x02 416#define PCIS_SIMPLECOMM_MODEM 0x03 417#define PCIS_SIMPLECOMM_GPIB 0x04 418#define PCIS_SIMPLECOMM_SMART_CARD 0x05 419#define PCIS_SIMPLECOMM_OTHER 0x80 420 421#define PCIC_BASEPERIPH 0x08 422#define PCIS_BASEPERIPH_PIC 0x00 423#define PCIP_BASEPERIPH_PIC_8259A 0x00 424#define PCIP_BASEPERIPH_PIC_ISA 0x01 425#define PCIP_BASEPERIPH_PIC_EISA 0x02 426#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 427#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 428#define PCIS_BASEPERIPH_DMA 0x01 429#define PCIS_BASEPERIPH_TIMER 0x02 430#define PCIS_BASEPERIPH_RTC 0x03 431#define PCIS_BASEPERIPH_PCIHOT 0x04 432#define PCIS_BASEPERIPH_SDHC 0x05 433#define PCIS_BASEPERIPH_IOMMU 0x06 434#define PCIS_BASEPERIPH_RCEC 0x07 435#define PCIS_BASEPERIPH_OTHER 0x80 436 437#define PCIC_INPUTDEV 0x09 438#define PCIS_INPUTDEV_KEYBOARD 0x00 439#define PCIS_INPUTDEV_DIGITIZER 0x01 440#define PCIS_INPUTDEV_MOUSE 0x02 441#define PCIS_INPUTDEV_SCANNER 0x03 442#define PCIS_INPUTDEV_GAMEPORT 0x04 443#define PCIS_INPUTDEV_OTHER 0x80 444 445#define PCIC_DOCKING 0x0a 446#define PCIS_DOCKING_GENERIC 0x00 447#define PCIS_DOCKING_OTHER 0x80 448 449#define PCIC_PROCESSOR 0x0b 450#define PCIS_PROCESSOR_386 0x00 451#define PCIS_PROCESSOR_486 0x01 452#define PCIS_PROCESSOR_PENTIUM 0x02 453#define PCIS_PROCESSOR_ALPHA 0x10 454#define PCIS_PROCESSOR_POWERPC 0x20 455#define PCIS_PROCESSOR_MIPS 0x30 456#define PCIS_PROCESSOR_COPROC 0x40 457 458#define PCIC_SERIALBUS 0x0c 459#define PCIS_SERIALBUS_FW 0x00 460#define PCIS_SERIALBUS_ACCESS 0x01 461#define PCIS_SERIALBUS_SSA 0x02 462#define PCIS_SERIALBUS_USB 0x03 463#define PCIP_SERIALBUS_USB_UHCI 0x00 464#define PCIP_SERIALBUS_USB_OHCI 0x10 465#define PCIP_SERIALBUS_USB_EHCI 0x20 466#define PCIP_SERIALBUS_USB_XHCI 0x30 467#define PCIP_SERIALBUS_USB_DEVICE 0xfe 468#define PCIS_SERIALBUS_FC 0x04 469#define PCIS_SERIALBUS_SMBUS 0x05 470#define PCIS_SERIALBUS_INFINIBAND 0x06 471#define PCIS_SERIALBUS_IPMI 0x07 472#define PCIP_SERIALBUS_IPMI_SMIC 0x00 473#define PCIP_SERIALBUS_IPMI_KCS 0x01 474#define PCIP_SERIALBUS_IPMI_BT 0x02 475#define PCIS_SERIALBUS_SERCOS 0x08 476#define PCIS_SERIALBUS_CANBUS 0x09 477#define PCIS_SERIALBUS_MIPI_I3C 0x0a 478 479#define PCIC_WIRELESS 0x0d 480#define PCIS_WIRELESS_IRDA 0x00 481#define PCIS_WIRELESS_IR 0x01 482#define PCIS_WIRELESS_RF 0x10 483#define PCIS_WIRELESS_BLUETOOTH 0x11 484#define PCIS_WIRELESS_BROADBAND 0x12 485#define PCIS_WIRELESS_80211A 0x20 486#define PCIS_WIRELESS_80211B 0x21 487#define PCIS_WIRELESS_CELL 0x40 488#define PCIS_WIRELESS_CELL_E 0x41 489#define PCIS_WIRELESS_OTHER 0x80 490 491#define PCIC_INTELLIIO 0x0e 492#define PCIS_INTELLIIO_I2O 0x00 493 494#define PCIC_SATCOM 0x0f 495#define PCIS_SATCOM_TV 0x01 496#define PCIS_SATCOM_AUDIO 0x02 497#define PCIS_SATCOM_VOICE 0x03 498#define PCIS_SATCOM_DATA 0x04 499 500#define PCIC_CRYPTO 0x10 501#define PCIS_CRYPTO_NETCOMP 0x00 502#define PCIS_CRYPTO_ENTERTAIN 0x10 503#define PCIS_CRYPTO_OTHER 0x80 504 505#define PCIC_DASP 0x11 506#define PCIS_DASP_DPIO 0x00 507#define PCIS_DASP_PERFCNTRS 0x01 508#define PCIS_DASP_COMM_SYNC 0x10 509#define PCIS_DASP_MGMT_CARD 0x20 510#define PCIS_DASP_OTHER 0x80 511 512#define PCIC_ACCEL 0x12 513#define PCIS_ACCEL_PROCESSING 0x00 514 515#define PCIC_INSTRUMENT 0x13 516 517#define PCIC_OTHER 0xff 518 519/* Bridge Control Values. */ 520#define PCIB_BCR_PERR_ENABLE 0x0001 521#define PCIB_BCR_SERR_ENABLE 0x0002 522#define PCIB_BCR_ISA_ENABLE 0x0004 523#define PCIB_BCR_VGA_ENABLE 0x0008 524#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 525#define PCIB_BCR_SECBUS_RESET 0x0040 526#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 527#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 528#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 529#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 530#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 531 532#define CBB_BCR_PERR_ENABLE 0x0001 533#define CBB_BCR_SERR_ENABLE 0x0002 534#define CBB_BCR_ISA_ENABLE 0x0004 535#define CBB_BCR_VGA_ENABLE 0x0008 536#define CBB_BCR_MASTER_ABORT_MODE 0x0020 537#define CBB_BCR_CARDBUS_RESET 0x0040 538#define CBB_BCR_IREQ_INT_ENABLE 0x0080 539#define CBB_BCR_PREFETCH_0_ENABLE 0x0100 540#define CBB_BCR_PREFETCH_1_ENABLE 0x0200 541#define CBB_BCR_WRITE_POSTING_ENABLE 0x0400 542 543/* PCI power manangement */ 544#define PCIR_POWER_CAP 0x2 545#define PCIM_PCAP_SPEC 0x0007 546#define PCIM_PCAP_PMEREQCLK 0x0008 547#define PCIM_PCAP_DEVSPECINIT 0x0020 548#define PCIM_PCAP_AUXPWR_0 0x0000 549#define PCIM_PCAP_AUXPWR_55 0x0040 550#define PCIM_PCAP_AUXPWR_100 0x0080 551#define PCIM_PCAP_AUXPWR_160 0x00c0 552#define PCIM_PCAP_AUXPWR_220 0x0100 553#define PCIM_PCAP_AUXPWR_270 0x0140 554#define PCIM_PCAP_AUXPWR_320 0x0180 555#define PCIM_PCAP_AUXPWR_375 0x01c0 556#define PCIM_PCAP_AUXPWRMASK 0x01c0 557#define PCIM_PCAP_D1SUPP 0x0200 558#define PCIM_PCAP_D2SUPP 0x0400 559#define PCIM_PCAP_D0PME 0x0800 560#define PCIM_PCAP_D1PME 0x1000 561#define PCIM_PCAP_D2PME 0x2000 562#define PCIM_PCAP_D3PME_HOT 0x4000 563#define PCIM_PCAP_D3PME_COLD 0x8000 564 565#define PCIR_POWER_STATUS 0x4 566#define PCIM_PSTAT_D0 0x0000 567#define PCIM_PSTAT_D1 0x0001 568#define PCIM_PSTAT_D2 0x0002 569#define PCIM_PSTAT_D3 0x0003 570#define PCIM_PSTAT_DMASK 0x0003 571#define PCIM_PSTAT_NOSOFTRESET 0x0008 572#define PCIM_PSTAT_PMEENABLE 0x0100 573#define PCIM_PSTAT_D0POWER 0x0000 574#define PCIM_PSTAT_D1POWER 0x0200 575#define PCIM_PSTAT_D2POWER 0x0400 576#define PCIM_PSTAT_D3POWER 0x0600 577#define PCIM_PSTAT_D0HEAT 0x0800 578#define PCIM_PSTAT_D1HEAT 0x0a00 579#define PCIM_PSTAT_D2HEAT 0x0c00 580#define PCIM_PSTAT_D3HEAT 0x0e00 581#define PCIM_PSTAT_DATASELMASK 0x1e00 582#define PCIM_PSTAT_DATAUNKN 0x0000 583#define PCIM_PSTAT_DATADIV10 0x2000 584#define PCIM_PSTAT_DATADIV100 0x4000 585#define PCIM_PSTAT_DATADIV1000 0x6000 586#define PCIM_PSTAT_DATADIVMASK 0x6000 587#define PCIM_PSTAT_PME 0x8000 588 589#define PCIR_POWER_BSE 0x6 590#define PCIM_PMCSR_BSE_D3B3 0x00 591#define PCIM_PMCSR_BSE_D3B2 0x40 592#define PCIM_PMCSR_BSE_BPCCE 0x80 593 594#define PCIR_POWER_DATA 0x7 595 596/* VPD capability registers */ 597#define PCIR_VPD_ADDR 0x2 598#define PCIR_VPD_DATA 0x4 599 600/* PCI Message Signalled Interrupts (MSI) */ 601#define PCIR_MSI_CTRL 0x2 602#define PCIM_MSICTRL_VECTOR 0x0100 603#define PCIM_MSICTRL_64BIT 0x0080 604#define PCIM_MSICTRL_MME_MASK 0x0070 605#define PCIM_MSICTRL_MME_1 0x0000 606#define PCIM_MSICTRL_MME_2 0x0010 607#define PCIM_MSICTRL_MME_4 0x0020 608#define PCIM_MSICTRL_MME_8 0x0030 609#define PCIM_MSICTRL_MME_16 0x0040 610#define PCIM_MSICTRL_MME_32 0x0050 611#define PCIM_MSICTRL_MMC_MASK 0x000E 612#define PCIM_MSICTRL_MMC_1 0x0000 613#define PCIM_MSICTRL_MMC_2 0x0002 614#define PCIM_MSICTRL_MMC_4 0x0004 615#define PCIM_MSICTRL_MMC_8 0x0006 616#define PCIM_MSICTRL_MMC_16 0x0008 617#define PCIM_MSICTRL_MMC_32 0x000A 618#define PCIM_MSICTRL_MSI_ENABLE 0x0001 619#define PCIR_MSI_ADDR 0x4 620#define PCIR_MSI_ADDR_HIGH 0x8 621#define PCIR_MSI_DATA 0x8 622#define PCIR_MSI_DATA_64BIT 0xc 623#define PCIR_MSI_MASK 0x10 624#define PCIR_MSI_PENDING 0x14 625 626/* PCI Enhanced Allocation registers */ 627#define PCIR_EA_NUM_ENT 2 /* Number of Capability Entries */ 628#define PCIM_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 629#define PCIR_EA_FIRST_ENT 4 /* First EA Entry in List */ 630#define PCIR_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ 631#define PCIM_EA_ES 0x00000007 /* Entry Size */ 632#define PCIM_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 633#define PCIM_EA_BEI_OFFSET 4 634/* 0-5 map to BARs 0-5 respectively */ 635#define PCIM_EA_BEI_BAR_0 0 636#define PCIM_EA_BEI_BAR_5 5 637#define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf) 638#define PCIM_EA_BEI_BRIDGE 0x6 /* Resource behind bridge */ 639#define PCIM_EA_BEI_ENI 0x7 /* Equivalent Not Indicated */ 640#define PCIM_EA_BEI_ROM 0x8 /* Expansion ROM */ 641/* 9-14 map to VF BARs 0-5 respectively */ 642#define PCIM_EA_BEI_VF_BAR_0 9 643#define PCIM_EA_BEI_VF_BAR_5 14 644#define PCIM_EA_BEI_RESERVED 0xf /* Reserved - Treat like ENI */ 645#define PCIM_EA_PP 0x0000ff00 /* Primary Properties */ 646#define PCIM_EA_PP_OFFSET 8 647#define PCIM_EA_SP_OFFSET 16 648#define PCIM_EA_SP 0x00ff0000 /* Secondary Properties */ 649#define PCIM_EA_P_MEM 0x00 /* Non-Prefetch Memory */ 650#define PCIM_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ 651#define PCIM_EA_P_IO 0x02 /* I/O Space */ 652#define PCIM_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ 653#define PCIM_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ 654#define PCIM_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ 655#define PCIM_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ 656#define PCIM_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ 657/* 0x08-0xfc reserved */ 658#define PCIM_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ 659#define PCIM_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ 660#define PCIM_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ 661#define PCIM_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ 662#define PCIM_EA_ENABLE 0x80000000 /* Enable for this entry */ 663#define PCIM_EA_BASE 4 /* Base Address Offset */ 664#define PCIM_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ 665/* bit 0 is reserved */ 666#define PCIM_EA_IS_64 0x00000002 /* 64-bit field flag */ 667#define PCIM_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 668/* Bridge config register */ 669#define PCIM_EA_SEC_NR(reg) ((reg) & 0xff) 670#define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff) 671 672/* PCI-X definitions */ 673 674/* For header type 0 devices */ 675#define PCIXR_COMMAND 0x2 676#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 677#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 678#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 679#define PCIXM_COMMAND_MAX_READ_512 0x0000 680#define PCIXM_COMMAND_MAX_READ_1024 0x0004 681#define PCIXM_COMMAND_MAX_READ_2048 0x0008 682#define PCIXM_COMMAND_MAX_READ_4096 0x000c 683#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 684#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 685#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 686#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 687#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 688#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 689#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 690#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 691#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 692#define PCIXM_COMMAND_VERSION 0x3000 693#define PCIXR_STATUS 0x4 694#define PCIXM_STATUS_DEVFN 0x000000FF 695#define PCIXM_STATUS_BUS 0x0000FF00 696#define PCIXM_STATUS_64BIT 0x00010000 697#define PCIXM_STATUS_133CAP 0x00020000 698#define PCIXM_STATUS_SC_DISCARDED 0x00040000 699#define PCIXM_STATUS_UNEXP_SC 0x00080000 700#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 701#define PCIXM_STATUS_MAX_READ 0x00600000 702#define PCIXM_STATUS_MAX_READ_512 0x00000000 703#define PCIXM_STATUS_MAX_READ_1024 0x00200000 704#define PCIXM_STATUS_MAX_READ_2048 0x00400000 705#define PCIXM_STATUS_MAX_READ_4096 0x00600000 706#define PCIXM_STATUS_MAX_SPLITS 0x03800000 707#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 708#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 709#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 710#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 711#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 712#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 713#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 714#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 715#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 716#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 717#define PCIXM_STATUS_266CAP 0x40000000 718#define PCIXM_STATUS_533CAP 0x80000000 719 720/* For header type 1 devices (PCI-X bridges) */ 721#define PCIXR_SEC_STATUS 0x2 722#define PCIXM_SEC_STATUS_64BIT 0x0001 723#define PCIXM_SEC_STATUS_133CAP 0x0002 724#define PCIXM_SEC_STATUS_SC_DISC 0x0004 725#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 726#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 727#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 728#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 729#define PCIXM_SEC_STATUS_VERSION 0x3000 730#define PCIXM_SEC_STATUS_266CAP 0x4000 731#define PCIXM_SEC_STATUS_533CAP 0x8000 732#define PCIXR_BRIDGE_STATUS 0x4 733#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 734#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 735#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 736#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 737#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 738#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 739#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 740#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 741#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 742#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 743#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 744 745/* HT (HyperTransport) Capability definitions */ 746#define PCIR_HT_COMMAND 0x2 747#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 748#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 749#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 750#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 751#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 752#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 753#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 754#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 755#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 756#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 757#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 758#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 759#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 760#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 761#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 762#define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 763#define PCIM_HTCAP_PM 0xe000 /* 11100 */ 764#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 765 766/* HT MSI Mapping Capability definitions. */ 767#define PCIM_HTCMD_MSI_ENABLE 0x0001 768#define PCIM_HTCMD_MSI_FIXED 0x0002 769#define PCIR_HTMSI_ADDRESS_LO 0x4 770#define PCIR_HTMSI_ADDRESS_HI 0x8 771 772/* PCI Vendor capability definitions */ 773#define PCIR_VENDOR_LENGTH 0x2 774#define PCIR_VENDOR_DATA 0x3 775 776/* PCI Device capability definitions */ 777#define PCIR_DEVICE_LENGTH 0x2 778 779/* PCI EHCI Debug Port definitions */ 780#define PCIR_DEBUG_PORT 0x2 781#define PCIM_DEBUG_PORT_OFFSET 0x1FFF 782#define PCIM_DEBUG_PORT_BAR 0xe000 783 784/* PCI-PCI Bridge Subvendor definitions */ 785#define PCIR_SUBVENDCAP_ID 0x4 786 787/* PCI Express definitions */ 788#define PCIER_FLAGS 0x2 789#define PCIEM_FLAGS_VERSION 0x000F 790#define PCIEM_FLAGS_TYPE 0x00F0 791#define PCIEM_TYPE_ENDPOINT 0x0000 792#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 793#define PCIEM_TYPE_ROOT_PORT 0x0040 794#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 795#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 796#define PCIEM_TYPE_PCI_BRIDGE 0x0070 797#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 798#define PCIEM_TYPE_ROOT_INT_EP 0x0090 799#define PCIEM_TYPE_ROOT_EC 0x00a0 800#define PCIEM_FLAGS_SLOT 0x0100 801#define PCIEM_FLAGS_IRQ 0x3e00 802#define PCIER_DEVICE_CAP 0x4 803#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 804#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 805#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 806#define PCIEM_CAP_L0S_LATENCY 0x000001c0 807#define PCIEM_CAP_L1_LATENCY 0x00000e00 808#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 809#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 810#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 811#define PCIEM_CAP_FLR 0x10000000 812#define PCIER_DEVICE_CTL 0x8 813#define PCIEM_CTL_COR_ENABLE 0x0001 814#define PCIEM_CTL_NFER_ENABLE 0x0002 815#define PCIEM_CTL_FER_ENABLE 0x0004 816#define PCIEM_CTL_URR_ENABLE 0x0008 817#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 818#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 819#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 820#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 821#define PCIEM_CTL_AUX_POWER_PM 0x0400 822#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 823#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 824#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 825#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 826#define PCIER_DEVICE_STA 0xa 827#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 828#define PCIEM_STA_NON_FATAL_ERROR 0x0002 829#define PCIEM_STA_FATAL_ERROR 0x0004 830#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 831#define PCIEM_STA_AUX_POWER 0x0010 832#define PCIEM_STA_TRANSACTION_PND 0x0020 833#define PCIER_LINK_CAP 0xc 834#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 835#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 836#define PCIEM_LINK_CAP_ASPM 0x00000c00 837#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 838#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 839#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 840#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 841#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 842#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 843#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 844#define PCIEM_LINK_CAP_PORT 0xff000000 845#define PCIER_LINK_CTL 0x10 846#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 847#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 848#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 849#define PCIEM_LINK_CTL_ASPMC 0x0003 850#define PCIEM_LINK_CTL_RCB 0x0008 851#define PCIEM_LINK_CTL_LINK_DIS 0x0010 852#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 853#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 854#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 855#define PCIEM_LINK_CTL_ECPM 0x0100 856#define PCIEM_LINK_CTL_HAWD 0x0200 857#define PCIEM_LINK_CTL_LBMIE 0x0400 858#define PCIEM_LINK_CTL_LABIE 0x0800 859#define PCIER_LINK_STA 0x12 860#define PCIEM_LINK_STA_SPEED 0x000f 861#define PCIEM_LINK_STA_WIDTH 0x03f0 862#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 863#define PCIEM_LINK_STA_TRAINING 0x0800 864#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 865#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 866#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 867#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 868#define PCIER_SLOT_CAP 0x14 869#define PCIEM_SLOT_CAP_APB 0x00000001 870#define PCIEM_SLOT_CAP_PCP 0x00000002 871#define PCIEM_SLOT_CAP_MRLSP 0x00000004 872#define PCIEM_SLOT_CAP_AIP 0x00000008 873#define PCIEM_SLOT_CAP_PIP 0x00000010 874#define PCIEM_SLOT_CAP_HPS 0x00000020 875#define PCIEM_SLOT_CAP_HPC 0x00000040 876#define PCIEM_SLOT_CAP_SPLV 0x00007f80 877#define PCIEM_SLOT_CAP_SPLS 0x00018000 878#define PCIEM_SLOT_CAP_EIP 0x00020000 879#define PCIEM_SLOT_CAP_NCCS 0x00040000 880#define PCIEM_SLOT_CAP_PSN 0xfff80000 881#define PCIER_SLOT_CTL 0x18 882#define PCIEM_SLOT_CTL_ABPE 0x0001 883#define PCIEM_SLOT_CTL_PFDE 0x0002 884#define PCIEM_SLOT_CTL_MRLSCE 0x0004 885#define PCIEM_SLOT_CTL_PDCE 0x0008 886#define PCIEM_SLOT_CTL_CCIE 0x0010 887#define PCIEM_SLOT_CTL_HPIE 0x0020 888#define PCIEM_SLOT_CTL_AIC 0x00c0 889#define PCIEM_SLOT_CTL_AI_ON 0x0040 890#define PCIEM_SLOT_CTL_AI_BLINK 0x0080 891#define PCIEM_SLOT_CTL_AI_OFF 0x00c0 892#define PCIEM_SLOT_CTL_PIC 0x0300 893#define PCIEM_SLOT_CTL_PI_ON 0x0100 894#define PCIEM_SLOT_CTL_PI_BLINK 0x0200 895#define PCIEM_SLOT_CTL_PI_OFF 0x0300 896#define PCIEM_SLOT_CTL_PCC 0x0400 897#define PCIEM_SLOT_CTL_PC_ON 0x0000 898#define PCIEM_SLOT_CTL_PC_OFF 0x0400 899#define PCIEM_SLOT_CTL_EIC 0x0800 900#define PCIEM_SLOT_CTL_DLLSCE 0x1000 901#define PCIER_SLOT_STA 0x1a 902#define PCIEM_SLOT_STA_ABP 0x0001 903#define PCIEM_SLOT_STA_PFD 0x0002 904#define PCIEM_SLOT_STA_MRLSC 0x0004 905#define PCIEM_SLOT_STA_PDC 0x0008 906#define PCIEM_SLOT_STA_CC 0x0010 907#define PCIEM_SLOT_STA_MRLSS 0x0020 908#define PCIEM_SLOT_STA_PDS 0x0040 909#define PCIEM_SLOT_STA_EIS 0x0080 910#define PCIEM_SLOT_STA_DLLSC 0x0100 911#define PCIER_ROOT_CTL 0x1c 912#define PCIEM_ROOT_CTL_SERR_CORR 0x0001 913#define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 914#define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 915#define PCIEM_ROOT_CTL_PME 0x0008 916#define PCIEM_ROOT_CTL_CRS_VIS 0x0010 917#define PCIER_ROOT_CAP 0x1e 918#define PCIEM_ROOT_CAP_CRS_VIS 0x0001 919#define PCIER_ROOT_STA 0x20 920#define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 921#define PCIEM_ROOT_STA_PME_STATUS 0x00010000 922#define PCIEM_ROOT_STA_PME_PEND 0x00020000 923#define PCIER_DEVICE_CAP2 0x24 924#define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f 925#define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001 926#define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002 927#define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004 928#define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008 929#define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010 930#define PCIEM_CAP2_ARI 0x00000020 931#define PCIER_DEVICE_CTL2 0x28 932#define PCIEM_CTL2_COMP_TIMO_VAL 0x000f 933#define PCIEM_CTL2_COMP_TIMO_50MS 0x0000 934#define PCIEM_CTL2_COMP_TIMO_100US 0x0001 935#define PCIEM_CTL2_COMP_TIMO_10MS 0x0002 936#define PCIEM_CTL2_COMP_TIMO_55MS 0x0005 937#define PCIEM_CTL2_COMP_TIMO_210MS 0x0006 938#define PCIEM_CTL2_COMP_TIMO_900MS 0x0009 939#define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a 940#define PCIEM_CTL2_COMP_TIMO_13S 0x000d 941#define PCIEM_CTL2_COMP_TIMO_64S 0x000e 942#define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010 943#define PCIEM_CTL2_ARI 0x0020 944#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 945#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 946#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 947#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 948#define PCIEM_CTL2_LTR_ENABLE 0x0400 949#define PCIEM_CTL2_OBFF 0x6000 950#define PCIEM_OBFF_DISABLE 0x0000 951#define PCIEM_OBFF_MSGA_ENABLE 0x2000 952#define PCIEM_OBFF_MSGB_ENABLE 0x4000 953#define PCIEM_OBFF_WAKE_ENABLE 0x6000 954#define PCIEM_CTL2_END2END_TLP 0x8000 955#define PCIER_DEVICE_STA2 0x2a 956#define PCIER_LINK_CAP2 0x2c 957#define PCIER_LINK_CTL2 0x30 958#define PCIER_LINK_STA2 0x32 959#define PCIER_SLOT_CAP2 0x34 960#define PCIER_SLOT_CTL2 0x38 961#define PCIER_SLOT_STA2 0x3a 962 963/* MSI-X definitions */ 964#define PCIR_MSIX_CTRL 0x2 965#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 966#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 967#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 968#define PCIR_MSIX_TABLE 0x4 969#define PCIR_MSIX_PBA 0x8 970#define PCIM_MSIX_BIR_MASK 0x7 971#define PCIM_MSIX_BIR_BAR_10 0 972#define PCIM_MSIX_BIR_BAR_14 1 973#define PCIM_MSIX_BIR_BAR_18 2 974#define PCIM_MSIX_BIR_BAR_1C 3 975#define PCIM_MSIX_BIR_BAR_20 4 976#define PCIM_MSIX_BIR_BAR_24 5 977#define PCIM_MSIX_VCTRL_MASK 0x1 978 979/* PCI Advanced Features definitions */ 980#define PCIR_PCIAF_CAP 0x3 981#define PCIM_PCIAFCAP_TP 0x01 982#define PCIM_PCIAFCAP_FLR 0x02 983#define PCIR_PCIAF_CTRL 0x4 984#define PCIR_PCIAFCTRL_FLR 0x01 985#define PCIR_PCIAF_STATUS 0x5 986#define PCIR_PCIAFSTATUS_TP 0x01 987 988/* Advanced Error Reporting */ 989#define PCIR_AER_UC_STATUS 0x04 990#define PCIM_AER_UC_TRAINING_ERROR 0x00000001 991#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 992#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 993#define PCIM_AER_UC_POISONED_TLP 0x00001000 994#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 995#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 996#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 997#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 998#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 999#define PCIM_AER_UC_MALFORMED_TLP 0x00040000 1000#define PCIM_AER_UC_ECRC_ERROR 0x00080000 1001#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 1002#define PCIM_AER_UC_ACS_VIOLATION 0x00200000 1003#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 1004#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 1005#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 1006#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 1007#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 1008#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 1009#define PCIR_AER_COR_STATUS 0x10 1010#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 1011#define PCIM_AER_COR_BAD_TLP 0x00000040 1012#define PCIM_AER_COR_BAD_DLLP 0x00000080 1013#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 1014#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 1015#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 1016#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 1017#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 1018#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 1019#define PCIR_AER_CAP_CONTROL 0x18 1020#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 1021#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 1022#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 1023#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 1024#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 1025#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 1026#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 1027#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 1028#define PCIR_AER_HEADER_LOG 0x1c 1029#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 1030#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 1031#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 1032#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 1033#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 1034#define PCIM_AER_ROOTERR_COR_ERR 0x00000001 1035#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 1036#define PCIM_AER_ROOTERR_UC_ERR 0x00000004 1037#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 1038#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 1039#define PCIM_AER_ROOTERR_NF_ERR 0x00000020 1040#define PCIM_AER_ROOTERR_F_ERR 0x00000040 1041#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 1042#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 1043#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 1044#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 1045 1046/* Virtual Channel definitions */ 1047#define PCIR_VC_CAP1 0x04 1048#define PCIM_VC_CAP1_EXT_COUNT 0x00000007 1049#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 1050#define PCIR_VC_CAP2 0x08 1051#define PCIR_VC_CONTROL 0x0C 1052#define PCIR_VC_STATUS 0x0E 1053#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 1054#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 1055#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 1056 1057/* Serial Number definitions */ 1058#define PCIR_SERIAL_LOW 0x04 1059#define PCIR_SERIAL_HIGH 0x08 1060 1061/* SR-IOV definitions */ 1062#define PCIR_SRIOV_CTL 0x08 1063#define PCIM_SRIOV_VF_EN 0x01 1064#define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */ 1065#define PCIM_SRIOV_ARI_EN 0x10 1066#define PCIR_SRIOV_TOTAL_VFS 0x0E 1067#define PCIR_SRIOV_NUM_VFS 0x10 1068#define PCIR_SRIOV_VF_OFF 0x14 1069#define PCIR_SRIOV_VF_STRIDE 0x16 1070#define PCIR_SRIOV_VF_DID 0x1A 1071#define PCIR_SRIOV_PAGE_CAP 0x1C 1072#define PCIR_SRIOV_PAGE_SIZE 0x20 1073 1074#define PCI_SRIOV_BASE_PAGE_SHIFT 12 1075 1076#define PCIR_SRIOV_BARS 0x24 1077#define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4) 1078 1079/* Extended Capability Vendor-Specific definitions */ 1080#define PCIR_VSEC_HEADER 0x04 1081#define PCIR_VSEC_ID(hdr) ((hdr) & 0xffff) 1082#define PCIR_VSEC_REV(hdr) (((hdr) & 0xf0000) >> 16) 1083#define PCIR_VSEC_LENGTH(hdr) (((hdr) & 0xfff00000) >> 20) 1084#define PCIR_VSEC_DATA 0x08 1085 1086/* 1087 * PCI Express Firmware Interface definitions 1088 */ 1089#define PCI_OSC_STATUS 0 1090#define PCI_OSC_SUPPORT 1 1091#define PCIM_OSC_SUPPORT_EXT_PCI_CONF 0x01 /* Extended PCI Config Space */ 1092#define PCIM_OSC_SUPPORT_ASPM 0x02 /* Active State Power Management */ 1093#define PCIM_OSC_SUPPORT_CPMC 0x04 /* Clock Power Management Cap */ 1094#define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */ 1095#define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */ 1096#define PCI_OSC_CTL 2 1097#define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */ 1098#define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */ 1099#define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */ 1100#define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */ 1101#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */ 1102 1103/* Access Control Services (ACS) definitions */ 1104#define PCIR_ACS_CAP 0x4 1105#define PCIM_ACS_SOURCE_VALIDATION 0x0001 1106#define PCIM_ACS_TRANSLATION_BLOCKING 0x0002 1107#define PCIM_ACS_P2P_REQ_REDIRECT 0x0004 1108#define PCIM_ACS_P2P_CMP_REDIRECT 0x0008 1109#define PCIM_ACS_P2P_UPSTREAM_FORWARDING 0x0010 1110#define PCIM_ACS_P2P_EGRESS_CTL 0x0020 1111#define PCIM_ACS_P2P_DIRECT_TRANSLATED 0x0040 1112#define PCIM_ACS_ENHANCED_CAP 0x0080 1113#define PCIM_ACS_EGRESS_CTL_VECTOR_SIZE 0xff00 1114#define PCIR_ACS_CTL 0x6 1115#define PCIM_ACS_SOURCE_VALIDATION_ENABLE 0x0001 1116#define PCIM_ACS_TRANSLATION_BLOCKING_ENABLE 0x0002 1117#define PCIM_ACS_P2P_REQ_REDIRECT_ENABLE 0x0004 1118#define PCIM_ACS_P2P_CMP_REDIRECT_ENABLE 0x0008 1119#define PCIM_ACS_P2P_UPSTREAM_FORWARDING_ENABLE 0x0010 1120#define PCIM_ACS_P2P_EGRESS_CTL_ENABLE 0x0020 1121#define PCIM_ACS_P2P_DIRECT_TRANSLATED_ENABLE 0x0040 1122#define PCIM_ACS_IO_REQ_BLOCKING_ENABLE 0x0080 1123#define PCIM_ACS_DSP_MEM_TGT_ACC_CTL 0x0300 1124#define PCIM_ACS_USP_MEM_TGT_ACC_CTL 0x0c00 1125#define PCIM_ACS_UNCLAIMED_REQ_REDIRECT_CTL 0x1000 1126#define PCIR_ACS_EGRESS_CONTROL_VECTOR 0x8 1127 1128/* 1129 * AMD IOMMU Base Capability 1130 * From AMD I/O Virtualization Technology (IOMMU) Specification 1131 * Publication # 48882 Revision: 3.09-PUB Date: October 2023 1132 */ 1133#define PCIR_AMDIOMMU_CAP_HEADER 0x0000 1134#define PCIR_AMDIOMMU_BASE_LOW 0x0004 1135#define PCIR_AMDIOMMU_BASE_HIGH 0x0008 1136#define PCIR_AMDIOMMU_RANGE 0x000c 1137#define PCIR_AMDIOMMU_MISC0 0x0010 1138#define PCIR_AMDIOMMU_MISC1 0x0014 1139 1140#define PCIM_AMDIOMMU_CAP_CAPEXT (1 << 28) 1141#define PCIM_AMDIOMMU_CAP_EFR (1 << 27) 1142#define PCIM_AMDIOMMU_CAP_NPCACHE (1 << 26) 1143#define PCIM_AMDIOMMU_CAP_HTTUN (1 << 25) 1144#define PCIM_AMDIOMMU_CAP_IOTLB (1 << 24) 1145#define PCIM_AMDIOMMU_CAP_REV_MASK (0x1f << 19) 1146#define PCIM_AMDIOMMU_CAP_REV_VAL (0x1 << 19) 1147#define PCIM_AMDIOMMU_CAP_TYPE_MASK (7 << 16) 1148#define PCIM_AMDIOMMU_CAP_TYPE_VAL (0x3 << 16) 1149 1150#define PCIM_AMDIOMMU_BASE_LOW_EN 0x00000001 1151#define PCIM_AMDIOMMU_BASE_LOW_ADDRM 0xffffc000 1152 1153#define PCIM_AMDIOMMU_RANGE_UNITID_MASK 0x1f 1154#define PCIM_AMDIOMMU_RANGE_RNGVALID (1 << 7) 1155#define PCIM_AMDIOMMU_RANGE_BUSNUM_MASK (0xffffu << 8) 1156#define PCIM_AMDIOMMU_RANGE_FIRSTDEV_MASK (0xffffu << 16) 1157#define PCIM_AMDIOMMU_RANGE_LASTDEV_MASK (0xffffu << 24) 1158 1159#define PCIM_AMDIOMMU_MISC0_MSINUMPPR_MASK (0x1f << 27) 1160#define PCIM_AMDIOMMU_MISC0_HTATSRESV (1 << 22) 1161#define PCIM_AMDIOMMU_MISC0_VASIZE_MASK (0x7f << 15) 1162#define PCIM_AMDIOMMU_MISC0_PASIZE_MASK (0x7f << 8) 1163#define PCIM_AMDIOMMU_MISC0_GVASIZE_MASK (0x3 << 5) 1164#define PCIM_AMDIOMMU_MISC0_MSINUM_MASK 0x1f 1165 1166#define PCIM_AMDIOMMU_MISC0_VASIZE_32 (0x20 << 15) 1167#define PCIM_AMDIOMMU_MISC0_VASIZE_40 (0x28 << 15) 1168#define PCIM_AMDIOMMU_MISC0_VASIZE_48 (0x30 << 15) 1169#define PCIM_AMDIOMMU_MISC0_VASIZE_64 (0x40 << 15) 1170 1171#define PCIM_AMDIOMMU_MISC0_PASIZE_40 (0x28 << 8) 1172#define PCIM_AMDIOMMU_MISC0_PASIZE_48 (0x30 << 8) 1173#define PCIM_AMDIOMMU_MISC0_PASIZE_52 (0x34 << 8) 1174 1175#define PCIM_AMDIOMMU_MISC0_GVASIZE_48 (0x2 << 5) 1176#define PCIM_AMDIOMMU_MISC0_GVASIZE_57 (0x3 << 5) 1177 1178#define PCIM_AMDIOMMU_MISC1_MSINUMGA_MASK 0x1f 1179 1180#endif /* __PCI_PCIREG_H */ 1181