1/******************************************************************************
2
3  Copyright (c) 2013-2018, Intel Corporation
4  All rights reserved.
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6  Redistribution and use in source and binary forms, with or without
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10      this list of conditions and the following disclaimer.
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32******************************************************************************/
33
34#ifndef _IXL_IW_H_
35#define _IXL_IW_H_
36
37#define IXL_IW_MAX_USER_PRIORITY 8
38#define IXL_IW_MAX_MSIX	64
39
40struct ixl_iw_msix_mapping {
41	u8	itr_indx;
42	int	aeq_vector;
43	int	ceq_cnt;
44	int	*ceq_vector;
45};
46
47struct ixl_iw_msix {
48	int	base;
49	int	count;
50};
51
52struct ixl_iw_pf {
53	void		*handle;
54	if_t		ifp;
55	device_t	dev;
56	struct resource	*pci_mem;
57	u8		pf_id;
58	u16		mtu;
59	struct ixl_iw_msix	iw_msix;
60	u16	qs_handle[IXL_IW_MAX_USER_PRIORITY];
61};
62
63struct ixl_iw_ops {
64	int (*init)(struct ixl_iw_pf *pf_info);
65	int (*stop)(struct ixl_iw_pf *pf_info);
66};
67
68int	ixl_iw_pf_reset(void *pf_handle);
69int	ixl_iw_pf_msix_init(void *pf_handle,
70	    struct ixl_iw_msix_mapping *msix_info);
71int	ixl_iw_register(struct ixl_iw_ops *iw_ops);
72int	ixl_iw_unregister(void);
73
74#endif /* _IXL_IW_H_ */
75