1/*-
2 * Instruction formats for the sequencer program downloaded to
3 * Aic7xxx SCSI host adapters
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Copyright (c) 1997, 1998, 2000 Justin T. Gibbs.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions, and the following disclaimer,
15 *    without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 *    substantially similar to the "NO WARRANTY" disclaimer below
18 *    ("Disclaimer") and any redistribution must be conditioned upon
19 *    including a substantially similar Disclaimer requirement for further
20 *    binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 *    of any contributors may be used to endorse or promote products derived
23 *    from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aicasm/aicasm_insformat.h#11 $
43 */
44
45struct ins_format1 {
46#if BYTE_ORDER == LITTLE_ENDIAN
47	uint32_t	immediate	: 8,
48			source		: 9,
49			destination	: 9,
50			ret		: 1,
51			opcode		: 4,
52			parity		: 1;
53#else
54	uint32_t	parity		: 1,
55			opcode		: 4,
56			ret		: 1,
57			destination	: 9,
58			source		: 9,
59			immediate	: 8;
60#endif
61};
62
63struct ins_format2 {
64#if BYTE_ORDER == LITTLE_ENDIAN
65	uint32_t	shift_control	: 8,
66			source		: 9,
67			destination	: 9,
68			ret		: 1,
69			opcode		: 4,
70			parity		: 1;
71#else
72	uint32_t	parity		: 1,
73			opcode		: 4,
74			ret		: 1,
75			destination	: 9,
76			source		: 9,
77			shift_control	: 8;
78#endif
79};
80
81struct ins_format3 {
82#if BYTE_ORDER == LITTLE_ENDIAN
83	uint32_t	immediate	: 8,
84			source		: 9,
85			address		: 10,
86			opcode		: 4,
87			parity		: 1;
88#else
89	uint32_t	parity		: 1,
90			opcode		: 4,
91			address		: 10,
92			source		: 9,
93			immediate	: 8;
94#endif
95};
96
97union ins_formats {
98		struct ins_format1 format1;
99		struct ins_format2 format2;
100		struct ins_format3 format3;
101		uint8_t		   bytes[4];
102		uint32_t	   integer;
103};
104struct instruction {
105	union	ins_formats format;
106	u_int	srcline;
107	struct symbol *patch_label;
108	STAILQ_ENTRY(instruction) links;
109};
110
111#define	AIC_OP_OR	0x0
112#define	AIC_OP_AND	0x1
113#define AIC_OP_XOR	0x2
114#define	AIC_OP_ADD	0x3
115#define	AIC_OP_ADC	0x4
116#define	AIC_OP_ROL	0x5
117#define	AIC_OP_BMOV	0x6
118
119#define	AIC_OP_JMP	0x8
120#define AIC_OP_JC	0x9
121#define AIC_OP_JNC	0xa
122#define AIC_OP_CALL	0xb
123#define	AIC_OP_JNE	0xc
124#define	AIC_OP_JNZ	0xd
125#define	AIC_OP_JE	0xe
126#define	AIC_OP_JZ	0xf
127
128/* Pseudo Ops */
129#define	AIC_OP_SHL	0x10
130#define	AIC_OP_SHR	0x20
131#define	AIC_OP_ROR	0x30
132