1254885Sdumbbell// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2254885Sdumbbell/* 3254885Sdumbbell * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4254885Sdumbbell */ 5254885Sdumbbell 6254885Sdumbbell#include "rk3588s.dtsi" 7254885Sdumbbell#include "rk3588-pinctrl.dtsi" 8254885Sdumbbell 9254885Sdumbbell/ { 10254885Sdumbbell pcie30_phy_grf: syscon@fd5b8000 { 11254885Sdumbbell compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 12254885Sdumbbell reg = <0x0 0xfd5b8000 0x0 0x10000>; 13254885Sdumbbell }; 14254885Sdumbbell 15254885Sdumbbell pipe_phy1_grf: syscon@fd5c0000 { 16254885Sdumbbell compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 17254885Sdumbbell reg = <0x0 0xfd5c0000 0x0 0x100>; 18254885Sdumbbell }; 19254885Sdumbbell 20254885Sdumbbell i2s8_8ch: i2s@fddc8000 { 21254885Sdumbbell compatible = "rockchip,rk3588-i2s-tdm"; 22254885Sdumbbell reg = <0x0 0xfddc8000 0x0 0x1000>; 23254885Sdumbbell interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 24254885Sdumbbell clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 25254885Sdumbbell clock-names = "mclk_tx", "mclk_rx", "hclk"; 26254885Sdumbbell assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 27254885Sdumbbell assigned-clock-parents = <&cru PLL_AUPLL>; 28254885Sdumbbell dmas = <&dmac2 22>; 29254885Sdumbbell dma-names = "tx"; 30254885Sdumbbell power-domains = <&power RK3588_PD_VO0>; 31254885Sdumbbell resets = <&cru SRST_M_I2S8_8CH_TX>; 32254885Sdumbbell reset-names = "tx-m"; 33254885Sdumbbell #sound-dai-cells = <0>; 34254885Sdumbbell status = "disabled"; 35254885Sdumbbell }; 36254885Sdumbbell 37254885Sdumbbell i2s6_8ch: i2s@fddf4000 { 38254885Sdumbbell compatible = "rockchip,rk3588-i2s-tdm"; 39254885Sdumbbell reg = <0x0 0xfddf4000 0x0 0x1000>; 40254885Sdumbbell interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 41254885Sdumbbell clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 42254885Sdumbbell clock-names = "mclk_tx", "mclk_rx", "hclk"; 43254885Sdumbbell assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 44254885Sdumbbell assigned-clock-parents = <&cru PLL_AUPLL>; 45254885Sdumbbell dmas = <&dmac2 4>; 46254885Sdumbbell dma-names = "tx"; 47254885Sdumbbell power-domains = <&power RK3588_PD_VO1>; 48282199Sdumbbell resets = <&cru SRST_M_I2S6_8CH_TX>; 49254885Sdumbbell reset-names = "tx-m"; 50254885Sdumbbell #sound-dai-cells = <0>; 51254885Sdumbbell status = "disabled"; 52254885Sdumbbell }; 53254885Sdumbbell 54254885Sdumbbell i2s7_8ch: i2s@fddf8000 { 55254885Sdumbbell compatible = "rockchip,rk3588-i2s-tdm"; 56254885Sdumbbell reg = <0x0 0xfddf8000 0x0 0x1000>; 57254885Sdumbbell interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 58254885Sdumbbell clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 59254885Sdumbbell clock-names = "mclk_tx", "mclk_rx", "hclk"; 60254885Sdumbbell assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 61254885Sdumbbell assigned-clock-parents = <&cru PLL_AUPLL>; 62254885Sdumbbell dmas = <&dmac2 21>; 63254885Sdumbbell dma-names = "rx"; 64254885Sdumbbell power-domains = <&power RK3588_PD_VO1>; 65254885Sdumbbell resets = <&cru SRST_M_I2S7_8CH_RX>; 66254885Sdumbbell reset-names = "rx-m"; 67254885Sdumbbell #sound-dai-cells = <0>; 68254885Sdumbbell status = "disabled"; 69254885Sdumbbell }; 70254885Sdumbbell 71254885Sdumbbell i2s10_8ch: i2s@fde00000 { 72254885Sdumbbell compatible = "rockchip,rk3588-i2s-tdm"; 73254885Sdumbbell reg = <0x0 0xfde00000 0x0 0x1000>; 74254885Sdumbbell interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 75254885Sdumbbell clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 76254885Sdumbbell clock-names = "mclk_tx", "mclk_rx", "hclk"; 77254885Sdumbbell assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 78254885Sdumbbell assigned-clock-parents = <&cru PLL_AUPLL>; 79254885Sdumbbell dmas = <&dmac2 24>; 80254885Sdumbbell dma-names = "rx"; 81254885Sdumbbell power-domains = <&power RK3588_PD_VO1>; 82254885Sdumbbell resets = <&cru SRST_M_I2S10_8CH_RX>; 83254885Sdumbbell reset-names = "rx-m"; 84254885Sdumbbell #sound-dai-cells = <0>; 85254885Sdumbbell status = "disabled"; 86254885Sdumbbell }; 87254885Sdumbbell 88254885Sdumbbell pcie3x4: pcie@fe150000 { 89254885Sdumbbell compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 90254885Sdumbbell #address-cells = <3>; 91254885Sdumbbell #size-cells = <2>; 92254885Sdumbbell bus-range = <0x00 0x0f>; 93254885Sdumbbell clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 94254885Sdumbbell <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 95254885Sdumbbell <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 96254885Sdumbbell clock-names = "aclk_mst", "aclk_slv", 97254885Sdumbbell "aclk_dbi", "pclk", 98254885Sdumbbell "aux", "pipe"; 99254885Sdumbbell device_type = "pci"; 100254885Sdumbbell interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 101254885Sdumbbell <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 102254885Sdumbbell <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 103254885Sdumbbell <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 104254885Sdumbbell <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 105254885Sdumbbell interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 106254885Sdumbbell #interrupt-cells = <1>; 107254885Sdumbbell interrupt-map-mask = <0 0 0 7>; 108254885Sdumbbell interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 109254885Sdumbbell <0 0 0 2 &pcie3x4_intc 1>, 110254885Sdumbbell <0 0 0 3 &pcie3x4_intc 2>, 111254885Sdumbbell <0 0 0 4 &pcie3x4_intc 3>; 112254885Sdumbbell linux,pci-domain = <0>; 113254885Sdumbbell max-link-speed = <3>; 114254885Sdumbbell msi-map = <0x0000 &its1 0x0000 0x1000>; 115254885Sdumbbell num-lanes = <4>; 116254885Sdumbbell phys = <&pcie30phy>; 117254885Sdumbbell phy-names = "pcie-phy"; 118254885Sdumbbell power-domains = <&power RK3588_PD_PCIE>; 119254885Sdumbbell ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 120254885Sdumbbell <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 121254885Sdumbbell <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; 122254885Sdumbbell reg = <0xa 0x40000000 0x0 0x00400000>, 123254885Sdumbbell <0x0 0xfe150000 0x0 0x00010000>, 124254885Sdumbbell <0x0 0xf0000000 0x0 0x00100000>; 125254885Sdumbbell reg-names = "dbi", "apb", "config"; 126254885Sdumbbell resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 127254885Sdumbbell reset-names = "pwr", "pipe"; 128254885Sdumbbell status = "disabled"; 129254885Sdumbbell 130254885Sdumbbell pcie3x4_intc: legacy-interrupt-controller { 131254885Sdumbbell interrupt-controller; 132254885Sdumbbell #address-cells = <0>; 133254885Sdumbbell #interrupt-cells = <1>; 134254885Sdumbbell interrupt-parent = <&gic>; 135254885Sdumbbell interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 136254885Sdumbbell }; 137254885Sdumbbell }; 138254885Sdumbbell 139254885Sdumbbell pcie3x2: pcie@fe160000 { 140254885Sdumbbell compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 141254885Sdumbbell #address-cells = <3>; 142254885Sdumbbell #size-cells = <2>; 143254885Sdumbbell bus-range = <0x10 0x1f>; 144254885Sdumbbell clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 145254885Sdumbbell <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 146254885Sdumbbell <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 147254885Sdumbbell clock-names = "aclk_mst", "aclk_slv", 148254885Sdumbbell "aclk_dbi", "pclk", 149254885Sdumbbell "aux", "pipe"; 150254885Sdumbbell device_type = "pci"; 151254885Sdumbbell interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 152254885Sdumbbell <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 153254885Sdumbbell <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 154254885Sdumbbell <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 155254885Sdumbbell <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 156254885Sdumbbell interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 157254885Sdumbbell #interrupt-cells = <1>; 158254885Sdumbbell interrupt-map-mask = <0 0 0 7>; 159254885Sdumbbell interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 160254885Sdumbbell <0 0 0 2 &pcie3x2_intc 1>, 161254885Sdumbbell <0 0 0 3 &pcie3x2_intc 2>, 162254885Sdumbbell <0 0 0 4 &pcie3x2_intc 3>; 163254885Sdumbbell linux,pci-domain = <1>; 164254885Sdumbbell max-link-speed = <3>; 165254885Sdumbbell msi-map = <0x1000 &its1 0x1000 0x1000>; 166254885Sdumbbell num-lanes = <2>; 167254885Sdumbbell phys = <&pcie30phy>; 168254885Sdumbbell phy-names = "pcie-phy"; 169254885Sdumbbell power-domains = <&power RK3588_PD_PCIE>; 170254885Sdumbbell ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 171254885Sdumbbell <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 172254885Sdumbbell <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; 173254885Sdumbbell reg = <0xa 0x40400000 0x0 0x00400000>, 174254885Sdumbbell <0x0 0xfe160000 0x0 0x00010000>, 175254885Sdumbbell <0x0 0xf1000000 0x0 0x00100000>; 176254885Sdumbbell reg-names = "dbi", "apb", "config"; 177254885Sdumbbell resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 178254885Sdumbbell reset-names = "pwr", "pipe"; 179254885Sdumbbell status = "disabled"; 180254885Sdumbbell 181254885Sdumbbell pcie3x2_intc: legacy-interrupt-controller { 182254885Sdumbbell interrupt-controller; 183254885Sdumbbell #address-cells = <0>; 184254885Sdumbbell #interrupt-cells = <1>; 185254885Sdumbbell interrupt-parent = <&gic>; 186254885Sdumbbell interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 187254885Sdumbbell }; 188254885Sdumbbell }; 189254885Sdumbbell 190254885Sdumbbell pcie2x1l0: pcie@fe170000 { 191254885Sdumbbell compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 192254885Sdumbbell bus-range = <0x20 0x2f>; 193254885Sdumbbell clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 194254885Sdumbbell <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 195254885Sdumbbell <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 196254885Sdumbbell clock-names = "aclk_mst", "aclk_slv", 197254885Sdumbbell "aclk_dbi", "pclk", 198254885Sdumbbell "aux", "pipe"; 199254885Sdumbbell device_type = "pci"; 200254885Sdumbbell interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 201254885Sdumbbell <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 202254885Sdumbbell <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 203254885Sdumbbell <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 204254885Sdumbbell <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 205254885Sdumbbell interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 206254885Sdumbbell #interrupt-cells = <1>; 207254885Sdumbbell interrupt-map-mask = <0 0 0 7>; 208254885Sdumbbell interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 209254885Sdumbbell <0 0 0 2 &pcie2x1l0_intc 1>, 210254885Sdumbbell <0 0 0 3 &pcie2x1l0_intc 2>, 211254885Sdumbbell <0 0 0 4 &pcie2x1l0_intc 3>; 212254885Sdumbbell linux,pci-domain = <2>; 213254885Sdumbbell max-link-speed = <2>; 214254885Sdumbbell msi-map = <0x2000 &its0 0x2000 0x1000>; 215254885Sdumbbell num-lanes = <1>; 216254885Sdumbbell phys = <&combphy1_ps PHY_TYPE_PCIE>; 217254885Sdumbbell phy-names = "pcie-phy"; 218254885Sdumbbell power-domains = <&power RK3588_PD_PCIE>; 219254885Sdumbbell ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 220254885Sdumbbell <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 221254885Sdumbbell <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; 222254885Sdumbbell reg = <0xa 0x40800000 0x0 0x00400000>, 223254885Sdumbbell <0x0 0xfe170000 0x0 0x00010000>, 224254885Sdumbbell <0x0 0xf2000000 0x0 0x00100000>; 225254885Sdumbbell reg-names = "dbi", "apb", "config"; 226254885Sdumbbell resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 227254885Sdumbbell reset-names = "pwr", "pipe"; 228254885Sdumbbell #address-cells = <3>; 229254885Sdumbbell #size-cells = <2>; 230254885Sdumbbell status = "disabled"; 231254885Sdumbbell 232254885Sdumbbell pcie2x1l0_intc: legacy-interrupt-controller { 233254885Sdumbbell interrupt-controller; 234254885Sdumbbell #address-cells = <0>; 235254885Sdumbbell #interrupt-cells = <1>; 236254885Sdumbbell interrupt-parent = <&gic>; 237254885Sdumbbell interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 238254885Sdumbbell }; 239254885Sdumbbell }; 240254885Sdumbbell 241254885Sdumbbell gmac0: ethernet@fe1b0000 { 242254885Sdumbbell compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 243254885Sdumbbell reg = <0x0 0xfe1b0000 0x0 0x10000>; 244254885Sdumbbell interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 245254885Sdumbbell <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 246254885Sdumbbell interrupt-names = "macirq", "eth_wake_irq"; 247254885Sdumbbell clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 248254885Sdumbbell <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 249254885Sdumbbell <&cru CLK_GMAC0_PTP_REF>; 250254885Sdumbbell clock-names = "stmmaceth", "clk_mac_ref", 251254885Sdumbbell "pclk_mac", "aclk_mac", 252254885Sdumbbell "ptp_ref"; 253254885Sdumbbell power-domains = <&power RK3588_PD_GMAC>; 254254885Sdumbbell resets = <&cru SRST_A_GMAC0>; 255254885Sdumbbell reset-names = "stmmaceth"; 256254885Sdumbbell rockchip,grf = <&sys_grf>; 257254885Sdumbbell rockchip,php-grf = <&php_grf>; 258254885Sdumbbell snps,axi-config = <&gmac0_stmmac_axi_setup>; 259254885Sdumbbell snps,mixed-burst; 260254885Sdumbbell snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 261254885Sdumbbell snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 262254885Sdumbbell snps,tso; 263254885Sdumbbell status = "disabled"; 264254885Sdumbbell 265254885Sdumbbell mdio0: mdio { 266254885Sdumbbell compatible = "snps,dwmac-mdio"; 267254885Sdumbbell #address-cells = <0x1>; 268254885Sdumbbell #size-cells = <0x0>; 269254885Sdumbbell }; 270254885Sdumbbell 271254885Sdumbbell gmac0_stmmac_axi_setup: stmmac-axi-config { 272254885Sdumbbell snps,blen = <0 0 0 0 16 8 4>; 273254885Sdumbbell snps,wr_osr_lmt = <4>; 274254885Sdumbbell snps,rd_osr_lmt = <8>; 275254885Sdumbbell }; 276254885Sdumbbell 277254885Sdumbbell gmac0_mtl_rx_setup: rx-queues-config { 278254885Sdumbbell snps,rx-queues-to-use = <2>; 279254885Sdumbbell queue0 {}; 280254885Sdumbbell queue1 {}; 281254885Sdumbbell }; 282254885Sdumbbell 283254885Sdumbbell gmac0_mtl_tx_setup: tx-queues-config { 284254885Sdumbbell snps,tx-queues-to-use = <2>; 285254885Sdumbbell queue0 {}; 286254885Sdumbbell queue1 {}; 287254885Sdumbbell }; 288254885Sdumbbell }; 289254885Sdumbbell 290254885Sdumbbell sata1: sata@fe220000 { 291254885Sdumbbell compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 292254885Sdumbbell reg = <0 0xfe220000 0 0x1000>; 293254885Sdumbbell interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 294254885Sdumbbell clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 295254885Sdumbbell <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 296254885Sdumbbell <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 297254885Sdumbbell clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 298254885Sdumbbell ports-implemented = <0x1>; 299254885Sdumbbell #address-cells = <1>; 300254885Sdumbbell #size-cells = <0>; 301254885Sdumbbell status = "disabled"; 302254885Sdumbbell 303254885Sdumbbell sata-port@0 { 304254885Sdumbbell reg = <0>; 305254885Sdumbbell hba-port-cap = <HBA_PORT_FBSCP>; 306254885Sdumbbell phys = <&combphy1_ps PHY_TYPE_SATA>; 307254885Sdumbbell phy-names = "sata-phy"; 308254885Sdumbbell snps,rx-ts-max = <32>; 309254885Sdumbbell snps,tx-ts-max = <32>; 310254885Sdumbbell }; 311269790Ssbruno }; 312269790Ssbruno 313269790Ssbruno combphy1_ps: phy@fee10000 { 314269790Ssbruno compatible = "rockchip,rk3588-naneng-combphy"; 315269790Ssbruno reg = <0x0 0xfee10000 0x0 0x100>; 316254885Sdumbbell clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 317254885Sdumbbell <&cru PCLK_PHP_ROOT>; 318254885Sdumbbell clock-names = "ref", "apb", "pipe"; 319254885Sdumbbell assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 320254885Sdumbbell assigned-clock-rates = <100000000>; 321254885Sdumbbell #phy-cells = <1>; 322254885Sdumbbell resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 323254885Sdumbbell reset-names = "phy", "apb"; 324254885Sdumbbell rockchip,pipe-grf = <&php_grf>; 325254885Sdumbbell rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 326254885Sdumbbell status = "disabled"; 327254885Sdumbbell }; 328254885Sdumbbell 329254885Sdumbbell pcie30phy: phy@fee80000 { 330254885Sdumbbell compatible = "rockchip,rk3588-pcie3-phy"; 331254885Sdumbbell reg = <0x0 0xfee80000 0x0 0x20000>; 332254885Sdumbbell #phy-cells = <0>; 333254885Sdumbbell clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 334254885Sdumbbell clock-names = "pclk"; 335254885Sdumbbell resets = <&cru SRST_PCIE30_PHY>; 336254885Sdumbbell reset-names = "phy"; 337254885Sdumbbell rockchip,pipe-grf = <&php_grf>; 338254885Sdumbbell rockchip,phy-grf = <&pcie30_phy_grf>; 339254885Sdumbbell status = "disabled"; 340254885Sdumbbell }; 341254885Sdumbbell}; 342254885Sdumbbell