1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2011 5 * Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the company nor the name of the author may be used to 17 * endorse or promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/bus.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/lock.h> 40#include <sys/malloc.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <machine/intr.h> 45 46#include <arm/arm/mpcore_timervar.h> 47#include <arm/ti/tivar.h> 48#include <arm/ti/ti_prcm.h> 49#include <arm/ti/omap4/omap4_reg.h> 50 51#include <dev/ofw/openfirm.h> 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55/* 56 * This file defines the clock configuration for the OMAP4xxx series of 57 * devices. 58 * 59 * How This is Suppose to Work 60 * =========================== 61 * - There is a top level omap_prcm module that defines all OMAP SoC drivers 62 * should use to enable/disable the system clocks regardless of the version 63 * of OMAP device they are running on. This top level PRCM module is just 64 * a thin shim to chip specific functions that perform the donkey work of 65 * configuring the clock - this file is the 'donkey' for OMAP44xx devices. 66 * 67 * - The key bit in this file is the omap_clk_devmap array, it's 68 * used by the omap_prcm driver to determine what clocks are valid and which 69 * functions to call to manipulate them. 70 * 71 * - In essence you just need to define some callbacks for each of the 72 * clocks and then you're done. 73 * 74 * - The other thing that is worth noting is that when the omap_prcm device 75 * is registered you typically pass in some memory ranges which are the 76 * SYS_MEMORY resources. These resources are in turn allocated using 77 * bus_allocate_resources(...) and the resource handles are passed to all 78 * individual clock callback handlers. 79 * 80 * 81 * 82 * OMAP4 devices are different from the previous OMAP3 devices in that there 83 * is no longer a separate functional and interface clock for each module, 84 * instead there is typically an interface clock that spans many modules. 85 */ 86 87#define FREQ_96MHZ 96000000 88#define FREQ_64MHZ 64000000 89#define FREQ_48MHZ 48000000 90#define FREQ_32KHZ 32000 91 92#define PRM_INSTANCE 1 93#define CM1_INSTANCE 2 94#define CM2_INSTANCE 3 95 96/** 97 * Address offsets from the PRM memory region to the top level clock control 98 * registers. 99 */ 100#define CKGEN_PRM_OFFSET 0x00000100UL 101#define MPU_PRM_OFFSET 0x00000300UL 102#define DSP_PRM_OFFSET 0x00000400UL 103#define ABE_PRM_OFFSET 0x00000500UL 104#define ALWAYS_ON_PRM_OFFSET 0x00000600UL 105#define CORE_PRM_OFFSET 0x00000700UL 106#define IVAHD_PRM_OFFSET 0x00000F00UL 107#define CAM_PRM_OFFSET 0x00001000UL 108#define DSS_PRM_OFFSET 0x00001100UL 109#define SGX_PRM_OFFSET 0x00001200UL 110#define L3INIT_PRM_OFFSET 0x00001300UL 111#define L4PER_PRM_OFFSET 0x00001400UL 112#define WKUP_PRM_OFFSET 0x00001700UL 113#define WKUP_CM_OFFSET 0x00001800UL 114#define EMU_PRM_OFFSET 0x00001900UL 115#define EMU_CM_OFFSET 0x00001A00UL 116#define DEVICE_PRM_OFFSET 0x00001B00UL 117#define INSTR_PRM_OFFSET 0x00001F00UL 118 119#define CM_ABE_DSS_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0000UL) 120#define CM_L4_WKUP_CLKSELL_OFFSET (CKGEN_PRM_OFFSET + 0x0008UL) 121#define CM_ABE_PLL_REF_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x000CUL) 122#define CM_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0010UL) 123 124/** 125 * Address offsets from the CM1 memory region to the top level clock control 126 * registers. 127 */ 128#define CKGEN_CM1_OFFSET 0x00000100UL 129#define MPU_CM1_OFFSET 0x00000300UL 130#define DSP_CM1_OFFSET 0x00000400UL 131#define ABE_CM1_OFFSET 0x00000500UL 132#define RESTORE_CM1_OFFSET 0x00000E00UL 133#define INSTR_CM1_OFFSET 0x00000F00UL 134 135#define CM_CLKSEL_DPLL_MPU (CKGEN_CM1_OFFSET + 0x006CUL) 136 137/** 138 * Address offsets from the CM2 memory region to the top level clock control 139 * registers. 140 */ 141#define INTRCONN_SOCKET_CM2_OFFSET 0x00000000UL 142#define CKGEN_CM2_OFFSET 0x00000100UL 143#define ALWAYS_ON_CM2_OFFSET 0x00000600UL 144#define CORE_CM2_OFFSET 0x00000700UL 145#define IVAHD_CM2_OFFSET 0x00000F00UL 146#define CAM_CM2_OFFSET 0x00001000UL 147#define DSS_CM2_OFFSET 0x00001100UL 148#define SGX_CM2_OFFSET 0x00001200UL 149#define L3INIT_CM2_OFFSET 0x00001300UL 150#define L4PER_CM2_OFFSET 0x00001400UL 151#define RESTORE_CM2_OFFSET 0x00001E00UL 152#define INSTR_CM2_OFFSET 0x00001F00UL 153 154#define CLKCTRL_MODULEMODE_MASK 0x00000003UL 155#define CLKCTRL_MODULEMODE_DISABLE 0x00000000UL 156#define CLKCTRL_MODULEMODE_AUTO 0x00000001UL 157#define CLKCTRL_MODULEMODE_ENABLE 0x00000001UL 158 159#define CLKCTRL_IDLEST_MASK 0x00030000UL 160#define CLKCTRL_IDLEST_ENABLED 0x00000000UL 161#define CLKCTRL_IDLEST_WAKING 0x00010000UL 162#define CLKCTRL_IDLEST_IDLE 0x00020000UL 163#define CLKCTRL_IDLEST_DISABLED 0x00030000UL 164 165static struct ofw_compat_data compat_data[] = { 166 {"ti,omap4-cm1", (uintptr_t)CM1_INSTANCE}, 167 {"ti,omap4-cm2", (uintptr_t)CM2_INSTANCE}, 168 {"ti,omap4-prm", (uintptr_t)PRM_INSTANCE}, 169 {NULL, (uintptr_t)0}, 170}; 171 172struct omap4_prcm_softc { 173 struct resource *sc_res; 174 int sc_rid; 175 int sc_instance; 176 int attach_done; 177}; 178 179static int omap4_clk_generic_activate(struct ti_clock_dev *clkdev); 180static int omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev); 181static int omap4_clk_generic_accessible(struct ti_clock_dev *clkdev); 182static int omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 183static int omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 184 185static int omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 186static int omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 187 188static int omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 189static int omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 190 191static int omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 192static int omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev); 193static int omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev); 194static int omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev); 195 196static int omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 197static int omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 198 199/** 200 * omap_clk_devmap - Array of clock devices available on OMAP4xxx devices 201 * 202 * This map only defines which clocks are valid and the callback functions 203 * for clock activate, deactivate, etc. It is used by the top level omap_prcm 204 * driver. 205 * 206 * The actual details of the clocks (config registers, bit fields, sources, 207 * etc) are in the private g_omap3_clk_details array below. 208 * 209 */ 210 211#define OMAP4_GENERIC_CLOCK_DEV(i) \ 212 { .id = (i), \ 213 .clk_activate = omap4_clk_generic_activate, \ 214 .clk_deactivate = omap4_clk_generic_deactivate, \ 215 .clk_set_source = omap4_clk_generic_set_source, \ 216 .clk_accessible = omap4_clk_generic_accessible, \ 217 .clk_get_source_freq = omap4_clk_generic_get_source_freq, \ 218 .clk_set_source_freq = NULL \ 219 } 220 221#define OMAP4_GPTIMER_CLOCK_DEV(i) \ 222 { .id = (i), \ 223 .clk_activate = omap4_clk_generic_activate, \ 224 .clk_deactivate = omap4_clk_generic_deactivate, \ 225 .clk_set_source = omap4_clk_gptimer_set_source, \ 226 .clk_accessible = omap4_clk_generic_accessible, \ 227 .clk_get_source_freq = omap4_clk_gptimer_get_source_freq, \ 228 .clk_set_source_freq = NULL \ 229 } 230 231#define OMAP4_HSMMC_CLOCK_DEV(i) \ 232 { .id = (i), \ 233 .clk_activate = omap4_clk_generic_activate, \ 234 .clk_deactivate = omap4_clk_generic_deactivate, \ 235 .clk_set_source = omap4_clk_hsmmc_set_source, \ 236 .clk_accessible = omap4_clk_generic_accessible, \ 237 .clk_get_source_freq = omap4_clk_hsmmc_get_source_freq, \ 238 .clk_set_source_freq = NULL \ 239 } 240 241#define OMAP4_HSUSBHOST_CLOCK_DEV(i) \ 242 { .id = (i), \ 243 .clk_activate = omap4_clk_hsusbhost_activate, \ 244 .clk_deactivate = omap4_clk_hsusbhost_deactivate, \ 245 .clk_set_source = omap4_clk_hsusbhost_set_source, \ 246 .clk_accessible = omap4_clk_hsusbhost_accessible, \ 247 .clk_get_source_freq = NULL, \ 248 .clk_set_source_freq = NULL \ 249 } 250 251struct ti_clock_dev ti_omap4_clk_devmap[] = { 252 /* System clocks */ 253 { .id = SYS_CLK, 254 .clk_activate = NULL, 255 .clk_deactivate = NULL, 256 .clk_set_source = NULL, 257 .clk_accessible = NULL, 258 .clk_get_source_freq = omap4_clk_get_sysclk_freq, 259 .clk_set_source_freq = NULL, 260 }, 261 /* MPU (ARM) core clocks */ 262 { .id = MPU_CLK, 263 .clk_activate = NULL, 264 .clk_deactivate = NULL, 265 .clk_set_source = NULL, 266 .clk_accessible = NULL, 267 .clk_get_source_freq = omap4_clk_get_arm_fclk_freq, 268 .clk_set_source_freq = NULL, 269 }, 270 271 /* UART device clocks */ 272 OMAP4_GENERIC_CLOCK_DEV(UART1_CLK), 273 OMAP4_GENERIC_CLOCK_DEV(UART2_CLK), 274 OMAP4_GENERIC_CLOCK_DEV(UART3_CLK), 275 OMAP4_GENERIC_CLOCK_DEV(UART4_CLK), 276 277 /* Timer device source clocks */ 278 OMAP4_GPTIMER_CLOCK_DEV(TIMER1_CLK), 279 OMAP4_GPTIMER_CLOCK_DEV(TIMER2_CLK), 280 OMAP4_GPTIMER_CLOCK_DEV(TIMER3_CLK), 281 OMAP4_GPTIMER_CLOCK_DEV(TIMER4_CLK), 282 OMAP4_GPTIMER_CLOCK_DEV(TIMER5_CLK), 283 OMAP4_GPTIMER_CLOCK_DEV(TIMER6_CLK), 284 OMAP4_GPTIMER_CLOCK_DEV(TIMER7_CLK), 285 OMAP4_GPTIMER_CLOCK_DEV(TIMER8_CLK), 286 OMAP4_GPTIMER_CLOCK_DEV(TIMER9_CLK), 287 OMAP4_GPTIMER_CLOCK_DEV(TIMER10_CLK), 288 OMAP4_GPTIMER_CLOCK_DEV(TIMER11_CLK), 289 290 /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */ 291 OMAP4_HSMMC_CLOCK_DEV(MMC1_CLK), 292 OMAP4_HSMMC_CLOCK_DEV(MMC2_CLK), 293 OMAP4_GENERIC_CLOCK_DEV(MMC3_CLK), 294 OMAP4_GENERIC_CLOCK_DEV(MMC4_CLK), 295 OMAP4_GENERIC_CLOCK_DEV(MMC5_CLK), 296 297 /* USB HS (high speed TLL, EHCI and OHCI) */ 298 OMAP4_HSUSBHOST_CLOCK_DEV(USBTLL_CLK), 299 OMAP4_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK), 300 OMAP4_HSUSBHOST_CLOCK_DEV(USBFSHOST_CLK), 301 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_PHY_CLK), 302 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_PHY_CLK), 303 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_UTMI_CLK), 304 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_UTMI_CLK), 305 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_HSIC_CLK), 306 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_HSIC_CLK), 307 308 /* GPIO */ 309 OMAP4_GENERIC_CLOCK_DEV(GPIO1_CLK), 310 OMAP4_GENERIC_CLOCK_DEV(GPIO2_CLK), 311 OMAP4_GENERIC_CLOCK_DEV(GPIO3_CLK), 312 OMAP4_GENERIC_CLOCK_DEV(GPIO4_CLK), 313 OMAP4_GENERIC_CLOCK_DEV(GPIO5_CLK), 314 OMAP4_GENERIC_CLOCK_DEV(GPIO6_CLK), 315 316 /* sDMA */ 317 OMAP4_GENERIC_CLOCK_DEV(SDMA_CLK), 318 319 /* I2C */ 320 OMAP4_GENERIC_CLOCK_DEV(I2C1_CLK), 321 OMAP4_GENERIC_CLOCK_DEV(I2C2_CLK), 322 OMAP4_GENERIC_CLOCK_DEV(I2C3_CLK), 323 OMAP4_GENERIC_CLOCK_DEV(I2C4_CLK), 324 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 325}; 326 327/** 328 * omap4_clk_details - Stores details for all the different clocks supported 329 * 330 * Whenever an operation on a clock is being performed (activated, deactivated, 331 * etc) this array is looked up to find the correct register and bit(s) we 332 * should be modifying. 333 * 334 */ 335struct omap4_clk_details { 336 clk_ident_t id; 337 338 uint32_t instance; 339 uint32_t clksel_reg; 340 341 int32_t src_freq; 342 343 uint32_t enable_mode; 344}; 345 346#define OMAP4_GENERIC_CLOCK_DETAILS(i, f, di, r, e) \ 347 { .id = (i), \ 348 .instance = (di), \ 349 .clksel_reg = (r), \ 350 .src_freq = (f), \ 351 .enable_mode = (e), \ 352 } 353 354static struct omap4_clk_details g_omap4_clk_details[] = { 355 /* UART */ 356 OMAP4_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CM2_INSTANCE, 357 (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE), 358 OMAP4_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CM2_INSTANCE, 359 (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE), 360 OMAP4_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, CM2_INSTANCE, 361 (L4PER_CM2_OFFSET + 0x0150), CLKCTRL_MODULEMODE_ENABLE), 362 OMAP4_GENERIC_CLOCK_DETAILS(UART4_CLK, FREQ_48MHZ, CM2_INSTANCE, 363 (L4PER_CM2_OFFSET + 0x0158), CLKCTRL_MODULEMODE_ENABLE), 364 365 /* General purpose timers */ 366 OMAP4_GENERIC_CLOCK_DETAILS(TIMER1_CLK, -1, PRM_INSTANCE, 367 (WKUP_CM_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 368 OMAP4_GENERIC_CLOCK_DETAILS(TIMER2_CLK, -1, CM2_INSTANCE, 369 (L4PER_CM2_OFFSET + 0x038), CLKCTRL_MODULEMODE_ENABLE), 370 OMAP4_GENERIC_CLOCK_DETAILS(TIMER3_CLK, -1, CM2_INSTANCE, 371 (L4PER_CM2_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 372 OMAP4_GENERIC_CLOCK_DETAILS(TIMER4_CLK, -1, CM2_INSTANCE, 373 (L4PER_CM2_OFFSET + 0x048), CLKCTRL_MODULEMODE_ENABLE), 374 OMAP4_GENERIC_CLOCK_DETAILS(TIMER5_CLK, -1, CM1_INSTANCE, 375 (ABE_CM1_OFFSET + 0x068), CLKCTRL_MODULEMODE_ENABLE), 376 OMAP4_GENERIC_CLOCK_DETAILS(TIMER6_CLK, -1, CM1_INSTANCE, 377 (ABE_CM1_OFFSET + 0x070), CLKCTRL_MODULEMODE_ENABLE), 378 OMAP4_GENERIC_CLOCK_DETAILS(TIMER7_CLK, -1, CM1_INSTANCE, 379 (ABE_CM1_OFFSET + 0x078), CLKCTRL_MODULEMODE_ENABLE), 380 OMAP4_GENERIC_CLOCK_DETAILS(TIMER8_CLK, -1, CM1_INSTANCE, 381 (ABE_CM1_OFFSET + 0x080), CLKCTRL_MODULEMODE_ENABLE), 382 OMAP4_GENERIC_CLOCK_DETAILS(TIMER9_CLK, -1, CM2_INSTANCE, 383 (L4PER_CM2_OFFSET + 0x050), CLKCTRL_MODULEMODE_ENABLE), 384 OMAP4_GENERIC_CLOCK_DETAILS(TIMER10_CLK, -1, CM2_INSTANCE, 385 (L4PER_CM2_OFFSET + 0x028), CLKCTRL_MODULEMODE_ENABLE), 386 OMAP4_GENERIC_CLOCK_DETAILS(TIMER11_CLK, -1, CM2_INSTANCE, 387 (L4PER_CM2_OFFSET + 0x030), CLKCTRL_MODULEMODE_ENABLE), 388 389 /* HSMMC (MMC1 and MMC2 can have different input clocks) */ 390 OMAP4_GENERIC_CLOCK_DETAILS(MMC1_CLK, -1, CM2_INSTANCE, 391 (L3INIT_CM2_OFFSET + 0x028), /*CLKCTRL_MODULEMODE_ENABLE*/2), 392 OMAP4_GENERIC_CLOCK_DETAILS(MMC2_CLK, -1, CM2_INSTANCE, 393 (L3INIT_CM2_OFFSET + 0x030), /*CLKCTRL_MODULEMODE_ENABLE*/2), 394 OMAP4_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_48MHZ, CM2_INSTANCE, 395 (L4PER_CM2_OFFSET + 0x120), /*CLKCTRL_MODULEMODE_ENABLE*/2), 396 OMAP4_GENERIC_CLOCK_DETAILS(MMC4_CLK, FREQ_48MHZ, CM2_INSTANCE, 397 (L4PER_CM2_OFFSET + 0x128), /*CLKCTRL_MODULEMODE_ENABLE*/2), 398 OMAP4_GENERIC_CLOCK_DETAILS(MMC5_CLK, FREQ_48MHZ, CM2_INSTANCE, 399 (L4PER_CM2_OFFSET + 0x160), /*CLKCTRL_MODULEMODE_ENABLE*/1), 400 401 /* GPIO modules */ 402 OMAP4_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, PRM_INSTANCE, 403 (WKUP_CM_OFFSET + 0x038), CLKCTRL_MODULEMODE_AUTO), 404 OMAP4_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, CM2_INSTANCE, 405 (L4PER_CM2_OFFSET + 0x060), CLKCTRL_MODULEMODE_AUTO), 406 OMAP4_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, CM2_INSTANCE, 407 (L4PER_CM2_OFFSET + 0x068), CLKCTRL_MODULEMODE_AUTO), 408 OMAP4_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, CM2_INSTANCE, 409 (L4PER_CM2_OFFSET + 0x070), CLKCTRL_MODULEMODE_AUTO), 410 OMAP4_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, CM2_INSTANCE, 411 (L4PER_CM2_OFFSET + 0x078), CLKCTRL_MODULEMODE_AUTO), 412 OMAP4_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, CM2_INSTANCE, 413 (L4PER_CM2_OFFSET + 0x080), CLKCTRL_MODULEMODE_AUTO), 414 415 /* sDMA block */ 416 OMAP4_GENERIC_CLOCK_DETAILS(SDMA_CLK, -1, CM2_INSTANCE, 417 (CORE_CM2_OFFSET + 0x300), CLKCTRL_MODULEMODE_AUTO), 418 419 /* I2C modules */ 420 OMAP4_GENERIC_CLOCK_DETAILS(I2C1_CLK, -1, CM2_INSTANCE, 421 (L4PER_CM2_OFFSET + 0x0A0), CLKCTRL_MODULEMODE_ENABLE), 422 OMAP4_GENERIC_CLOCK_DETAILS(I2C2_CLK, -1, CM2_INSTANCE, 423 (L4PER_CM2_OFFSET + 0x0A8), CLKCTRL_MODULEMODE_ENABLE), 424 OMAP4_GENERIC_CLOCK_DETAILS(I2C3_CLK, -1, CM2_INSTANCE, 425 (L4PER_CM2_OFFSET + 0x0B0), CLKCTRL_MODULEMODE_ENABLE), 426 OMAP4_GENERIC_CLOCK_DETAILS(I2C4_CLK, -1, CM2_INSTANCE, 427 (L4PER_CM2_OFFSET + 0x0B8), CLKCTRL_MODULEMODE_ENABLE), 428 429 { INVALID_CLK_IDENT, 0, 0, 0, 0 }, 430}; 431 432/** 433 * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come 434 * alive. 435 * 436 */ 437#define MAX_MODULE_ENABLE_WAIT 100 438 439/** 440 * ARRAY_SIZE - Macro to return the number of elements in a static const array. 441 * 442 */ 443#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 444 445/** 446 * omap4_clk_details - writes a 32-bit value to one of the timer registers 447 * @timer: Timer device context 448 * @off: The offset of a register from the timer register address range 449 * @val: The value to write into the register 450 * 451 * 452 * RETURNS: 453 * nothing 454 */ 455static struct omap4_clk_details* 456omap4_clk_details(clk_ident_t id) 457{ 458 struct omap4_clk_details *walker; 459 460 for (walker = g_omap4_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 461 if (id == walker->id) 462 return (walker); 463 } 464 465 return NULL; 466} 467 468static struct omap4_prcm_softc * 469omap4_prcm_get_instance_softc(int module_instance) 470{ 471 int i, maxunit; 472 devclass_t prcm_devclass; 473 device_t dev; 474 struct omap4_prcm_softc *sc; 475 476 prcm_devclass = devclass_find("omap4_prcm"); 477 maxunit = devclass_get_maxunit(prcm_devclass); 478 479 for (i = 0; i < maxunit; i++) { 480 dev = devclass_get_device(prcm_devclass, i); 481 sc = device_get_softc(dev); 482 if (sc->sc_instance == module_instance) 483 return (sc); 484 } 485 486 return (NULL); 487} 488 489/** 490 * omap4_clk_generic_activate - checks if a module is accessible 491 * @module: identifier for the module to check, see omap3_prcm.h for a list 492 * of possible modules. 493 * Example: OMAP3_MODULE_MMC1 494 * 495 * 496 * 497 * LOCKING: 498 * Inherits the locks from the omap_prcm driver, no internal locking. 499 * 500 * RETURNS: 501 * Returns 0 on success or a positive error code on failure. 502 */ 503static int 504omap4_clk_generic_activate(struct ti_clock_dev *clkdev) 505{ 506 struct omap4_prcm_softc *sc; 507 struct omap4_clk_details* clk_details; 508 struct resource* clk_mem_res; 509 uint32_t clksel; 510 unsigned int i; 511 clk_details = omap4_clk_details(clkdev->id); 512 513 if (clk_details == NULL) 514 return (ENXIO); 515 516 sc = omap4_prcm_get_instance_softc(clk_details->instance); 517 if (sc == NULL) 518 return ENXIO; 519 520 clk_mem_res = sc->sc_res; 521 522 if (clk_mem_res == NULL) 523 return (EINVAL); 524 525 /* All the 'generic' clocks have a CLKCTRL register which is more or less 526 * generic - the have at least two fielda called MODULEMODE and IDLEST. 527 */ 528 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 529 clksel &= ~CLKCTRL_MODULEMODE_MASK; 530 clksel |= clk_details->enable_mode; 531 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 532 533 /* Now poll on the IDLEST register to tell us if the module has come up. 534 * TODO: We need to take into account the parent clocks. 535 */ 536 537 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 538 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 539 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 540 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 541 break; 542 DELAY(10); 543 } 544 545 /* Check the enabled state */ 546 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 547 printf("Error: failed to enable module with clock %d\n", clkdev->id); 548 printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel); 549 return (ETIMEDOUT); 550 } 551 552 return (0); 553} 554 555/** 556 * omap4_clk_generic_deactivate - checks if a module is accessible 557 * @module: identifier for the module to check, see omap3_prcm.h for a list 558 * of possible modules. 559 * Example: OMAP3_MODULE_MMC1 560 * 561 * 562 * 563 * LOCKING: 564 * Inherits the locks from the omap_prcm driver, no internal locking. 565 * 566 * RETURNS: 567 * Returns 0 on success or a positive error code on failure. 568 */ 569static int 570omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev) 571{ 572 struct omap4_prcm_softc *sc; 573 struct omap4_clk_details* clk_details; 574 struct resource* clk_mem_res; 575 uint32_t clksel; 576 577 clk_details = omap4_clk_details(clkdev->id); 578 579 if (clk_details == NULL) 580 return (ENXIO); 581 582 sc = omap4_prcm_get_instance_softc(clk_details->instance); 583 if (sc == NULL) 584 return ENXIO; 585 586 clk_mem_res = sc->sc_res; 587 588 if (clk_mem_res == NULL) 589 return (EINVAL); 590 591 /* All the 'generic' clocks have a CLKCTRL register which is more or less 592 * generic - the have at least two fielda called MODULEMODE and IDLEST. 593 */ 594 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 595 clksel &= ~CLKCTRL_MODULEMODE_MASK; 596 clksel |= CLKCTRL_MODULEMODE_DISABLE; 597 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 598 599 return (0); 600} 601 602/** 603 * omap4_clk_generic_set_source - checks if a module is accessible 604 * @module: identifier for the module to check, see omap3_prcm.h for a list 605 * of possible modules. 606 * Example: OMAP3_MODULE_MMC1 607 * 608 * 609 * 610 * LOCKING: 611 * Inherits the locks from the omap_prcm driver, no internal locking. 612 * 613 * RETURNS: 614 * Returns 0 on success or a positive error code on failure. 615 */ 616static int 617omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, 618 clk_src_t clksrc) 619{ 620 621 return (0); 622} 623 624/** 625 * omap4_clk_generic_accessible - checks if a module is accessible 626 * @module: identifier for the module to check, see omap3_prcm.h for a list 627 * of possible modules. 628 * Example: OMAP3_MODULE_MMC1 629 * 630 * 631 * 632 * LOCKING: 633 * Inherits the locks from the omap_prcm driver, no internal locking. 634 * 635 * RETURNS: 636 * Returns 0 on success or a negative error code on failure. 637 */ 638static int 639omap4_clk_generic_accessible(struct ti_clock_dev *clkdev) 640{ 641 struct omap4_prcm_softc *sc; 642 struct omap4_clk_details* clk_details; 643 struct resource* clk_mem_res; 644 uint32_t clksel; 645 646 clk_details = omap4_clk_details(clkdev->id); 647 648 if (clk_details == NULL) 649 return (ENXIO); 650 651 sc = omap4_prcm_get_instance_softc(clk_details->instance); 652 if (sc == NULL) 653 return ENXIO; 654 655 clk_mem_res = sc->sc_res; 656 657 if (clk_mem_res == NULL) 658 return (EINVAL); 659 660 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 661 662 /* Check the enabled state */ 663 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 664 return (0); 665 666 return (1); 667} 668 669/** 670 * omap4_clk_generic_get_source_freq - checks if a module is accessible 671 * @module: identifier for the module to check, see omap3_prcm.h for a list 672 * of possible modules. 673 * Example: OMAP3_MODULE_MMC1 674 * 675 * 676 * 677 * LOCKING: 678 * Inherits the locks from the omap_prcm driver, no internal locking. 679 * 680 * RETURNS: 681 * Returns 0 on success or a negative error code on failure. 682 */ 683static int 684omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, 685 unsigned int *freq 686 ) 687{ 688 struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); 689 690 if (clk_details == NULL) 691 return (ENXIO); 692 693 /* Simply return the stored frequency */ 694 if (freq) 695 *freq = (unsigned int)clk_details->src_freq; 696 697 return (0); 698} 699 700/** 701 * omap4_clk_gptimer_set_source - checks if a module is accessible 702 * @module: identifier for the module to check, see omap3_prcm.h for a list 703 * of possible modules. 704 * Example: OMAP3_MODULE_MMC1 705 * 706 * 707 * 708 * LOCKING: 709 * Inherits the locks from the omap_prcm driver, no internal locking. 710 * 711 * RETURNS: 712 * Returns 0 on success or a negative error code on failure. 713 */ 714static int 715omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, 716 clk_src_t clksrc) 717{ 718 struct omap4_prcm_softc *sc; 719 struct omap4_clk_details* clk_details; 720 struct resource* clk_mem_res; 721 722 clk_details = omap4_clk_details(clkdev->id); 723 724 if (clk_details == NULL) 725 return (ENXIO); 726 727 sc = omap4_prcm_get_instance_softc(clk_details->instance); 728 if (sc == NULL) 729 return ENXIO; 730 731 clk_mem_res = sc->sc_res; 732 733 if (clk_mem_res == NULL) 734 return (EINVAL); 735 736 /* TODO: Implement */ 737 738 return (0); 739} 740 741/** 742 * omap4_clk_gptimer_get_source_freq - checks if a module is accessible 743 * @module: identifier for the module to check, see omap3_prcm.h for a list 744 * of possible modules. 745 * Example: OMAP3_MODULE_MMC1 746 * 747 * 748 * 749 * LOCKING: 750 * Inherits the locks from the omap_prcm driver, no internal locking. 751 * 752 * RETURNS: 753 * Returns 0 on success or a negative error code on failure. 754 */ 755static int 756omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, 757 unsigned int *freq 758 ) 759{ 760 struct omap4_prcm_softc *sc; 761 struct omap4_clk_details* clk_details; 762 struct resource* clk_mem_res; 763 uint32_t clksel; 764 unsigned int src_freq; 765 766 clk_details = omap4_clk_details(clkdev->id); 767 768 if (clk_details == NULL) 769 return (ENXIO); 770 771 sc = omap4_prcm_get_instance_softc(clk_details->instance); 772 if (sc == NULL) 773 return ENXIO; 774 775 clk_mem_res = sc->sc_res; 776 777 if (clk_mem_res == NULL) 778 return (EINVAL); 779 780 /* Need to read the CLKSEL field to determine the clock source */ 781 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 782 if (clksel & (0x1UL << 24)) 783 src_freq = FREQ_32KHZ; 784 else 785 omap4_clk_get_sysclk_freq(NULL, &src_freq); 786 787 /* Return the frequency */ 788 if (freq) 789 *freq = src_freq; 790 791 return (0); 792} 793 794/** 795 * omap4_clk_hsmmc_set_source - sets the source clock (freq) 796 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 797 * 798 * The MMC 1 and 2 clocks can be source from either a 64MHz or 96MHz clock. 799 * 800 * LOCKING: 801 * Inherits the locks from the omap_prcm driver, no internal locking. 802 * 803 * RETURNS: 804 * Returns 0 on success or a negative error code on failure. 805 */ 806static int 807omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, 808 clk_src_t clksrc) 809{ 810 struct omap4_prcm_softc *sc; 811 struct omap4_clk_details* clk_details; 812 struct resource* clk_mem_res; 813 uint32_t clksel; 814 815 clk_details = omap4_clk_details(clkdev->id); 816 817 if (clk_details == NULL) 818 return (ENXIO); 819 820 sc = omap4_prcm_get_instance_softc(clk_details->instance); 821 if (sc == NULL) 822 return ENXIO; 823 824 clk_mem_res = sc->sc_res; 825 826 if (clk_mem_res == NULL) 827 return (EINVAL); 828 829 /* For MMC modules 3, 4 & 5 you can't change the freq, it's always 48MHz */ 830 if ((clkdev->id == MMC3_CLK) || (clkdev->id == MMC4_CLK) || 831 (clkdev->id == MMC5_CLK)) { 832 if (clksrc != F48MHZ_CLK) 833 return (EINVAL); 834 return 0; 835 } 836 837 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 838 839 /* Bit 24 is set if 96MHz clock or cleared for 64MHz clock */ 840 if (clksrc == F64MHZ_CLK) 841 clksel &= ~(0x1UL << 24); 842 else if (clksrc == F96MHZ_CLK) 843 clksel |= (0x1UL << 24); 844 else 845 return (EINVAL); 846 847 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 848 849 return (0); 850} 851 852/** 853 * omap4_clk_hsmmc_get_source_freq - checks if a module is accessible 854 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 855 * 856 * 857 * 858 * LOCKING: 859 * Inherits the locks from the omap_prcm driver, no internal locking. 860 * 861 * RETURNS: 862 * Returns 0 on success or a negative error code on failure. 863 */ 864static int 865omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, 866 unsigned int *freq 867 ) 868{ 869 struct omap4_prcm_softc *sc; 870 struct omap4_clk_details* clk_details; 871 struct resource* clk_mem_res; 872 uint32_t clksel; 873 unsigned int src_freq; 874 875 clk_details = omap4_clk_details(clkdev->id); 876 877 if (clk_details == NULL) 878 return (ENXIO); 879 880 sc = omap4_prcm_get_instance_softc(clk_details->instance); 881 if (sc == NULL) 882 return ENXIO; 883 884 clk_mem_res = sc->sc_res; 885 886 if (clk_mem_res == NULL) 887 return (EINVAL); 888 889 switch (clkdev->id) { 890 case MMC1_CLK: 891 case MMC2_CLK: 892 /* Need to read the CLKSEL field to determine the clock source */ 893 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 894 if (clksel & (0x1UL << 24)) 895 src_freq = FREQ_96MHZ; 896 else 897 src_freq = FREQ_64MHZ; 898 break; 899 case MMC3_CLK: 900 case MMC4_CLK: 901 case MMC5_CLK: 902 src_freq = FREQ_48MHZ; 903 break; 904 default: 905 return (EINVAL); 906 } 907 908 /* Return the frequency */ 909 if (freq) 910 *freq = src_freq; 911 912 return (0); 913} 914 915/** 916 * omap4_clk_get_sysclk_freq - gets the sysclk frequency 917 * @sc: pointer to the clk module/device context 918 * 919 * Read the clocking information from the power-control/boot-strap registers, 920 * and stored in two global variables. 921 * 922 * RETURNS: 923 * nothing, values are saved in global variables 924 */ 925static int 926omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, 927 unsigned int *freq) 928{ 929 uint32_t clksel; 930 uint32_t sysclk; 931 struct omap4_prcm_softc *sc; 932 933 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 934 if (sc == NULL) 935 return ENXIO; 936 937 /* Read the input clock freq from the configuration register (CM_SYS_CLKSEL) */ 938 clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET); 939 switch (clksel & 0x7) { 940 case 0x1: 941 /* 12Mhz */ 942 sysclk = 12000000; 943 break; 944 case 0x3: 945 /* 16.8Mhz */ 946 sysclk = 16800000; 947 break; 948 case 0x4: 949 /* 19.2Mhz */ 950 sysclk = 19200000; 951 break; 952 case 0x5: 953 /* 26Mhz */ 954 sysclk = 26000000; 955 break; 956 case 0x7: 957 /* 38.4Mhz */ 958 sysclk = 38400000; 959 break; 960 default: 961 panic("%s: Invalid clock freq", __func__); 962 } 963 964 /* Return the value */ 965 if (freq) 966 *freq = sysclk; 967 968 return (0); 969} 970 971/** 972 * omap4_clk_get_arm_fclk_freq - gets the MPU clock frequency 973 * @clkdev: ignored 974 * @freq: pointer which upon return will contain the freq in hz 975 * @mem_res: array of allocated memory resources 976 * 977 * Reads the frequency setting information registers and returns the value 978 * in the freq variable. 979 * 980 * RETURNS: 981 * returns 0 on success, a positive error code on failure. 982 */ 983static int 984omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, 985 unsigned int *freq) 986{ 987 uint32_t clksel; 988 uint32_t pll_mult, pll_div; 989 uint32_t mpuclk, sysclk; 990 struct omap4_prcm_softc *sc; 991 992 sc = omap4_prcm_get_instance_softc(CM1_INSTANCE); 993 if (sc == NULL) 994 return ENXIO; 995 996 /* Read the clksel register which contains the DPLL multiple and divide 997 * values. These are applied to the sysclk. 998 */ 999 clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU); 1000 1001 pll_mult = ((clksel >> 8) & 0x7ff); 1002 pll_div = (clksel & 0x7f) + 1; 1003 1004 /* Get the system clock freq */ 1005 omap4_clk_get_sysclk_freq(NULL, &sysclk); 1006 1007 /* Calculate the MPU freq */ 1008 mpuclk = ((uint64_t)sysclk * pll_mult) / pll_div; 1009 1010 /* Return the value */ 1011 if (freq) 1012 *freq = mpuclk; 1013 1014 return (0); 1015} 1016 1017/** 1018 * omap4_clk_hsusbhost_activate - activates the USB clocks for the given module 1019 * @clkdev: pointer to the clock device structure. 1020 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1021 * 1022 * The USB clocking setup seems to be a bit more tricky than the other modules, 1023 * to start with the clocking diagram for the HS host module shows 13 different 1024 * clocks. So to try and make it easier to follow the clocking activation 1025 * and deactivation is handled in its own set of callbacks. 1026 * 1027 * LOCKING: 1028 * Inherits the locks from the omap_prcm driver, no internal locking. 1029 * 1030 * RETURNS: 1031 * Returns 0 on success or a positive error code on failure. 1032 */ 1033 1034struct dpll_param { 1035 unsigned int m; 1036 unsigned int n; 1037 unsigned int m2; 1038 unsigned int m3; 1039 unsigned int m4; 1040 unsigned int m5; 1041 unsigned int m6; 1042 unsigned int m7; 1043}; 1044/* USB parameters */ 1045struct dpll_param usb_dpll_param[7] = { 1046 /* 12M values */ 1047 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1048 /* 13M values */ 1049 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1050 /* 16.8M values */ 1051 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1052 /* 19.2M values */ 1053 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1054 /* 26M values */ 1055 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1056 /* 27M values */ 1057 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1058 /* 38.4M values */ 1059#ifdef CONFIG_OMAP4_SDC 1060 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1061#else 1062 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1063#endif 1064}; 1065static int 1066omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev) 1067{ 1068 struct omap4_prcm_softc *sc; 1069 struct resource* clk_mem_res; 1070 uint32_t clksel_reg_off; 1071 uint32_t clksel; 1072 unsigned int i; 1073 1074 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1075 if (sc == NULL) 1076 return ENXIO; 1077 1078 switch (clkdev->id) { 1079 case USBTLL_CLK: 1080 /* For the USBTLL module we need to enable the following clocks: 1081 * - INIT_L4_ICLK (will be enabled by bootloader) 1082 * - TLL_CH0_FCLK 1083 * - TLL_CH1_FCLK 1084 */ 1085 1086 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1087 clk_mem_res = sc->sc_res; 1088 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1089 1090 /* Enable the module and also enable the optional func clocks for 1091 * channels 0 & 1 (is this needed ?) 1092 */ 1093 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1094 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1095 clksel |= CLKCTRL_MODULEMODE_ENABLE; 1096 1097 clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */ 1098 clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */ 1099 break; 1100 1101 case USBHSHOST_CLK: 1102 case USBP1_PHY_CLK: 1103 case USBP2_PHY_CLK: 1104 case USBP1_UTMI_CLK: 1105 case USBP2_UTMI_CLK: 1106 case USBP1_HSIC_CLK: 1107 case USBP2_HSIC_CLK: 1108 /* For the USB HS HOST module we need to enable the following clocks: 1109 * - INIT_L4_ICLK (will be enabled by bootloader) 1110 * - INIT_L3_ICLK (will be enabled by bootloader) 1111 * - INIT_48MC_FCLK 1112 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1113 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1114 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1115 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1116 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1117 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1118 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1119 */ 1120 1121 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1122 clk_mem_res = sc->sc_res; 1123 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1124 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1125 /* Enable the module and also enable the optional func clocks */ 1126 if (clkdev->id == USBHSHOST_CLK) { 1127 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1128 clksel |= /*CLKCTRL_MODULEMODE_ENABLE*/2; 1129 1130 clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1131 } 1132 1133 else if (clkdev->id == USBP1_UTMI_CLK) 1134 clksel |= (0x1 << 8); /* UTMI_P1_CLK */ 1135 else if (clkdev->id == USBP2_UTMI_CLK) 1136 clksel |= (0x1 << 9); /* UTMI_P2_CLK */ 1137 1138 else if (clkdev->id == USBP1_HSIC_CLK) 1139 clksel |= (0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1140 else if (clkdev->id == USBP2_HSIC_CLK) 1141 clksel |= (0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1142 1143 break; 1144 1145 default: 1146 return (EINVAL); 1147 } 1148 1149 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1150 1151 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 1152 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 1153 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1154 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 1155 break; 1156 } 1157 1158 /* Check the enabled state */ 1159 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 1160 printf("Error: HERE failed to enable module with clock %d\n", clkdev->id); 1161 printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel); 1162 return (ETIMEDOUT); 1163 } 1164 1165 return (0); 1166} 1167 1168/** 1169 * omap4_clk_generic_deactivate - checks if a module is accessible 1170 * @clkdev: pointer to the clock device structure. 1171 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1172 * 1173 * 1174 * 1175 * LOCKING: 1176 * Inherits the locks from the omap_prcm driver, no internal locking. 1177 * 1178 * RETURNS: 1179 * Returns 0 on success or a positive error code on failure. 1180 */ 1181static int 1182omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev) 1183{ 1184 struct omap4_prcm_softc *sc; 1185 struct resource* clk_mem_res; 1186 uint32_t clksel_reg_off; 1187 uint32_t clksel; 1188 1189 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1190 if (sc == NULL) 1191 return ENXIO; 1192 1193 switch (clkdev->id) { 1194 case USBTLL_CLK: 1195 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1196 clk_mem_res = sc->sc_res; 1197 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1198 1199 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1200 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1201 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1202 break; 1203 1204 case USBHSHOST_CLK: 1205 case USBP1_PHY_CLK: 1206 case USBP2_PHY_CLK: 1207 case USBP1_UTMI_CLK: 1208 case USBP2_UTMI_CLK: 1209 case USBP1_HSIC_CLK: 1210 case USBP2_HSIC_CLK: 1211 /* For the USB HS HOST module we need to enable the following clocks: 1212 * - INIT_L4_ICLK (will be enabled by bootloader) 1213 * - INIT_L3_ICLK (will be enabled by bootloader) 1214 * - INIT_48MC_FCLK 1215 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1216 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1217 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1218 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1219 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1220 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1221 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1222 */ 1223 1224 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1225 clk_mem_res = sc->sc_res; 1226 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1227 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1228 1229 /* Enable the module and also enable the optional func clocks */ 1230 if (clkdev->id == USBHSHOST_CLK) { 1231 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1232 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1233 1234 clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1235 } 1236 1237 else if (clkdev->id == USBP1_UTMI_CLK) 1238 clksel &= ~(0x1 << 8); /* UTMI_P1_CLK */ 1239 else if (clkdev->id == USBP2_UTMI_CLK) 1240 clksel &= ~(0x1 << 9); /* UTMI_P2_CLK */ 1241 1242 else if (clkdev->id == USBP1_HSIC_CLK) 1243 clksel &= ~(0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1244 else if (clkdev->id == USBP2_HSIC_CLK) 1245 clksel &= ~(0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1246 1247 break; 1248 1249 default: 1250 return (EINVAL); 1251 } 1252 1253 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1254 1255 return (0); 1256} 1257 1258/** 1259 * omap4_clk_hsusbhost_accessible - checks if a module is accessible 1260 * @clkdev: pointer to the clock device structure. 1261 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1262 * 1263 * 1264 * 1265 * LOCKING: 1266 * Inherits the locks from the omap_prcm driver, no internal locking. 1267 * 1268 * RETURNS: 1269 * Returns 0 if module is not enable, 1 if module is enabled or a negative 1270 * error code on failure. 1271 */ 1272static int 1273omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev) 1274{ 1275 struct omap4_prcm_softc *sc; 1276 struct resource* clk_mem_res; 1277 uint32_t clksel_reg_off; 1278 uint32_t clksel; 1279 1280 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1281 if (sc == NULL) 1282 return ENXIO; 1283 1284 if (clkdev->id == USBTLL_CLK) { 1285 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1286 clk_mem_res = sc->sc_res; 1287 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1288 } 1289 else if (clkdev->id == USBHSHOST_CLK) { 1290 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1291 clk_mem_res = sc->sc_res; 1292 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1293 } 1294 else { 1295 return (EINVAL); 1296 } 1297 1298 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1299 1300 /* Check the enabled state */ 1301 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 1302 return (0); 1303 1304 return (1); 1305} 1306 1307/** 1308 * omap4_clk_hsusbhost_set_source - sets the source clocks 1309 * @clkdev: pointer to the clock device structure. 1310 * @clksrc: the clock source ID for the given clock. 1311 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1312 * 1313 * 1314 * 1315 * LOCKING: 1316 * Inherits the locks from the omap_prcm driver, no internal locking. 1317 * 1318 * RETURNS: 1319 * Returns 0 if successful otherwise a negative error code on failure. 1320 */ 1321static int 1322omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, 1323 clk_src_t clksrc) 1324{ 1325 struct omap4_prcm_softc *sc; 1326 struct resource* clk_mem_res; 1327 uint32_t clksel_reg_off; 1328 uint32_t clksel; 1329 unsigned int bit; 1330 1331 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1332 if (sc == NULL) 1333 return ENXIO; 1334 1335 if (clkdev->id == USBP1_PHY_CLK) 1336 bit = 24; 1337 else if (clkdev->id != USBP2_PHY_CLK) 1338 bit = 25; 1339 else 1340 return (EINVAL); 1341 1342 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1343 clk_mem_res = sc->sc_res; 1344 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1345 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1346 1347 /* Set the clock source to either external or internal */ 1348 if (clksrc == EXT_CLK) 1349 clksel |= (0x1 << bit); 1350 else 1351 clksel &= ~(0x1 << bit); 1352 1353 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1354 1355 return (0); 1356} 1357 1358#define PRM_RSTCTRL 0x1b00 1359#define PRM_RSTCTRL_RESET 0x2 1360 1361static void 1362omap4_prcm_reset(void) 1363{ 1364 struct omap4_prcm_softc *sc; 1365 1366 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 1367 if (sc == NULL) 1368 return; 1369 1370 bus_write_4(sc->sc_res, PRM_RSTCTRL, 1371 bus_read_4(sc->sc_res, PRM_RSTCTRL) | PRM_RSTCTRL_RESET); 1372 bus_read_4(sc->sc_res, PRM_RSTCTRL); 1373} 1374 1375/** 1376 * omap4_prcm_probe - probe function for the driver 1377 * @dev: prcm device handle 1378 * 1379 * Simply sets the name of the driver module. 1380 * 1381 * LOCKING: 1382 * None 1383 * 1384 * RETURNS: 1385 * Always returns 0 1386 */ 1387static int 1388omap4_prcm_probe(device_t dev) 1389{ 1390 const struct ofw_compat_data *ocd; 1391 1392 if (!ofw_bus_status_okay(dev)) 1393 return (ENXIO); 1394 1395 ocd = ofw_bus_search_compatible(dev, compat_data); 1396 if ((int)ocd->ocd_data == 0) 1397 return (ENXIO); 1398 1399 switch ((int)ocd->ocd_data) { 1400 case PRM_INSTANCE: 1401 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (PRM)"); 1402 break; 1403 case CM1_INSTANCE: 1404 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C1)"); 1405 break; 1406 case CM2_INSTANCE: 1407 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C2)"); 1408 break; 1409 default: 1410 device_printf(dev, "unknown instance type: %d\n", (int)ocd->ocd_data); 1411 return (ENXIO); 1412 } 1413 1414 return (BUS_PROBE_DEFAULT); 1415} 1416 1417/** 1418 * omap_prcm_attach - attach function for the driver 1419 * @dev: prcm device handle 1420 * 1421 * Allocates and sets up the driver context, this simply entails creating a 1422 * bus mappings for the PRCM register set. 1423 * 1424 * LOCKING: 1425 * None 1426 * 1427 * RETURNS: 1428 * Always returns 0 1429 */ 1430 1431extern uint32_t platform_arm_tmr_freq; 1432 1433static int 1434omap4_prcm_attach(device_t dev) 1435{ 1436 struct omap4_prcm_softc *sc; 1437 const struct ofw_compat_data *ocd; 1438 1439 sc = device_get_softc(dev); 1440 ocd = ofw_bus_search_compatible(dev, compat_data); 1441 sc->sc_instance = (int)ocd->ocd_data; 1442 1443 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 1444 RF_ACTIVE); 1445 if (sc->sc_res == NULL) { 1446 device_printf(dev, "could not allocate resources\n"); 1447 return (ENXIO); 1448 } 1449 1450 ti_cpu_reset = omap4_prcm_reset; 1451 1452 return (0); 1453} 1454 1455static void 1456omap4_prcm_new_pass(device_t dev) 1457{ 1458 struct omap4_prcm_softc *sc = device_get_softc(dev); 1459 unsigned int freq; 1460 1461 if (sc->attach_done || 1462 bus_current_pass < (BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY)) { 1463 bus_generic_new_pass(dev); 1464 return; 1465 } 1466 sc->attach_done = 1; 1467 1468 /* 1469 * In order to determine ARM frequency we need both RPM and CM1 1470 * instances up and running. So wait until all CRM devices are 1471 * initialized. Should be replaced with proper clock framework 1472 */ 1473 if (device_get_unit(dev) == 2) { 1474 omap4_clk_get_arm_fclk_freq(NULL, &freq); 1475 arm_tmr_change_frequency(freq / 2); 1476 } 1477 1478 return; 1479} 1480 1481static device_method_t omap4_prcm_methods[] = { 1482 DEVMETHOD(device_probe, omap4_prcm_probe), 1483 DEVMETHOD(device_attach, omap4_prcm_attach), 1484 1485 /* Bus interface */ 1486 DEVMETHOD(bus_new_pass, omap4_prcm_new_pass), 1487 1488 {0, 0}, 1489}; 1490 1491static driver_t omap4_prcm_driver = { 1492 "omap4_prcm", 1493 omap4_prcm_methods, 1494 sizeof(struct omap4_prcm_softc), 1495}; 1496 1497EARLY_DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver, 0, 0, 1498 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1499MODULE_VERSION(omap4_prcm, 1); 1500