1/*- 2 * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#ifndef _A10_DMAC_H_ 28#define _A10_DMAC_H_ 29 30#define AWIN_DMA_IRQ_EN_REG 0x0000 31#define AWIN_DMA_IRQ_PEND_STA_REG 0x0004 32#define AWIN_NDMA_AUTO_GATE_REG 0x0008 33#define AWIN_NDMA_REG(n) (0x100+0x20*(n)) 34#define AWIN_NDMA_CTL_REG 0x0000 35#define AWIN_NDMA_SRC_ADDR_REG 0x0004 36#define AWIN_NDMA_DEST_ADDR_REG 0x0008 37#define AWIN_NDMA_BC_REG 0x000c 38#define AWIN_DDMA_REG(n) (0x300+0x20*(n)) 39#define AWIN_DDMA_CTL_REG 0x0000 40#define AWIN_DDMA_SRC_START_ADDR_REG 0x0004 41#define AWIN_DDMA_DEST_START_ADDR_REG 0x0008 42#define AWIN_DDMA_BC_REG 0x000c 43#define AWIN_DDMA_PARA_REG 0x0018 44#define AWIN_DMA_IRQ_END_MASK 0xaaaaaaaa 45#define AWIN_DMA_IRQ_HF_MASK 0x55555555 46#define AWIN_DMA_IRQ_DDMA 0xffff0000 47#define AWIN_DMA_IRQ_DDMA_END(n) (1U << (17+2*(n))) 48#define AWIN_DMA_IRQ_DDMA_HF(n) (1U << (16+2*(n))) 49#define AWIN_DMA_IRQ_NDMA 0x0000ffff 50#define AWIN_DMA_IRQ_NDMA_END(n) (1U << (1+2*(n))) 51#define AWIN_DMA_IRQ_NDMA_HF(n) (1U << (0+2*(n))) 52#define AWIN_NDMA_AUTO_GATING_DIS (1U << 16) 53#define AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT 25 54#define AWIN_DMA_CTL_DST_DATA_WIDTH_MASK (3U << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) 55#define AWIN_DMA_CTL_DATA_WIDTH_8 0 56#define AWIN_DMA_CTL_DATA_WIDTH_16 1 57#define AWIN_DMA_CTL_DATA_WIDTH_32 2 58#define AWIN_DMA_CTL_DST_BURST_LEN_SHIFT 23 59#define AWIN_DMA_CTL_DST_BURST_LEN_MASK (3 << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) 60#define AWIN_DMA_CTL_BURST_LEN_1 0 61#define AWIN_DMA_CTL_BURST_LEN_4 1 62#define AWIN_DMA_CTL_BURST_LEN_8 2 63#define AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT 16 64#define AWIN_DMA_CTL_DST_DRQ_TYPE_MASK (0x1f << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) 65#define AWIN_DMA_CTL_BC_REMAINING (1U << 15) 66#define AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT 9 67#define AWIN_DMA_CTL_SRC_DATA_WIDTH_MASK (3U << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) 68#define AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT 7 69#define AWIN_DMA_CTL_SRC_BURST_LEN_MASK (3U << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) 70#define AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT 0 71#define AWIN_DMA_CTL_SRC_DRQ_TYPE_MASK (0x1f << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT) 72#define AWIN_NDMA_CTL_DMA_LOADING (1U << 31) 73#define AWIN_NDMA_CTL_DMA_CONTIN_MODE (1U << 30) 74#define AWIN_NDMA_CTL_WAIT_STATE_LOG2_SHIFT 27 75#define AWIN_NDMA_CTL_WAIT_STATE_LOG2_MASK (7U << AWIN_NDMA_CTL_WAIT_STATE_LOG2_SHIFT) 76#define AWIN_NDMA_CTL_DST_NON_SECURE (1U << 22) 77#define AWIN_NDMA_CTL_DST_ADDR_NOINCR (1U << 21) 78#define AWIN_NDMA_CTL_DRQ_IRO 0 79#define AWIN_NDMA_CTL_DRQ_IR1 1 80#define AWIN_NDMA_CTL_DRQ_SPDIF 2 81#define AWIN_NDMA_CTL_DRQ_IISO 3 82#define AWIN_NDMA_CTL_DRQ_IIS1 4 83#define AWIN_NDMA_CTL_DRQ_AC97 5 84#define AWIN_NDMA_CTL_DRQ_IIS2 6 85#define AWIN_NDMA_CTL_DRQ_UARTO 8 86#define AWIN_NDMA_CTL_DRQ_UART1 9 87#define AWIN_NDMA_CTL_DRQ_UART2 10 88#define AWIN_NDMA_CTL_DRQ_UART3 11 89#define AWIN_NDMA_CTL_DRQ_UART4 12 90#define AWIN_NDMA_CTL_DRQ_UART5 13 91#define AWIN_NDMA_CTL_DRQ_UART6 14 92#define AWIN_NDMA_CTL_DRQ_UART7 15 93#define AWIN_NDMA_CTL_DRQ_DDC 16 94#define AWIN_NDMA_CTL_DRQ_USB_EP1 17 95#define AWIN_NDMA_CTL_DRQ_CODEC 19 96#define AWIN_NDMA_CTL_DRQ_SRAM 21 97#define AWIN_NDMA_CTL_DRQ_SDRAM 22 98#define AWIN_NDMA_CTL_DRQ_TP_AD 23 99#define AWIN_NDMA_CTL_DRQ_SPI0 24 100#define AWIN_NDMA_CTL_DRQ_SPI1 25 101#define AWIN_NDMA_CTL_DRQ_SPI2 26 102#define AWIN_NDMA_CTL_DRQ_SPI3 27 103#define AWIN_NDMA_CTL_DRQ_USB_EP2 28 104#define AWIN_NDMA_CTL_DRQ_USB_EP3 29 105#define AWIN_NDMA_CTL_DRQ_USB_EP4 30 106#define AWIN_NDMA_CTL_DRQ_USB_EP5 31 107#define AWIN_NDMA_CTL_SRC_NON_SECURE (1U << 6) 108#define AWIN_NDMA_CTL_SRC_ADDR_NOINCR (1U << 5) 109#define AWIN_NDMA_BC_COUNT 0x0003ffff 110#define AWIN_DDMA_CTL_DMA_LOADING (1U << 31) 111#define AWIN_DDMA_CTL_BUSY (1U << 30) 112#define AWIN_DDMA_CTL_DMA_CONTIN_MODE (1U << 29) 113#define AWIN_DDMA_CTL_DST_NON_SECURE (1U << 28) 114#define AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT 21 115#define AWIN_DDMA_CTL_DST_ADDR_MODE_MASK (3U << AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT) 116#define AWIN_DDMA_CTL_DMA_ADDR_LINEAR 0 117#define AWIN_DDMA_CTL_DMA_ADDR_IO 1 118#define AWIN_DDMA_CTL_DMA_ADDR_HPAGE 2 119#define AWIN_DDMA_CTL_DMA_ADDR_VPAGE 3 120#define AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT 16 121#define AWIN_DDMA_CTL_DST_DRQ_TYPE_MASK (0x1f << AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT) 122#define AWIN_DDMA_CTL_DRQ_SRAM 0 123#define AWIN_DDMA_CTL_DRQ_SDRAM 1 124#define AWIN_DDMA_CTL_DRQ_NFC 3 125#define AWIN_DDMA_CTL_DRQ_USB0 4 126#define AWIN_DDMA_CTL_DRQ_EMAC_TX 6 127#define AWIN_DDMA_CTL_DRQ_EMAC_RX 7 128#define AWIN_DDMA_CTL_DRQ_SPI1_TX 8 129#define AWIN_DDMA_CTL_DRQ_SPI1_RX 9 130#define AWIN_DDMA_CTL_DRQ_SS_TX 10 131#define AWIN_DDMA_CTL_DRQ_SS_RX 11 132#define AWIN_DDMA_CTL_DRQ_TCON0 14 133#define AWIN_DDMA_CTL_DRQ_TCON1 15 134#define AWIN_DDMA_CTL_DRQ_MS_TX 23 135#define AWIN_DDMA_CTL_DRQ_MS_RX 23 136#define AWIN_DDMA_CTL_DRQ_HDMI_AUDIO 24 137#define AWIN_DDMA_CTL_DRQ_SPI0_TX 26 138#define AWIN_DDMA_CTL_DRQ_SPI0_RX 27 139#define AWIN_DDMA_CTL_DRQ_SPI2_TX 28 140#define AWIN_DDMA_CTL_DRQ_SPI2_RX 29 141#define AWIN_DDMA_CTL_DRQ_SPI3_TX 30 142#define AWIN_DDMA_CTL_DRQ_SPI3_RX 31 143#define AWIN_DDMA_CTL_SRC_NON_SECURE (1U << 12) 144#define AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT 5 145#define AWIN_DDMA_CTL_SRC_ADDR_MODE_MASK (3U << AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT) 146#define AWIN_DDMA_BC_COUNT 0x00003fff 147#define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT 24 148#define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) 149#define AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT 16 150#define AWIN_DDMA_PARA_DST_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) 151#define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT 8 152#define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) 153#define AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT 0 154#define AWIN_DDMA_PARA_SRC_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT) 155 156#endif /* !_A10_DMAC_H_ */ 157