1/*-
2 * Copyright (c) 2015 John H. Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 2019 Mitchell Horne
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifndef __KVM_RISCV_H__
28#define	__KVM_RISCV_H__
29
30#ifdef __riscv
31#include <machine/pte.h>
32#endif
33
34typedef uint64_t	riscv_physaddr_t;
35typedef uint64_t	riscv_pt_entry_t;
36
37#define	RISCV_PAGE_SHIFT	12
38#define	RISCV_PAGE_SIZE		(1 << RISCV_PAGE_SHIFT)
39#define	RISCV_PAGE_MASK		(RISCV_PAGE_SIZE - 1)
40
41/* Source: sys/riscv/include/pte.h */
42#define	RISCV_L3_SHIFT		12
43#define	RISCV_L3_SIZE		(1 << L3_SHIFT)
44#define	RISCV_L3_OFFSET 	(L3_SIZE - 1)
45
46#define	RISCV_PTE_SW_MANAGED	(1 << 9)
47#define	RISCV_PTE_SW_WIRED	(1 << 8)
48#define	RISCV_PTE_D		(1 << 7) /* Dirty */
49#define	RISCV_PTE_A		(1 << 6) /* Accessed */
50#define	RISCV_PTE_G		(1 << 5) /* Global */
51#define	RISCV_PTE_U		(1 << 4) /* User */
52#define	RISCV_PTE_X		(1 << 3) /* Execute */
53#define	RISCV_PTE_W		(1 << 2) /* Write */
54#define	RISCV_PTE_R		(1 << 1) /* Read */
55#define	RISCV_PTE_V		(1 << 0) /* Valid */
56#define	RISCV_PTE_RWX		(RISCV_PTE_R | RISCV_PTE_W | RISCV_PTE_X)
57
58#define	RISCV_PTE_PPN0_S	10
59
60#ifdef __riscv
61_Static_assert(sizeof(pt_entry_t) == sizeof(riscv_pt_entry_t),
62    "pt_entry_t size mismatch");
63
64_Static_assert(PAGE_SHIFT == RISCV_PAGE_SHIFT, "PAGE_SHIFT mismatch");
65_Static_assert(PAGE_SIZE == RISCV_PAGE_SIZE, "PAGE_SIZE mismatch");
66_Static_assert(PAGE_MASK == RISCV_PAGE_MASK, "PAGE_MASK mismatch");
67
68_Static_assert(L3_SHIFT == RISCV_L3_SHIFT, "L3_SHIFT mismatch");
69_Static_assert(L3_SIZE == RISCV_L3_SIZE, "L3_SIZE mismatch");
70_Static_assert(L3_OFFSET == RISCV_L3_OFFSET, "L3_OFFSET mismatch");
71_Static_assert(PTE_PPN0_S == RISCV_PTE_PPN0_S, "PTE_PPN0_S mismatch");
72
73_Static_assert(PTE_SW_MANAGED == RISCV_PTE_SW_MANAGED,
74    "PTE_SW_MANAGED mismatch");
75_Static_assert(PTE_SW_WIRED == RISCV_PTE_SW_WIRED, "PTE_SW_WIRED mismatch");
76_Static_assert(PTE_D == RISCV_PTE_D, "PTE_D mismatch");
77_Static_assert(PTE_A == RISCV_PTE_A, "PTE_A mismatch");
78_Static_assert(PTE_G == RISCV_PTE_G, "PTE_G mismatch");
79_Static_assert(PTE_U == RISCV_PTE_U, "PTE_U mismatch");
80_Static_assert(PTE_X == RISCV_PTE_X, "PTE_X mismatch");
81_Static_assert(PTE_W == RISCV_PTE_W, "PTE_W mismatch");
82_Static_assert(PTE_R == RISCV_PTE_R, "PTE_R mismatch");
83_Static_assert(PTE_V == RISCV_PTE_V, "PTE_V mismatch");
84_Static_assert(PTE_RWX == RISCV_PTE_RWX, "PTE_RWX mismatch");
85#endif
86
87#endif /* !__KVM_RISCV_H__ */
88