1//===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides RISC-V specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetStreamer.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCTargetDesc.h"
16#include "llvm/MC/MCSymbol.h"
17#include "llvm/Support/FormattedStream.h"
18#include "llvm/Support/RISCVAttributes.h"
19#include "llvm/Support/RISCVISAInfo.h"
20
21using namespace llvm;
22
23RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
24
25void RISCVTargetStreamer::finish() { finishAttributeSection(); }
26void RISCVTargetStreamer::reset() {}
27
28void RISCVTargetStreamer::emitDirectiveOptionPush() {}
29void RISCVTargetStreamer::emitDirectiveOptionPop() {}
30void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
31void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
32void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
33void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
34void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
35void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
36void RISCVTargetStreamer::emitDirectiveOptionArch(
37    ArrayRef<RISCVOptionArchArg> Args) {}
38void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
39void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
40void RISCVTargetStreamer::finishAttributeSection() {}
41void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
42                                            StringRef String) {}
43void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
44                                               unsigned IntValue,
45                                               StringRef StringValue) {}
46void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
47  assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
48  TargetABI = ABI;
49}
50
51void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
52  HasRVC = STI.hasFeature(RISCV::FeatureStdExtC);
53  HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso);
54}
55
56void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
57                                               bool EmitStackAlign) {
58  if (EmitStackAlign) {
59    if (TargetABI == RISCVABI::ABI_ILP32E)
60      emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
61    else if (TargetABI == RISCVABI::ABI_LP64E)
62      emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_8);
63    else
64      emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
65  }
66
67  auto ParseResult = RISCVFeatures::parseFeatureBits(
68      STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
69  if (!ParseResult) {
70    report_fatal_error(ParseResult.takeError());
71  } else {
72    auto &ISAInfo = *ParseResult;
73    emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
74  }
75}
76
77// This part is for ascii assembly output
78RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
79                                               formatted_raw_ostream &OS)
80    : RISCVTargetStreamer(S), OS(OS) {}
81
82void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
83  OS << "\t.option\tpush\n";
84}
85
86void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
87  OS << "\t.option\tpop\n";
88}
89
90void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
91  OS << "\t.option\tpic\n";
92}
93
94void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
95  OS << "\t.option\tnopic\n";
96}
97
98void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
99  OS << "\t.option\trvc\n";
100}
101
102void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
103  OS << "\t.option\tnorvc\n";
104}
105
106void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
107  OS << "\t.option\trelax\n";
108}
109
110void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
111  OS << "\t.option\tnorelax\n";
112}
113
114void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
115    ArrayRef<RISCVOptionArchArg> Args) {
116  OS << "\t.option\tarch";
117  for (const auto &Arg : Args) {
118    OS << ", ";
119    switch (Arg.Type) {
120    case RISCVOptionArchArgType::Full:
121      break;
122    case RISCVOptionArchArgType::Plus:
123      OS << "+";
124      break;
125    case RISCVOptionArchArgType::Minus:
126      OS << "-";
127      break;
128    }
129    OS << Arg.Value;
130  }
131  OS << "\n";
132}
133
134void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
135  OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
136}
137
138void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
139  OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
140}
141
142void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
143                                               StringRef String) {
144  OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
145}
146
147void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
148                                                  unsigned IntValue,
149                                                  StringRef StringValue) {}
150
151void RISCVTargetAsmStreamer::finishAttributeSection() {}
152