1178676Ssam/* $FreeBSD$ */ 2210111Sbschmidt/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3178676Ssam 4178676Ssam/*- 5198429Srpaulo * Copyright (c) 2007, 2008 6178676Ssam * Damien Bergamini <damien.bergamini@free.fr> 7178676Ssam * 8178676Ssam * Permission to use, copy, modify, and distribute this software for any 9178676Ssam * purpose with or without fee is hereby granted, provided that the above 10178676Ssam * copyright notice and this permission notice appear in all copies. 11178676Ssam * 12178676Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13178676Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14178676Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15178676Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16178676Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17178676Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18178676Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19178676Ssam */ 20178676Ssam 21178676Ssam#define IWN_TX_RING_COUNT 256 22198429Srpaulo#define IWN_TX_RING_LOMARK 192 23198429Srpaulo#define IWN_TX_RING_HIMARK 224 24198429Srpaulo#define IWN_RX_RING_COUNT_LOG 6 25198429Srpaulo#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26178676Ssam 27198429Srpaulo#define IWN4965_NTXQUEUES 16 28198429Srpaulo#define IWN5000_NTXQUEUES 20 29178676Ssam 30221651Sbschmidt#define IWN4965_FIRSTAGGQUEUE 7 31221651Sbschmidt#define IWN5000_FIRSTAGGQUEUE 10 32221651Sbschmidt 33198429Srpaulo#define IWN4965_NDMACHNLS 7 34198429Srpaulo#define IWN5000_NDMACHNLS 8 35178676Ssam 36198429Srpaulo#define IWN_SRVC_DMACHNL 9 37198429Srpaulo 38201209Srpaulo#define IWN_ICT_SIZE 4096 39201209Srpaulo#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 40201209Srpaulo 41198429Srpaulo/* Maximum number of DMA segments for TX. */ 42178676Ssam#define IWN_MAX_SCATTER 20 43178676Ssam 44198429Srpaulo/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 45178676Ssam#define IWN_RBUF_SIZE (4 * 1024) 46178676Ssam 47198429Srpaulo#if defined(__LP64__) 48198429Srpaulo/* HW supports 36-bit DMA addresses. */ 49198429Srpaulo#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 50198429Srpaulo#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 51198429Srpaulo#else 52198429Srpaulo#define IWN_LOADDR(paddr) (paddr) 53198429Srpaulo#define IWN_HIADDR(paddr) (0) 54198429Srpaulo#endif 55198429Srpaulo 56178676Ssam/* 57178676Ssam * Control and status registers. 58178676Ssam */ 59198429Srpaulo#define IWN_HW_IF_CONFIG 0x000 60198429Srpaulo#define IWN_INT_COALESCING 0x004 61201209Srpaulo#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 62198429Srpaulo#define IWN_INT 0x008 63201209Srpaulo#define IWN_INT_MASK 0x00c 64198429Srpaulo#define IWN_FH_INT 0x010 65178676Ssam#define IWN_RESET 0x020 66198429Srpaulo#define IWN_GP_CNTRL 0x024 67198429Srpaulo#define IWN_HW_REV 0x028 68198429Srpaulo#define IWN_EEPROM 0x02c 69198429Srpaulo#define IWN_EEPROM_GP 0x030 70198429Srpaulo#define IWN_OTP_GP 0x034 71198429Srpaulo#define IWN_GIO 0x03c 72201209Srpaulo#define IWN_GP_DRIVER 0x050 73198429Srpaulo#define IWN_UCODE_GP1_CLR 0x05c 74198429Srpaulo#define IWN_LED 0x094 75201209Srpaulo#define IWN_DRAM_INT_TBL 0x0a0 76220729Sbschmidt#define IWN_SHADOW_REG_CTRL 0x0a8 77198429Srpaulo#define IWN_GIO_CHICKEN 0x100 78198429Srpaulo#define IWN_ANA_PLL 0x20c 79201209Srpaulo#define IWN_HW_REV_WA 0x22c 80198429Srpaulo#define IWN_DBG_HPET_MEM 0x240 81201209Srpaulo#define IWN_DBG_LINK_PWR_MGMT 0x250 82198429Srpaulo#define IWN_MEM_RADDR 0x40c 83178676Ssam#define IWN_MEM_WADDR 0x410 84178676Ssam#define IWN_MEM_WDATA 0x418 85198429Srpaulo#define IWN_MEM_RDATA 0x41c 86220726Sbschmidt#define IWN_PRPH_WADDR 0x444 87220726Sbschmidt#define IWN_PRPH_RADDR 0x448 88220726Sbschmidt#define IWN_PRPH_WDATA 0x44c 89220726Sbschmidt#define IWN_PRPH_RDATA 0x450 90198429Srpaulo#define IWN_HBUS_TARG_WRPTR 0x460 91178676Ssam 92198429Srpaulo/* 93198429Srpaulo * Flow-Handler registers. 94198429Srpaulo */ 95198429Srpaulo#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 96198429Srpaulo#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 97198429Srpaulo#define IWN_FH_KW_ADDR 0x197c 98198429Srpaulo#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 99198429Srpaulo#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 100198429Srpaulo#define IWN_FH_STATUS_WPTR 0x1bc0 101198429Srpaulo#define IWN_FH_RX_BASE 0x1bc4 102198429Srpaulo#define IWN_FH_RX_WPTR 0x1bc8 103198429Srpaulo#define IWN_FH_RX_CONFIG 0x1c00 104198429Srpaulo#define IWN_FH_RX_STATUS 0x1c44 105198429Srpaulo#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 106198429Srpaulo#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 107198429Srpaulo#define IWN_FH_TX_CHICKEN 0x1e98 108198429Srpaulo#define IWN_FH_TX_STATUS 0x1eb0 109178676Ssam 110198429Srpaulo/* 111198429Srpaulo * TX scheduler registers. 112198429Srpaulo */ 113198429Srpaulo#define IWN_SCHED_BASE 0xa02c00 114198429Srpaulo#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 115198429Srpaulo#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 116198429Srpaulo#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 117198429Srpaulo#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 118198429Srpaulo#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 119198429Srpaulo#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 120198429Srpaulo#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 121198429Srpaulo#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 122198429Srpaulo#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 123198429Srpaulo#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 124198429Srpaulo#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 125198429Srpaulo#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 126198429Srpaulo#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 127198429Srpaulo#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 128178676Ssam 129178676Ssam/* 130198429Srpaulo * Offsets in TX scheduler's SRAM. 131198429Srpaulo */ 132198429Srpaulo#define IWN4965_SCHED_CTX_OFF 0x380 133198429Srpaulo#define IWN4965_SCHED_CTX_LEN 416 134198429Srpaulo#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 135198429Srpaulo#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 136198429Srpaulo#define IWN5000_SCHED_CTX_OFF 0x600 137198429Srpaulo#define IWN5000_SCHED_CTX_LEN 520 138198429Srpaulo#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 139198429Srpaulo#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 140198429Srpaulo 141198429Srpaulo/* 142178676Ssam * NIC internal memory offsets. 143178676Ssam */ 144201209Srpaulo#define IWN_APMG_CLK_CTRL 0x3000 145201209Srpaulo#define IWN_APMG_CLK_EN 0x3004 146198429Srpaulo#define IWN_APMG_CLK_DIS 0x3008 147198429Srpaulo#define IWN_APMG_PS 0x300c 148201209Srpaulo#define IWN_APMG_DIGITAL_SVR 0x3058 149201209Srpaulo#define IWN_APMG_ANALOG_SVR 0x306c 150198429Srpaulo#define IWN_APMG_PCI_STT 0x3010 151198429Srpaulo#define IWN_BSM_WR_CTRL 0x3400 152198429Srpaulo#define IWN_BSM_WR_MEM_SRC 0x3404 153198429Srpaulo#define IWN_BSM_WR_MEM_DST 0x3408 154198429Srpaulo#define IWN_BSM_WR_DWCOUNT 0x340c 155198429Srpaulo#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 156198429Srpaulo#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 157198429Srpaulo#define IWN_BSM_DRAM_DATA_ADDR 0x3498 158198429Srpaulo#define IWN_BSM_DRAM_DATA_SIZE 0x349c 159198429Srpaulo#define IWN_BSM_SRAM_BASE 0x3800 160178676Ssam 161198429Srpaulo/* Possible flags for register IWN_HW_IF_CONFIG. */ 162198429Srpaulo#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 163198429Srpaulo#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 164198429Srpaulo#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 165198429Srpaulo#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 166198429Srpaulo#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 167198429Srpaulo#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 168198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 169198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 170178676Ssam 171201209Srpaulo/* Possible values for register IWN_INT_PERIODIC. */ 172201209Srpaulo#define IWN_INT_PERIODIC_DIS 0x00 173201209Srpaulo#define IWN_INT_PERIODIC_ENA 0xff 174201209Srpaulo 175198429Srpaulo/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 176198429Srpaulo#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 177178676Ssam 178198429Srpaulo/* Possible values for IWN_BSM_WR_MEM_DST. */ 179198429Srpaulo#define IWN_FW_TEXT_BASE 0x00000000 180198429Srpaulo#define IWN_FW_DATA_BASE 0x00800000 181178676Ssam 182198429Srpaulo/* Possible flags for register IWN_RESET. */ 183198429Srpaulo#define IWN_RESET_NEVO (1 << 0) 184198429Srpaulo#define IWN_RESET_SW (1 << 7) 185198429Srpaulo#define IWN_RESET_MASTER_DISABLED (1 << 8) 186198429Srpaulo#define IWN_RESET_STOP_MASTER (1 << 9) 187201209Srpaulo#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 188178676Ssam 189198429Srpaulo/* Possible flags for register IWN_GP_CNTRL. */ 190198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 191198429Srpaulo#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 192198429Srpaulo#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 193198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 194198429Srpaulo#define IWN_GP_CNTRL_SLEEP (1 << 4) 195198429Srpaulo#define IWN_GP_CNTRL_RFKILL (1 << 27) 196178676Ssam 197198429Srpaulo/* Possible flags for register IWN_HW_REV. */ 198198429Srpaulo#define IWN_HW_REV_TYPE_SHIFT 4 199198429Srpaulo#define IWN_HW_REV_TYPE_MASK 0x000000f0 200198429Srpaulo#define IWN_HW_REV_TYPE_4965 0 201198429Srpaulo#define IWN_HW_REV_TYPE_5300 2 202198429Srpaulo#define IWN_HW_REV_TYPE_5350 3 203198429Srpaulo#define IWN_HW_REV_TYPE_5150 4 204198429Srpaulo#define IWN_HW_REV_TYPE_5100 5 205198429Srpaulo#define IWN_HW_REV_TYPE_1000 6 206198429Srpaulo#define IWN_HW_REV_TYPE_6000 7 207198429Srpaulo#define IWN_HW_REV_TYPE_6050 8 208210109Sbschmidt#define IWN_HW_REV_TYPE_6005 11 209178676Ssam 210198429Srpaulo/* Possible flags for register IWN_GIO_CHICKEN. */ 211198429Srpaulo#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 212198429Srpaulo#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 213178676Ssam 214198429Srpaulo/* Possible flags for register IWN_GIO. */ 215198429Srpaulo#define IWN_GIO_L0S_ENA (1 << 1) 216178676Ssam 217201209Srpaulo/* Possible flags for register IWN_GP_DRIVER. */ 218201209Srpaulo#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 219201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 220201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 221206444Sbschmidt#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 222220729Sbschmidt#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 223201209Srpaulo 224198429Srpaulo/* Possible flags for register IWN_UCODE_GP1_CLR. */ 225198429Srpaulo#define IWN_UCODE_GP1_RFKILL (1 << 1) 226198429Srpaulo#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 227198429Srpaulo#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 228178676Ssam 229198429Srpaulo/* Possible flags/values for register IWN_LED. */ 230198429Srpaulo#define IWN_LED_BSM_CTRL (1 << 5) 231198429Srpaulo#define IWN_LED_OFF 0x00000038 232198429Srpaulo#define IWN_LED_ON 0x00000078 233178676Ssam 234201209Srpaulo/* Possible flags for register IWN_DRAM_INT_TBL. */ 235201209Srpaulo#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 236201209Srpaulo#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 237201209Srpaulo 238198429Srpaulo/* Possible values for register IWN_ANA_PLL. */ 239198429Srpaulo#define IWN_ANA_PLL_INIT 0x00880300 240178676Ssam 241198429Srpaulo/* Possible flags for register IWN_FH_RX_STATUS. */ 242198429Srpaulo#define IWN_FH_RX_STATUS_IDLE (1 << 24) 243178676Ssam 244198429Srpaulo/* Possible flags for register IWN_BSM_WR_CTRL. */ 245198429Srpaulo#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 246198429Srpaulo#define IWN_BSM_WR_CTRL_START (1 << 31) 247178676Ssam 248198429Srpaulo/* Possible flags for register IWN_INT. */ 249198429Srpaulo#define IWN_INT_ALIVE (1 << 0) 250198429Srpaulo#define IWN_INT_WAKEUP (1 << 1) 251198429Srpaulo#define IWN_INT_SW_RX (1 << 3) 252198429Srpaulo#define IWN_INT_CT_REACHED (1 << 6) 253198429Srpaulo#define IWN_INT_RF_TOGGLED (1 << 7) 254198429Srpaulo#define IWN_INT_SW_ERR (1 << 25) 255201209Srpaulo#define IWN_INT_SCHED (1 << 26) 256198429Srpaulo#define IWN_INT_FH_TX (1 << 27) 257201209Srpaulo#define IWN_INT_RX_PERIODIC (1 << 28) 258198429Srpaulo#define IWN_INT_HW_ERR (1 << 29) 259198429Srpaulo#define IWN_INT_FH_RX (1 << 31) 260178676Ssam 261198429Srpaulo/* Shortcut. */ 262201209Srpaulo#define IWN_INT_MASK_DEF \ 263198429Srpaulo (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 264198429Srpaulo IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 265198429Srpaulo IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 266178676Ssam 267198429Srpaulo/* Possible flags for register IWN_FH_INT. */ 268198429Srpaulo#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 269198429Srpaulo#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 270198429Srpaulo#define IWN_FH_INT_HI_PRIOR (1 << 30) 271198429Srpaulo/* Shortcuts for the above. */ 272198429Srpaulo#define IWN_FH_INT_TX \ 273198429Srpaulo (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 274198429Srpaulo#define IWN_FH_INT_RX \ 275198429Srpaulo (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 276178676Ssam 277198429Srpaulo/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 278198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 279198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 280198429Srpaulo#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 281178676Ssam 282198429Srpaulo/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 283198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 284198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 285198429Srpaulo#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 286198429Srpaulo 287198429Srpaulo/* Possible flags for register IWN_FH_TX_CHICKEN. */ 288198429Srpaulo#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 289198429Srpaulo 290198429Srpaulo/* Possible flags for register IWN_FH_TX_STATUS. */ 291220659Sbschmidt#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 292198429Srpaulo 293198429Srpaulo/* Possible flags for register IWN_FH_RX_CONFIG. */ 294198429Srpaulo#define IWN_FH_RX_CONFIG_ENA (1 << 31) 295198429Srpaulo#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 296198429Srpaulo#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 297198429Srpaulo#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 298198429Srpaulo#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 299198429Srpaulo#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 300198429Srpaulo#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 301198429Srpaulo 302198429Srpaulo/* Possible flags for register IWN_FH_TX_CONFIG. */ 303198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 304198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 305198429Srpaulo 306198429Srpaulo/* Possible flags for register IWN_EEPROM. */ 307198429Srpaulo#define IWN_EEPROM_READ_VALID (1 << 0) 308198429Srpaulo#define IWN_EEPROM_CMD (1 << 1) 309198429Srpaulo 310198429Srpaulo/* Possible flags for register IWN_EEPROM_GP. */ 311198429Srpaulo#define IWN_EEPROM_GP_IF_OWNER 0x00000180 312198429Srpaulo 313198429Srpaulo/* Possible flags for register IWN_OTP_GP. */ 314198429Srpaulo#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 315198429Srpaulo#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 316198429Srpaulo#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 317198429Srpaulo#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 318198429Srpaulo 319198429Srpaulo/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 320198429Srpaulo#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 321198429Srpaulo#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 322198429Srpaulo#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 323198429Srpaulo#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 324198429Srpaulo#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 325198429Srpaulo#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 326198429Srpaulo#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 327198429Srpaulo 328201209Srpaulo/* Possible flags for registers IWN_APMG_CLK_*. */ 329198429Srpaulo#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 330198429Srpaulo#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 331198429Srpaulo 332198429Srpaulo/* Possible flags for register IWN_APMG_PS. */ 333198429Srpaulo#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 334198429Srpaulo#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 335198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VMAIN 0 336198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VAUX 2 337198429Srpaulo#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 338198429Srpaulo#define IWN_APMG_PS_RESET_REQ (1 << 26) 339198429Srpaulo 340201209Srpaulo/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 341201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 342201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 343201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 344201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 345201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 346201209Srpaulo 347198429Srpaulo/* Possible flags for IWN_APMG_PCI_STT. */ 348198429Srpaulo#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 349198429Srpaulo 350198429Srpaulo/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 351178676Ssam#define IWN_FW_UPDATED (1 << 31) 352178676Ssam 353198429Srpaulo#define IWN_SCHED_WINSZ 64 354198429Srpaulo#define IWN_SCHED_LIMIT 64 355198429Srpaulo#define IWN4965_SCHED_COUNT 512 356198429Srpaulo#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 357198429Srpaulo#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 358198429Srpaulo#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 359178676Ssam 360198429Srpaulostruct iwn_tx_desc { 361198429Srpaulo uint8_t reserved1[3]; 362198429Srpaulo uint8_t nsegs; 363198429Srpaulo struct { 364198429Srpaulo uint32_t addr; 365198429Srpaulo uint16_t len; 366198429Srpaulo } __packed segs[IWN_MAX_SCATTER]; 367198429Srpaulo /* Pad to 128 bytes. */ 368198429Srpaulo uint32_t reserved2; 369198429Srpaulo} __packed; 370178676Ssam 371198429Srpaulostruct iwn_rx_status { 372178676Ssam uint16_t closed_count; 373178676Ssam uint16_t closed_rx_count; 374178676Ssam uint16_t finished_count; 375178676Ssam uint16_t finished_rx_count; 376178676Ssam uint32_t reserved[2]; 377178676Ssam} __packed; 378178676Ssam 379178676Ssamstruct iwn_rx_desc { 380178676Ssam uint32_t len; 381178676Ssam uint8_t type; 382198429Srpaulo#define IWN_UC_READY 1 383198429Srpaulo#define IWN_ADD_NODE_DONE 24 384198429Srpaulo#define IWN_TX_DONE 28 385198429Srpaulo#define IWN5000_CALIBRATION_RESULT 102 386198429Srpaulo#define IWN5000_CALIBRATION_DONE 103 387198429Srpaulo#define IWN_START_SCAN 130 388198429Srpaulo#define IWN_STOP_SCAN 132 389198429Srpaulo#define IWN_RX_STATISTICS 156 390198429Srpaulo#define IWN_BEACON_STATISTICS 157 391198429Srpaulo#define IWN_STATE_CHANGED 161 392198429Srpaulo#define IWN_BEACON_MISSED 162 393198429Srpaulo#define IWN_RX_PHY 192 394198429Srpaulo#define IWN_MPDU_RX_DONE 193 395198429Srpaulo#define IWN_RX_DONE 195 396201209Srpaulo#define IWN_RX_COMPRESSED_BA 197 397178676Ssam 398178676Ssam uint8_t flags; 399178676Ssam uint8_t idx; 400178676Ssam uint8_t qid; 401178676Ssam} __packed; 402178676Ssam 403198429Srpaulo/* Possible RX status flags. */ 404198429Srpaulo#define IWN_RX_NO_CRC_ERR (1 << 0) 405198429Srpaulo#define IWN_RX_NO_OVFL_ERR (1 << 1) 406198429Srpaulo/* Shortcut for the above. */ 407178676Ssam#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 408198429Srpaulo#define IWN_RX_MPDU_MIC_OK (1 << 6) 409198429Srpaulo#define IWN_RX_CIPHER_MASK (7 << 8) 410198429Srpaulo#define IWN_RX_CIPHER_CCMP (2 << 8) 411198429Srpaulo#define IWN_RX_MPDU_DEC (1 << 11) 412198429Srpaulo#define IWN_RX_DECRYPT_MASK (3 << 11) 413198429Srpaulo#define IWN_RX_DECRYPT_OK (3 << 11) 414178676Ssam 415178676Ssamstruct iwn_tx_cmd { 416178676Ssam uint8_t code; 417201209Srpaulo#define IWN_CMD_RXON 16 418201209Srpaulo#define IWN_CMD_RXON_ASSOC 17 419198429Srpaulo#define IWN_CMD_EDCA_PARAMS 19 420198429Srpaulo#define IWN_CMD_TIMING 20 421198429Srpaulo#define IWN_CMD_ADD_NODE 24 422198429Srpaulo#define IWN_CMD_TX_DATA 28 423198429Srpaulo#define IWN_CMD_LINK_QUALITY 78 424198429Srpaulo#define IWN_CMD_SET_LED 72 425198429Srpaulo#define IWN5000_CMD_WIMAX_COEX 90 426198429Srpaulo#define IWN5000_CMD_CALIB_CONFIG 101 427202986Srpaulo#define IWN5000_CMD_CALIB_RESULT 102 428202986Srpaulo#define IWN5000_CMD_CALIB_COMPLETE 103 429198429Srpaulo#define IWN_CMD_SET_POWER_MODE 119 430198429Srpaulo#define IWN_CMD_SCAN 128 431202986Srpaulo#define IWN_CMD_SCAN_RESULTS 131 432201209Srpaulo#define IWN_CMD_TXPOWER_DBM 149 433198429Srpaulo#define IWN_CMD_TXPOWER 151 434201209Srpaulo#define IWN5000_CMD_TX_ANT_CONFIG 152 435198429Srpaulo#define IWN_CMD_BT_COEX 155 436198429Srpaulo#define IWN_CMD_GET_STATISTICS 156 437198429Srpaulo#define IWN_CMD_SET_CRITICAL_TEMP 164 438198429Srpaulo#define IWN_CMD_SET_SENSITIVITY 168 439198429Srpaulo#define IWN_CMD_PHY_CALIB 176 440220891Sbschmidt#define IWN_CMD_BT_COEX_PRIOTABLE 204 441220891Sbschmidt#define IWN_CMD_BT_COEX_PROT 205 442198429Srpaulo 443178676Ssam uint8_t flags; 444178676Ssam uint8_t idx; 445178676Ssam uint8_t qid; 446178676Ssam uint8_t data[136]; 447178676Ssam} __packed; 448178676Ssam 449198429Srpaulo/* Antenna flags, used in various commands. */ 450198429Srpaulo#define IWN_ANT_A (1 << 0) 451198429Srpaulo#define IWN_ANT_B (1 << 1) 452198429Srpaulo#define IWN_ANT_C (1 << 2) 453201209Srpaulo/* Shortcuts. */ 454201209Srpaulo#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 455201209Srpaulo#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 456198429Srpaulo#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 457198429Srpaulo 458201209Srpaulo/* Structure for command IWN_CMD_RXON. */ 459198429Srpaulostruct iwn_rxon { 460178676Ssam uint8_t myaddr[IEEE80211_ADDR_LEN]; 461178676Ssam uint16_t reserved1; 462178676Ssam uint8_t bssid[IEEE80211_ADDR_LEN]; 463178676Ssam uint16_t reserved2; 464178676Ssam uint8_t wlap[IEEE80211_ADDR_LEN]; 465178676Ssam uint16_t reserved3; 466178676Ssam uint8_t mode; 467178676Ssam#define IWN_MODE_HOSTAP 1 468178676Ssam#define IWN_MODE_STA 3 469178676Ssam#define IWN_MODE_IBSS 4 470178676Ssam#define IWN_MODE_MONITOR 6 471198429Srpaulo 472198429Srpaulo uint8_t air; 473178676Ssam uint16_t rxchain; 474201209Srpaulo#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 475201209Srpaulo#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 476201209Srpaulo#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 477201209Srpaulo#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 478198429Srpaulo#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 479198429Srpaulo#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 480198429Srpaulo#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 481198429Srpaulo 482198429Srpaulo uint8_t ofdm_mask; 483198429Srpaulo uint8_t cck_mask; 484178676Ssam uint16_t associd; 485178676Ssam uint32_t flags; 486201209Srpaulo#define IWN_RXON_24GHZ (1 << 0) 487201209Srpaulo#define IWN_RXON_CCK (1 << 1) 488201209Srpaulo#define IWN_RXON_AUTO (1 << 2) 489201209Srpaulo#define IWN_RXON_SHSLOT (1 << 4) 490201209Srpaulo#define IWN_RXON_SHPREAMBLE (1 << 5) 491201209Srpaulo#define IWN_RXON_NODIVERSITY (1 << 7) 492201209Srpaulo#define IWN_RXON_ANTENNA_A (1 << 8) 493201209Srpaulo#define IWN_RXON_ANTENNA_B (1 << 9) 494201209Srpaulo#define IWN_RXON_TSF (1 << 15) 495221653Sbschmidt#define IWN_RXON_HT_HT40MINUS (1 << 22) 496221653Sbschmidt#define IWN_RXON_HT_PROTMODE(x) (x << 23) 497221653Sbschmidt#define IWN_RXON_HT_MODEPURE40 (1 << 25) 498221653Sbschmidt#define IWN_RXON_HT_MODEMIXED (2 << 25) 499201209Srpaulo#define IWN_RXON_CTS_TO_SELF (1 << 30) 500198429Srpaulo 501178676Ssam uint32_t filter; 502198429Srpaulo#define IWN_FILTER_PROMISC (1 << 0) 503198429Srpaulo#define IWN_FILTER_CTL (1 << 1) 504198429Srpaulo#define IWN_FILTER_MULTICAST (1 << 2) 505198429Srpaulo#define IWN_FILTER_NODECRYPT (1 << 3) 506198429Srpaulo#define IWN_FILTER_BSS (1 << 5) 507198429Srpaulo#define IWN_FILTER_BEACON (1 << 6) 508198429Srpaulo 509198429Srpaulo uint8_t chan; 510198429Srpaulo uint8_t reserved4; 511198429Srpaulo uint8_t ht_single_mask; 512198429Srpaulo uint8_t ht_dual_mask; 513201209Srpaulo /* The following fields are for >=5000 Series only. */ 514198429Srpaulo uint8_t ht_triple_mask; 515198429Srpaulo uint8_t reserved5; 516198429Srpaulo uint16_t acquisition; 517198429Srpaulo uint16_t reserved6; 518178676Ssam} __packed; 519178676Ssam 520198429Srpaulo#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 521198429Srpaulo#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 522198429Srpaulo 523198429Srpaulo/* Structure for command IWN_CMD_ASSOCIATE. */ 524178676Ssamstruct iwn_assoc { 525178676Ssam uint32_t flags; 526178676Ssam uint32_t filter; 527178676Ssam uint8_t ofdm_mask; 528178676Ssam uint8_t cck_mask; 529178676Ssam uint16_t reserved; 530178676Ssam} __packed; 531178676Ssam 532198429Srpaulo/* Structure for command IWN_CMD_EDCA_PARAMS. */ 533178676Ssamstruct iwn_edca_params { 534178676Ssam uint32_t flags; 535178676Ssam#define IWN_EDCA_UPDATE (1 << 0) 536178676Ssam#define IWN_EDCA_TXOP (1 << 4) 537178676Ssam 538178676Ssam struct { 539178676Ssam uint16_t cwmin; 540178676Ssam uint16_t cwmax; 541178676Ssam uint8_t aifsn; 542178676Ssam uint8_t reserved; 543178676Ssam uint16_t txoplimit; 544201209Srpaulo } __packed ac[WME_NUM_AC]; 545178676Ssam} __packed; 546178676Ssam 547198429Srpaulo/* Structure for command IWN_CMD_TIMING. */ 548198429Srpaulostruct iwn_cmd_timing { 549178676Ssam uint64_t tstamp; 550178676Ssam uint16_t bintval; 551178676Ssam uint16_t atim; 552178676Ssam uint32_t binitval; 553178676Ssam uint16_t lintval; 554178676Ssam uint16_t reserved; 555178676Ssam} __packed; 556178676Ssam 557198429Srpaulo/* Structure for command IWN_CMD_ADD_NODE. */ 558178676Ssamstruct iwn_node_info { 559178676Ssam uint8_t control; 560178676Ssam#define IWN_NODE_UPDATE (1 << 0) 561198429Srpaulo 562178676Ssam uint8_t reserved1[3]; 563198429Srpaulo 564178676Ssam uint8_t macaddr[IEEE80211_ADDR_LEN]; 565178676Ssam uint16_t reserved2; 566178676Ssam uint8_t id; 567178676Ssam#define IWN_ID_BSS 0 568198429Srpaulo#define IWN5000_ID_BROADCAST 15 569198429Srpaulo#define IWN4965_ID_BROADCAST 31 570198429Srpaulo 571178676Ssam uint8_t flags; 572198429Srpaulo#define IWN_FLAG_SET_KEY (1 << 0) 573198429Srpaulo#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 574198429Srpaulo#define IWN_FLAG_SET_TXRATE (1 << 2) 575198429Srpaulo#define IWN_FLAG_SET_ADDBA (1 << 3) 576198429Srpaulo#define IWN_FLAG_SET_DELBA (1 << 4) 577198429Srpaulo 578178676Ssam uint16_t reserved3; 579198429Srpaulo uint16_t kflags; 580198429Srpaulo#define IWN_KFLAG_CCMP (1 << 1) 581198429Srpaulo#define IWN_KFLAG_MAP (1 << 3) 582198429Srpaulo#define IWN_KFLAG_KID(kid) ((kid) << 8) 583198429Srpaulo#define IWN_KFLAG_INVALID (1 << 11) 584198429Srpaulo#define IWN_KFLAG_GROUP (1 << 14) 585198429Srpaulo 586178676Ssam uint8_t tsc2; /* TKIP TSC2 */ 587178676Ssam uint8_t reserved4; 588178676Ssam uint16_t ttak[5]; 589198429Srpaulo uint8_t kid; 590198429Srpaulo uint8_t reserved5; 591198429Srpaulo uint8_t key[16]; 592198429Srpaulo /* The following 3 fields are for 5000 Series only. */ 593198429Srpaulo uint64_t tsc; 594198429Srpaulo uint8_t rxmic[8]; 595198429Srpaulo uint8_t txmic[8]; 596198429Srpaulo 597178676Ssam uint32_t htflags; 598221653Sbschmidt#define IWN_SMPS_MIMO_PROT (1 << 17) 599198429Srpaulo#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 600221653Sbschmidt#define IWN_NODE_HT40 (1 << 21) 601221653Sbschmidt#define IWN_SMPS_MIMO_DIS (1 << 22) 602198429Srpaulo#define IWN_AMDPU_DENSITY(x) ((x) << 23) 603198429Srpaulo 604178676Ssam uint32_t mask; 605198429Srpaulo uint16_t disable_tid; 606198429Srpaulo uint16_t reserved6; 607198429Srpaulo uint8_t addba_tid; 608198429Srpaulo uint8_t delba_tid; 609198429Srpaulo uint16_t addba_ssn; 610198429Srpaulo uint32_t reserved7; 611198429Srpaulo} __packed; 612198429Srpaulo 613198429Srpaulostruct iwn4965_node_info { 614198429Srpaulo uint8_t control; 615198429Srpaulo uint8_t reserved1[3]; 616198429Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 617198429Srpaulo uint16_t reserved2; 618198429Srpaulo uint8_t id; 619198429Srpaulo uint8_t flags; 620198429Srpaulo uint16_t reserved3; 621198429Srpaulo uint16_t kflags; 622198429Srpaulo uint8_t tsc2; /* TKIP TSC2 */ 623198429Srpaulo uint8_t reserved4; 624198429Srpaulo uint16_t ttak[5]; 625198429Srpaulo uint8_t kid; 626198429Srpaulo uint8_t reserved5; 627198429Srpaulo uint8_t key[16]; 628198429Srpaulo uint32_t htflags; 629198429Srpaulo uint32_t mask; 630198429Srpaulo uint16_t disable_tid; 631198429Srpaulo uint16_t reserved6; 632198429Srpaulo uint8_t addba_tid; 633198429Srpaulo uint8_t delba_tid; 634198429Srpaulo uint16_t addba_ssn; 635198429Srpaulo uint32_t reserved7; 636198429Srpaulo} __packed; 637198429Srpaulo 638221649Sbschmidt#define IWN_RFLAG_MCS (1 << 8) 639221648Sbschmidt#define IWN_RFLAG_CCK (1 << 9) 640221649Sbschmidt#define IWN_RFLAG_GREENFIELD (1 << 10) 641221649Sbschmidt#define IWN_RFLAG_HT40 (1 << 11) 642221649Sbschmidt#define IWN_RFLAG_DUPLICATE (1 << 12) 643221649Sbschmidt#define IWN_RFLAG_SGI (1 << 13) 644221648Sbschmidt#define IWN_RFLAG_ANT(x) ((x) << 14) 645178676Ssam 646198429Srpaulo/* Structure for command IWN_CMD_TX_DATA. */ 647178676Ssamstruct iwn_cmd_data { 648178676Ssam uint16_t len; 649178676Ssam uint16_t lnext; 650178676Ssam uint32_t flags; 651198429Srpaulo#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 652178676Ssam#define IWN_TX_NEED_RTS (1 << 1) 653178676Ssam#define IWN_TX_NEED_CTS (1 << 2) 654178676Ssam#define IWN_TX_NEED_ACK (1 << 3) 655198429Srpaulo#define IWN_TX_LINKQ (1 << 4) 656198429Srpaulo#define IWN_TX_IMM_BA (1 << 6) 657178676Ssam#define IWN_TX_FULL_TXOP (1 << 7) 658178676Ssam#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 659178676Ssam#define IWN_TX_AUTO_SEQ (1 << 13) 660198429Srpaulo#define IWN_TX_MORE_FRAG (1 << 14) 661178676Ssam#define IWN_TX_INSERT_TSTAMP (1 << 16) 662178676Ssam#define IWN_TX_NEED_PADDING (1 << 20) 663178676Ssam 664198429Srpaulo uint32_t scratch; 665221648Sbschmidt uint32_t rate; 666198429Srpaulo 667178676Ssam uint8_t id; 668178676Ssam uint8_t security; 669178676Ssam#define IWN_CIPHER_WEP40 1 670178676Ssam#define IWN_CIPHER_CCMP 2 671178676Ssam#define IWN_CIPHER_TKIP 3 672178676Ssam#define IWN_CIPHER_WEP104 9 673178676Ssam 674198429Srpaulo uint8_t linkq; 675178676Ssam uint8_t reserved2; 676198429Srpaulo uint8_t key[16]; 677178676Ssam uint16_t fnext; 678178676Ssam uint16_t reserved3; 679178676Ssam uint32_t lifetime; 680178676Ssam#define IWN_LIFETIME_INFINITE 0xffffffff 681178676Ssam 682178676Ssam uint32_t loaddr; 683178676Ssam uint8_t hiaddr; 684178676Ssam uint8_t rts_ntries; 685178676Ssam uint8_t data_ntries; 686178676Ssam uint8_t tid; 687178676Ssam uint16_t timeout; 688178676Ssam uint16_t txop; 689178676Ssam} __packed; 690178676Ssam 691198429Srpaulo/* Structure for command IWN_CMD_LINK_QUALITY. */ 692178676Ssam#define IWN_MAX_TX_RETRIES 16 693178676Ssamstruct iwn_cmd_link_quality { 694178676Ssam uint8_t id; 695178676Ssam uint8_t reserved1; 696178676Ssam uint16_t ctl; 697178676Ssam uint8_t flags; 698198429Srpaulo uint8_t mimo; 699198429Srpaulo uint8_t antmsk_1stream; 700198429Srpaulo uint8_t antmsk_2stream; 701201209Srpaulo uint8_t ridx[WME_NUM_AC]; 702198429Srpaulo uint16_t ampdu_limit; 703198429Srpaulo uint8_t ampdu_threshold; 704198429Srpaulo uint8_t ampdu_max; 705178676Ssam uint32_t reserved2; 706221648Sbschmidt uint32_t retry[IWN_MAX_TX_RETRIES]; 707178676Ssam uint32_t reserved3; 708178676Ssam} __packed; 709178676Ssam 710198429Srpaulo/* Structure for command IWN_CMD_SET_LED. */ 711178676Ssamstruct iwn_cmd_led { 712178676Ssam uint32_t unit; /* multiplier (in usecs) */ 713178676Ssam uint8_t which; 714178676Ssam#define IWN_LED_ACTIVITY 1 715178676Ssam#define IWN_LED_LINK 2 716178676Ssam 717178676Ssam uint8_t off; 718178676Ssam uint8_t on; 719178676Ssam uint8_t reserved; 720178676Ssam} __packed; 721178676Ssam 722198429Srpaulo/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 723198429Srpaulostruct iwn5000_wimax_coex { 724198429Srpaulo uint32_t flags; 725201209Srpaulo#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 726201209Srpaulo#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 727201209Srpaulo#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 728201209Srpaulo#define IWN_WIMAX_COEX_ENABLE (1 << 7) 729201209Srpaulo 730201209Srpaulo struct iwn5000_wimax_event { 731198429Srpaulo uint8_t request; 732198429Srpaulo uint8_t window; 733198429Srpaulo uint8_t reserved; 734198429Srpaulo uint8_t flags; 735198429Srpaulo } __packed events[16]; 736198429Srpaulo} __packed; 737198429Srpaulo 738198429Srpaulo/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 739198429Srpaulostruct iwn5000_calib_elem { 740198429Srpaulo uint32_t enable; 741198429Srpaulo uint32_t start; 742227967Sbschmidt#define IWN5000_CALIB_DC (1 << 1) 743227967Sbschmidt 744198429Srpaulo uint32_t send; 745198429Srpaulo uint32_t apply; 746198429Srpaulo uint32_t reserved; 747198429Srpaulo} __packed; 748198429Srpaulo 749198429Srpaulostruct iwn5000_calib_status { 750198429Srpaulo struct iwn5000_calib_elem once; 751198429Srpaulo struct iwn5000_calib_elem perd; 752198429Srpaulo uint32_t flags; 753198429Srpaulo} __packed; 754198429Srpaulo 755198429Srpaulostruct iwn5000_calib_config { 756198429Srpaulo struct iwn5000_calib_status ucode; 757198429Srpaulo struct iwn5000_calib_status driver; 758198429Srpaulo uint32_t reserved; 759198429Srpaulo} __packed; 760198429Srpaulo 761198429Srpaulo/* Structure for command IWN_CMD_SET_POWER_MODE. */ 762198429Srpaulostruct iwn_pmgt_cmd { 763178676Ssam uint16_t flags; 764198429Srpaulo#define IWN_PS_ALLOW_SLEEP (1 << 0) 765198429Srpaulo#define IWN_PS_NOTIFY (1 << 1) 766198429Srpaulo#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 767198429Srpaulo#define IWN_PS_PCI_PMGT (1 << 3) 768198429Srpaulo#define IWN_PS_FAST_PD (1 << 4) 769178676Ssam 770198429Srpaulo uint8_t keepalive; 771178676Ssam uint8_t debug; 772198429Srpaulo uint32_t rxtimeout; 773198429Srpaulo uint32_t txtimeout; 774198429Srpaulo uint32_t intval[5]; 775178676Ssam uint32_t beacons; 776178676Ssam} __packed; 777178676Ssam 778198429Srpaulo/* Structures for command IWN_CMD_SCAN. */ 779178676Ssamstruct iwn_scan_essid { 780178676Ssam uint8_t id; 781178676Ssam uint8_t len; 782178676Ssam uint8_t data[IEEE80211_NWID_LEN]; 783178676Ssam} __packed; 784178676Ssam 785178676Ssamstruct iwn_scan_hdr { 786178676Ssam uint16_t len; 787178676Ssam uint8_t reserved1; 788178676Ssam uint8_t nchan; 789198429Srpaulo uint16_t quiet_time; 790198429Srpaulo uint16_t quiet_threshold; 791178676Ssam uint16_t crc_threshold; 792178676Ssam uint16_t rxchain; 793178676Ssam uint32_t max_svc; /* background scans */ 794178676Ssam uint32_t pause_svc; /* background scans */ 795178676Ssam uint32_t flags; 796178676Ssam uint32_t filter; 797178676Ssam 798198429Srpaulo /* Followed by a struct iwn_cmd_data. */ 799198429Srpaulo /* Followed by an array of 20 structs iwn_scan_essid. */ 800198429Srpaulo /* Followed by probe request body. */ 801198429Srpaulo /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 802178676Ssam} __packed; 803178676Ssam 804178676Ssamstruct iwn_scan_chan { 805198429Srpaulo uint32_t flags; 806198429Srpaulo#define IWN_CHAN_ACTIVE (1 << 0) 807198429Srpaulo#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 808178676Ssam 809198429Srpaulo uint16_t chan; 810178676Ssam uint8_t rf_gain; 811178676Ssam uint8_t dsp_gain; 812178676Ssam uint16_t active; /* msecs */ 813178676Ssam uint16_t passive; /* msecs */ 814178676Ssam} __packed; 815178676Ssam 816198429Srpaulo/* Maximum size of a scan command. */ 817198429Srpaulo#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 818198429Srpaulo 819198429Srpaulo/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 820178676Ssam#define IWN_RIDX_MAX 32 821198429Srpaulostruct iwn4965_cmd_txpower { 822198429Srpaulo uint8_t band; 823198429Srpaulo uint8_t reserved1; 824198429Srpaulo uint8_t chan; 825198429Srpaulo uint8_t reserved2; 826178676Ssam struct { 827198429Srpaulo uint8_t rf_gain[2]; 828198429Srpaulo uint8_t dsp_gain[2]; 829198429Srpaulo } __packed power[IWN_RIDX_MAX + 1]; 830178676Ssam} __packed; 831178676Ssam 832198429Srpaulo/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 833198429Srpaulostruct iwn5000_cmd_txpower { 834198429Srpaulo int8_t global_limit; /* in half-dBm */ 835198429Srpaulo#define IWN5000_TXPOWER_AUTO 0x7f 836198429Srpaulo#define IWN5000_TXPOWER_MAX_DBM 16 837198429Srpaulo 838198429Srpaulo uint8_t flags; 839198429Srpaulo#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 840198429Srpaulo 841198429Srpaulo int8_t srv_limit; /* in half-dBm */ 842198429Srpaulo uint8_t reserved; 843198429Srpaulo} __packed; 844198429Srpaulo 845220891Sbschmidt/* Structures for command IWN_CMD_BLUETOOTH. */ 846178676Ssamstruct iwn_bluetooth { 847178676Ssam uint8_t flags; 848206444Sbschmidt#define IWN_BT_COEX_CHAN_ANN (1 << 0) 849206444Sbschmidt#define IWN_BT_COEX_BT_PRIO (1 << 1) 850206444Sbschmidt#define IWN_BT_COEX_2_WIRE (1 << 2) 851201209Srpaulo 852201209Srpaulo uint8_t lead_time; 853201209Srpaulo#define IWN_BT_LEAD_TIME_DEF 30 854201209Srpaulo 855201209Srpaulo uint8_t max_kill; 856201209Srpaulo#define IWN_BT_MAX_KILL_DEF 5 857201209Srpaulo 858178676Ssam uint8_t reserved; 859201209Srpaulo uint32_t kill_ack; 860201209Srpaulo uint32_t kill_cts; 861178676Ssam} __packed; 862178676Ssam 863220891Sbschmidtstruct iwn6000_btcoex_config { 864220891Sbschmidt uint8_t flags; 865220891Sbschmidt uint8_t lead_time; 866220891Sbschmidt uint8_t max_kill; 867220891Sbschmidt uint8_t bt3_t7_timer; 868220891Sbschmidt uint32_t kill_ack; 869220891Sbschmidt uint32_t kill_cts; 870220891Sbschmidt uint8_t sample_time; 871220891Sbschmidt uint8_t bt3_t2_timer; 872220891Sbschmidt uint16_t bt4_reaction; 873220891Sbschmidt uint32_t lookup_table[12]; 874220891Sbschmidt uint16_t bt4_decision; 875220891Sbschmidt uint16_t valid; 876220891Sbschmidt uint8_t prio_boost; 877220891Sbschmidt uint8_t tx_prio_boost; 878220891Sbschmidt uint16_t rx_prio_boost; 879220891Sbschmidt} __packed; 880220891Sbschmidt 881220891Sbschmidtstruct iwn_btcoex_priotable { 882220891Sbschmidt uint8_t calib_init1; 883220891Sbschmidt uint8_t calib_init2; 884220891Sbschmidt uint8_t calib_periodic_low1; 885220891Sbschmidt uint8_t calib_periodic_low2; 886220891Sbschmidt uint8_t calib_periodic_high1; 887220891Sbschmidt uint8_t calib_periodic_high2; 888220891Sbschmidt uint8_t dtim; 889220891Sbschmidt uint8_t scan52; 890220891Sbschmidt uint8_t scan24; 891220891Sbschmidt uint8_t reserved[7]; 892220891Sbschmidt} __packed; 893220891Sbschmidt 894220891Sbschmidtstruct iwn_btcoex_prot { 895220891Sbschmidt uint8_t open; 896220891Sbschmidt uint8_t type; 897220891Sbschmidt uint8_t reserved[2]; 898220891Sbschmidt} __packed; 899220891Sbschmidt 900198429Srpaulo/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 901178676Ssamstruct iwn_critical_temp { 902178676Ssam uint32_t reserved; 903178676Ssam uint32_t tempM; 904178676Ssam uint32_t tempR; 905198429Srpaulo/* degK <-> degC conversion macros. */ 906178676Ssam#define IWN_CTOK(c) ((c) + 273) 907178676Ssam#define IWN_KTOC(k) ((k) - 273) 908178676Ssam#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 909178676Ssam} __packed; 910178676Ssam 911220729Sbschmidt/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 912178676Ssamstruct iwn_sensitivity_cmd { 913178676Ssam uint16_t which; 914178676Ssam#define IWN_SENSITIVITY_DEFAULTTBL 0 915178676Ssam#define IWN_SENSITIVITY_WORKTBL 1 916178676Ssam 917178676Ssam uint16_t energy_cck; 918178676Ssam uint16_t energy_ofdm; 919178676Ssam uint16_t corr_ofdm_x1; 920178676Ssam uint16_t corr_ofdm_mrc_x1; 921178676Ssam uint16_t corr_cck_mrc_x4; 922178676Ssam uint16_t corr_ofdm_x4; 923178676Ssam uint16_t corr_ofdm_mrc_x4; 924178676Ssam uint16_t corr_barker; 925178676Ssam uint16_t corr_barker_mrc; 926178676Ssam uint16_t corr_cck_x4; 927178676Ssam uint16_t energy_ofdm_th; 928178676Ssam} __packed; 929178676Ssam 930220729Sbschmidtstruct iwn_enhanced_sensitivity_cmd { 931220729Sbschmidt uint16_t which; 932220729Sbschmidt uint16_t energy_cck; 933220729Sbschmidt uint16_t energy_ofdm; 934220729Sbschmidt uint16_t corr_ofdm_x1; 935220729Sbschmidt uint16_t corr_ofdm_mrc_x1; 936220729Sbschmidt uint16_t corr_cck_mrc_x4; 937220729Sbschmidt uint16_t corr_ofdm_x4; 938220729Sbschmidt uint16_t corr_ofdm_mrc_x4; 939220729Sbschmidt uint16_t corr_barker; 940220729Sbschmidt uint16_t corr_barker_mrc; 941220729Sbschmidt uint16_t corr_cck_x4; 942220729Sbschmidt uint16_t energy_ofdm_th; 943220729Sbschmidt /* "Enhanced" part. */ 944220729Sbschmidt uint16_t ina_det_ofdm; 945220729Sbschmidt uint16_t ina_det_cck; 946220729Sbschmidt uint16_t corr_11_9_en; 947220729Sbschmidt uint16_t ofdm_det_slope_mrc; 948220729Sbschmidt uint16_t ofdm_det_icept_mrc; 949220729Sbschmidt uint16_t ofdm_det_slope; 950220729Sbschmidt uint16_t ofdm_det_icept; 951220729Sbschmidt uint16_t cck_det_slope_mrc; 952220729Sbschmidt uint16_t cck_det_icept_mrc; 953220729Sbschmidt uint16_t cck_det_slope; 954220729Sbschmidt uint16_t cck_det_icept; 955220729Sbschmidt uint16_t reserved; 956220729Sbschmidt} __packed; 957220729Sbschmidt 958198429Srpaulo/* Structures for command IWN_CMD_PHY_CALIB. */ 959198429Srpaulostruct iwn_phy_calib { 960198429Srpaulo uint8_t code; 961198429Srpaulo#define IWN4965_PHY_CALIB_DIFF_GAIN 7 962198429Srpaulo#define IWN5000_PHY_CALIB_DC 8 963198429Srpaulo#define IWN5000_PHY_CALIB_LO 9 964198429Srpaulo#define IWN5000_PHY_CALIB_TX_IQ 11 965198429Srpaulo#define IWN5000_PHY_CALIB_CRYSTAL 15 966198429Srpaulo#define IWN5000_PHY_CALIB_BASE_BAND 16 967201209Srpaulo#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 968220676Sbschmidt#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 969220676Sbschmidt 970198429Srpaulo#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 971198429Srpaulo#define IWN5000_PHY_CALIB_NOISE_GAIN 19 972178676Ssam 973198429Srpaulo uint8_t group; 974198429Srpaulo uint8_t ngroups; 975198429Srpaulo uint8_t isvalid; 976198429Srpaulo} __packed; 977178676Ssam 978198429Srpaulostruct iwn5000_phy_calib_crystal { 979198429Srpaulo uint8_t code; 980198429Srpaulo uint8_t group; 981198429Srpaulo uint8_t ngroups; 982198429Srpaulo uint8_t isvalid; 983198429Srpaulo 984198429Srpaulo uint8_t cap_pin[2]; 985198429Srpaulo uint8_t reserved[2]; 986178676Ssam} __packed; 987178676Ssam 988220676Sbschmidtstruct iwn5000_phy_calib_temp_offset { 989220676Sbschmidt uint8_t code; 990220676Sbschmidt uint8_t group; 991220676Sbschmidt uint8_t ngroups; 992220676Sbschmidt uint8_t isvalid; 993220676Sbschmidt int16_t offset; 994220676Sbschmidt#define IWN_DEFAULT_TEMP_OFFSET 2700 995220676Sbschmidt 996220676Sbschmidt uint16_t reserved; 997220676Sbschmidt} __packed; 998220676Sbschmidt 999198429Srpaulostruct iwn_phy_calib_gain { 1000198429Srpaulo uint8_t code; 1001198429Srpaulo uint8_t group; 1002198429Srpaulo uint8_t ngroups; 1003198429Srpaulo uint8_t isvalid; 1004178676Ssam 1005198429Srpaulo int8_t gain[3]; 1006198429Srpaulo uint8_t reserved; 1007198429Srpaulo} __packed; 1008198429Srpaulo 1009198429Srpaulo/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1010198429Srpaulostruct iwn_spectrum_cmd { 1011198429Srpaulo uint16_t len; 1012198429Srpaulo uint8_t token; 1013198429Srpaulo uint8_t id; 1014198429Srpaulo uint8_t origin; 1015198429Srpaulo uint8_t periodic; 1016198429Srpaulo uint16_t timeout; 1017198429Srpaulo uint32_t start; 1018198429Srpaulo uint32_t reserved1; 1019198429Srpaulo uint32_t flags; 1020198429Srpaulo uint32_t filter; 1021198429Srpaulo uint16_t nchan; 1022198429Srpaulo uint16_t reserved2; 1023198429Srpaulo struct { 1024198429Srpaulo uint32_t duration; 1025198429Srpaulo uint8_t chan; 1026198429Srpaulo uint8_t type; 1027198429Srpaulo#define IWN_MEASUREMENT_BASIC (1 << 0) 1028198429Srpaulo#define IWN_MEASUREMENT_CCA (1 << 1) 1029198429Srpaulo#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1030198429Srpaulo#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1031198429Srpaulo#define IWN_MEASUREMENT_FRAME (1 << 4) 1032198429Srpaulo#define IWN_MEASUREMENT_IDLE (1 << 7) 1033198429Srpaulo 1034198429Srpaulo uint16_t reserved; 1035198429Srpaulo } __packed chan[10]; 1036198429Srpaulo} __packed; 1037198429Srpaulo 1038198429Srpaulo/* Structure for IWN_UC_READY notification. */ 1039178676Ssam#define IWN_NATTEN_GROUPS 5 1040178676Ssamstruct iwn_ucode_info { 1041178676Ssam uint8_t minor; 1042178676Ssam uint8_t major; 1043178676Ssam uint16_t reserved1; 1044178676Ssam uint8_t revision[8]; 1045178676Ssam uint8_t type; 1046178676Ssam uint8_t subtype; 1047178676Ssam#define IWN_UCODE_RUNTIME 0 1048178676Ssam#define IWN_UCODE_INIT 9 1049178676Ssam 1050178676Ssam uint16_t reserved2; 1051178676Ssam uint32_t logptr; 1052198429Srpaulo uint32_t errptr; 1053178676Ssam uint32_t tstamp; 1054178676Ssam uint32_t valid; 1055178676Ssam 1056198429Srpaulo /* The following fields are for UCODE_INIT only. */ 1057178676Ssam int32_t volt; 1058178676Ssam struct { 1059178676Ssam int32_t chan20MHz; 1060178676Ssam int32_t chan40MHz; 1061178676Ssam } __packed temp[4]; 1062198429Srpaulo int32_t atten[IWN_NATTEN_GROUPS][2]; 1063178676Ssam} __packed; 1064178676Ssam 1065198429Srpaulo/* Structures for IWN_TX_DONE notification. */ 1066198429Srpaulo#define IWN_TX_SUCCESS 0x00 1067198429Srpaulo#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1068198429Srpaulo#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1069198429Srpaulo#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1070198429Srpaulo#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1071198429Srpaulo#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1072198429Srpaulo#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1073198429Srpaulo 1074198429Srpaulostruct iwn4965_tx_stat { 1075178676Ssam uint8_t nframes; 1076201209Srpaulo uint8_t btkillcnt; 1077201209Srpaulo uint8_t rtsfailcnt; 1078201209Srpaulo uint8_t ackfailcnt; 1079221648Sbschmidt uint32_t rate; 1080178676Ssam uint16_t duration; 1081178676Ssam uint16_t reserved; 1082178676Ssam uint32_t power[2]; 1083178676Ssam uint32_t status; 1084178676Ssam} __packed; 1085178676Ssam 1086198429Srpaulostruct iwn5000_tx_stat { 1087198429Srpaulo uint8_t nframes; 1088201209Srpaulo uint8_t btkillcnt; 1089201209Srpaulo uint8_t rtsfailcnt; 1090201209Srpaulo uint8_t ackfailcnt; 1091221648Sbschmidt uint32_t rate; 1092198429Srpaulo uint16_t duration; 1093198429Srpaulo uint16_t reserved; 1094198429Srpaulo uint32_t power[2]; 1095198429Srpaulo uint32_t info; 1096198429Srpaulo uint16_t seq; 1097198429Srpaulo uint16_t len; 1098201209Srpaulo uint8_t tlc; 1099201209Srpaulo uint8_t ratid; 1100201209Srpaulo uint8_t fc[2]; 1101198429Srpaulo uint16_t status; 1102198429Srpaulo uint16_t sequence; 1103198429Srpaulo} __packed; 1104198429Srpaulo 1105198429Srpaulo/* Structure for IWN_BEACON_MISSED notification. */ 1106178676Ssamstruct iwn_beacon_missed { 1107178676Ssam uint32_t consecutive; 1108178676Ssam uint32_t total; 1109178676Ssam uint32_t expected; 1110178676Ssam uint32_t received; 1111178676Ssam} __packed; 1112178676Ssam 1113198429Srpaulo/* Structure for IWN_MPDU_RX_DONE notification. */ 1114198429Srpaulostruct iwn_rx_mpdu { 1115178676Ssam uint16_t len; 1116178676Ssam uint16_t reserved; 1117178676Ssam} __packed; 1118178676Ssam 1119198429Srpaulo/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1120198429Srpaulostruct iwn4965_rx_phystat { 1121198429Srpaulo uint16_t antenna; 1122198429Srpaulo uint16_t agc; 1123198429Srpaulo uint8_t rssi[6]; 1124198429Srpaulo} __packed; 1125198429Srpaulo 1126198429Srpaulostruct iwn5000_rx_phystat { 1127198429Srpaulo uint32_t reserved1; 1128198429Srpaulo uint32_t agc; 1129198429Srpaulo uint16_t rssi[3]; 1130198429Srpaulo} __packed; 1131198429Srpaulo 1132178676Ssamstruct iwn_rx_stat { 1133178676Ssam uint8_t phy_len; 1134178676Ssam uint8_t cfg_phy_len; 1135178676Ssam#define IWN_STAT_MAXLEN 20 1136178676Ssam 1137178676Ssam uint8_t id; 1138178676Ssam uint8_t reserved1; 1139178676Ssam uint64_t tstamp; 1140178676Ssam uint32_t beacon; 1141178676Ssam uint16_t flags; 1142198429Srpaulo#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1143198429Srpaulo 1144178676Ssam uint16_t chan; 1145198429Srpaulo uint8_t phybuf[32]; 1146221648Sbschmidt uint32_t rate; 1147178676Ssam uint16_t len; 1148178676Ssam uint16_t reserve3; 1149178676Ssam} __packed; 1150178676Ssam 1151198429Srpaulo#define IWN_RSSI_TO_DBM 44 1152198429Srpaulo 1153201209Srpaulo/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1154201209Srpaulostruct iwn_compressed_ba { 1155201209Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 1156201209Srpaulo uint16_t reserved; 1157201209Srpaulo uint8_t id; 1158201209Srpaulo uint8_t tid; 1159201209Srpaulo uint16_t seq; 1160201209Srpaulo uint64_t bitmap; 1161201209Srpaulo uint16_t qid; 1162201209Srpaulo uint16_t ssn; 1163201209Srpaulo} __packed; 1164201209Srpaulo 1165198429Srpaulo/* Structure for IWN_START_SCAN notification. */ 1166178676Ssamstruct iwn_start_scan { 1167178676Ssam uint64_t tstamp; 1168178676Ssam uint32_t tbeacon; 1169178676Ssam uint8_t chan; 1170178676Ssam uint8_t band; 1171178676Ssam uint16_t reserved; 1172178676Ssam uint32_t status; 1173178676Ssam} __packed; 1174178676Ssam 1175198429Srpaulo/* Structure for IWN_STOP_SCAN notification. */ 1176178676Ssamstruct iwn_stop_scan { 1177178676Ssam uint8_t nchan; 1178178676Ssam uint8_t status; 1179178676Ssam uint8_t reserved; 1180178676Ssam uint8_t chan; 1181178676Ssam uint64_t tsf; 1182178676Ssam} __packed; 1183178676Ssam 1184198429Srpaulo/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1185198429Srpaulostruct iwn_spectrum_notif { 1186198429Srpaulo uint8_t id; 1187198429Srpaulo uint8_t token; 1188198429Srpaulo uint8_t idx; 1189198429Srpaulo uint8_t state; 1190198429Srpaulo#define IWN_MEASUREMENT_START 0 1191198429Srpaulo#define IWN_MEASUREMENT_STOP 1 1192198429Srpaulo 1193198429Srpaulo uint32_t start; 1194198429Srpaulo uint8_t band; 1195198429Srpaulo uint8_t chan; 1196198429Srpaulo uint8_t type; 1197198429Srpaulo uint8_t reserved1; 1198198429Srpaulo uint32_t cca_ofdm; 1199198429Srpaulo uint32_t cca_cck; 1200198429Srpaulo uint32_t cca_time; 1201198429Srpaulo uint8_t basic; 1202198429Srpaulo uint8_t reserved2[3]; 1203198429Srpaulo uint32_t ofdm[8]; 1204198429Srpaulo uint32_t cck[8]; 1205198429Srpaulo uint32_t stop; 1206198429Srpaulo uint32_t status; 1207198429Srpaulo#define IWN_MEASUREMENT_OK 0 1208198429Srpaulo#define IWN_MEASUREMENT_CONCURRENT 1 1209198429Srpaulo#define IWN_MEASUREMENT_CSA_CONFLICT 2 1210198429Srpaulo#define IWN_MEASUREMENT_TGH_CONFLICT 3 1211198429Srpaulo#define IWN_MEASUREMENT_STOPPED 6 1212198429Srpaulo#define IWN_MEASUREMENT_TIMEOUT 7 1213198429Srpaulo#define IWN_MEASUREMENT_FAILED 8 1214198429Srpaulo} __packed; 1215198429Srpaulo 1216201209Srpaulo/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1217178676Ssamstruct iwn_rx_phy_stats { 1218178676Ssam uint32_t ina; 1219178676Ssam uint32_t fina; 1220178676Ssam uint32_t bad_plcp; 1221178676Ssam uint32_t bad_crc32; 1222178676Ssam uint32_t overrun; 1223178676Ssam uint32_t eoverrun; 1224178676Ssam uint32_t good_crc32; 1225178676Ssam uint32_t fa; 1226178676Ssam uint32_t bad_fina_sync; 1227178676Ssam uint32_t sfd_timeout; 1228178676Ssam uint32_t fina_timeout; 1229178676Ssam uint32_t no_rts_ack; 1230178676Ssam uint32_t rxe_limit; 1231178676Ssam uint32_t ack; 1232178676Ssam uint32_t cts; 1233178676Ssam uint32_t ba_resp; 1234178676Ssam uint32_t dsp_kill; 1235178676Ssam uint32_t bad_mh; 1236178676Ssam uint32_t rssi_sum; 1237178676Ssam uint32_t reserved; 1238178676Ssam} __packed; 1239178676Ssam 1240178676Ssamstruct iwn_rx_general_stats { 1241178676Ssam uint32_t bad_cts; 1242178676Ssam uint32_t bad_ack; 1243178676Ssam uint32_t not_bss; 1244178676Ssam uint32_t filtered; 1245178676Ssam uint32_t bad_chan; 1246178676Ssam uint32_t beacons; 1247178676Ssam uint32_t missed_beacons; 1248178676Ssam uint32_t adc_saturated; /* time in 0.8us */ 1249178676Ssam uint32_t ina_searched; /* time in 0.8us */ 1250178676Ssam uint32_t noise[3]; 1251178676Ssam uint32_t flags; 1252178676Ssam uint32_t load; 1253178676Ssam uint32_t fa; 1254178676Ssam uint32_t rssi[3]; 1255178676Ssam uint32_t energy[3]; 1256178676Ssam} __packed; 1257178676Ssam 1258178676Ssamstruct iwn_rx_ht_phy_stats { 1259178676Ssam uint32_t bad_plcp; 1260178676Ssam uint32_t overrun; 1261178676Ssam uint32_t eoverrun; 1262178676Ssam uint32_t good_crc32; 1263178676Ssam uint32_t bad_crc32; 1264178676Ssam uint32_t bad_mh; 1265178676Ssam uint32_t good_ampdu_crc32; 1266178676Ssam uint32_t ampdu; 1267178676Ssam uint32_t fragment; 1268178676Ssam uint32_t reserved; 1269178676Ssam} __packed; 1270178676Ssam 1271178676Ssamstruct iwn_rx_stats { 1272178676Ssam struct iwn_rx_phy_stats ofdm; 1273178676Ssam struct iwn_rx_phy_stats cck; 1274178676Ssam struct iwn_rx_general_stats general; 1275178676Ssam struct iwn_rx_ht_phy_stats ht; 1276178676Ssam} __packed; 1277178676Ssam 1278178676Ssamstruct iwn_tx_stats { 1279178676Ssam uint32_t preamble; 1280178676Ssam uint32_t rx_detected; 1281178676Ssam uint32_t bt_defer; 1282178676Ssam uint32_t bt_kill; 1283178676Ssam uint32_t short_len; 1284178676Ssam uint32_t cts_timeout; 1285178676Ssam uint32_t ack_timeout; 1286178676Ssam uint32_t exp_ack; 1287178676Ssam uint32_t ack; 1288178676Ssam uint32_t msdu; 1289178676Ssam uint32_t busrt_err1; 1290178676Ssam uint32_t burst_err2; 1291178676Ssam uint32_t cts_collision; 1292178676Ssam uint32_t ack_collision; 1293178676Ssam uint32_t ba_timeout; 1294178676Ssam uint32_t ba_resched; 1295178676Ssam uint32_t query_ampdu; 1296178676Ssam uint32_t query; 1297178676Ssam uint32_t query_ampdu_frag; 1298178676Ssam uint32_t query_mismatch; 1299178676Ssam uint32_t not_ready; 1300178676Ssam uint32_t underrun; 1301178676Ssam uint32_t bt_ht_kill; 1302178676Ssam uint32_t rx_ba_resp; 1303178676Ssam uint32_t reserved[2]; 1304178676Ssam} __packed; 1305178676Ssam 1306178676Ssamstruct iwn_general_stats { 1307178676Ssam uint32_t temp; 1308178676Ssam uint32_t temp_m; 1309178676Ssam uint32_t burst_check; 1310178676Ssam uint32_t burst; 1311178676Ssam uint32_t reserved1[4]; 1312178676Ssam uint32_t sleep; 1313178676Ssam uint32_t slot_out; 1314178676Ssam uint32_t slot_idle; 1315178676Ssam uint32_t ttl_tstamp; 1316178676Ssam uint32_t tx_ant_a; 1317178676Ssam uint32_t tx_ant_b; 1318178676Ssam uint32_t exec; 1319178676Ssam uint32_t probe; 1320178676Ssam uint32_t reserved2[2]; 1321178676Ssam uint32_t rx_enabled; 1322178676Ssam uint32_t reserved3[3]; 1323178676Ssam} __packed; 1324178676Ssam 1325178676Ssamstruct iwn_stats { 1326178676Ssam uint32_t flags; 1327178676Ssam struct iwn_rx_stats rx; 1328178676Ssam struct iwn_tx_stats tx; 1329178676Ssam struct iwn_general_stats general; 1330178676Ssam} __packed; 1331178676Ssam 1332178676Ssam 1333198429Srpaulo/* Firmware error dump. */ 1334198429Srpaulostruct iwn_fw_dump { 1335198429Srpaulo uint32_t valid; 1336198429Srpaulo uint32_t id; 1337198429Srpaulo uint32_t pc; 1338198429Srpaulo uint32_t branch_link[2]; 1339198429Srpaulo uint32_t interrupt_link[2]; 1340198429Srpaulo uint32_t error_data[2]; 1341198429Srpaulo uint32_t src_line; 1342198429Srpaulo uint32_t tsf; 1343198429Srpaulo uint32_t time[2]; 1344198429Srpaulo} __packed; 1345198429Srpaulo 1346210111Sbschmidt/* TLV firmware header. */ 1347210111Sbschmidtstruct iwn_fw_tlv_hdr { 1348210111Sbschmidt uint32_t zero; /* Always 0, to differentiate from legacy. */ 1349210111Sbschmidt uint32_t signature; 1350210111Sbschmidt#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1351210111Sbschmidt 1352210111Sbschmidt uint8_t descr[64]; 1353210111Sbschmidt uint32_t rev; 1354210111Sbschmidt#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1355210111Sbschmidt 1356210111Sbschmidt uint32_t build; 1357210111Sbschmidt uint64_t altmask; 1358210111Sbschmidt} __packed; 1359210111Sbschmidt 1360210111Sbschmidt/* TLV header. */ 1361210111Sbschmidtstruct iwn_fw_tlv { 1362210111Sbschmidt uint16_t type; 1363210111Sbschmidt#define IWN_FW_TLV_MAIN_TEXT 1 1364210111Sbschmidt#define IWN_FW_TLV_MAIN_DATA 2 1365210111Sbschmidt#define IWN_FW_TLV_INIT_TEXT 3 1366210111Sbschmidt#define IWN_FW_TLV_INIT_DATA 4 1367210111Sbschmidt#define IWN_FW_TLV_BOOT_TEXT 5 1368210111Sbschmidt#define IWN_FW_TLV_PBREQ_MAXLEN 6 1369220866Sbschmidt#define IWN_FW_TLV_ENH_SENS 14 1370220866Sbschmidt#define IWN_FW_TLV_PHY_CALIB 15 1371210111Sbschmidt 1372210111Sbschmidt uint16_t alt; 1373210111Sbschmidt uint32_t len; 1374210111Sbschmidt} __packed; 1375210111Sbschmidt 1376198429Srpaulo#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1377198429Srpaulo#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1378198429Srpaulo#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1379198429Srpaulo#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1380178676Ssam#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1381198429Srpaulo#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1382198429Srpaulo#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1383178676Ssam 1384178676Ssam/* 1385178676Ssam * Offsets into EEPROM. 1386178676Ssam */ 1387178676Ssam#define IWN_EEPROM_MAC 0x015 1388220729Sbschmidt#define IWN_EEPROM_SKU_CAP 0x045 1389198429Srpaulo#define IWN_EEPROM_RFCFG 0x048 1390198429Srpaulo#define IWN4965_EEPROM_DOMAIN 0x060 1391198429Srpaulo#define IWN4965_EEPROM_BAND1 0x063 1392198429Srpaulo#define IWN5000_EEPROM_REG 0x066 1393198429Srpaulo#define IWN5000_EEPROM_CAL 0x067 1394198429Srpaulo#define IWN4965_EEPROM_BAND2 0x072 1395198429Srpaulo#define IWN4965_EEPROM_BAND3 0x080 1396198429Srpaulo#define IWN4965_EEPROM_BAND4 0x08d 1397198429Srpaulo#define IWN4965_EEPROM_BAND5 0x099 1398198429Srpaulo#define IWN4965_EEPROM_BAND6 0x0a0 1399198429Srpaulo#define IWN4965_EEPROM_BAND7 0x0a8 1400198429Srpaulo#define IWN4965_EEPROM_MAXPOW 0x0e8 1401198429Srpaulo#define IWN4965_EEPROM_VOLTAGE 0x0e9 1402198429Srpaulo#define IWN4965_EEPROM_BANDS 0x0ea 1403198429Srpaulo/* Indirect offsets. */ 1404198429Srpaulo#define IWN5000_EEPROM_DOMAIN 0x001 1405198429Srpaulo#define IWN5000_EEPROM_BAND1 0x004 1406198429Srpaulo#define IWN5000_EEPROM_BAND2 0x013 1407198429Srpaulo#define IWN5000_EEPROM_BAND3 0x021 1408198429Srpaulo#define IWN5000_EEPROM_BAND4 0x02e 1409198429Srpaulo#define IWN5000_EEPROM_BAND5 0x03a 1410198429Srpaulo#define IWN5000_EEPROM_BAND6 0x041 1411221635Sbschmidt#define IWN6000_EEPROM_BAND6 0x040 1412198429Srpaulo#define IWN5000_EEPROM_BAND7 0x049 1413201209Srpaulo#define IWN6000_EEPROM_ENHINFO 0x054 1414198429Srpaulo#define IWN5000_EEPROM_CRYSTAL 0x128 1415198429Srpaulo#define IWN5000_EEPROM_TEMP 0x12a 1416198429Srpaulo#define IWN5000_EEPROM_VOLT 0x12b 1417178676Ssam 1418220729Sbschmidt/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1419220729Sbschmidt#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1420220729Sbschmidt#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1421220729Sbschmidt#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1422220729Sbschmidt 1423198429Srpaulo/* Possible flags for IWN_EEPROM_RFCFG. */ 1424198429Srpaulo#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1425198429Srpaulo#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1426198429Srpaulo#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1427198429Srpaulo#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1428198429Srpaulo#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1429198429Srpaulo 1430178676Ssamstruct iwn_eeprom_chan { 1431178676Ssam uint8_t flags; 1432178676Ssam#define IWN_EEPROM_CHAN_VALID (1 << 0) 1433198429Srpaulo#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1434198429Srpaulo#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1435198429Srpaulo#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1436178676Ssam 1437178676Ssam int8_t maxpwr; 1438178676Ssam} __packed; 1439178676Ssam 1440201209Srpaulostruct iwn_eeprom_enhinfo { 1441221637Sbschmidt uint8_t flags; 1442221637Sbschmidt#define IWN_ENHINFO_VALID 0x01 1443221637Sbschmidt#define IWN_ENHINFO_5GHZ 0x02 1444221637Sbschmidt#define IWN_ENHINFO_OFDM 0x04 1445221637Sbschmidt#define IWN_ENHINFO_HT40 0x08 1446221637Sbschmidt#define IWN_ENHINFO_HTAP 0x10 1447221637Sbschmidt#define IWN_ENHINFO_RES1 0x20 1448221637Sbschmidt#define IWN_ENHINFO_RES2 0x40 1449221637Sbschmidt#define IWN_ENHINFO_COMMON 0x80 1450221637Sbschmidt 1451221637Sbschmidt uint8_t chan; 1452201209Srpaulo int8_t chain[3]; /* max power in half-dBm */ 1453201209Srpaulo uint8_t reserved; 1454201209Srpaulo int8_t mimo2; /* max power in half-dBm */ 1455201209Srpaulo int8_t mimo3; /* max power in half-dBm */ 1456201209Srpaulo} __packed; 1457201209Srpaulo 1458206444Sbschmidtstruct iwn5000_eeprom_calib_hdr { 1459206444Sbschmidt uint8_t version; 1460206444Sbschmidt uint8_t pa_type; 1461206444Sbschmidt uint16_t volt; 1462206444Sbschmidt} __packed; 1463206444Sbschmidt 1464178676Ssam#define IWN_NSAMPLES 3 1465198429Srpaulostruct iwn4965_eeprom_chan_samples { 1466178676Ssam uint8_t num; 1467178676Ssam struct { 1468178676Ssam uint8_t temp; 1469178676Ssam uint8_t gain; 1470178676Ssam uint8_t power; 1471178676Ssam int8_t pa_det; 1472198429Srpaulo } samples[2][IWN_NSAMPLES]; 1473178676Ssam} __packed; 1474178676Ssam 1475178676Ssam#define IWN_NBANDS 8 1476198429Srpaulostruct iwn4965_eeprom_band { 1477178676Ssam uint8_t lo; /* low channel number */ 1478178676Ssam uint8_t hi; /* high channel number */ 1479198429Srpaulo struct iwn4965_eeprom_chan_samples chans[2]; 1480178676Ssam} __packed; 1481178676Ssam 1482198429Srpaulo/* 1483198429Srpaulo * Offsets of channels descriptions in EEPROM. 1484198429Srpaulo */ 1485198429Srpaulostatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1486198429Srpaulo IWN4965_EEPROM_BAND1, 1487198429Srpaulo IWN4965_EEPROM_BAND2, 1488198429Srpaulo IWN4965_EEPROM_BAND3, 1489198429Srpaulo IWN4965_EEPROM_BAND4, 1490198429Srpaulo IWN4965_EEPROM_BAND5, 1491198429Srpaulo IWN4965_EEPROM_BAND6, 1492198429Srpaulo IWN4965_EEPROM_BAND7 1493198429Srpaulo}; 1494178676Ssam 1495198429Srpaulostatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1496198429Srpaulo IWN5000_EEPROM_BAND1, 1497198429Srpaulo IWN5000_EEPROM_BAND2, 1498198429Srpaulo IWN5000_EEPROM_BAND3, 1499198429Srpaulo IWN5000_EEPROM_BAND4, 1500198429Srpaulo IWN5000_EEPROM_BAND5, 1501198429Srpaulo IWN5000_EEPROM_BAND6, 1502198429Srpaulo IWN5000_EEPROM_BAND7 1503198429Srpaulo}; 1504198429Srpaulo 1505221635Sbschmidtstatic const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1506221635Sbschmidt IWN5000_EEPROM_BAND1, 1507221635Sbschmidt IWN5000_EEPROM_BAND2, 1508221635Sbschmidt IWN5000_EEPROM_BAND3, 1509221635Sbschmidt IWN5000_EEPROM_BAND4, 1510221635Sbschmidt IWN5000_EEPROM_BAND5, 1511221635Sbschmidt IWN6000_EEPROM_BAND6, 1512221635Sbschmidt IWN5000_EEPROM_BAND7 1513221635Sbschmidt}; 1514221635Sbschmidt 1515198429Srpaulo#define IWN_CHAN_BANDS_COUNT 7 1516198429Srpaulo#define IWN_MAX_CHAN_PER_BAND 14 1517198429Srpaulostatic const struct iwn_chan_band { 1518198429Srpaulo uint8_t nchan; 1519198429Srpaulo uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1520198429Srpaulo} iwn_bands[] = { 1521198429Srpaulo /* 20MHz channels, 2GHz band. */ 1522198429Srpaulo { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1523198429Srpaulo /* 20MHz channels, 5GHz band. */ 1524198429Srpaulo { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1525198429Srpaulo { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1526198429Srpaulo { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1527198429Srpaulo { 6, { 145, 149, 153, 157, 161, 165 } }, 1528198429Srpaulo /* 40MHz channels (primary channels), 2GHz band. */ 1529198429Srpaulo { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1530198429Srpaulo /* 40MHz channels (primary channels), 5GHz band. */ 1531198429Srpaulo { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1532198429Srpaulo}; 1533198429Srpaulo 1534220726Sbschmidt#define IWN1000_OTP_NBLOCKS 3 1535220726Sbschmidt#define IWN6000_OTP_NBLOCKS 4 1536201209Srpaulo#define IWN6050_OTP_NBLOCKS 7 1537198429Srpaulo 1538198429Srpaulo/* HW rate indices. */ 1539220715Sbschmidt#define IWN_RIDX_CCK1 0 1540220715Sbschmidt#define IWN_RIDX_OFDM6 4 1541198429Srpaulo 1542198429Srpaulo#define IWN4965_MAX_PWR_INDEX 107 1543198429Srpaulo 1544178676Ssam/* 1545178676Ssam * RF Tx gain values from highest to lowest power (values obtained from 1546178676Ssam * the reference driver.) 1547178676Ssam */ 1548198429Srpaulostatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1549178676Ssam 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1550178676Ssam 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1551178676Ssam 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1552178676Ssam 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1553178676Ssam 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1554178676Ssam 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1555178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1556178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1557178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1558178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1559178676Ssam}; 1560178676Ssam 1561198429Srpaulostatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1562178676Ssam 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1563178676Ssam 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1564178676Ssam 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1565178676Ssam 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1566178676Ssam 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1567178676Ssam 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1568178676Ssam 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1569178676Ssam 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1570178676Ssam 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1571178676Ssam 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1572178676Ssam}; 1573178676Ssam 1574178676Ssam/* 1575178676Ssam * DSP pre-DAC gain values from highest to lowest power (values obtained 1576178676Ssam * from the reference driver.) 1577178676Ssam */ 1578198429Srpaulostatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1579178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1580178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1581178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1582178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1583178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1584178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1585178676Ssam 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1586178676Ssam 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1587178676Ssam 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1588178676Ssam 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1589178676Ssam}; 1590178676Ssam 1591198429Srpaulostatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1592178676Ssam 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1593178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1594178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1595178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1596178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1597178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1598178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1599178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1600178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1601178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1602178676Ssam}; 1603178676Ssam 1604198429Srpaulo/* 1605198429Srpaulo * Power saving settings (values obtained from the reference driver.) 1606198429Srpaulo */ 1607198429Srpaulo#define IWN_NDTIMRANGES 3 1608198429Srpaulo#define IWN_NPOWERLEVELS 6 1609198429Srpaulostatic const struct iwn_pmgt { 1610198429Srpaulo uint32_t rxtimeout; 1611198429Srpaulo uint32_t txtimeout; 1612198429Srpaulo uint32_t intval[5]; 1613198429Srpaulo int skip_dtim; 1614198429Srpaulo} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1615198429Srpaulo /* DTIM <= 2 */ 1616198429Srpaulo { 1617198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1618198429Srpaulo { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1619198429Srpaulo { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1620198429Srpaulo { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1621198429Srpaulo { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1622198429Srpaulo { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1623198429Srpaulo }, 1624198429Srpaulo /* 3 <= DTIM <= 10 */ 1625198429Srpaulo { 1626198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1627198429Srpaulo { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1628198429Srpaulo { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1629198429Srpaulo { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1630198429Srpaulo { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1631198429Srpaulo { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1632198429Srpaulo }, 1633198429Srpaulo /* DTIM >= 11 */ 1634198429Srpaulo { 1635198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1636198429Srpaulo { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1637198429Srpaulo { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1638198429Srpaulo { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1639198429Srpaulo { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1640198429Srpaulo { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1641198429Srpaulo } 1642198429Srpaulo}; 1643198429Srpaulo 1644198429Srpaulostruct iwn_sensitivity_limits { 1645198429Srpaulo uint32_t min_ofdm_x1; 1646198429Srpaulo uint32_t max_ofdm_x1; 1647198429Srpaulo uint32_t min_ofdm_mrc_x1; 1648198429Srpaulo uint32_t max_ofdm_mrc_x1; 1649198429Srpaulo uint32_t min_ofdm_x4; 1650198429Srpaulo uint32_t max_ofdm_x4; 1651198429Srpaulo uint32_t min_ofdm_mrc_x4; 1652198429Srpaulo uint32_t max_ofdm_mrc_x4; 1653198429Srpaulo uint32_t min_cck_x4; 1654198429Srpaulo uint32_t max_cck_x4; 1655198429Srpaulo uint32_t min_cck_mrc_x4; 1656198429Srpaulo uint32_t max_cck_mrc_x4; 1657198429Srpaulo uint32_t min_energy_cck; 1658198429Srpaulo uint32_t energy_cck; 1659198429Srpaulo uint32_t energy_ofdm; 1660198429Srpaulo}; 1661198429Srpaulo 1662198429Srpaulo/* 1663198429Srpaulo * RX sensitivity limits (values obtained from the reference driver.) 1664198429Srpaulo */ 1665198429Srpaulostatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1666198429Srpaulo 105, 140, 1667201209Srpaulo 220, 270, 1668198429Srpaulo 85, 120, 1669198429Srpaulo 170, 210, 1670198429Srpaulo 125, 200, 1671198429Srpaulo 200, 400, 1672198429Srpaulo 97, 1673198429Srpaulo 100, 1674198429Srpaulo 100 1675198429Srpaulo}; 1676198429Srpaulo 1677198429Srpaulostatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1678206444Sbschmidt 120, 120, /* min = max for performance bug in DSP. */ 1679206444Sbschmidt 240, 240, /* min = max for performance bug in DSP. */ 1680198429Srpaulo 90, 120, 1681198429Srpaulo 170, 210, 1682198429Srpaulo 125, 200, 1683198429Srpaulo 170, 400, 1684198429Srpaulo 95, 1685198429Srpaulo 95, 1686198429Srpaulo 95 1687198429Srpaulo}; 1688198429Srpaulo 1689201209Srpaulostatic const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1690201209Srpaulo 105, 105, /* min = max for performance bug in DSP. */ 1691201209Srpaulo 220, 220, /* min = max for performance bug in DSP. */ 1692201209Srpaulo 90, 120, 1693201209Srpaulo 170, 210, 1694201209Srpaulo 125, 200, 1695201209Srpaulo 170, 400, 1696201209Srpaulo 95, 1697201209Srpaulo 95, 1698201209Srpaulo 95 1699201209Srpaulo}; 1700201209Srpaulo 1701206444Sbschmidtstatic const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1702206444Sbschmidt 120, 155, 1703206444Sbschmidt 240, 290, 1704220726Sbschmidt 90, 120, 1705206444Sbschmidt 170, 210, 1706206444Sbschmidt 125, 200, 1707206444Sbschmidt 170, 400, 1708220726Sbschmidt 95, 1709220726Sbschmidt 95, 1710220726Sbschmidt 95 1711206444Sbschmidt}; 1712206444Sbschmidt 1713201209Srpaulostatic const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1714206444Sbschmidt 105, 110, 1715201209Srpaulo 192, 232, 1716201209Srpaulo 80, 145, 1717201209Srpaulo 128, 232, 1718201209Srpaulo 125, 175, 1719201209Srpaulo 160, 310, 1720201209Srpaulo 97, 1721201209Srpaulo 97, 1722201209Srpaulo 100 1723201209Srpaulo}; 1724201209Srpaulo 1725198429Srpaulo/* Map TID to TX scheduler's FIFO. */ 1726198429Srpaulostatic const uint8_t iwn_tid2fifo[] = { 1727198429Srpaulo 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1728198429Srpaulo}; 1729198429Srpaulo 1730201209Srpaulo/* WiFi/WiMAX coexist event priority table for 6050. */ 1731201209Srpaulostatic const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1732201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1733201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1734201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1735201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1736201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1737201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 1738201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1739201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1740201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 1741201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1742201209Srpaulo { 0x06, 0x03, 0x00, 0x07 }, 1743201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1744201209Srpaulo { 0x06, 0x06, 0x00, 0x03 }, 1745201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 1746201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 1747201209Srpaulo { 0x04, 0x03, 0x00, 0x00 } 1748201209Srpaulo}; 1749201209Srpaulo 1750198429Srpaulo/* Firmware errors. */ 1751198429Srpaulostatic const char * const iwn_fw_errmsg[] = { 1752198429Srpaulo "OK", 1753198429Srpaulo "FAIL", 1754198429Srpaulo "BAD_PARAM", 1755198429Srpaulo "BAD_CHECKSUM", 1756198429Srpaulo "NMI_INTERRUPT_WDG", 1757198429Srpaulo "SYSASSERT", 1758198429Srpaulo "FATAL_ERROR", 1759198429Srpaulo "BAD_COMMAND", 1760198429Srpaulo "HW_ERROR_TUNE_LOCK", 1761198429Srpaulo "HW_ERROR_TEMPERATURE", 1762198429Srpaulo "ILLEGAL_CHAN_FREQ", 1763198429Srpaulo "VCC_NOT_STABLE", 1764198429Srpaulo "FH_ERROR", 1765198429Srpaulo "NMI_INTERRUPT_HOST", 1766198429Srpaulo "NMI_INTERRUPT_ACTION_PT", 1767198429Srpaulo "NMI_INTERRUPT_UNKNOWN", 1768198429Srpaulo "UCODE_VERSION_MISMATCH", 1769198429Srpaulo "HW_ERROR_ABS_LOCK", 1770198429Srpaulo "HW_ERROR_CAL_LOCK_FAIL", 1771198429Srpaulo "NMI_INTERRUPT_INST_ACTION_PT", 1772198429Srpaulo "NMI_INTERRUPT_DATA_ACTION_PT", 1773198429Srpaulo "NMI_TRM_HW_ER", 1774198429Srpaulo "NMI_INTERRUPT_TRM", 1775264780Sbrueffer "NMI_INTERRUPT_BREAKPOINT", 1776198429Srpaulo "DEBUG_0", 1777198429Srpaulo "DEBUG_1", 1778198429Srpaulo "DEBUG_2", 1779198429Srpaulo "DEBUG_3", 1780206444Sbschmidt "ADVANCED_SYSASSERT" 1781198429Srpaulo}; 1782198429Srpaulo 1783198429Srpaulo/* Find least significant bit that is set. */ 1784198429Srpaulo#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1785198429Srpaulo 1786178676Ssam#define IWN_READ(sc, reg) \ 1787178676Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1788178676Ssam 1789178676Ssam#define IWN_WRITE(sc, reg, val) \ 1790178676Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1791178676Ssam 1792201209Srpaulo#define IWN_WRITE_1(sc, reg, val) \ 1793201209Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1794201209Srpaulo 1795198429Srpaulo#define IWN_SETBITS(sc, reg, mask) \ 1796198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1797198429Srpaulo 1798198429Srpaulo#define IWN_CLRBITS(sc, reg, mask) \ 1799198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1800201209Srpaulo 1801201209Srpaulo#define IWN_BARRIER_WRITE(sc) \ 1802201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1803201209Srpaulo BUS_SPACE_BARRIER_WRITE) 1804201209Srpaulo 1805201209Srpaulo#define IWN_BARRIER_READ_WRITE(sc) \ 1806201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1807201209Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1808