1176667Sjfv/****************************************************************************** 2176667Sjfv 3220375Sjfv Copyright (c) 2001-2011, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD$*/ 34176667Sjfv 35176667Sjfv#ifndef _IGB_H_DEFINED_ 36176667Sjfv#define _IGB_H_DEFINED_ 37176667Sjfv 38176667Sjfv/* Tunables */ 39176667Sjfv 40176667Sjfv/* 41176667Sjfv * IGB_TXD: Maximum number of Transmit Descriptors 42176667Sjfv * 43176667Sjfv * This value is the number of transmit descriptors allocated by the driver. 44176667Sjfv * Increasing this value allows the driver to queue more transmits. Each 45176667Sjfv * descriptor is 16 bytes. 46176667Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 47176667Sjfv * desscriptors should meet the following condition. 48176667Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49176667Sjfv */ 50205869Sjfv#define IGB_MIN_TXD 256 51205869Sjfv#define IGB_DEFAULT_TXD 1024 52176667Sjfv#define IGB_MAX_TXD 4096 53176667Sjfv 54176667Sjfv/* 55235527Sjfv * IGB_RXD: Maximum number of Receive Descriptors 56176667Sjfv * 57176667Sjfv * This value is the number of receive descriptors allocated by the driver. 58176667Sjfv * Increasing this value allows the driver to buffer more incoming packets. 59176667Sjfv * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60176667Sjfv * descriptor. The maximum MTU size is 16110. 61176667Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 62176667Sjfv * desscriptors should meet the following condition. 63176667Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64176667Sjfv */ 65205869Sjfv#define IGB_MIN_RXD 256 66205869Sjfv#define IGB_DEFAULT_RXD 1024 67176667Sjfv#define IGB_MAX_RXD 4096 68176667Sjfv 69176667Sjfv/* 70176667Sjfv * IGB_TIDV - Transmit Interrupt Delay Value 71176667Sjfv * Valid Range: 0-65535 (0=off) 72176667Sjfv * Default Value: 64 73176667Sjfv * This value delays the generation of transmit interrupts in units of 74176667Sjfv * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75176667Sjfv * efficiency if properly tuned for specific network traffic. If the 76176667Sjfv * system is reporting dropped transmits, this value may be set too high 77176667Sjfv * causing the driver to run out of available transmit descriptors. 78176667Sjfv */ 79176667Sjfv#define IGB_TIDV 64 80176667Sjfv 81176667Sjfv/* 82176667Sjfv * IGB_TADV - Transmit Absolute Interrupt Delay Value 83176667Sjfv * Valid Range: 0-65535 (0=off) 84176667Sjfv * Default Value: 64 85176667Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 86176667Sjfv * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87176667Sjfv * this value ensures that an interrupt is generated after the initial 88176667Sjfv * packet is sent on the wire within the set amount of time. Proper tuning, 89176667Sjfv * along with IGB_TIDV, may improve traffic throughput in specific 90176667Sjfv * network conditions. 91176667Sjfv */ 92176667Sjfv#define IGB_TADV 64 93176667Sjfv 94176667Sjfv/* 95176667Sjfv * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96176667Sjfv * Valid Range: 0-65535 (0=off) 97176667Sjfv * Default Value: 0 98176667Sjfv * This value delays the generation of receive interrupts in units of 1.024 99176667Sjfv * microseconds. Receive interrupt reduction can improve CPU efficiency if 100176667Sjfv * properly tuned for specific network traffic. Increasing this value adds 101176667Sjfv * extra latency to frame reception and can end up decreasing the throughput 102176667Sjfv * of TCP traffic. If the system is reporting dropped receives, this value 103176667Sjfv * may be set too high, causing the driver to run out of available receive 104176667Sjfv * descriptors. 105176667Sjfv * 106176667Sjfv * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107176667Sjfv * may hang (stop transmitting) under certain network conditions. 108176667Sjfv * If this occurs a WATCHDOG message is logged in the system 109176667Sjfv * event log. In addition, the controller is automatically reset, 110176667Sjfv * restoring the network connection. To eliminate the potential 111176667Sjfv * for the hang ensure that IGB_RDTR is set to 0. 112176667Sjfv */ 113176667Sjfv#define IGB_RDTR 0 114176667Sjfv 115176667Sjfv/* 116176667Sjfv * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117176667Sjfv * Valid Range: 0-65535 (0=off) 118176667Sjfv * Default Value: 64 119176667Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 120176667Sjfv * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121176667Sjfv * this value ensures that an interrupt is generated after the initial 122176667Sjfv * packet is received within the set amount of time. Proper tuning, 123176667Sjfv * along with IGB_RDTR, may improve traffic throughput in specific network 124176667Sjfv * conditions. 125176667Sjfv */ 126176667Sjfv#define IGB_RADV 64 127176667Sjfv 128176667Sjfv/* 129176667Sjfv * This parameter controls the duration of transmit watchdog timer. 130176667Sjfv */ 131200243Sjfv#define IGB_WATCHDOG (10 * hz) 132176667Sjfv 133176667Sjfv/* 134176667Sjfv * This parameter controls when the driver calls the routine to reclaim 135220375Sjfv * transmit descriptors. Cleaning earlier seems a win. 136176667Sjfv */ 137220375Sjfv#define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 138176667Sjfv 139176667Sjfv/* 140176667Sjfv * This parameter controls whether or not autonegotation is enabled. 141176667Sjfv * 0 - Disable autonegotiation 142176667Sjfv * 1 - Enable autonegotiation 143176667Sjfv */ 144176667Sjfv#define DO_AUTO_NEG 1 145176667Sjfv 146176667Sjfv/* 147176667Sjfv * This parameter control whether or not the driver will wait for 148176667Sjfv * autonegotiation to complete. 149176667Sjfv * 1 - Wait for autonegotiation to complete 150176667Sjfv * 0 - Don't wait for autonegotiation to complete 151176667Sjfv */ 152176667Sjfv#define WAIT_FOR_AUTO_NEG_DEFAULT 0 153176667Sjfv 154176667Sjfv/* Tunables -- End */ 155176667Sjfv 156176667Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 157176667Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 158176667Sjfv ADVERTISE_1000_FULL) 159176667Sjfv 160176667Sjfv#define AUTO_ALL_MODES 0 161176667Sjfv 162176667Sjfv/* PHY master/slave setting */ 163176667Sjfv#define IGB_MASTER_SLAVE e1000_ms_hw_default 164176667Sjfv 165176667Sjfv/* 166176667Sjfv * Micellaneous constants 167176667Sjfv */ 168176667Sjfv#define IGB_VENDOR_ID 0x8086 169176667Sjfv 170176667Sjfv#define IGB_JUMBO_PBA 0x00000028 171176667Sjfv#define IGB_DEFAULT_PBA 0x00000030 172176667Sjfv#define IGB_SMARTSPEED_DOWNSHIFT 3 173176667Sjfv#define IGB_SMARTSPEED_MAX 15 174190872Sjfv#define IGB_MAX_LOOP 10 175203049Sjfv 176203049Sjfv#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 177176667Sjfv#define IGB_RX_HTHRESH 8 178176667Sjfv#define IGB_RX_WTHRESH 1 179176667Sjfv 180203049Sjfv#define IGB_TX_PTHRESH 8 181203049Sjfv#define IGB_TX_HTHRESH 1 182218530Sjfv#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 183203049Sjfv adapter->msix_mem) ? 1 : 16) 184203049Sjfv 185176667Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 186176667Sjfv#define PCI_ANY_ID (~0U) 187176667Sjfv#define ETHER_ALIGN 2 188176667Sjfv#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 189176667Sjfv#define IGB_FC_PAUSE_TIME 0x0680 190176667Sjfv#define IGB_EEPROM_APME 0x400; 191235527Sjfv/* Queue minimum free for use */ 192235527Sjfv#define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 193235527Sjfv/* Queue bit defines */ 194235527Sjfv#define IGB_QUEUE_IDLE 1 195235527Sjfv#define IGB_QUEUE_WORKING 2 196235527Sjfv#define IGB_QUEUE_HUNG 4 197235527Sjfv#define IGB_QUEUE_DEPLETED 8 198176667Sjfv 199176667Sjfv/* 200176667Sjfv * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201176667Sjfv * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202176667Sjfv * also optimize cache line size effect. H/W supports up to cache line size 128. 203176667Sjfv */ 204176667Sjfv#define IGB_DBA_ALIGN 128 205176667Sjfv 206176667Sjfv#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207176667Sjfv 208176667Sjfv/* PCI Config defines */ 209176667Sjfv#define IGB_MSIX_BAR 3 210176667Sjfv 211176667Sjfv/* Defines for printing debug information */ 212176667Sjfv#define DEBUG_INIT 0 213176667Sjfv#define DEBUG_IOCTL 0 214176667Sjfv#define DEBUG_HW 0 215176667Sjfv 216176667Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 217176667Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 218176667Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 219176667Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 220176667Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 221176667Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 222176667Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 223176667Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 224176667Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 225176667Sjfv 226176667Sjfv#define IGB_MAX_SCATTER 64 227194865Sjfv#define IGB_VFTA_SIZE 128 228194865Sjfv#define IGB_BR_SIZE 4096 /* ring buf size */ 229176667Sjfv#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 230176667Sjfv#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 231190872Sjfv#define IGB_HDR_BUF 128 232200243Sjfv#define IGB_PKTTYPE_MASK 0x0000FFF0 233176667Sjfv#define ETH_ZLEN 60 234176667Sjfv#define ETH_ADDR_LEN 6 235176667Sjfv 236190872Sjfv/* Offload bits in mbuf flag */ 237190872Sjfv#if __FreeBSD_version >= 800000 238190872Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 239190872Sjfv#else 240190872Sjfv#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 241190872Sjfv#endif 242190872Sjfv 243203049Sjfv/* Define the starting Interrupt rate per Queue */ 244203049Sjfv#define IGB_INTS_PER_SEC 8000 245215781Sjfv#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 246203049Sjfv 247182416Sjfv#define IGB_LINK_ITR 2000 248182416Sjfv 249181027Sjfv/* Precision Time Sync (IEEE 1588) defines */ 250181027Sjfv#define ETHERTYPE_IEEE1588 0x88F7 251181027Sjfv#define PICOSECS_PER_TICK 20833 252181027Sjfv#define TSYNC_PORT 319 /* UDP port for the protocol */ 253176667Sjfv 254176667Sjfv/* 255176667Sjfv * Bus dma allocation structure used by 256176667Sjfv * e1000_dma_malloc and e1000_dma_free. 257176667Sjfv */ 258176667Sjfvstruct igb_dma_alloc { 259176667Sjfv bus_addr_t dma_paddr; 260176667Sjfv caddr_t dma_vaddr; 261176667Sjfv bus_dma_tag_t dma_tag; 262176667Sjfv bus_dmamap_t dma_map; 263176667Sjfv bus_dma_segment_t dma_seg; 264176667Sjfv int dma_nseg; 265176667Sjfv}; 266176667Sjfv 267176667Sjfv 268176667Sjfv/* 269203049Sjfv** Driver queue struct: this is the interrupt container 270203049Sjfv** for the associated tx and rx ring. 271203049Sjfv*/ 272203049Sjfvstruct igb_queue { 273203049Sjfv struct adapter *adapter; 274203049Sjfv u32 msix; /* This queue's MSIX vector */ 275203049Sjfv u32 eims; /* This queue's EIMS bit */ 276203049Sjfv u32 eitr_setting; 277203049Sjfv struct resource *res; 278203049Sjfv void *tag; 279203049Sjfv struct tx_ring *txr; 280203049Sjfv struct rx_ring *rxr; 281203049Sjfv struct task que_task; 282203049Sjfv struct taskqueue *tq; 283203049Sjfv u64 irqs; 284203049Sjfv}; 285203049Sjfv 286203049Sjfv/* 287203049Sjfv * Transmit ring: one per queue 288176667Sjfv */ 289176667Sjfvstruct tx_ring { 290176667Sjfv struct adapter *adapter; 291176667Sjfv u32 me; 292176667Sjfv struct mtx tx_mtx; 293182416Sjfv char mtx_name[16]; 294203049Sjfv struct igb_dma_alloc txdma; 295176667Sjfv struct e1000_tx_desc *tx_base; 296176667Sjfv u32 next_avail_desc; 297176667Sjfv u32 next_to_clean; 298176667Sjfv volatile u16 tx_avail; 299190872Sjfv struct igb_tx_buffer *tx_buffers; 300252899Sjfv#ifndef IGB_LEGACY_TX 301194865Sjfv struct buf_ring *br; 302247478Sjhb struct task txq_task; 303194865Sjfv#endif 304203049Sjfv bus_dma_tag_t txtag; 305194865Sjfv 306203049Sjfv u32 bytes; 307203049Sjfv u32 packets; 308203049Sjfv 309215781Sjfv int queue_status; 310200243Sjfv int watchdog_time; 311209616Sjfv int tdt; 312209616Sjfv int tdh; 313176667Sjfv u64 no_desc_avail; 314176667Sjfv u64 tx_packets; 315176667Sjfv}; 316176667Sjfv 317176667Sjfv/* 318203049Sjfv * Receive ring: one per queue 319176667Sjfv */ 320176667Sjfvstruct rx_ring { 321176667Sjfv struct adapter *adapter; 322176667Sjfv u32 me; 323203049Sjfv struct igb_dma_alloc rxdma; 324176667Sjfv union e1000_adv_rx_desc *rx_base; 325181027Sjfv struct lro_ctrl lro; 326194865Sjfv bool lro_enabled; 327194865Sjfv bool hdr_split; 328203049Sjfv bool discard; 329176667Sjfv struct mtx rx_mtx; 330182416Sjfv char mtx_name[16]; 331205869Sjfv u32 next_to_refresh; 332176667Sjfv u32 next_to_check; 333200243Sjfv struct igb_rx_buf *rx_buffers; 334205869Sjfv bus_dma_tag_t htag; /* dma tag for rx head */ 335205869Sjfv bus_dma_tag_t ptag; /* dma tag for rx packet */ 336176667Sjfv /* 337176667Sjfv * First/last mbuf pointers, for 338176667Sjfv * collecting multisegment RX packets. 339176667Sjfv */ 340176667Sjfv struct mbuf *fmp; 341176667Sjfv struct mbuf *lmp; 342182416Sjfv 343182416Sjfv u32 bytes; 344203049Sjfv u32 packets; 345209616Sjfv int rdt; 346209616Sjfv int rdh; 347182416Sjfv 348176667Sjfv /* Soft stats */ 349190872Sjfv u64 rx_split_packets; 350203049Sjfv u64 rx_discarded; 351176667Sjfv u64 rx_packets; 352176667Sjfv u64 rx_bytes; 353176667Sjfv}; 354176667Sjfv 355176667Sjfvstruct adapter { 356176667Sjfv struct ifnet *ifp; 357176667Sjfv struct e1000_hw hw; 358176667Sjfv 359176667Sjfv struct e1000_osdep osdep; 360176667Sjfv struct device *dev; 361206001Smarius struct cdev *led_dev; 362176667Sjfv 363176667Sjfv struct resource *pci_mem; 364176667Sjfv struct resource *msix_mem; 365194865Sjfv struct resource *res; 366194865Sjfv void *tag; 367218530Sjfv u32 que_mask; 368176667Sjfv 369176667Sjfv int linkvec; 370178523Sjfv int link_mask; 371203090Sjfv struct task link_task; 372176667Sjfv int link_irq; 373176667Sjfv 374176667Sjfv struct ifmedia media; 375176667Sjfv struct callout timer; 376176667Sjfv int msix; /* total vectors allocated */ 377176667Sjfv int if_flags; 378176667Sjfv int max_frame_size; 379176667Sjfv int min_frame_size; 380213234Sjfv int pause_frames; 381176667Sjfv struct mtx core_mtx; 382176667Sjfv int igb_insert_vlan_header; 383194865Sjfv u16 num_queues; 384218530Sjfv u16 vf_ifp; /* a VF interface */ 385194865Sjfv 386181027Sjfv eventhandler_tag vlan_attach; 387181027Sjfv eventhandler_tag vlan_detach; 388194865Sjfv u32 num_vlans; 389190872Sjfv 390176667Sjfv /* Management and WOL features */ 391176667Sjfv int wol; 392176667Sjfv int has_manage; 393176667Sjfv 394215781Sjfv /* 395215781Sjfv ** Shadow VFTA table, this is needed because 396215781Sjfv ** the real vlan filter table gets cleared during 397215781Sjfv ** a soft reset and the driver needs to be able 398215781Sjfv ** to repopulate it. 399215781Sjfv */ 400215781Sjfv u32 shadow_vfta[IGB_VFTA_SIZE]; 401215781Sjfv 402215781Sjfv /* Info about the interface */ 403223350Sjfv u16 link_active; 404223350Sjfv u16 fc; 405176667Sjfv u16 link_speed; 406176667Sjfv u16 link_duplex; 407176667Sjfv u32 smartspeed; 408223350Sjfv u32 dmac; 409223676Sjhb int enable_aim; 410176667Sjfv 411203049Sjfv /* Interface queues */ 412203049Sjfv struct igb_queue *queues; 413203049Sjfv 414176667Sjfv /* 415176667Sjfv * Transmit rings 416176667Sjfv */ 417176667Sjfv struct tx_ring *tx_rings; 418176667Sjfv u16 num_tx_desc; 419176667Sjfv 420213234Sjfv /* Multicast array pointer */ 421213234Sjfv u8 *mta; 422213234Sjfv 423176667Sjfv /* 424176667Sjfv * Receive rings 425176667Sjfv */ 426176667Sjfv struct rx_ring *rx_rings; 427190872Sjfv bool rx_hdr_split; 428176667Sjfv u16 num_rx_desc; 429176667Sjfv int rx_process_limit; 430190872Sjfv u32 rx_mbuf_sz; 431190872Sjfv u32 rx_mask; 432176667Sjfv 433176667Sjfv /* Misc stats maintained by the driver */ 434176667Sjfv unsigned long dropped_pkts; 435190872Sjfv unsigned long mbuf_defrag_failed; 436190872Sjfv unsigned long mbuf_header_failed; 437190872Sjfv unsigned long mbuf_packet_failed; 438176667Sjfv unsigned long no_tx_map_avail; 439176667Sjfv unsigned long no_tx_dma_setup; 440176667Sjfv unsigned long watchdog_events; 441176667Sjfv unsigned long rx_overruns; 442209241Sgnn unsigned long device_control; 443209241Sgnn unsigned long rx_control; 444209241Sgnn unsigned long int_mask; 445209241Sgnn unsigned long eint_mask; 446209241Sgnn unsigned long packet_buf_alloc_rx; 447209241Sgnn unsigned long packet_buf_alloc_tx; 448176667Sjfv 449176667Sjfv boolean_t in_detach; 450176667Sjfv 451194865Sjfv#ifdef IGB_IEEE1588 452194865Sjfv /* IEEE 1588 precision time support */ 453194865Sjfv struct cyclecounter cycles; 454194865Sjfv struct nettimer clock; 455194865Sjfv struct nettime_compare compare; 456194865Sjfv struct hwtstamp_ctrl hwtstamp; 457181027Sjfv#endif 458176667Sjfv 459209611Sjfv void *stats; 460176667Sjfv}; 461176667Sjfv 462176667Sjfv/* ****************************************************************************** 463176667Sjfv * vendor_info_array 464176667Sjfv * 465176667Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 466176667Sjfv * should load. 467176667Sjfv * 468176667Sjfv * ******************************************************************************/ 469176667Sjfvtypedef struct _igb_vendor_info_t { 470176667Sjfv unsigned int vendor_id; 471176667Sjfv unsigned int device_id; 472176667Sjfv unsigned int subvendor_id; 473176667Sjfv unsigned int subdevice_id; 474176667Sjfv unsigned int index; 475176667Sjfv} igb_vendor_info_t; 476176667Sjfv 477176667Sjfv 478190872Sjfvstruct igb_tx_buffer { 479176667Sjfv int next_eop; /* Index of the desc to watch */ 480176667Sjfv struct mbuf *m_head; 481176667Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 482176667Sjfv}; 483176667Sjfv 484200243Sjfvstruct igb_rx_buf { 485190872Sjfv struct mbuf *m_head; 486190872Sjfv struct mbuf *m_pack; 487205869Sjfv bus_dmamap_t hmap; /* bus_dma map for header */ 488205869Sjfv bus_dmamap_t pmap; /* bus_dma map for packet */ 489190872Sjfv}; 490190872Sjfv 491220375Sjfv/* 492220375Sjfv** Find the number of unrefreshed RX descriptors 493220375Sjfv*/ 494220375Sjfvstatic inline u16 495220375Sjfvigb_rx_unrefreshed(struct rx_ring *rxr) 496220375Sjfv{ 497220375Sjfv struct adapter *adapter = rxr->adapter; 498220375Sjfv 499220375Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 500220375Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 501220375Sjfv else 502220375Sjfv return ((adapter->num_rx_desc + rxr->next_to_check) - 503220375Sjfv rxr->next_to_refresh - 1); 504220375Sjfv} 505220375Sjfv 506176667Sjfv#define IGB_CORE_LOCK_INIT(_sc, _name) \ 507176667Sjfv mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 508176667Sjfv#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 509203049Sjfv#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 510203049Sjfv#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 511203049Sjfv#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 512203049Sjfv 513200243Sjfv#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 514200243Sjfv#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 515203049Sjfv#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 516200243Sjfv#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 517203049Sjfv#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 518203049Sjfv 519203049Sjfv#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 520200243Sjfv#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 521176667Sjfv#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 522209611Sjfv#define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 523176667Sjfv 524209611Sjfv#define UPDATE_VF_REG(reg, last, cur) \ 525209611Sjfv{ \ 526209611Sjfv u32 new = E1000_READ_REG(hw, reg); \ 527209611Sjfv if (new < last) \ 528209611Sjfv cur += 0x100000000LL; \ 529209611Sjfv last = new; \ 530209611Sjfv cur &= 0xFFFFFFFF00000000LL; \ 531209611Sjfv cur |= new; \ 532209611Sjfv} 533209611Sjfv 534221187Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 535209616Sjfvstatic __inline int 536209616Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 537209616Sjfv{ 538209616Sjfv#ifdef ALTQ 539209616Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 540209616Sjfv return (1); 541209616Sjfv#endif 542209616Sjfv return (!buf_ring_empty(br)); 543209616Sjfv} 544209616Sjfv#endif 545209616Sjfv 546176667Sjfv#endif /* _IGB_H_DEFINED_ */ 547176667Sjfv 548176667Sjfv 549