1177867Sjfv/****************************************************************************** 2169240Sjfv 3248292Sjfv Copyright (c) 2001-2013, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35169240Sjfv#ifndef _E1000_HW_H_ 36169240Sjfv#define _E1000_HW_H_ 37169240Sjfv 38169240Sjfv#include "e1000_osdep.h" 39169240Sjfv#include "e1000_regs.h" 40169240Sjfv#include "e1000_defines.h" 41169240Sjfv 42169240Sjfvstruct e1000_hw; 43169240Sjfv 44235527Sjfv#define E1000_DEV_ID_82542 0x1000 45235527Sjfv#define E1000_DEV_ID_82543GC_FIBER 0x1001 46235527Sjfv#define E1000_DEV_ID_82543GC_COPPER 0x1004 47235527Sjfv#define E1000_DEV_ID_82544EI_COPPER 0x1008 48235527Sjfv#define E1000_DEV_ID_82544EI_FIBER 0x1009 49235527Sjfv#define E1000_DEV_ID_82544GC_COPPER 0x100C 50235527Sjfv#define E1000_DEV_ID_82544GC_LOM 0x100D 51235527Sjfv#define E1000_DEV_ID_82540EM 0x100E 52235527Sjfv#define E1000_DEV_ID_82540EM_LOM 0x1015 53235527Sjfv#define E1000_DEV_ID_82540EP_LOM 0x1016 54235527Sjfv#define E1000_DEV_ID_82540EP 0x1017 55235527Sjfv#define E1000_DEV_ID_82540EP_LP 0x101E 56235527Sjfv#define E1000_DEV_ID_82545EM_COPPER 0x100F 57235527Sjfv#define E1000_DEV_ID_82545EM_FIBER 0x1011 58235527Sjfv#define E1000_DEV_ID_82545GM_COPPER 0x1026 59235527Sjfv#define E1000_DEV_ID_82545GM_FIBER 0x1027 60235527Sjfv#define E1000_DEV_ID_82545GM_SERDES 0x1028 61235527Sjfv#define E1000_DEV_ID_82546EB_COPPER 0x1010 62235527Sjfv#define E1000_DEV_ID_82546EB_FIBER 0x1012 63235527Sjfv#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64235527Sjfv#define E1000_DEV_ID_82546GB_COPPER 0x1079 65235527Sjfv#define E1000_DEV_ID_82546GB_FIBER 0x107A 66235527Sjfv#define E1000_DEV_ID_82546GB_SERDES 0x107B 67235527Sjfv#define E1000_DEV_ID_82546GB_PCIE 0x108A 68235527Sjfv#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69235527Sjfv#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70235527Sjfv#define E1000_DEV_ID_82541EI 0x1013 71235527Sjfv#define E1000_DEV_ID_82541EI_MOBILE 0x1018 72235527Sjfv#define E1000_DEV_ID_82541ER_LOM 0x1014 73235527Sjfv#define E1000_DEV_ID_82541ER 0x1078 74235527Sjfv#define E1000_DEV_ID_82541GI 0x1076 75235527Sjfv#define E1000_DEV_ID_82541GI_LF 0x107C 76235527Sjfv#define E1000_DEV_ID_82541GI_MOBILE 0x1077 77235527Sjfv#define E1000_DEV_ID_82547EI 0x1019 78235527Sjfv#define E1000_DEV_ID_82547EI_MOBILE 0x101A 79235527Sjfv#define E1000_DEV_ID_82547GI 0x1075 80235527Sjfv#define E1000_DEV_ID_82571EB_COPPER 0x105E 81235527Sjfv#define E1000_DEV_ID_82571EB_FIBER 0x105F 82235527Sjfv#define E1000_DEV_ID_82571EB_SERDES 0x1060 83235527Sjfv#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84235527Sjfv#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85235527Sjfv#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86235527Sjfv#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87235527Sjfv#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88235527Sjfv#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89235527Sjfv#define E1000_DEV_ID_82572EI_COPPER 0x107D 90235527Sjfv#define E1000_DEV_ID_82572EI_FIBER 0x107E 91235527Sjfv#define E1000_DEV_ID_82572EI_SERDES 0x107F 92235527Sjfv#define E1000_DEV_ID_82572EI 0x10B9 93235527Sjfv#define E1000_DEV_ID_82573E 0x108B 94235527Sjfv#define E1000_DEV_ID_82573E_IAMT 0x108C 95235527Sjfv#define E1000_DEV_ID_82573L 0x109A 96235527Sjfv#define E1000_DEV_ID_82574L 0x10D3 97235527Sjfv#define E1000_DEV_ID_82574LA 0x10F6 98235527Sjfv#define E1000_DEV_ID_82583V 0x150C 99235527Sjfv#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100235527Sjfv#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101235527Sjfv#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102235527Sjfv#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103235527Sjfv#define E1000_DEV_ID_ICH8_82567V_3 0x1501 104235527Sjfv#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105235527Sjfv#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106235527Sjfv#define E1000_DEV_ID_ICH8_IGP_C 0x104B 107235527Sjfv#define E1000_DEV_ID_ICH8_IFE 0x104C 108235527Sjfv#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109235527Sjfv#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110235527Sjfv#define E1000_DEV_ID_ICH8_IGP_M 0x104D 111235527Sjfv#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112235527Sjfv#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113235527Sjfv#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114235527Sjfv#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115235527Sjfv#define E1000_DEV_ID_ICH9_BM 0x10E5 116235527Sjfv#define E1000_DEV_ID_ICH9_IGP_C 0x294C 117235527Sjfv#define E1000_DEV_ID_ICH9_IFE 0x10C0 118235527Sjfv#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119235527Sjfv#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120235527Sjfv#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121235527Sjfv#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122235527Sjfv#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123235527Sjfv#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124235527Sjfv#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125235527Sjfv#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126235527Sjfv#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127235527Sjfv#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128235527Sjfv#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129235527Sjfv#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130235527Sjfv#define E1000_DEV_ID_PCH2_LV_LM 0x1502 131235527Sjfv#define E1000_DEV_ID_PCH2_LV_V 0x1503 132248292Sjfv#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133248292Sjfv#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134248292Sjfv#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135248292Sjfv#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136235527Sjfv#define E1000_DEV_ID_82576 0x10C9 137235527Sjfv#define E1000_DEV_ID_82576_FIBER 0x10E6 138235527Sjfv#define E1000_DEV_ID_82576_SERDES 0x10E7 139235527Sjfv#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 140235527Sjfv#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 141235527Sjfv#define E1000_DEV_ID_82576_NS 0x150A 142235527Sjfv#define E1000_DEV_ID_82576_NS_SERDES 0x1518 143235527Sjfv#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 144235527Sjfv#define E1000_DEV_ID_82576_VF 0x10CA 145248292Sjfv#define E1000_DEV_ID_82576_VF_HV 0x152D 146235527Sjfv#define E1000_DEV_ID_I350_VF 0x1520 147248292Sjfv#define E1000_DEV_ID_I350_VF_HV 0x152F 148235527Sjfv#define E1000_DEV_ID_82575EB_COPPER 0x10A7 149235527Sjfv#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 150235527Sjfv#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 151235527Sjfv#define E1000_DEV_ID_82580_COPPER 0x150E 152235527Sjfv#define E1000_DEV_ID_82580_FIBER 0x150F 153235527Sjfv#define E1000_DEV_ID_82580_SERDES 0x1510 154235527Sjfv#define E1000_DEV_ID_82580_SGMII 0x1511 155235527Sjfv#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 156235527Sjfv#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 157235527Sjfv#define E1000_DEV_ID_I350_COPPER 0x1521 158235527Sjfv#define E1000_DEV_ID_I350_FIBER 0x1522 159235527Sjfv#define E1000_DEV_ID_I350_SERDES 0x1523 160235527Sjfv#define E1000_DEV_ID_I350_SGMII 0x1524 161235527Sjfv#define E1000_DEV_ID_I350_DA4 0x1546 162238262Sjfv#define E1000_DEV_ID_I210_COPPER 0x1533 163238262Sjfv#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 164238262Sjfv#define E1000_DEV_ID_I210_COPPER_IT 0x1535 165238262Sjfv#define E1000_DEV_ID_I210_FIBER 0x1536 166238262Sjfv#define E1000_DEV_ID_I210_SERDES 0x1537 167238262Sjfv#define E1000_DEV_ID_I210_SGMII 0x1538 168238262Sjfv#define E1000_DEV_ID_I211_COPPER 0x1539 169235527Sjfv#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 170235527Sjfv#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 171235527Sjfv#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 172235527Sjfv#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 173248292Sjfv 174235527Sjfv#define E1000_REVISION_0 0 175235527Sjfv#define E1000_REVISION_1 1 176235527Sjfv#define E1000_REVISION_2 2 177235527Sjfv#define E1000_REVISION_3 3 178235527Sjfv#define E1000_REVISION_4 4 179169240Sjfv 180235527Sjfv#define E1000_FUNC_0 0 181235527Sjfv#define E1000_FUNC_1 1 182235527Sjfv#define E1000_FUNC_2 2 183235527Sjfv#define E1000_FUNC_3 3 184169240Sjfv 185235527Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 186235527Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 187235527Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 188235527Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 189190872Sjfv 190181027Sjfvenum e1000_mac_type { 191169240Sjfv e1000_undefined = 0, 192169240Sjfv e1000_82542, 193169240Sjfv e1000_82543, 194169240Sjfv e1000_82544, 195169240Sjfv e1000_82540, 196169240Sjfv e1000_82545, 197169240Sjfv e1000_82545_rev_3, 198169240Sjfv e1000_82546, 199169240Sjfv e1000_82546_rev_3, 200169240Sjfv e1000_82541, 201169240Sjfv e1000_82541_rev_2, 202169240Sjfv e1000_82547, 203169240Sjfv e1000_82547_rev_2, 204169240Sjfv e1000_82571, 205169240Sjfv e1000_82572, 206169240Sjfv e1000_82573, 207178523Sjfv e1000_82574, 208194865Sjfv e1000_82583, 209169240Sjfv e1000_80003es2lan, 210169240Sjfv e1000_ich8lan, 211169240Sjfv e1000_ich9lan, 212178523Sjfv e1000_ich10lan, 213194865Sjfv e1000_pchlan, 214213234Sjfv e1000_pch2lan, 215248292Sjfv e1000_pch_lpt, 216177867Sjfv e1000_82575, 217181027Sjfv e1000_82576, 218200243Sjfv e1000_82580, 219218530Sjfv e1000_i350, 220238262Sjfv e1000_i210, 221238262Sjfv e1000_i211, 222209616Sjfv e1000_vfadapt, 223218530Sjfv e1000_vfadapt_i350, 224177867Sjfv e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 225181027Sjfv}; 226169240Sjfv 227181027Sjfvenum e1000_media_type { 228169240Sjfv e1000_media_type_unknown = 0, 229169240Sjfv e1000_media_type_copper = 1, 230169240Sjfv e1000_media_type_fiber = 2, 231169240Sjfv e1000_media_type_internal_serdes = 3, 232169240Sjfv e1000_num_media_types 233181027Sjfv}; 234169240Sjfv 235181027Sjfvenum e1000_nvm_type { 236169240Sjfv e1000_nvm_unknown = 0, 237169240Sjfv e1000_nvm_none, 238169240Sjfv e1000_nvm_eeprom_spi, 239169240Sjfv e1000_nvm_eeprom_microwire, 240169240Sjfv e1000_nvm_flash_hw, 241169240Sjfv e1000_nvm_flash_sw 242181027Sjfv}; 243169240Sjfv 244181027Sjfvenum e1000_nvm_override { 245169240Sjfv e1000_nvm_override_none = 0, 246169240Sjfv e1000_nvm_override_spi_small, 247169240Sjfv e1000_nvm_override_spi_large, 248169240Sjfv e1000_nvm_override_microwire_small, 249169240Sjfv e1000_nvm_override_microwire_large 250181027Sjfv}; 251169240Sjfv 252181027Sjfvenum e1000_phy_type { 253169240Sjfv e1000_phy_unknown = 0, 254169240Sjfv e1000_phy_none, 255169240Sjfv e1000_phy_m88, 256169240Sjfv e1000_phy_igp, 257169240Sjfv e1000_phy_igp_2, 258169240Sjfv e1000_phy_gg82563, 259169240Sjfv e1000_phy_igp_3, 260169240Sjfv e1000_phy_ife, 261176667Sjfv e1000_phy_bm, 262194865Sjfv e1000_phy_82578, 263194865Sjfv e1000_phy_82577, 264213234Sjfv e1000_phy_82579, 265248292Sjfv e1000_phy_i217, 266200243Sjfv e1000_phy_82580, 267181027Sjfv e1000_phy_vf, 268238262Sjfv e1000_phy_i210, 269181027Sjfv}; 270169240Sjfv 271181027Sjfvenum e1000_bus_type { 272169240Sjfv e1000_bus_type_unknown = 0, 273169240Sjfv e1000_bus_type_pci, 274169240Sjfv e1000_bus_type_pcix, 275169240Sjfv e1000_bus_type_pci_express, 276169240Sjfv e1000_bus_type_reserved 277181027Sjfv}; 278169240Sjfv 279181027Sjfvenum e1000_bus_speed { 280169240Sjfv e1000_bus_speed_unknown = 0, 281169240Sjfv e1000_bus_speed_33, 282169240Sjfv e1000_bus_speed_66, 283169240Sjfv e1000_bus_speed_100, 284169240Sjfv e1000_bus_speed_120, 285169240Sjfv e1000_bus_speed_133, 286169240Sjfv e1000_bus_speed_2500, 287173788Sjfv e1000_bus_speed_5000, 288169240Sjfv e1000_bus_speed_reserved 289181027Sjfv}; 290169240Sjfv 291181027Sjfvenum e1000_bus_width { 292169240Sjfv e1000_bus_width_unknown = 0, 293169240Sjfv e1000_bus_width_pcie_x1, 294169240Sjfv e1000_bus_width_pcie_x2, 295169240Sjfv e1000_bus_width_pcie_x4 = 4, 296173788Sjfv e1000_bus_width_pcie_x8 = 8, 297169240Sjfv e1000_bus_width_32, 298169240Sjfv e1000_bus_width_64, 299169240Sjfv e1000_bus_width_reserved 300181027Sjfv}; 301169240Sjfv 302181027Sjfvenum e1000_1000t_rx_status { 303169240Sjfv e1000_1000t_rx_status_not_ok = 0, 304169240Sjfv e1000_1000t_rx_status_ok, 305169240Sjfv e1000_1000t_rx_status_undefined = 0xFF 306181027Sjfv}; 307169240Sjfv 308181027Sjfvenum e1000_rev_polarity { 309169240Sjfv e1000_rev_polarity_normal = 0, 310169240Sjfv e1000_rev_polarity_reversed, 311169240Sjfv e1000_rev_polarity_undefined = 0xFF 312181027Sjfv}; 313169240Sjfv 314185353Sjfvenum e1000_fc_mode { 315169240Sjfv e1000_fc_none = 0, 316169240Sjfv e1000_fc_rx_pause, 317169240Sjfv e1000_fc_tx_pause, 318169240Sjfv e1000_fc_full, 319169240Sjfv e1000_fc_default = 0xFF 320181027Sjfv}; 321169240Sjfv 322181027Sjfvenum e1000_ffe_config { 323169240Sjfv e1000_ffe_config_enabled = 0, 324169240Sjfv e1000_ffe_config_active, 325169240Sjfv e1000_ffe_config_blocked 326181027Sjfv}; 327169240Sjfv 328181027Sjfvenum e1000_dsp_config { 329169240Sjfv e1000_dsp_config_disabled = 0, 330169240Sjfv e1000_dsp_config_enabled, 331169240Sjfv e1000_dsp_config_activated, 332169240Sjfv e1000_dsp_config_undefined = 0xFF 333181027Sjfv}; 334169240Sjfv 335185353Sjfvenum e1000_ms_type { 336185353Sjfv e1000_ms_hw_default = 0, 337185353Sjfv e1000_ms_force_master, 338185353Sjfv e1000_ms_force_slave, 339185353Sjfv e1000_ms_auto 340185353Sjfv}; 341185353Sjfv 342185353Sjfvenum e1000_smart_speed { 343185353Sjfv e1000_smart_speed_default = 0, 344185353Sjfv e1000_smart_speed_on, 345185353Sjfv e1000_smart_speed_off 346185353Sjfv}; 347185353Sjfv 348190872Sjfvenum e1000_serdes_link_state { 349190872Sjfv e1000_serdes_link_down = 0, 350190872Sjfv e1000_serdes_link_autoneg_progress, 351190872Sjfv e1000_serdes_link_autoneg_complete, 352190872Sjfv e1000_serdes_link_forced_up 353190872Sjfv}; 354190872Sjfv 355213234Sjfv#define __le16 u16 356213234Sjfv#define __le32 u32 357213234Sjfv#define __le64 u64 358169240Sjfv/* Receive Descriptor */ 359169240Sjfvstruct e1000_rx_desc { 360185353Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 361185353Sjfv __le16 length; /* Length of data DMAed into data buffer */ 362235527Sjfv __le16 csum; /* Packet checksum */ 363235527Sjfv u8 status; /* Descriptor status */ 364235527Sjfv u8 errors; /* Descriptor Errors */ 365185353Sjfv __le16 special; 366169240Sjfv}; 367169240Sjfv 368169240Sjfv/* Receive Descriptor - Extended */ 369169240Sjfvunion e1000_rx_desc_extended { 370169240Sjfv struct { 371185353Sjfv __le64 buffer_addr; 372185353Sjfv __le64 reserved; 373169240Sjfv } read; 374169240Sjfv struct { 375169240Sjfv struct { 376235527Sjfv __le32 mrq; /* Multiple Rx Queues */ 377169240Sjfv union { 378235527Sjfv __le32 rss; /* RSS Hash */ 379169240Sjfv struct { 380185353Sjfv __le16 ip_id; /* IP id */ 381185353Sjfv __le16 csum; /* Packet Checksum */ 382169240Sjfv } csum_ip; 383169240Sjfv } hi_dword; 384169240Sjfv } lower; 385169240Sjfv struct { 386185353Sjfv __le32 status_error; /* ext status/error */ 387185353Sjfv __le16 length; 388235527Sjfv __le16 vlan; /* VLAN tag */ 389169240Sjfv } upper; 390169240Sjfv } wb; /* writeback */ 391169240Sjfv}; 392169240Sjfv 393169240Sjfv#define MAX_PS_BUFFERS 4 394169240Sjfv/* Receive Descriptor - Packet Split */ 395169240Sjfvunion e1000_rx_desc_packet_split { 396169240Sjfv struct { 397169240Sjfv /* one buffer for protocol header(s), three data buffers */ 398185353Sjfv __le64 buffer_addr[MAX_PS_BUFFERS]; 399169240Sjfv } read; 400169240Sjfv struct { 401169240Sjfv struct { 402235527Sjfv __le32 mrq; /* Multiple Rx Queues */ 403169240Sjfv union { 404235527Sjfv __le32 rss; /* RSS Hash */ 405169240Sjfv struct { 406185353Sjfv __le16 ip_id; /* IP id */ 407185353Sjfv __le16 csum; /* Packet Checksum */ 408169240Sjfv } csum_ip; 409169240Sjfv } hi_dword; 410169240Sjfv } lower; 411169240Sjfv struct { 412185353Sjfv __le32 status_error; /* ext status/error */ 413235527Sjfv __le16 length0; /* length of buffer 0 */ 414235527Sjfv __le16 vlan; /* VLAN tag */ 415169240Sjfv } middle; 416169240Sjfv struct { 417185353Sjfv __le16 header_status; 418185353Sjfv __le16 length[3]; /* length of buffers 1-3 */ 419169240Sjfv } upper; 420185353Sjfv __le64 reserved; 421169240Sjfv } wb; /* writeback */ 422169240Sjfv}; 423169240Sjfv 424169240Sjfv/* Transmit Descriptor */ 425169240Sjfvstruct e1000_tx_desc { 426185353Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 427169240Sjfv union { 428185353Sjfv __le32 data; 429169240Sjfv struct { 430235527Sjfv __le16 length; /* Data buffer length */ 431235527Sjfv u8 cso; /* Checksum offset */ 432235527Sjfv u8 cmd; /* Descriptor control */ 433169240Sjfv } flags; 434169240Sjfv } lower; 435169240Sjfv union { 436185353Sjfv __le32 data; 437169240Sjfv struct { 438235527Sjfv u8 status; /* Descriptor status */ 439235527Sjfv u8 css; /* Checksum start */ 440185353Sjfv __le16 special; 441169240Sjfv } fields; 442169240Sjfv } upper; 443169240Sjfv}; 444169240Sjfv 445169240Sjfv/* Offload Context Descriptor */ 446169240Sjfvstruct e1000_context_desc { 447169240Sjfv union { 448185353Sjfv __le32 ip_config; 449169240Sjfv struct { 450235527Sjfv u8 ipcss; /* IP checksum start */ 451235527Sjfv u8 ipcso; /* IP checksum offset */ 452235527Sjfv __le16 ipcse; /* IP checksum end */ 453169240Sjfv } ip_fields; 454169240Sjfv } lower_setup; 455169240Sjfv union { 456185353Sjfv __le32 tcp_config; 457169240Sjfv struct { 458235527Sjfv u8 tucss; /* TCP checksum start */ 459235527Sjfv u8 tucso; /* TCP checksum offset */ 460235527Sjfv __le16 tucse; /* TCP checksum end */ 461169240Sjfv } tcp_fields; 462169240Sjfv } upper_setup; 463185353Sjfv __le32 cmd_and_length; 464169240Sjfv union { 465185353Sjfv __le32 data; 466169240Sjfv struct { 467235527Sjfv u8 status; /* Descriptor status */ 468235527Sjfv u8 hdr_len; /* Header length */ 469235527Sjfv __le16 mss; /* Maximum segment size */ 470169240Sjfv } fields; 471169240Sjfv } tcp_seg_setup; 472169240Sjfv}; 473169240Sjfv 474169240Sjfv/* Offload data descriptor */ 475169240Sjfvstruct e1000_data_desc { 476235527Sjfv __le64 buffer_addr; /* Address of the descriptor's buffer address */ 477169240Sjfv union { 478185353Sjfv __le32 data; 479169240Sjfv struct { 480235527Sjfv __le16 length; /* Data buffer length */ 481169240Sjfv u8 typ_len_ext; 482169240Sjfv u8 cmd; 483169240Sjfv } flags; 484169240Sjfv } lower; 485169240Sjfv union { 486185353Sjfv __le32 data; 487169240Sjfv struct { 488235527Sjfv u8 status; /* Descriptor status */ 489235527Sjfv u8 popts; /* Packet Options */ 490185353Sjfv __le16 special; 491169240Sjfv } fields; 492169240Sjfv } upper; 493169240Sjfv}; 494169240Sjfv 495169240Sjfv/* Statistics counters collected by the MAC */ 496169240Sjfvstruct e1000_hw_stats { 497169240Sjfv u64 crcerrs; 498169240Sjfv u64 algnerrc; 499169240Sjfv u64 symerrs; 500169240Sjfv u64 rxerrc; 501169240Sjfv u64 mpc; 502169240Sjfv u64 scc; 503169240Sjfv u64 ecol; 504169240Sjfv u64 mcc; 505169240Sjfv u64 latecol; 506169240Sjfv u64 colc; 507169240Sjfv u64 dc; 508169240Sjfv u64 tncrs; 509169240Sjfv u64 sec; 510169240Sjfv u64 cexterr; 511169240Sjfv u64 rlec; 512169240Sjfv u64 xonrxc; 513169240Sjfv u64 xontxc; 514169240Sjfv u64 xoffrxc; 515169240Sjfv u64 xofftxc; 516169240Sjfv u64 fcruc; 517169240Sjfv u64 prc64; 518169240Sjfv u64 prc127; 519169240Sjfv u64 prc255; 520169240Sjfv u64 prc511; 521169240Sjfv u64 prc1023; 522169240Sjfv u64 prc1522; 523169240Sjfv u64 gprc; 524169240Sjfv u64 bprc; 525169240Sjfv u64 mprc; 526169240Sjfv u64 gptc; 527173788Sjfv u64 gorc; 528173788Sjfv u64 gotc; 529169240Sjfv u64 rnbc; 530169240Sjfv u64 ruc; 531169240Sjfv u64 rfc; 532169240Sjfv u64 roc; 533169240Sjfv u64 rjc; 534169240Sjfv u64 mgprc; 535169240Sjfv u64 mgpdc; 536169240Sjfv u64 mgptc; 537173788Sjfv u64 tor; 538173788Sjfv u64 tot; 539169240Sjfv u64 tpr; 540169240Sjfv u64 tpt; 541169240Sjfv u64 ptc64; 542169240Sjfv u64 ptc127; 543169240Sjfv u64 ptc255; 544169240Sjfv u64 ptc511; 545169240Sjfv u64 ptc1023; 546169240Sjfv u64 ptc1522; 547169240Sjfv u64 mptc; 548169240Sjfv u64 bptc; 549169240Sjfv u64 tsctc; 550169240Sjfv u64 tsctfc; 551169240Sjfv u64 iac; 552169240Sjfv u64 icrxptc; 553169240Sjfv u64 icrxatc; 554169240Sjfv u64 ictxptc; 555169240Sjfv u64 ictxatc; 556169240Sjfv u64 ictxqec; 557169240Sjfv u64 ictxqmtc; 558169240Sjfv u64 icrxdmtc; 559169240Sjfv u64 icrxoc; 560169240Sjfv u64 cbtmpc; 561169240Sjfv u64 htdpmc; 562169240Sjfv u64 cbrdpc; 563169240Sjfv u64 cbrmpc; 564169240Sjfv u64 rpthc; 565169240Sjfv u64 hgptc; 566169240Sjfv u64 htcbdpc; 567173788Sjfv u64 hgorc; 568173788Sjfv u64 hgotc; 569169240Sjfv u64 lenerrs; 570169240Sjfv u64 scvpc; 571169240Sjfv u64 hrmpc; 572185353Sjfv u64 doosync; 573235527Sjfv u64 o2bgptc; 574235527Sjfv u64 o2bspc; 575235527Sjfv u64 b2ospc; 576235527Sjfv u64 b2ogprc; 577169240Sjfv}; 578169240Sjfv 579209616Sjfvstruct e1000_vf_stats { 580209616Sjfv u64 base_gprc; 581209616Sjfv u64 base_gptc; 582209616Sjfv u64 base_gorc; 583209616Sjfv u64 base_gotc; 584209616Sjfv u64 base_mprc; 585209616Sjfv u64 base_gotlbc; 586209616Sjfv u64 base_gptlbc; 587209616Sjfv u64 base_gorlbc; 588209616Sjfv u64 base_gprlbc; 589185353Sjfv 590209616Sjfv u32 last_gprc; 591209616Sjfv u32 last_gptc; 592209616Sjfv u32 last_gorc; 593209616Sjfv u32 last_gotc; 594209616Sjfv u32 last_mprc; 595209616Sjfv u32 last_gotlbc; 596209616Sjfv u32 last_gptlbc; 597209616Sjfv u32 last_gorlbc; 598209616Sjfv u32 last_gprlbc; 599209616Sjfv 600209616Sjfv u64 gprc; 601209616Sjfv u64 gptc; 602209616Sjfv u64 gorc; 603209616Sjfv u64 gotc; 604209616Sjfv u64 mprc; 605209616Sjfv u64 gotlbc; 606209616Sjfv u64 gptlbc; 607209616Sjfv u64 gorlbc; 608209616Sjfv u64 gprlbc; 609209616Sjfv}; 610209616Sjfv 611169240Sjfvstruct e1000_phy_stats { 612169240Sjfv u32 idle_errors; 613169240Sjfv u32 receive_errors; 614169240Sjfv}; 615169240Sjfv 616169240Sjfvstruct e1000_host_mng_dhcp_cookie { 617169240Sjfv u32 signature; 618169240Sjfv u8 status; 619169240Sjfv u8 reserved0; 620169240Sjfv u16 vlan_id; 621169240Sjfv u32 reserved1; 622169240Sjfv u16 reserved2; 623169240Sjfv u8 reserved3; 624169240Sjfv u8 checksum; 625169240Sjfv}; 626169240Sjfv 627169240Sjfv/* Host Interface "Rev 1" */ 628169240Sjfvstruct e1000_host_command_header { 629169240Sjfv u8 command_id; 630169240Sjfv u8 command_length; 631169240Sjfv u8 command_options; 632169240Sjfv u8 checksum; 633169240Sjfv}; 634169240Sjfv 635235527Sjfv#define E1000_HI_MAX_DATA_LENGTH 252 636169240Sjfvstruct e1000_host_command_info { 637169240Sjfv struct e1000_host_command_header command_header; 638169240Sjfv u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 639169240Sjfv}; 640169240Sjfv 641169240Sjfv/* Host Interface "Rev 2" */ 642169240Sjfvstruct e1000_host_mng_command_header { 643169240Sjfv u8 command_id; 644169240Sjfv u8 checksum; 645169240Sjfv u16 reserved1; 646169240Sjfv u16 reserved2; 647169240Sjfv u16 command_length; 648169240Sjfv}; 649169240Sjfv 650235527Sjfv#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 651169240Sjfvstruct e1000_host_mng_command_info { 652169240Sjfv struct e1000_host_mng_command_header command_header; 653169240Sjfv u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 654169240Sjfv}; 655169240Sjfv 656169240Sjfv#include "e1000_mac.h" 657169240Sjfv#include "e1000_phy.h" 658169240Sjfv#include "e1000_nvm.h" 659169240Sjfv#include "e1000_manage.h" 660209616Sjfv#include "e1000_mbx.h" 661169240Sjfv 662248292Sjfv/* Function pointers for the MAC. */ 663177867Sjfvstruct e1000_mac_operations { 664177867Sjfv s32 (*init_params)(struct e1000_hw *); 665190872Sjfv s32 (*id_led_init)(struct e1000_hw *); 666173788Sjfv s32 (*blink_led)(struct e1000_hw *); 667248292Sjfv bool (*check_mng_mode)(struct e1000_hw *); 668173788Sjfv s32 (*check_for_link)(struct e1000_hw *); 669173788Sjfv s32 (*cleanup_led)(struct e1000_hw *); 670173788Sjfv void (*clear_hw_cntrs)(struct e1000_hw *); 671173788Sjfv void (*clear_vfta)(struct e1000_hw *); 672173788Sjfv s32 (*get_bus_info)(struct e1000_hw *); 673185353Sjfv void (*set_lan_id)(struct e1000_hw *); 674173788Sjfv s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 675173788Sjfv s32 (*led_on)(struct e1000_hw *); 676173788Sjfv s32 (*led_off)(struct e1000_hw *); 677190872Sjfv void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 678173788Sjfv s32 (*reset_hw)(struct e1000_hw *); 679173788Sjfv s32 (*init_hw)(struct e1000_hw *); 680181027Sjfv void (*shutdown_serdes)(struct e1000_hw *); 681203049Sjfv void (*power_up_serdes)(struct e1000_hw *); 682173788Sjfv s32 (*setup_link)(struct e1000_hw *); 683173788Sjfv s32 (*setup_physical_interface)(struct e1000_hw *); 684173788Sjfv s32 (*setup_led)(struct e1000_hw *); 685173788Sjfv void (*write_vfta)(struct e1000_hw *, u32, u32); 686185353Sjfv void (*config_collision_dist)(struct e1000_hw *); 687185353Sjfv void (*rar_set)(struct e1000_hw *, u8*, u32); 688185353Sjfv s32 (*read_mac_addr)(struct e1000_hw *); 689185353Sjfv s32 (*validate_mdi_setting)(struct e1000_hw *); 690248292Sjfv s32 (*set_obff_timer)(struct e1000_hw *, u32); 691238262Sjfv s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 692238262Sjfv void (*release_swfw_sync)(struct e1000_hw *, u16); 693177867Sjfv}; 694169240Sjfv 695248292Sjfv/* When to use various PHY register access functions: 696235527Sjfv * 697235527Sjfv * Func Caller 698235527Sjfv * Function Does Does When to use 699235527Sjfv * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 700235527Sjfv * X_reg L,P,A n/a for simple PHY reg accesses 701235527Sjfv * X_reg_locked P,A L for multiple accesses of different regs 702235527Sjfv * on different pages 703235527Sjfv * X_reg_page A L,P for multiple accesses of different regs 704235527Sjfv * on the same page 705235527Sjfv * 706235527Sjfv * Where X=[read|write], L=locking, P=sets page, A=register access 707235527Sjfv * 708235527Sjfv */ 709177867Sjfvstruct e1000_phy_operations { 710177867Sjfv s32 (*init_params)(struct e1000_hw *); 711177867Sjfv s32 (*acquire)(struct e1000_hw *); 712185353Sjfv s32 (*cfg_on_link_up)(struct e1000_hw *); 713173788Sjfv s32 (*check_polarity)(struct e1000_hw *); 714173788Sjfv s32 (*check_reset_block)(struct e1000_hw *); 715177867Sjfv s32 (*commit)(struct e1000_hw *); 716173788Sjfv s32 (*force_speed_duplex)(struct e1000_hw *); 717173788Sjfv s32 (*get_cfg_done)(struct e1000_hw *hw); 718173788Sjfv s32 (*get_cable_length)(struct e1000_hw *); 719177867Sjfv s32 (*get_info)(struct e1000_hw *); 720235527Sjfv s32 (*set_page)(struct e1000_hw *, u16); 721177867Sjfv s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 722200243Sjfv s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 723235527Sjfv s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 724177867Sjfv void (*release)(struct e1000_hw *); 725177867Sjfv s32 (*reset)(struct e1000_hw *); 726173788Sjfv s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 727173788Sjfv s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 728177867Sjfv s32 (*write_reg)(struct e1000_hw *, u32, u16); 729200243Sjfv s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 730235527Sjfv s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 731177867Sjfv void (*power_up)(struct e1000_hw *); 732177867Sjfv void (*power_down)(struct e1000_hw *); 733235527Sjfv s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 734235527Sjfv s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 735177867Sjfv}; 736169240Sjfv 737248292Sjfv/* Function pointers for the NVM. */ 738177867Sjfvstruct e1000_nvm_operations { 739177867Sjfv s32 (*init_params)(struct e1000_hw *); 740177867Sjfv s32 (*acquire)(struct e1000_hw *); 741177867Sjfv s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 742177867Sjfv void (*release)(struct e1000_hw *); 743177867Sjfv void (*reload)(struct e1000_hw *); 744177867Sjfv s32 (*update)(struct e1000_hw *); 745173788Sjfv s32 (*valid_led_default)(struct e1000_hw *, u16 *); 746177867Sjfv s32 (*validate)(struct e1000_hw *); 747177867Sjfv s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 748169240Sjfv}; 749169240Sjfv 750169240Sjfvstruct e1000_mac_info { 751177867Sjfv struct e1000_mac_operations ops; 752218530Sjfv u8 addr[ETH_ADDR_LEN]; 753218530Sjfv u8 perm_addr[ETH_ADDR_LEN]; 754169240Sjfv 755181027Sjfv enum e1000_mac_type type; 756169240Sjfv 757169240Sjfv u32 collision_delta; 758169240Sjfv u32 ledctl_default; 759169240Sjfv u32 ledctl_mode1; 760169240Sjfv u32 ledctl_mode2; 761169240Sjfv u32 mc_filter_type; 762169240Sjfv u32 tx_packet_delta; 763169240Sjfv u32 txcw; 764169240Sjfv 765169240Sjfv u16 current_ifs_val; 766169240Sjfv u16 ifs_max_val; 767169240Sjfv u16 ifs_min_val; 768169240Sjfv u16 ifs_ratio; 769169240Sjfv u16 ifs_step_size; 770169240Sjfv u16 mta_reg_count; 771200243Sjfv u16 uta_reg_count; 772194865Sjfv 773194865Sjfv /* Maximum size of the MTA register table in all supported adapters */ 774194865Sjfv #define MAX_MTA_REG 128 775190872Sjfv u32 mta_shadow[MAX_MTA_REG]; 776169240Sjfv u16 rar_entry_count; 777169240Sjfv 778169240Sjfv u8 forced_speed_duplex; 779169240Sjfv 780173788Sjfv bool adaptive_ifs; 781205869Sjfv bool has_fwsm; 782173788Sjfv bool arc_subsystem_valid; 783173788Sjfv bool asf_firmware_present; 784173788Sjfv bool autoneg; 785173788Sjfv bool autoneg_failed; 786173788Sjfv bool get_link_status; 787173788Sjfv bool in_ifs_mode; 788173788Sjfv bool report_tx_early; 789190872Sjfv enum e1000_serdes_link_state serdes_link_state; 790173788Sjfv bool serdes_has_link; 791173788Sjfv bool tx_pkt_filtering; 792248292Sjfv u32 max_frame_size; 793169240Sjfv}; 794169240Sjfv 795169240Sjfvstruct e1000_phy_info { 796177867Sjfv struct e1000_phy_operations ops; 797181027Sjfv enum e1000_phy_type type; 798169240Sjfv 799181027Sjfv enum e1000_1000t_rx_status local_rx; 800181027Sjfv enum e1000_1000t_rx_status remote_rx; 801181027Sjfv enum e1000_ms_type ms_type; 802181027Sjfv enum e1000_ms_type original_ms_type; 803181027Sjfv enum e1000_rev_polarity cable_polarity; 804181027Sjfv enum e1000_smart_speed smart_speed; 805169240Sjfv 806169240Sjfv u32 addr; 807169240Sjfv u32 id; 808169240Sjfv u32 reset_delay_us; /* in usec */ 809169240Sjfv u32 revision; 810169240Sjfv 811181027Sjfv enum e1000_media_type media_type; 812173788Sjfv 813169240Sjfv u16 autoneg_advertised; 814169240Sjfv u16 autoneg_mask; 815169240Sjfv u16 cable_length; 816169240Sjfv u16 max_cable_length; 817169240Sjfv u16 min_cable_length; 818169240Sjfv 819169240Sjfv u8 mdix; 820169240Sjfv 821173788Sjfv bool disable_polarity_correction; 822173788Sjfv bool is_mdix; 823173788Sjfv bool polarity_correction; 824173788Sjfv bool speed_downgraded; 825173788Sjfv bool autoneg_wait_to_complete; 826169240Sjfv}; 827169240Sjfv 828169240Sjfvstruct e1000_nvm_info { 829177867Sjfv struct e1000_nvm_operations ops; 830181027Sjfv enum e1000_nvm_type type; 831181027Sjfv enum e1000_nvm_override override; 832169240Sjfv 833169240Sjfv u32 flash_bank_size; 834169240Sjfv u32 flash_base_addr; 835169240Sjfv 836169240Sjfv u16 word_size; 837169240Sjfv u16 delay_usec; 838169240Sjfv u16 address_bits; 839169240Sjfv u16 opcode_bits; 840169240Sjfv u16 page_size; 841169240Sjfv}; 842169240Sjfv 843169240Sjfvstruct e1000_bus_info { 844181027Sjfv enum e1000_bus_type type; 845181027Sjfv enum e1000_bus_speed speed; 846181027Sjfv enum e1000_bus_width width; 847169240Sjfv 848169240Sjfv u16 func; 849169240Sjfv u16 pci_cmd_word; 850169240Sjfv}; 851169240Sjfv 852173788Sjfvstruct e1000_fc_info { 853235527Sjfv u32 high_water; /* Flow control high-water mark */ 854235527Sjfv u32 low_water; /* Flow control low-water mark */ 855235527Sjfv u16 pause_time; /* Flow control pause timer */ 856235527Sjfv u16 refresh_time; /* Flow control refresh timer */ 857235527Sjfv bool send_xon; /* Flow control send XON */ 858235527Sjfv bool strict_ieee; /* Strict IEEE mode */ 859235527Sjfv enum e1000_fc_mode current_mode; /* FC mode in effect */ 860235527Sjfv enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 861173788Sjfv}; 862173788Sjfv 863213234Sjfvstruct e1000_mbx_operations { 864213234Sjfv s32 (*init_params)(struct e1000_hw *hw); 865213234Sjfv s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 866213234Sjfv s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 867213234Sjfv s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 868213234Sjfv s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 869213234Sjfv s32 (*check_for_msg)(struct e1000_hw *, u16); 870213234Sjfv s32 (*check_for_ack)(struct e1000_hw *, u16); 871213234Sjfv s32 (*check_for_rst)(struct e1000_hw *, u16); 872213234Sjfv}; 873213234Sjfv 874213234Sjfvstruct e1000_mbx_stats { 875213234Sjfv u32 msgs_tx; 876213234Sjfv u32 msgs_rx; 877213234Sjfv 878213234Sjfv u32 acks; 879213234Sjfv u32 reqs; 880213234Sjfv u32 rsts; 881213234Sjfv}; 882213234Sjfv 883213234Sjfvstruct e1000_mbx_info { 884213234Sjfv struct e1000_mbx_operations ops; 885213234Sjfv struct e1000_mbx_stats stats; 886213234Sjfv u32 timeout; 887213234Sjfv u32 usec_delay; 888213234Sjfv u16 size; 889213234Sjfv}; 890213234Sjfv 891185353Sjfvstruct e1000_dev_spec_82541 { 892185353Sjfv enum e1000_dsp_config dsp_config; 893185353Sjfv enum e1000_ffe_config ffe_config; 894185353Sjfv u16 spd_default; 895185353Sjfv bool phy_init_script; 896185353Sjfv}; 897185353Sjfv 898185353Sjfvstruct e1000_dev_spec_82542 { 899185353Sjfv bool dma_fairness; 900185353Sjfv}; 901185353Sjfv 902185353Sjfvstruct e1000_dev_spec_82543 { 903185353Sjfv u32 tbi_compatibility; 904185353Sjfv bool dma_fairness; 905185353Sjfv bool init_phy_disabled; 906185353Sjfv}; 907185353Sjfv 908185353Sjfvstruct e1000_dev_spec_82571 { 909185353Sjfv bool laa_is_present; 910194865Sjfv u32 smb_counter; 911213234Sjfv E1000_MUTEX swflag_mutex; 912185353Sjfv}; 913185353Sjfv 914200243Sjfvstruct e1000_dev_spec_80003es2lan { 915200243Sjfv bool mdic_wa_enable; 916200243Sjfv}; 917200243Sjfv 918185353Sjfvstruct e1000_shadow_ram { 919185353Sjfv u16 value; 920185353Sjfv bool modified; 921185353Sjfv}; 922185353Sjfv 923248292Sjfv#define E1000_SHADOW_RAM_WORDS 2048 924185353Sjfv 925185353Sjfvstruct e1000_dev_spec_ich8lan { 926185353Sjfv bool kmrn_lock_loss_workaround_enabled; 927185353Sjfv struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 928200243Sjfv E1000_MUTEX nvm_mutex; 929200243Sjfv E1000_MUTEX swflag_mutex; 930200243Sjfv bool nvm_k1_enabled; 931238262Sjfv bool eee_disable; 932248292Sjfv u16 eee_lp_ability; 933185353Sjfv}; 934185353Sjfv 935185353Sjfvstruct e1000_dev_spec_82575 { 936185353Sjfv bool sgmii_active; 937190872Sjfv bool global_device_reset; 938238262Sjfv bool eee_disable; 939235527Sjfv bool module_plugged; 940248292Sjfv bool clear_semaphore_once; 941235527Sjfv u32 mtu; 942248292Sjfv struct sfp_e1000_flags eth_flags; 943185353Sjfv}; 944185353Sjfv 945185353Sjfvstruct e1000_dev_spec_vf { 946218530Sjfv u32 vf_number; 947218530Sjfv u32 v2p_mailbox; 948185353Sjfv}; 949185353Sjfv 950169240Sjfvstruct e1000_hw { 951169240Sjfv void *back; 952169240Sjfv 953169240Sjfv u8 *hw_addr; 954169240Sjfv u8 *flash_address; 955169240Sjfv unsigned long io_base; 956169240Sjfv 957169240Sjfv struct e1000_mac_info mac; 958173788Sjfv struct e1000_fc_info fc; 959169240Sjfv struct e1000_phy_info phy; 960169240Sjfv struct e1000_nvm_info nvm; 961169240Sjfv struct e1000_bus_info bus; 962209616Sjfv struct e1000_mbx_info mbx; 963169240Sjfv struct e1000_host_mng_dhcp_cookie mng_cookie; 964169240Sjfv 965185353Sjfv union { 966218530Sjfv struct e1000_dev_spec_82541 _82541; 967218530Sjfv struct e1000_dev_spec_82542 _82542; 968218530Sjfv struct e1000_dev_spec_82543 _82543; 969218530Sjfv struct e1000_dev_spec_82571 _82571; 970200243Sjfv struct e1000_dev_spec_80003es2lan _80003es2lan; 971218530Sjfv struct e1000_dev_spec_ich8lan ich8lan; 972218530Sjfv struct e1000_dev_spec_82575 _82575; 973218530Sjfv struct e1000_dev_spec_vf vf; 974185353Sjfv } dev_spec; 975169240Sjfv 976169240Sjfv u16 device_id; 977169240Sjfv u16 subsystem_vendor_id; 978169240Sjfv u16 subsystem_device_id; 979169240Sjfv u16 vendor_id; 980169240Sjfv 981169240Sjfv u8 revision_id; 982169240Sjfv}; 983169240Sjfv 984181027Sjfv#include "e1000_82541.h" 985181027Sjfv#include "e1000_82543.h" 986181027Sjfv#include "e1000_82571.h" 987181027Sjfv#include "e1000_80003es2lan.h" 988181027Sjfv#include "e1000_ich8lan.h" 989181027Sjfv#include "e1000_82575.h" 990238262Sjfv#include "e1000_i210.h" 991181027Sjfv 992169240Sjfv/* These functions must be implemented by drivers */ 993169240Sjfvvoid e1000_pci_clear_mwi(struct e1000_hw *hw); 994169240Sjfvvoid e1000_pci_set_mwi(struct e1000_hw *hw); 995169240Sjfvs32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 996194865Sjfvs32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 997169240Sjfvvoid e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 998169240Sjfvvoid e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 999169240Sjfv 1000169240Sjfv#endif 1001