1177867Sjfv/****************************************************************************** 2169240Sjfv 3203049Sjfv Copyright (c) 2001-2010, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD$*/ 34169240Sjfv 35185353Sjfv/* 36185353Sjfv * 82542 Gigabit Ethernet Controller 37169240Sjfv */ 38169240Sjfv 39169240Sjfv#include "e1000_api.h" 40169240Sjfv 41177867Sjfvstatic s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 42177867Sjfvstatic s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 43177867Sjfvstatic s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 44177867Sjfvstatic s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 45177867Sjfvstatic s32 e1000_reset_hw_82542(struct e1000_hw *hw); 46177867Sjfvstatic s32 e1000_init_hw_82542(struct e1000_hw *hw); 47177867Sjfvstatic s32 e1000_setup_link_82542(struct e1000_hw *hw); 48177867Sjfvstatic s32 e1000_led_on_82542(struct e1000_hw *hw); 49177867Sjfvstatic s32 e1000_led_off_82542(struct e1000_hw *hw); 50177867Sjfvstatic void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 51177867Sjfvstatic void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 52195409Sjfvstatic s32 e1000_read_mac_addr_82542(struct e1000_hw *hw); 53169240Sjfv 54169240Sjfv/** 55169240Sjfv * e1000_init_phy_params_82542 - Init PHY func ptrs. 56169589Sjfv * @hw: pointer to the HW structure 57169240Sjfv **/ 58177867Sjfvstatic s32 e1000_init_phy_params_82542(struct e1000_hw *hw) 59169240Sjfv{ 60169240Sjfv struct e1000_phy_info *phy = &hw->phy; 61169240Sjfv s32 ret_val = E1000_SUCCESS; 62169240Sjfv 63169240Sjfv DEBUGFUNC("e1000_init_phy_params_82542"); 64169240Sjfv 65169240Sjfv phy->type = e1000_phy_none; 66169240Sjfv 67169240Sjfv return ret_val; 68169240Sjfv} 69169240Sjfv 70169240Sjfv/** 71169240Sjfv * e1000_init_nvm_params_82542 - Init NVM func ptrs. 72169589Sjfv * @hw: pointer to the HW structure 73169240Sjfv **/ 74177867Sjfvstatic s32 e1000_init_nvm_params_82542(struct e1000_hw *hw) 75169240Sjfv{ 76169240Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 77169240Sjfv 78169240Sjfv DEBUGFUNC("e1000_init_nvm_params_82542"); 79169240Sjfv 80169240Sjfv nvm->address_bits = 6; 81169240Sjfv nvm->delay_usec = 50; 82169240Sjfv nvm->opcode_bits = 3; 83169240Sjfv nvm->type = e1000_nvm_eeprom_microwire; 84169240Sjfv nvm->word_size = 64; 85169240Sjfv 86169240Sjfv /* Function Pointers */ 87177867Sjfv nvm->ops.read = e1000_read_nvm_microwire; 88177867Sjfv nvm->ops.release = e1000_stop_nvm; 89177867Sjfv nvm->ops.write = e1000_write_nvm_microwire; 90177867Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 91177867Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 92169240Sjfv 93169240Sjfv return E1000_SUCCESS; 94169240Sjfv} 95169240Sjfv 96169240Sjfv/** 97169240Sjfv * e1000_init_mac_params_82542 - Init MAC func ptrs. 98169589Sjfv * @hw: pointer to the HW structure 99169240Sjfv **/ 100177867Sjfvstatic s32 e1000_init_mac_params_82542(struct e1000_hw *hw) 101169240Sjfv{ 102169240Sjfv struct e1000_mac_info *mac = &hw->mac; 103169240Sjfv 104169240Sjfv DEBUGFUNC("e1000_init_mac_params_82542"); 105169240Sjfv 106169240Sjfv /* Set media type */ 107173788Sjfv hw->phy.media_type = e1000_media_type_fiber; 108169240Sjfv 109169240Sjfv /* Set mta register count */ 110169240Sjfv mac->mta_reg_count = 128; 111169240Sjfv /* Set rar entry count */ 112169240Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES; 113169240Sjfv 114169240Sjfv /* Function pointers */ 115169240Sjfv 116169240Sjfv /* bus type/speed/width */ 117177867Sjfv mac->ops.get_bus_info = e1000_get_bus_info_82542; 118185353Sjfv /* function id */ 119185353Sjfv mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 120169240Sjfv /* reset */ 121177867Sjfv mac->ops.reset_hw = e1000_reset_hw_82542; 122169240Sjfv /* hw initialization */ 123177867Sjfv mac->ops.init_hw = e1000_init_hw_82542; 124169240Sjfv /* link setup */ 125177867Sjfv mac->ops.setup_link = e1000_setup_link_82542; 126169240Sjfv /* phy/fiber/serdes setup */ 127177867Sjfv mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic; 128169240Sjfv /* check for link */ 129177867Sjfv mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 130169240Sjfv /* multicast address update */ 131177867Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 132169240Sjfv /* writing VFTA */ 133177867Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 134169240Sjfv /* clearing VFTA */ 135177867Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 136195409Sjfv /* read mac address */ 137195409Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82542; 138177867Sjfv /* set RAR */ 139177867Sjfv mac->ops.rar_set = e1000_rar_set_82542; 140169240Sjfv /* turn on/off LED */ 141177867Sjfv mac->ops.led_on = e1000_led_on_82542; 142177867Sjfv mac->ops.led_off = e1000_led_off_82542; 143169240Sjfv /* clear hardware counters */ 144177867Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 145169240Sjfv /* link info */ 146177867Sjfv mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic; 147169240Sjfv 148185353Sjfv return E1000_SUCCESS; 149169240Sjfv} 150169240Sjfv 151169240Sjfv/** 152169240Sjfv * e1000_init_function_pointers_82542 - Init func ptrs. 153169589Sjfv * @hw: pointer to the HW structure 154169240Sjfv * 155185353Sjfv * Called to initialize all function pointers and parameters. 156169240Sjfv **/ 157173788Sjfvvoid e1000_init_function_pointers_82542(struct e1000_hw *hw) 158169240Sjfv{ 159169240Sjfv DEBUGFUNC("e1000_init_function_pointers_82542"); 160169240Sjfv 161177867Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82542; 162177867Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 163177867Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82542; 164169240Sjfv} 165169240Sjfv 166169240Sjfv/** 167169240Sjfv * e1000_get_bus_info_82542 - Obtain bus information for adapter 168169589Sjfv * @hw: pointer to the HW structure 169169240Sjfv * 170169240Sjfv * This will obtain information about the HW bus for which the 171185353Sjfv * adapter is attached and stores it in the hw structure. 172169240Sjfv **/ 173177867Sjfvstatic s32 e1000_get_bus_info_82542(struct e1000_hw *hw) 174169240Sjfv{ 175169240Sjfv DEBUGFUNC("e1000_get_bus_info_82542"); 176169240Sjfv 177169240Sjfv hw->bus.type = e1000_bus_type_pci; 178169240Sjfv hw->bus.speed = e1000_bus_speed_unknown; 179169240Sjfv hw->bus.width = e1000_bus_width_unknown; 180169240Sjfv 181169240Sjfv return E1000_SUCCESS; 182169240Sjfv} 183169240Sjfv 184169240Sjfv/** 185169240Sjfv * e1000_reset_hw_82542 - Reset hardware 186169589Sjfv * @hw: pointer to the HW structure 187169240Sjfv * 188185353Sjfv * This resets the hardware into a known state. 189169240Sjfv **/ 190177867Sjfvstatic s32 e1000_reset_hw_82542(struct e1000_hw *hw) 191169240Sjfv{ 192169240Sjfv struct e1000_bus_info *bus = &hw->bus; 193169240Sjfv s32 ret_val = E1000_SUCCESS; 194218581Sjfv u32 ctrl; 195169240Sjfv 196169240Sjfv DEBUGFUNC("e1000_reset_hw_82542"); 197169240Sjfv 198169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 199169240Sjfv DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 200169240Sjfv e1000_pci_clear_mwi(hw); 201169240Sjfv } 202169240Sjfv 203169240Sjfv DEBUGOUT("Masking off all interrupts\n"); 204169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 205169240Sjfv 206169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 207169240Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 208169240Sjfv E1000_WRITE_FLUSH(hw); 209169240Sjfv 210173788Sjfv /* 211173788Sjfv * Delay to allow any outstanding PCI transactions to complete before 212169240Sjfv * resetting the device 213169240Sjfv */ 214169240Sjfv msec_delay(10); 215169240Sjfv 216169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 217169240Sjfv 218169240Sjfv DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 219169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 220169240Sjfv 221177867Sjfv hw->nvm.ops.reload(hw); 222169240Sjfv msec_delay(2); 223169240Sjfv 224169240Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 225218581Sjfv E1000_READ_REG(hw, E1000_ICR); 226169240Sjfv 227169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 228169240Sjfv if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 229169240Sjfv e1000_pci_set_mwi(hw); 230169240Sjfv } 231169240Sjfv 232169240Sjfv return ret_val; 233169240Sjfv} 234169240Sjfv 235169240Sjfv/** 236169240Sjfv * e1000_init_hw_82542 - Initialize hardware 237169589Sjfv * @hw: pointer to the HW structure 238169240Sjfv * 239185353Sjfv * This inits the hardware readying it for operation. 240169240Sjfv **/ 241177867Sjfvstatic s32 e1000_init_hw_82542(struct e1000_hw *hw) 242169240Sjfv{ 243169240Sjfv struct e1000_mac_info *mac = &hw->mac; 244185353Sjfv struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; 245169240Sjfv s32 ret_val = E1000_SUCCESS; 246169240Sjfv u32 ctrl; 247169240Sjfv u16 i; 248169240Sjfv 249169240Sjfv DEBUGFUNC("e1000_init_hw_82542"); 250169240Sjfv 251169240Sjfv /* Disabling VLAN filtering */ 252169240Sjfv E1000_WRITE_REG(hw, E1000_VET, 0); 253177867Sjfv mac->ops.clear_vfta(hw); 254169240Sjfv 255169240Sjfv /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 256169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 257169240Sjfv DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 258169240Sjfv e1000_pci_clear_mwi(hw); 259169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 260169240Sjfv E1000_WRITE_FLUSH(hw); 261169240Sjfv msec_delay(5); 262169240Sjfv } 263169240Sjfv 264169240Sjfv /* Setup the receive address. */ 265169240Sjfv e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 266169240Sjfv 267169240Sjfv /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 268169240Sjfv if (hw->revision_id == E1000_REVISION_2) { 269169240Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 270169240Sjfv E1000_WRITE_FLUSH(hw); 271169240Sjfv msec_delay(1); 272169240Sjfv if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 273169240Sjfv e1000_pci_set_mwi(hw); 274169240Sjfv } 275169240Sjfv 276169240Sjfv /* Zero out the Multicast HASH table */ 277169240Sjfv DEBUGOUT("Zeroing the MTA\n"); 278169240Sjfv for (i = 0; i < mac->mta_reg_count; i++) 279169240Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 280169240Sjfv 281173788Sjfv /* 282173788Sjfv * Set the PCI priority bit correctly in the CTRL register. This 283169240Sjfv * determines if the adapter gives priority to receives, or if it 284169240Sjfv * gives equal priority to transmits and receives. 285169240Sjfv */ 286169240Sjfv if (dev_spec->dma_fairness) { 287169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 288169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 289169240Sjfv } 290169240Sjfv 291169240Sjfv /* Setup link and flow control */ 292169240Sjfv ret_val = e1000_setup_link_82542(hw); 293169240Sjfv 294173788Sjfv /* 295173788Sjfv * Clear all of the statistics registers (clear on read). It is 296169240Sjfv * important that we do this after we have tried to establish link 297169240Sjfv * because the symbol error count will increment wildly if there 298169240Sjfv * is no link. 299169240Sjfv */ 300169240Sjfv e1000_clear_hw_cntrs_82542(hw); 301169240Sjfv 302169240Sjfv return ret_val; 303169240Sjfv} 304169240Sjfv 305169240Sjfv/** 306169240Sjfv * e1000_setup_link_82542 - Setup flow control and link settings 307169589Sjfv * @hw: pointer to the HW structure 308169240Sjfv * 309169240Sjfv * Determines which flow control settings to use, then configures flow 310169240Sjfv * control. Calls the appropriate media-specific link configuration 311169240Sjfv * function. Assuming the adapter has a valid link partner, a valid link 312169240Sjfv * should be established. Assumes the hardware has previously been reset 313185353Sjfv * and the transmitter and receiver are not enabled. 314169240Sjfv **/ 315177867Sjfvstatic s32 e1000_setup_link_82542(struct e1000_hw *hw) 316169240Sjfv{ 317169240Sjfv struct e1000_mac_info *mac = &hw->mac; 318169240Sjfv s32 ret_val = E1000_SUCCESS; 319169240Sjfv 320169240Sjfv DEBUGFUNC("e1000_setup_link_82542"); 321169240Sjfv 322169240Sjfv ret_val = e1000_set_default_fc_generic(hw); 323169240Sjfv if (ret_val) 324169240Sjfv goto out; 325169240Sjfv 326185353Sjfv hw->fc.requested_mode &= ~e1000_fc_tx_pause; 327169240Sjfv 328169240Sjfv if (mac->report_tx_early == 1) 329185353Sjfv hw->fc.requested_mode &= ~e1000_fc_rx_pause; 330169240Sjfv 331173788Sjfv /* 332185353Sjfv * Save off the requested flow control mode for use later. Depending 333185353Sjfv * on the link partner's capabilities, we may or may not use this mode. 334169240Sjfv */ 335185353Sjfv hw->fc.current_mode = hw->fc.requested_mode; 336169240Sjfv 337185353Sjfv DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 338185353Sjfv hw->fc.current_mode); 339169240Sjfv 340169240Sjfv /* Call the necessary subroutine to configure the link. */ 341177867Sjfv ret_val = mac->ops.setup_physical_interface(hw); 342169240Sjfv if (ret_val) 343169240Sjfv goto out; 344169240Sjfv 345173788Sjfv /* 346173788Sjfv * Initialize the flow control address, type, and PAUSE timer 347169240Sjfv * registers to their default values. This is done even if flow 348169240Sjfv * control is disabled, because it does not hurt anything to 349169240Sjfv * initialize these registers. 350169240Sjfv */ 351169240Sjfv DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 352169240Sjfv 353169240Sjfv E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 354169240Sjfv E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 355169240Sjfv E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 356169240Sjfv 357173788Sjfv E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 358169240Sjfv 359169240Sjfv ret_val = e1000_set_fc_watermarks_generic(hw); 360169240Sjfv 361169240Sjfvout: 362169240Sjfv return ret_val; 363169240Sjfv} 364169240Sjfv 365169240Sjfv/** 366169240Sjfv * e1000_led_on_82542 - Turn on SW controllable LED 367169589Sjfv * @hw: pointer to the HW structure 368169240Sjfv * 369185353Sjfv * Turns the SW defined LED on. 370169240Sjfv **/ 371177867Sjfvstatic s32 e1000_led_on_82542(struct e1000_hw *hw) 372169240Sjfv{ 373169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 374169240Sjfv 375169240Sjfv DEBUGFUNC("e1000_led_on_82542"); 376169240Sjfv 377169240Sjfv ctrl |= E1000_CTRL_SWDPIN0; 378169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 379169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 380169240Sjfv 381169240Sjfv return E1000_SUCCESS; 382169240Sjfv} 383169240Sjfv 384169240Sjfv/** 385169240Sjfv * e1000_led_off_82542 - Turn off SW controllable LED 386169589Sjfv * @hw: pointer to the HW structure 387169240Sjfv * 388185353Sjfv * Turns the SW defined LED off. 389169240Sjfv **/ 390177867Sjfvstatic s32 e1000_led_off_82542(struct e1000_hw *hw) 391169240Sjfv{ 392169240Sjfv u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 393169240Sjfv 394169240Sjfv DEBUGFUNC("e1000_led_off_82542"); 395169240Sjfv 396169240Sjfv ctrl &= ~E1000_CTRL_SWDPIN0; 397169240Sjfv ctrl |= E1000_CTRL_SWDPIO0; 398169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 399169240Sjfv 400169240Sjfv return E1000_SUCCESS; 401169240Sjfv} 402169240Sjfv 403169240Sjfv/** 404177867Sjfv * e1000_rar_set_82542 - Set receive address register 405177867Sjfv * @hw: pointer to the HW structure 406177867Sjfv * @addr: pointer to the receive address 407177867Sjfv * @index: receive address array register 408177867Sjfv * 409177867Sjfv * Sets the receive address array register at index to the address passed 410177867Sjfv * in by addr. 411177867Sjfv **/ 412177867Sjfvstatic void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 413177867Sjfv{ 414177867Sjfv u32 rar_low, rar_high; 415177867Sjfv 416177867Sjfv DEBUGFUNC("e1000_rar_set_82542"); 417177867Sjfv 418177867Sjfv /* 419177867Sjfv * HW expects these in little endian so we reverse the byte order 420177867Sjfv * from network order (big endian) to little endian 421177867Sjfv */ 422177867Sjfv rar_low = ((u32) addr[0] | 423177867Sjfv ((u32) addr[1] << 8) | 424177867Sjfv ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 425177867Sjfv 426177867Sjfv rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 427177867Sjfv 428177867Sjfv /* If MAC address zero, no need to set the AV bit */ 429185353Sjfv if (rar_low || rar_high) 430185353Sjfv rar_high |= E1000_RAH_AV; 431177867Sjfv 432177867Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 433177867Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 434177867Sjfv} 435177867Sjfv 436177867Sjfv/** 437176667Sjfv * e1000_translate_register_82542 - Translate the proper register offset 438169589Sjfv * @reg: e1000 register to be read 439169240Sjfv * 440169240Sjfv * Registers in 82542 are located in different offsets than other adapters 441169240Sjfv * even though they function in the same manner. This function takes in 442169240Sjfv * the name of the register to read and returns the correct offset for 443169240Sjfv * 82542 silicon. 444169240Sjfv **/ 445173788Sjfvu32 e1000_translate_register_82542(u32 reg) 446169240Sjfv{ 447173788Sjfv /* 448173788Sjfv * Some of the 82542 registers are located at different 449169240Sjfv * offsets than they are in newer adapters. 450169240Sjfv * Despite the difference in location, the registers 451169240Sjfv * function in the same manner. 452169240Sjfv */ 453169240Sjfv switch (reg) { 454169240Sjfv case E1000_RA: 455169240Sjfv reg = 0x00040; 456169240Sjfv break; 457169240Sjfv case E1000_RDTR: 458169240Sjfv reg = 0x00108; 459169240Sjfv break; 460173788Sjfv case E1000_RDBAL(0): 461169240Sjfv reg = 0x00110; 462169240Sjfv break; 463173788Sjfv case E1000_RDBAH(0): 464169240Sjfv reg = 0x00114; 465169240Sjfv break; 466173788Sjfv case E1000_RDLEN(0): 467169240Sjfv reg = 0x00118; 468169240Sjfv break; 469173788Sjfv case E1000_RDH(0): 470169240Sjfv reg = 0x00120; 471169240Sjfv break; 472173788Sjfv case E1000_RDT(0): 473169240Sjfv reg = 0x00128; 474169240Sjfv break; 475173788Sjfv case E1000_RDBAL(1): 476169240Sjfv reg = 0x00138; 477169240Sjfv break; 478173788Sjfv case E1000_RDBAH(1): 479169240Sjfv reg = 0x0013C; 480169240Sjfv break; 481173788Sjfv case E1000_RDLEN(1): 482169240Sjfv reg = 0x00140; 483169240Sjfv break; 484173788Sjfv case E1000_RDH(1): 485169240Sjfv reg = 0x00148; 486169240Sjfv break; 487173788Sjfv case E1000_RDT(1): 488169240Sjfv reg = 0x00150; 489169240Sjfv break; 490169240Sjfv case E1000_FCRTH: 491169240Sjfv reg = 0x00160; 492169240Sjfv break; 493169240Sjfv case E1000_FCRTL: 494169240Sjfv reg = 0x00168; 495169240Sjfv break; 496169240Sjfv case E1000_MTA: 497169240Sjfv reg = 0x00200; 498169240Sjfv break; 499173788Sjfv case E1000_TDBAL(0): 500169240Sjfv reg = 0x00420; 501169240Sjfv break; 502173788Sjfv case E1000_TDBAH(0): 503169240Sjfv reg = 0x00424; 504169240Sjfv break; 505173788Sjfv case E1000_TDLEN(0): 506169240Sjfv reg = 0x00428; 507169240Sjfv break; 508173788Sjfv case E1000_TDH(0): 509169240Sjfv reg = 0x00430; 510169240Sjfv break; 511173788Sjfv case E1000_TDT(0): 512169240Sjfv reg = 0x00438; 513169240Sjfv break; 514169240Sjfv case E1000_TIDV: 515169240Sjfv reg = 0x00440; 516169240Sjfv break; 517169240Sjfv case E1000_VFTA: 518169240Sjfv reg = 0x00600; 519169240Sjfv break; 520169240Sjfv case E1000_TDFH: 521169240Sjfv reg = 0x08010; 522169240Sjfv break; 523169240Sjfv case E1000_TDFT: 524169240Sjfv reg = 0x08018; 525169240Sjfv break; 526169240Sjfv default: 527169240Sjfv break; 528169240Sjfv } 529169240Sjfv 530169240Sjfv return reg; 531169240Sjfv} 532169240Sjfv 533169240Sjfv/** 534169240Sjfv * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 535169589Sjfv * @hw: pointer to the HW structure 536169240Sjfv * 537169240Sjfv * Clears the hardware counters by reading the counter registers. 538169240Sjfv **/ 539177867Sjfvstatic void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 540169240Sjfv{ 541169240Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 542169240Sjfv 543169240Sjfv e1000_clear_hw_cntrs_base_generic(hw); 544169240Sjfv 545185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 546185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 547185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 548185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 549185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 550185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 551185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 552185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 553185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 554185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 555185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 556185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 557169240Sjfv} 558195409Sjfv 559195409Sjfv/** 560195409Sjfv * e1000_read_mac_addr_82542 - Read device MAC address 561195409Sjfv * @hw: pointer to the HW structure 562195409Sjfv * 563195409Sjfv * Reads the device MAC address from the EEPROM and stores the value. 564195409Sjfv **/ 565195409Sjfvstatic s32 e1000_read_mac_addr_82542(struct e1000_hw *hw) 566195409Sjfv{ 567195409Sjfv s32 ret_val = E1000_SUCCESS; 568195409Sjfv u16 offset, nvm_data, i; 569195409Sjfv 570195409Sjfv DEBUGFUNC("e1000_read_mac_addr"); 571195409Sjfv 572195409Sjfv for (i = 0; i < ETH_ADDR_LEN; i += 2) { 573195409Sjfv offset = i >> 1; 574195409Sjfv ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 575195409Sjfv if (ret_val) { 576195409Sjfv DEBUGOUT("NVM Read Error\n"); 577195409Sjfv goto out; 578195409Sjfv } 579195409Sjfv hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 580195409Sjfv hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 581195409Sjfv } 582195409Sjfv 583195409Sjfv for (i = 0; i < ETH_ADDR_LEN; i++) 584195409Sjfv hw->mac.addr[i] = hw->mac.perm_addr[i]; 585195409Sjfv 586195409Sjfvout: 587195409Sjfv return ret_val; 588195409Sjfv} 589