1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-usbnx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon usbnx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_USBNX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_USBNX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 64215976Sjmallett cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id) 72215976Sjmallett{ 73215976Sjmallett if (!( 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79215976Sjmallett cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull; 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id) 87215976Sjmallett{ 88215976Sjmallett if (!( 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 91215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 94215976Sjmallett cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull; 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id) 102215976Sjmallett{ 103215976Sjmallett if (!( 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 121215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 122215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 123215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 124215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull; 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id) 132215976Sjmallett{ 133215976Sjmallett if (!( 134215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 139215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull; 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id) 147215976Sjmallett{ 148215976Sjmallett if (!( 149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull; 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull) 159215976Sjmallett#endif 160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id) 162215976Sjmallett{ 163215976Sjmallett if (!( 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 166215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 169215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 184215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull; 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id) 192215976Sjmallett{ 193215976Sjmallett if (!( 194215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 196215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 197215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 198215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 199215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id); 200215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull; 201215976Sjmallett} 202215976Sjmallett#else 203215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull) 204215976Sjmallett#endif 205215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id) 207215976Sjmallett{ 208215976Sjmallett if (!( 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 226215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 229215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 241215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 244215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id); 245215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull; 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull) 249215976Sjmallett#endif 250215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id) 252215976Sjmallett{ 253215976Sjmallett if (!( 254215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id); 260215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull; 261215976Sjmallett} 262215976Sjmallett#else 263215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull) 264215976Sjmallett#endif 265215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id) 267215976Sjmallett{ 268215976Sjmallett if (!( 269215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id); 275215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull; 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull) 279215976Sjmallett#endif 280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id) 282215976Sjmallett{ 283215976Sjmallett if (!( 284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id); 290215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull; 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id) 297215976Sjmallett{ 298215976Sjmallett if (!( 299215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id); 305215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull; 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id) 312215976Sjmallett{ 313215976Sjmallett if (!( 314215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 315215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 316215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 317215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 318215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 319215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id); 320215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull; 321215976Sjmallett} 322215976Sjmallett#else 323215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull) 324215976Sjmallett#endif 325215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id) 327215976Sjmallett{ 328215976Sjmallett if (!( 329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 334215976Sjmallett cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull; 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallettstatic inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id) 342215976Sjmallett{ 343215976Sjmallett if (!( 344215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 349215976Sjmallett cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id); 350215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull; 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id) 357215976Sjmallett{ 358215976Sjmallett if (!( 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364215976Sjmallett cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull; 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallettstatic inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id) 372215976Sjmallett{ 373215976Sjmallett if (!( 374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 377215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379215976Sjmallett cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id) 387215976Sjmallett{ 388215976Sjmallett if (!( 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 390215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 391215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 392215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 393215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 394215976Sjmallett cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 395215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull; 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull) 399215976Sjmallett#endif 400215976Sjmallett 401215976Sjmallett/** 402215976Sjmallett * cvmx_usbn#_bist_status 403215976Sjmallett * 404215976Sjmallett * USBN_BIST_STATUS = USBN's Control and Status 405215976Sjmallett * 406215976Sjmallett * Contain general control bits and status information for the USBN. 407215976Sjmallett */ 408215976Sjmallettunion cvmx_usbnx_bist_status 409215976Sjmallett{ 410215976Sjmallett uint64_t u64; 411215976Sjmallett struct cvmx_usbnx_bist_status_s 412215976Sjmallett { 413215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 414215976Sjmallett uint64_t reserved_7_63 : 57; 415215976Sjmallett uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */ 416215976Sjmallett uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */ 417215976Sjmallett uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */ 418215976Sjmallett uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */ 419215976Sjmallett uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 420215976Sjmallett uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 421215976Sjmallett uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 422215976Sjmallett#else 423215976Sjmallett uint64_t nof_bis : 1; 424215976Sjmallett uint64_t nif_bis : 1; 425215976Sjmallett uint64_t usbc_bis : 1; 426215976Sjmallett uint64_t n2uf_bis : 1; 427215976Sjmallett uint64_t e2hc_bis : 1; 428215976Sjmallett uint64_t u2nf_bis : 1; 429215976Sjmallett uint64_t u2nc_bis : 1; 430215976Sjmallett uint64_t reserved_7_63 : 57; 431215976Sjmallett#endif 432215976Sjmallett } s; 433215976Sjmallett struct cvmx_usbnx_bist_status_cn30xx 434215976Sjmallett { 435215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 436215976Sjmallett uint64_t reserved_3_63 : 61; 437215976Sjmallett uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 438215976Sjmallett uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 439215976Sjmallett uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 440215976Sjmallett#else 441215976Sjmallett uint64_t nof_bis : 1; 442215976Sjmallett uint64_t nif_bis : 1; 443215976Sjmallett uint64_t usbc_bis : 1; 444215976Sjmallett uint64_t reserved_3_63 : 61; 445215976Sjmallett#endif 446215976Sjmallett } cn30xx; 447215976Sjmallett struct cvmx_usbnx_bist_status_cn30xx cn31xx; 448215976Sjmallett struct cvmx_usbnx_bist_status_s cn50xx; 449215976Sjmallett struct cvmx_usbnx_bist_status_s cn52xx; 450215976Sjmallett struct cvmx_usbnx_bist_status_s cn52xxp1; 451215976Sjmallett struct cvmx_usbnx_bist_status_s cn56xx; 452215976Sjmallett struct cvmx_usbnx_bist_status_s cn56xxp1; 453215976Sjmallett}; 454215976Sjmalletttypedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t; 455215976Sjmallett 456215976Sjmallett/** 457215976Sjmallett * cvmx_usbn#_clk_ctl 458215976Sjmallett * 459215976Sjmallett * USBN_CLK_CTL = USBN's Clock Control 460215976Sjmallett * 461215976Sjmallett * This register is used to control the frequency of the hclk and the hreset and phy_rst signals. 462215976Sjmallett */ 463215976Sjmallettunion cvmx_usbnx_clk_ctl 464215976Sjmallett{ 465215976Sjmallett uint64_t u64; 466215976Sjmallett struct cvmx_usbnx_clk_ctl_s 467215976Sjmallett { 468215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 469215976Sjmallett uint64_t reserved_20_63 : 44; 470215976Sjmallett uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 471215976Sjmallett from the eclk. 472215976Sjmallett Also see the field DIVIDE. DIVIDE2<1> must currently 473215976Sjmallett be zero because it is not implemented, so the maximum 474215976Sjmallett ratio of eclk/hclk is currently 16. 475215976Sjmallett The actual divide number for hclk is: 476215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1) */ 477215976Sjmallett uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 478215976Sjmallett generate the hclk in the USB Subsystem is held 479215976Sjmallett in reset. This bit must be set to '0' before 480215976Sjmallett changing the value os DIVIDE in this register. 481215976Sjmallett The reset to the HCLK_DIVIDERis also asserted 482215976Sjmallett when core reset is asserted. */ 483215976Sjmallett uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 484215976Sjmallett '1' USB-PHY XO block is powered-down during 485215976Sjmallett suspend. 486215976Sjmallett '0' USB-PHY XO block is powered-up during 487215976Sjmallett suspend. 488215976Sjmallett The value of this field must be set while POR is 489215976Sjmallett active. */ 490215976Sjmallett uint64_t reserved_14_15 : 2; 491215976Sjmallett uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 492215976Sjmallett remain powered in Suspend Mode. 493215976Sjmallett '1' The USB-PHY XO Bias, Bandgap and PLL are 494215976Sjmallett powered down in suspend mode. 495215976Sjmallett The value of this field must be set while POR is 496215976Sjmallett active. */ 497215976Sjmallett uint64_t p_c_sel : 2; /**< Phy clock speed select. 498215976Sjmallett Selects the reference clock / crystal frequency. 499215976Sjmallett '11': Reserved 500215976Sjmallett '10': 48 MHz (reserved when a crystal is used) 501215976Sjmallett '01': 24 MHz (reserved when a crystal is used) 502215976Sjmallett '00': 12 MHz 503215976Sjmallett The value of this field must be set while POR is 504215976Sjmallett active. 505215976Sjmallett NOTE: if a crystal is used as a reference clock, 506215976Sjmallett this field must be set to 12 MHz. */ 507215976Sjmallett uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 508215976Sjmallett uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 509215976Sjmallett in the USBC, for normal operation this must be '0'. */ 510215976Sjmallett uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 511215976Sjmallett to '1' transition. */ 512215976Sjmallett uint64_t por : 1; /**< Power On Reset for the PHY. 513215976Sjmallett Resets all the PHYS registers and state machines. */ 514215976Sjmallett uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 515215976Sjmallett '0' the hclk will not be generated. SEE DIVIDE 516215976Sjmallett field of this register. */ 517215976Sjmallett uint64_t prst : 1; /**< When this field is '0' the reset associated with 518215976Sjmallett the phy_clk functionality in the USB Subsystem is 519215976Sjmallett help in reset. This bit should not be set to '1' 520215976Sjmallett until the time it takes 6 clocks (hclk or phy_clk, 521215976Sjmallett whichever is slower) has passed. Under normal 522215976Sjmallett operation once this bit is set to '1' it should not 523215976Sjmallett be set to '0'. */ 524215976Sjmallett uint64_t hrst : 1; /**< When this field is '0' the reset associated with 525215976Sjmallett the hclk functioanlity in the USB Subsystem is 526215976Sjmallett held in reset.This bit should not be set to '1' 527215976Sjmallett until 12ms after phy_clk is stable. Under normal 528215976Sjmallett operation, once this bit is set to '1' it should 529215976Sjmallett not be set to '0'. */ 530215976Sjmallett uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 531215976Sjmallett is the eclk frequency divided by the value of 532215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 533215976Sjmallett DIVIDE2 of this register. 534215976Sjmallett The hclk frequency should be less than 125Mhz. 535215976Sjmallett After writing a value to this field the SW should 536215976Sjmallett read the field for the value written. 537215976Sjmallett The ENABLE field of this register should not be set 538215976Sjmallett until AFTER this field is set and then read. */ 539215976Sjmallett#else 540215976Sjmallett uint64_t divide : 3; 541215976Sjmallett uint64_t hrst : 1; 542215976Sjmallett uint64_t prst : 1; 543215976Sjmallett uint64_t enable : 1; 544215976Sjmallett uint64_t por : 1; 545215976Sjmallett uint64_t s_bist : 1; 546215976Sjmallett uint64_t sd_mode : 2; 547215976Sjmallett uint64_t cdiv_byp : 1; 548215976Sjmallett uint64_t p_c_sel : 2; 549215976Sjmallett uint64_t p_com_on : 1; 550215976Sjmallett uint64_t reserved_14_15 : 2; 551215976Sjmallett uint64_t p_x_on : 1; 552215976Sjmallett uint64_t hclk_rst : 1; 553215976Sjmallett uint64_t divide2 : 2; 554215976Sjmallett uint64_t reserved_20_63 : 44; 555215976Sjmallett#endif 556215976Sjmallett } s; 557215976Sjmallett struct cvmx_usbnx_clk_ctl_cn30xx 558215976Sjmallett { 559215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 560215976Sjmallett uint64_t reserved_18_63 : 46; 561215976Sjmallett uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 562215976Sjmallett generate the hclk in the USB Subsystem is held 563215976Sjmallett in reset. This bit must be set to '0' before 564215976Sjmallett changing the value os DIVIDE in this register. 565215976Sjmallett The reset to the HCLK_DIVIDERis also asserted 566215976Sjmallett when core reset is asserted. */ 567215976Sjmallett uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 568215976Sjmallett '1' USB-PHY XO block is powered-down during 569215976Sjmallett suspend. 570215976Sjmallett '0' USB-PHY XO block is powered-up during 571215976Sjmallett suspend. 572215976Sjmallett The value of this field must be set while POR is 573215976Sjmallett active. */ 574215976Sjmallett uint64_t p_rclk : 1; /**< Phy refrence clock enable. 575215976Sjmallett '1' The PHY PLL uses the XO block output as a 576215976Sjmallett reference. 577215976Sjmallett '0' Reserved. */ 578215976Sjmallett uint64_t p_xenbn : 1; /**< Phy external clock enable. 579215976Sjmallett '1' The XO block uses the clock from a crystal. 580215976Sjmallett '0' The XO block uses an external clock supplied 581215976Sjmallett on the XO pin. USB_XI should be tied to 582215976Sjmallett ground for this usage. */ 583215976Sjmallett uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 584215976Sjmallett remain powered in Suspend Mode. 585215976Sjmallett '1' The USB-PHY XO Bias, Bandgap and PLL are 586215976Sjmallett powered down in suspend mode. 587215976Sjmallett The value of this field must be set while POR is 588215976Sjmallett active. */ 589215976Sjmallett uint64_t p_c_sel : 2; /**< Phy clock speed select. 590215976Sjmallett Selects the reference clock / crystal frequency. 591215976Sjmallett '11': Reserved 592215976Sjmallett '10': 48 MHz 593215976Sjmallett '01': 24 MHz 594215976Sjmallett '00': 12 MHz 595215976Sjmallett The value of this field must be set while POR is 596215976Sjmallett active. */ 597215976Sjmallett uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 598215976Sjmallett uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 599215976Sjmallett in the USBC, for normal operation this must be '0'. */ 600215976Sjmallett uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 601215976Sjmallett to '1' transition. */ 602215976Sjmallett uint64_t por : 1; /**< Power On Reset for the PHY. 603215976Sjmallett Resets all the PHYS registers and state machines. */ 604215976Sjmallett uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 605215976Sjmallett '0' the hclk will not be generated. */ 606215976Sjmallett uint64_t prst : 1; /**< When this field is '0' the reset associated with 607215976Sjmallett the phy_clk functionality in the USB Subsystem is 608215976Sjmallett help in reset. This bit should not be set to '1' 609215976Sjmallett until the time it takes 6 clocks (hclk or phy_clk, 610215976Sjmallett whichever is slower) has passed. Under normal 611215976Sjmallett operation once this bit is set to '1' it should not 612215976Sjmallett be set to '0'. */ 613215976Sjmallett uint64_t hrst : 1; /**< When this field is '0' the reset associated with 614215976Sjmallett the hclk functioanlity in the USB Subsystem is 615215976Sjmallett held in reset.This bit should not be set to '1' 616215976Sjmallett until 12ms after phy_clk is stable. Under normal 617215976Sjmallett operation, once this bit is set to '1' it should 618215976Sjmallett not be set to '0'. */ 619215976Sjmallett uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived 620215976Sjmallett from the eclk. The eclk will be divided by the 621215976Sjmallett value of this field +1 to determine the hclk 622215976Sjmallett frequency. (Also see HRST of this register). 623215976Sjmallett The hclk frequency must be less than 125 MHz. */ 624215976Sjmallett#else 625215976Sjmallett uint64_t divide : 3; 626215976Sjmallett uint64_t hrst : 1; 627215976Sjmallett uint64_t prst : 1; 628215976Sjmallett uint64_t enable : 1; 629215976Sjmallett uint64_t por : 1; 630215976Sjmallett uint64_t s_bist : 1; 631215976Sjmallett uint64_t sd_mode : 2; 632215976Sjmallett uint64_t cdiv_byp : 1; 633215976Sjmallett uint64_t p_c_sel : 2; 634215976Sjmallett uint64_t p_com_on : 1; 635215976Sjmallett uint64_t p_xenbn : 1; 636215976Sjmallett uint64_t p_rclk : 1; 637215976Sjmallett uint64_t p_x_on : 1; 638215976Sjmallett uint64_t hclk_rst : 1; 639215976Sjmallett uint64_t reserved_18_63 : 46; 640215976Sjmallett#endif 641215976Sjmallett } cn30xx; 642215976Sjmallett struct cvmx_usbnx_clk_ctl_cn30xx cn31xx; 643215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx 644215976Sjmallett { 645215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 646215976Sjmallett uint64_t reserved_20_63 : 44; 647215976Sjmallett uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 648215976Sjmallett from the eclk. 649215976Sjmallett Also see the field DIVIDE. DIVIDE2<1> must currently 650215976Sjmallett be zero because it is not implemented, so the maximum 651215976Sjmallett ratio of eclk/hclk is currently 16. 652215976Sjmallett The actual divide number for hclk is: 653215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1) */ 654215976Sjmallett uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 655215976Sjmallett generate the hclk in the USB Subsystem is held 656215976Sjmallett in reset. This bit must be set to '0' before 657215976Sjmallett changing the value os DIVIDE in this register. 658215976Sjmallett The reset to the HCLK_DIVIDERis also asserted 659215976Sjmallett when core reset is asserted. */ 660215976Sjmallett uint64_t reserved_16_16 : 1; 661215976Sjmallett uint64_t p_rtype : 2; /**< PHY reference clock type 662215976Sjmallett '0' The USB-PHY uses a 12MHz crystal as a clock 663215976Sjmallett source at the USB_XO and USB_XI pins 664215976Sjmallett '1' Reserved 665215976Sjmallett '2' The USB_PHY uses 12/24/48MHz 2.5V board clock 666215976Sjmallett at the USB_XO pin. USB_XI should be tied to 667215976Sjmallett ground in this case. 668215976Sjmallett '3' Reserved 669215976Sjmallett (bit 14 was P_XENBN on 3xxx) 670215976Sjmallett (bit 15 was P_RCLK on 3xxx) */ 671215976Sjmallett uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 672215976Sjmallett remain powered in Suspend Mode. 673215976Sjmallett '1' The USB-PHY XO Bias, Bandgap and PLL are 674215976Sjmallett powered down in suspend mode. 675215976Sjmallett The value of this field must be set while POR is 676215976Sjmallett active. */ 677215976Sjmallett uint64_t p_c_sel : 2; /**< Phy clock speed select. 678215976Sjmallett Selects the reference clock / crystal frequency. 679215976Sjmallett '11': Reserved 680215976Sjmallett '10': 48 MHz (reserved when a crystal is used) 681215976Sjmallett '01': 24 MHz (reserved when a crystal is used) 682215976Sjmallett '00': 12 MHz 683215976Sjmallett The value of this field must be set while POR is 684215976Sjmallett active. 685215976Sjmallett NOTE: if a crystal is used as a reference clock, 686215976Sjmallett this field must be set to 12 MHz. */ 687215976Sjmallett uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 688215976Sjmallett uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 689215976Sjmallett in the USBC, for normal operation this must be '0'. */ 690215976Sjmallett uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 691215976Sjmallett to '1' transition. */ 692215976Sjmallett uint64_t por : 1; /**< Power On Reset for the PHY. 693215976Sjmallett Resets all the PHYS registers and state machines. */ 694215976Sjmallett uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 695215976Sjmallett '0' the hclk will not be generated. SEE DIVIDE 696215976Sjmallett field of this register. */ 697215976Sjmallett uint64_t prst : 1; /**< When this field is '0' the reset associated with 698215976Sjmallett the phy_clk functionality in the USB Subsystem is 699215976Sjmallett help in reset. This bit should not be set to '1' 700215976Sjmallett until the time it takes 6 clocks (hclk or phy_clk, 701215976Sjmallett whichever is slower) has passed. Under normal 702215976Sjmallett operation once this bit is set to '1' it should not 703215976Sjmallett be set to '0'. */ 704215976Sjmallett uint64_t hrst : 1; /**< When this field is '0' the reset associated with 705215976Sjmallett the hclk functioanlity in the USB Subsystem is 706215976Sjmallett held in reset.This bit should not be set to '1' 707215976Sjmallett until 12ms after phy_clk is stable. Under normal 708215976Sjmallett operation, once this bit is set to '1' it should 709215976Sjmallett not be set to '0'. */ 710215976Sjmallett uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 711215976Sjmallett is the eclk frequency divided by the value of 712215976Sjmallett (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 713215976Sjmallett DIVIDE2 of this register. 714215976Sjmallett The hclk frequency should be less than 125Mhz. 715215976Sjmallett After writing a value to this field the SW should 716215976Sjmallett read the field for the value written. 717215976Sjmallett The ENABLE field of this register should not be set 718215976Sjmallett until AFTER this field is set and then read. */ 719215976Sjmallett#else 720215976Sjmallett uint64_t divide : 3; 721215976Sjmallett uint64_t hrst : 1; 722215976Sjmallett uint64_t prst : 1; 723215976Sjmallett uint64_t enable : 1; 724215976Sjmallett uint64_t por : 1; 725215976Sjmallett uint64_t s_bist : 1; 726215976Sjmallett uint64_t sd_mode : 2; 727215976Sjmallett uint64_t cdiv_byp : 1; 728215976Sjmallett uint64_t p_c_sel : 2; 729215976Sjmallett uint64_t p_com_on : 1; 730215976Sjmallett uint64_t p_rtype : 2; 731215976Sjmallett uint64_t reserved_16_16 : 1; 732215976Sjmallett uint64_t hclk_rst : 1; 733215976Sjmallett uint64_t divide2 : 2; 734215976Sjmallett uint64_t reserved_20_63 : 44; 735215976Sjmallett#endif 736215976Sjmallett } cn50xx; 737215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn52xx; 738215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1; 739215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn56xx; 740215976Sjmallett struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1; 741215976Sjmallett}; 742215976Sjmalletttypedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t; 743215976Sjmallett 744215976Sjmallett/** 745215976Sjmallett * cvmx_usbn#_ctl_status 746215976Sjmallett * 747215976Sjmallett * USBN_CTL_STATUS = USBN's Control And Status Register 748215976Sjmallett * 749215976Sjmallett * Contains general control and status information for the USBN block. 750215976Sjmallett */ 751215976Sjmallettunion cvmx_usbnx_ctl_status 752215976Sjmallett{ 753215976Sjmallett uint64_t u64; 754215976Sjmallett struct cvmx_usbnx_ctl_status_s 755215976Sjmallett { 756215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 757215976Sjmallett uint64_t reserved_6_63 : 58; 758215976Sjmallett uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page 759215976Sjmallett bit in the L2C store operation to the IOB. */ 760215976Sjmallett uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */ 761215976Sjmallett uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode. 762215976Sjmallett For normal operation this bit should be '0'. */ 763215976Sjmallett uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB 764215976Sjmallett for USB-CORE FIFO access to be inverted. Also data 765215976Sjmallett writen to and read from the AHB will have it byte 766215976Sjmallett order swapped. If the orginal order was A-B-C-D the 767215976Sjmallett new byte order will be D-C-B-A. */ 768215976Sjmallett uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C. 769215976Sjmallett IN: A-B-C-D-E-F-G-H 770215976Sjmallett OUT0: A-B-C-D-E-F-G-H 771215976Sjmallett OUT1: H-G-F-E-D-C-B-A 772215976Sjmallett OUT2: D-C-B-A-H-G-F-E 773215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 774215976Sjmallett#else 775215976Sjmallett uint64_t l2c_emod : 2; 776215976Sjmallett uint64_t inv_a2 : 1; 777215976Sjmallett uint64_t dma_test : 1; 778215976Sjmallett uint64_t dma_stt : 1; 779215976Sjmallett uint64_t dma_0pag : 1; 780215976Sjmallett uint64_t reserved_6_63 : 58; 781215976Sjmallett#endif 782215976Sjmallett } s; 783215976Sjmallett struct cvmx_usbnx_ctl_status_s cn30xx; 784215976Sjmallett struct cvmx_usbnx_ctl_status_s cn31xx; 785215976Sjmallett struct cvmx_usbnx_ctl_status_s cn50xx; 786215976Sjmallett struct cvmx_usbnx_ctl_status_s cn52xx; 787215976Sjmallett struct cvmx_usbnx_ctl_status_s cn52xxp1; 788215976Sjmallett struct cvmx_usbnx_ctl_status_s cn56xx; 789215976Sjmallett struct cvmx_usbnx_ctl_status_s cn56xxp1; 790215976Sjmallett}; 791215976Sjmalletttypedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t; 792215976Sjmallett 793215976Sjmallett/** 794215976Sjmallett * cvmx_usbn#_dma0_inb_chn0 795215976Sjmallett * 796215976Sjmallett * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0 797215976Sjmallett * 798215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel0. 799215976Sjmallett * Writing of this register sets the base address. 800215976Sjmallett */ 801215976Sjmallettunion cvmx_usbnx_dma0_inb_chn0 802215976Sjmallett{ 803215976Sjmallett uint64_t u64; 804215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s 805215976Sjmallett { 806215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 807215976Sjmallett uint64_t reserved_36_63 : 28; 808215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 809215976Sjmallett#else 810215976Sjmallett uint64_t addr : 36; 811215976Sjmallett uint64_t reserved_36_63 : 28; 812215976Sjmallett#endif 813215976Sjmallett } s; 814215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn30xx; 815215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn31xx; 816215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn50xx; 817215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn52xx; 818215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1; 819215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn56xx; 820215976Sjmallett struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1; 821215976Sjmallett}; 822215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t; 823215976Sjmallett 824215976Sjmallett/** 825215976Sjmallett * cvmx_usbn#_dma0_inb_chn1 826215976Sjmallett * 827215976Sjmallett * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1 828215976Sjmallett * 829215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel1. 830215976Sjmallett * Writing of this register sets the base address. 831215976Sjmallett */ 832215976Sjmallettunion cvmx_usbnx_dma0_inb_chn1 833215976Sjmallett{ 834215976Sjmallett uint64_t u64; 835215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s 836215976Sjmallett { 837215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 838215976Sjmallett uint64_t reserved_36_63 : 28; 839215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 840215976Sjmallett#else 841215976Sjmallett uint64_t addr : 36; 842215976Sjmallett uint64_t reserved_36_63 : 28; 843215976Sjmallett#endif 844215976Sjmallett } s; 845215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn30xx; 846215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn31xx; 847215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn50xx; 848215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn52xx; 849215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1; 850215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn56xx; 851215976Sjmallett struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1; 852215976Sjmallett}; 853215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t; 854215976Sjmallett 855215976Sjmallett/** 856215976Sjmallett * cvmx_usbn#_dma0_inb_chn2 857215976Sjmallett * 858215976Sjmallett * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2 859215976Sjmallett * 860215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel2. 861215976Sjmallett * Writing of this register sets the base address. 862215976Sjmallett */ 863215976Sjmallettunion cvmx_usbnx_dma0_inb_chn2 864215976Sjmallett{ 865215976Sjmallett uint64_t u64; 866215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s 867215976Sjmallett { 868215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 869215976Sjmallett uint64_t reserved_36_63 : 28; 870215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 871215976Sjmallett#else 872215976Sjmallett uint64_t addr : 36; 873215976Sjmallett uint64_t reserved_36_63 : 28; 874215976Sjmallett#endif 875215976Sjmallett } s; 876215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn30xx; 877215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn31xx; 878215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn50xx; 879215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn52xx; 880215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1; 881215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn56xx; 882215976Sjmallett struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1; 883215976Sjmallett}; 884215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t; 885215976Sjmallett 886215976Sjmallett/** 887215976Sjmallett * cvmx_usbn#_dma0_inb_chn3 888215976Sjmallett * 889215976Sjmallett * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3 890215976Sjmallett * 891215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel3. 892215976Sjmallett * Writing of this register sets the base address. 893215976Sjmallett */ 894215976Sjmallettunion cvmx_usbnx_dma0_inb_chn3 895215976Sjmallett{ 896215976Sjmallett uint64_t u64; 897215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s 898215976Sjmallett { 899215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 900215976Sjmallett uint64_t reserved_36_63 : 28; 901215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 902215976Sjmallett#else 903215976Sjmallett uint64_t addr : 36; 904215976Sjmallett uint64_t reserved_36_63 : 28; 905215976Sjmallett#endif 906215976Sjmallett } s; 907215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn30xx; 908215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn31xx; 909215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn50xx; 910215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn52xx; 911215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1; 912215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn56xx; 913215976Sjmallett struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1; 914215976Sjmallett}; 915215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t; 916215976Sjmallett 917215976Sjmallett/** 918215976Sjmallett * cvmx_usbn#_dma0_inb_chn4 919215976Sjmallett * 920215976Sjmallett * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4 921215976Sjmallett * 922215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel4. 923215976Sjmallett * Writing of this register sets the base address. 924215976Sjmallett */ 925215976Sjmallettunion cvmx_usbnx_dma0_inb_chn4 926215976Sjmallett{ 927215976Sjmallett uint64_t u64; 928215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s 929215976Sjmallett { 930215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 931215976Sjmallett uint64_t reserved_36_63 : 28; 932215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 933215976Sjmallett#else 934215976Sjmallett uint64_t addr : 36; 935215976Sjmallett uint64_t reserved_36_63 : 28; 936215976Sjmallett#endif 937215976Sjmallett } s; 938215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn30xx; 939215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn31xx; 940215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn50xx; 941215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn52xx; 942215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1; 943215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn56xx; 944215976Sjmallett struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1; 945215976Sjmallett}; 946215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t; 947215976Sjmallett 948215976Sjmallett/** 949215976Sjmallett * cvmx_usbn#_dma0_inb_chn5 950215976Sjmallett * 951215976Sjmallett * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5 952215976Sjmallett * 953215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel5. 954215976Sjmallett * Writing of this register sets the base address. 955215976Sjmallett */ 956215976Sjmallettunion cvmx_usbnx_dma0_inb_chn5 957215976Sjmallett{ 958215976Sjmallett uint64_t u64; 959215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s 960215976Sjmallett { 961215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 962215976Sjmallett uint64_t reserved_36_63 : 28; 963215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 964215976Sjmallett#else 965215976Sjmallett uint64_t addr : 36; 966215976Sjmallett uint64_t reserved_36_63 : 28; 967215976Sjmallett#endif 968215976Sjmallett } s; 969215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn30xx; 970215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn31xx; 971215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn50xx; 972215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn52xx; 973215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1; 974215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn56xx; 975215976Sjmallett struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1; 976215976Sjmallett}; 977215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t; 978215976Sjmallett 979215976Sjmallett/** 980215976Sjmallett * cvmx_usbn#_dma0_inb_chn6 981215976Sjmallett * 982215976Sjmallett * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6 983215976Sjmallett * 984215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel6. 985215976Sjmallett * Writing of this register sets the base address. 986215976Sjmallett */ 987215976Sjmallettunion cvmx_usbnx_dma0_inb_chn6 988215976Sjmallett{ 989215976Sjmallett uint64_t u64; 990215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s 991215976Sjmallett { 992215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 993215976Sjmallett uint64_t reserved_36_63 : 28; 994215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 995215976Sjmallett#else 996215976Sjmallett uint64_t addr : 36; 997215976Sjmallett uint64_t reserved_36_63 : 28; 998215976Sjmallett#endif 999215976Sjmallett } s; 1000215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn30xx; 1001215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn31xx; 1002215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn50xx; 1003215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn52xx; 1004215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1; 1005215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn56xx; 1006215976Sjmallett struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1; 1007215976Sjmallett}; 1008215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t; 1009215976Sjmallett 1010215976Sjmallett/** 1011215976Sjmallett * cvmx_usbn#_dma0_inb_chn7 1012215976Sjmallett * 1013215976Sjmallett * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7 1014215976Sjmallett * 1015215976Sjmallett * Contains the starting address for use when USB0 writes to L2C via Channel7. 1016215976Sjmallett * Writing of this register sets the base address. 1017215976Sjmallett */ 1018215976Sjmallettunion cvmx_usbnx_dma0_inb_chn7 1019215976Sjmallett{ 1020215976Sjmallett uint64_t u64; 1021215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s 1022215976Sjmallett { 1023215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1024215976Sjmallett uint64_t reserved_36_63 : 28; 1025215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 1026215976Sjmallett#else 1027215976Sjmallett uint64_t addr : 36; 1028215976Sjmallett uint64_t reserved_36_63 : 28; 1029215976Sjmallett#endif 1030215976Sjmallett } s; 1031215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn30xx; 1032215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn31xx; 1033215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn50xx; 1034215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn52xx; 1035215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1; 1036215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn56xx; 1037215976Sjmallett struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1; 1038215976Sjmallett}; 1039215976Sjmalletttypedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t; 1040215976Sjmallett 1041215976Sjmallett/** 1042215976Sjmallett * cvmx_usbn#_dma0_outb_chn0 1043215976Sjmallett * 1044215976Sjmallett * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0 1045215976Sjmallett * 1046215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel0. 1047215976Sjmallett * Writing of this register sets the base address. 1048215976Sjmallett */ 1049215976Sjmallettunion cvmx_usbnx_dma0_outb_chn0 1050215976Sjmallett{ 1051215976Sjmallett uint64_t u64; 1052215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s 1053215976Sjmallett { 1054215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1055215976Sjmallett uint64_t reserved_36_63 : 28; 1056215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1057215976Sjmallett#else 1058215976Sjmallett uint64_t addr : 36; 1059215976Sjmallett uint64_t reserved_36_63 : 28; 1060215976Sjmallett#endif 1061215976Sjmallett } s; 1062215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn30xx; 1063215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn31xx; 1064215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn50xx; 1065215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn52xx; 1066215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1; 1067215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn56xx; 1068215976Sjmallett struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1; 1069215976Sjmallett}; 1070215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t; 1071215976Sjmallett 1072215976Sjmallett/** 1073215976Sjmallett * cvmx_usbn#_dma0_outb_chn1 1074215976Sjmallett * 1075215976Sjmallett * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1 1076215976Sjmallett * 1077215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel1. 1078215976Sjmallett * Writing of this register sets the base address. 1079215976Sjmallett */ 1080215976Sjmallettunion cvmx_usbnx_dma0_outb_chn1 1081215976Sjmallett{ 1082215976Sjmallett uint64_t u64; 1083215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s 1084215976Sjmallett { 1085215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1086215976Sjmallett uint64_t reserved_36_63 : 28; 1087215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1088215976Sjmallett#else 1089215976Sjmallett uint64_t addr : 36; 1090215976Sjmallett uint64_t reserved_36_63 : 28; 1091215976Sjmallett#endif 1092215976Sjmallett } s; 1093215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn30xx; 1094215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn31xx; 1095215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn50xx; 1096215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn52xx; 1097215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1; 1098215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn56xx; 1099215976Sjmallett struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1; 1100215976Sjmallett}; 1101215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t; 1102215976Sjmallett 1103215976Sjmallett/** 1104215976Sjmallett * cvmx_usbn#_dma0_outb_chn2 1105215976Sjmallett * 1106215976Sjmallett * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2 1107215976Sjmallett * 1108215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel2. 1109215976Sjmallett * Writing of this register sets the base address. 1110215976Sjmallett */ 1111215976Sjmallettunion cvmx_usbnx_dma0_outb_chn2 1112215976Sjmallett{ 1113215976Sjmallett uint64_t u64; 1114215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s 1115215976Sjmallett { 1116215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1117215976Sjmallett uint64_t reserved_36_63 : 28; 1118215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1119215976Sjmallett#else 1120215976Sjmallett uint64_t addr : 36; 1121215976Sjmallett uint64_t reserved_36_63 : 28; 1122215976Sjmallett#endif 1123215976Sjmallett } s; 1124215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn30xx; 1125215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn31xx; 1126215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn50xx; 1127215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn52xx; 1128215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1; 1129215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn56xx; 1130215976Sjmallett struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1; 1131215976Sjmallett}; 1132215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t; 1133215976Sjmallett 1134215976Sjmallett/** 1135215976Sjmallett * cvmx_usbn#_dma0_outb_chn3 1136215976Sjmallett * 1137215976Sjmallett * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3 1138215976Sjmallett * 1139215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel3. 1140215976Sjmallett * Writing of this register sets the base address. 1141215976Sjmallett */ 1142215976Sjmallettunion cvmx_usbnx_dma0_outb_chn3 1143215976Sjmallett{ 1144215976Sjmallett uint64_t u64; 1145215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s 1146215976Sjmallett { 1147215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1148215976Sjmallett uint64_t reserved_36_63 : 28; 1149215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1150215976Sjmallett#else 1151215976Sjmallett uint64_t addr : 36; 1152215976Sjmallett uint64_t reserved_36_63 : 28; 1153215976Sjmallett#endif 1154215976Sjmallett } s; 1155215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn30xx; 1156215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn31xx; 1157215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn50xx; 1158215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn52xx; 1159215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1; 1160215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn56xx; 1161215976Sjmallett struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1; 1162215976Sjmallett}; 1163215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t; 1164215976Sjmallett 1165215976Sjmallett/** 1166215976Sjmallett * cvmx_usbn#_dma0_outb_chn4 1167215976Sjmallett * 1168215976Sjmallett * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4 1169215976Sjmallett * 1170215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel4. 1171215976Sjmallett * Writing of this register sets the base address. 1172215976Sjmallett */ 1173215976Sjmallettunion cvmx_usbnx_dma0_outb_chn4 1174215976Sjmallett{ 1175215976Sjmallett uint64_t u64; 1176215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s 1177215976Sjmallett { 1178215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1179215976Sjmallett uint64_t reserved_36_63 : 28; 1180215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1181215976Sjmallett#else 1182215976Sjmallett uint64_t addr : 36; 1183215976Sjmallett uint64_t reserved_36_63 : 28; 1184215976Sjmallett#endif 1185215976Sjmallett } s; 1186215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn30xx; 1187215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn31xx; 1188215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn50xx; 1189215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn52xx; 1190215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1; 1191215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn56xx; 1192215976Sjmallett struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1; 1193215976Sjmallett}; 1194215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t; 1195215976Sjmallett 1196215976Sjmallett/** 1197215976Sjmallett * cvmx_usbn#_dma0_outb_chn5 1198215976Sjmallett * 1199215976Sjmallett * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5 1200215976Sjmallett * 1201215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel5. 1202215976Sjmallett * Writing of this register sets the base address. 1203215976Sjmallett */ 1204215976Sjmallettunion cvmx_usbnx_dma0_outb_chn5 1205215976Sjmallett{ 1206215976Sjmallett uint64_t u64; 1207215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s 1208215976Sjmallett { 1209215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1210215976Sjmallett uint64_t reserved_36_63 : 28; 1211215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1212215976Sjmallett#else 1213215976Sjmallett uint64_t addr : 36; 1214215976Sjmallett uint64_t reserved_36_63 : 28; 1215215976Sjmallett#endif 1216215976Sjmallett } s; 1217215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn30xx; 1218215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn31xx; 1219215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn50xx; 1220215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn52xx; 1221215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1; 1222215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn56xx; 1223215976Sjmallett struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1; 1224215976Sjmallett}; 1225215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t; 1226215976Sjmallett 1227215976Sjmallett/** 1228215976Sjmallett * cvmx_usbn#_dma0_outb_chn6 1229215976Sjmallett * 1230215976Sjmallett * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6 1231215976Sjmallett * 1232215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel6. 1233215976Sjmallett * Writing of this register sets the base address. 1234215976Sjmallett */ 1235215976Sjmallettunion cvmx_usbnx_dma0_outb_chn6 1236215976Sjmallett{ 1237215976Sjmallett uint64_t u64; 1238215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s 1239215976Sjmallett { 1240215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1241215976Sjmallett uint64_t reserved_36_63 : 28; 1242215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1243215976Sjmallett#else 1244215976Sjmallett uint64_t addr : 36; 1245215976Sjmallett uint64_t reserved_36_63 : 28; 1246215976Sjmallett#endif 1247215976Sjmallett } s; 1248215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn30xx; 1249215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn31xx; 1250215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn50xx; 1251215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn52xx; 1252215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1; 1253215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn56xx; 1254215976Sjmallett struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1; 1255215976Sjmallett}; 1256215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t; 1257215976Sjmallett 1258215976Sjmallett/** 1259215976Sjmallett * cvmx_usbn#_dma0_outb_chn7 1260215976Sjmallett * 1261215976Sjmallett * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7 1262215976Sjmallett * 1263215976Sjmallett * Contains the starting address for use when USB0 reads from L2C via Channel7. 1264215976Sjmallett * Writing of this register sets the base address. 1265215976Sjmallett */ 1266215976Sjmallettunion cvmx_usbnx_dma0_outb_chn7 1267215976Sjmallett{ 1268215976Sjmallett uint64_t u64; 1269215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s 1270215976Sjmallett { 1271215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1272215976Sjmallett uint64_t reserved_36_63 : 28; 1273215976Sjmallett uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1274215976Sjmallett#else 1275215976Sjmallett uint64_t addr : 36; 1276215976Sjmallett uint64_t reserved_36_63 : 28; 1277215976Sjmallett#endif 1278215976Sjmallett } s; 1279215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn30xx; 1280215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn31xx; 1281215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn50xx; 1282215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn52xx; 1283215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1; 1284215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn56xx; 1285215976Sjmallett struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1; 1286215976Sjmallett}; 1287215976Sjmalletttypedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t; 1288215976Sjmallett 1289215976Sjmallett/** 1290215976Sjmallett * cvmx_usbn#_dma_test 1291215976Sjmallett * 1292215976Sjmallett * USBN_DMA_TEST = USBN's DMA TestRegister 1293215976Sjmallett * 1294215976Sjmallett * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs 1295215976Sjmallett */ 1296215976Sjmallettunion cvmx_usbnx_dma_test 1297215976Sjmallett{ 1298215976Sjmallett uint64_t u64; 1299215976Sjmallett struct cvmx_usbnx_dma_test_s 1300215976Sjmallett { 1301215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1302215976Sjmallett uint64_t reserved_40_63 : 24; 1303215976Sjmallett uint64_t done : 1; /**< This field is set when a DMA completes. Writing a 1304215976Sjmallett '1' to this field clears this bit. */ 1305215976Sjmallett uint64_t req : 1; /**< DMA Request. Writing a 1 to this register 1306215976Sjmallett will cause a DMA request as specified in the other 1307215976Sjmallett fields of this register to take place. This field 1308215976Sjmallett will always read as '0'. */ 1309215976Sjmallett uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */ 1310215976Sjmallett uint64_t count : 11; /**< DMA Request Count. */ 1311215976Sjmallett uint64_t channel : 5; /**< DMA Channel/Enpoint. */ 1312215976Sjmallett uint64_t burst : 4; /**< DMA Burst Size. */ 1313215976Sjmallett#else 1314215976Sjmallett uint64_t burst : 4; 1315215976Sjmallett uint64_t channel : 5; 1316215976Sjmallett uint64_t count : 11; 1317215976Sjmallett uint64_t f_addr : 18; 1318215976Sjmallett uint64_t req : 1; 1319215976Sjmallett uint64_t done : 1; 1320215976Sjmallett uint64_t reserved_40_63 : 24; 1321215976Sjmallett#endif 1322215976Sjmallett } s; 1323215976Sjmallett struct cvmx_usbnx_dma_test_s cn30xx; 1324215976Sjmallett struct cvmx_usbnx_dma_test_s cn31xx; 1325215976Sjmallett struct cvmx_usbnx_dma_test_s cn50xx; 1326215976Sjmallett struct cvmx_usbnx_dma_test_s cn52xx; 1327215976Sjmallett struct cvmx_usbnx_dma_test_s cn52xxp1; 1328215976Sjmallett struct cvmx_usbnx_dma_test_s cn56xx; 1329215976Sjmallett struct cvmx_usbnx_dma_test_s cn56xxp1; 1330215976Sjmallett}; 1331215976Sjmalletttypedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t; 1332215976Sjmallett 1333215976Sjmallett/** 1334215976Sjmallett * cvmx_usbn#_int_enb 1335215976Sjmallett * 1336215976Sjmallett * USBN_INT_ENB = USBN's Interrupt Enable 1337215976Sjmallett * 1338215976Sjmallett * The USBN's interrupt enable register. 1339215976Sjmallett */ 1340215976Sjmallettunion cvmx_usbnx_int_enb 1341215976Sjmallett{ 1342215976Sjmallett uint64_t u64; 1343215976Sjmallett struct cvmx_usbnx_int_enb_s 1344215976Sjmallett { 1345215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1346215976Sjmallett uint64_t reserved_38_63 : 26; 1347215976Sjmallett uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1348215976Sjmallett register is asserted the USBN will assert an 1349215976Sjmallett interrupt. */ 1350215976Sjmallett uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1351215976Sjmallett register is asserted the USBN will assert an 1352215976Sjmallett interrupt. */ 1353215976Sjmallett uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1354215976Sjmallett register is asserted the USBN will assert an 1355215976Sjmallett interrupt. */ 1356215976Sjmallett uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1357215976Sjmallett register is asserted the USBN will assert an 1358215976Sjmallett interrupt. */ 1359215976Sjmallett uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1360215976Sjmallett register is asserted the USBN will assert an 1361215976Sjmallett interrupt. */ 1362215976Sjmallett uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1363215976Sjmallett register is asserted the USBN will assert an 1364215976Sjmallett interrupt. */ 1365215976Sjmallett uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM 1366215976Sjmallett register is asserted the USBN will assert an 1367215976Sjmallett interrupt. */ 1368215976Sjmallett uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM 1369215976Sjmallett register is asserted the USBN will assert an 1370215976Sjmallett interrupt. */ 1371215976Sjmallett uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM 1372215976Sjmallett register is asserted the USBN will assert an 1373215976Sjmallett interrupt. */ 1374215976Sjmallett uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM 1375215976Sjmallett register is asserted the USBN will assert an 1376215976Sjmallett interrupt. */ 1377215976Sjmallett uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM 1378215976Sjmallett register is asserted the USBN will assert an 1379215976Sjmallett interrupt. */ 1380215976Sjmallett uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM 1381215976Sjmallett register is asserted the USBN will assert an 1382215976Sjmallett interrupt. */ 1383215976Sjmallett uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1384215976Sjmallett register is asserted the USBN will assert an 1385215976Sjmallett interrupt. */ 1386215976Sjmallett uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1387215976Sjmallett register is asserted the USBN will assert an 1388215976Sjmallett interrupt. */ 1389215976Sjmallett uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1390215976Sjmallett register is asserted the USBN will assert an 1391215976Sjmallett interrupt. */ 1392215976Sjmallett uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1393215976Sjmallett register is asserted the USBN will assert an 1394215976Sjmallett interrupt. */ 1395215976Sjmallett uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1396215976Sjmallett register is asserted the USBN will assert an 1397215976Sjmallett interrupt. */ 1398215976Sjmallett uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1399215976Sjmallett register is asserted the USBN will assert an 1400215976Sjmallett interrupt. */ 1401215976Sjmallett uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1402215976Sjmallett register is asserted the USBN will assert an 1403215976Sjmallett interrupt. */ 1404215976Sjmallett uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1405215976Sjmallett register is asserted the USBN will assert an 1406215976Sjmallett interrupt. */ 1407215976Sjmallett uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1408215976Sjmallett register is asserted the USBN will assert an 1409215976Sjmallett interrupt. */ 1410215976Sjmallett uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1411215976Sjmallett register is asserted the USBN will assert an 1412215976Sjmallett interrupt. */ 1413215976Sjmallett uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1414215976Sjmallett register is asserted the USBN will assert an 1415215976Sjmallett interrupt. */ 1416215976Sjmallett uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1417215976Sjmallett register is asserted the USBN will assert an 1418215976Sjmallett interrupt. */ 1419215976Sjmallett uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1420215976Sjmallett register is asserted the USBN will assert an 1421215976Sjmallett interrupt. */ 1422215976Sjmallett uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1423215976Sjmallett register is asserted the USBN will assert an 1424215976Sjmallett interrupt. */ 1425215976Sjmallett uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1426215976Sjmallett register is asserted the USBN will assert an 1427215976Sjmallett interrupt. */ 1428215976Sjmallett uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1429215976Sjmallett register is asserted the USBN will assert an 1430215976Sjmallett interrupt. */ 1431215976Sjmallett uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1432215976Sjmallett register is asserted the USBN will assert an 1433215976Sjmallett interrupt. */ 1434215976Sjmallett uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1435215976Sjmallett register is asserted the USBN will assert an 1436215976Sjmallett interrupt. */ 1437215976Sjmallett uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1438215976Sjmallett register is asserted the USBN will assert an 1439215976Sjmallett interrupt. */ 1440215976Sjmallett uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1441215976Sjmallett register is asserted the USBN will assert an 1442215976Sjmallett interrupt. */ 1443215976Sjmallett uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1444215976Sjmallett register is asserted the USBN will assert an 1445215976Sjmallett interrupt. */ 1446215976Sjmallett uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1447215976Sjmallett register is asserted the USBN will assert an 1448215976Sjmallett interrupt. */ 1449215976Sjmallett uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1450215976Sjmallett register is asserted the USBN will assert an 1451215976Sjmallett interrupt. */ 1452215976Sjmallett uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1453215976Sjmallett register is asserted the USBN will assert an 1454215976Sjmallett interrupt. */ 1455215976Sjmallett uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1456215976Sjmallett register is asserted the USBN will assert an 1457215976Sjmallett interrupt. */ 1458215976Sjmallett uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1459215976Sjmallett register is asserted the USBN will assert an 1460215976Sjmallett interrupt. */ 1461215976Sjmallett#else 1462215976Sjmallett uint64_t pr_po_e : 1; 1463215976Sjmallett uint64_t pr_pu_f : 1; 1464215976Sjmallett uint64_t nr_po_e : 1; 1465215976Sjmallett uint64_t nr_pu_f : 1; 1466215976Sjmallett uint64_t lr_po_e : 1; 1467215976Sjmallett uint64_t lr_pu_f : 1; 1468215976Sjmallett uint64_t pt_po_e : 1; 1469215976Sjmallett uint64_t pt_pu_f : 1; 1470215976Sjmallett uint64_t nt_po_e : 1; 1471215976Sjmallett uint64_t nt_pu_f : 1; 1472215976Sjmallett uint64_t lt_po_e : 1; 1473215976Sjmallett uint64_t lt_pu_f : 1; 1474215976Sjmallett uint64_t dcred_e : 1; 1475215976Sjmallett uint64_t dcred_f : 1; 1476215976Sjmallett uint64_t l2c_s_e : 1; 1477215976Sjmallett uint64_t l2c_a_f : 1; 1478215976Sjmallett uint64_t l2_fi_e : 1; 1479215976Sjmallett uint64_t l2_fi_f : 1; 1480215976Sjmallett uint64_t rg_fi_e : 1; 1481215976Sjmallett uint64_t rg_fi_f : 1; 1482215976Sjmallett uint64_t rq_q2_f : 1; 1483215976Sjmallett uint64_t rq_q2_e : 1; 1484215976Sjmallett uint64_t rq_q3_f : 1; 1485215976Sjmallett uint64_t rq_q3_e : 1; 1486215976Sjmallett uint64_t uod_pe : 1; 1487215976Sjmallett uint64_t uod_pf : 1; 1488215976Sjmallett uint64_t n2u_pf : 1; 1489215976Sjmallett uint64_t n2u_pe : 1; 1490215976Sjmallett uint64_t u2n_d_pe : 1; 1491215976Sjmallett uint64_t u2n_d_pf : 1; 1492215976Sjmallett uint64_t u2n_c_pf : 1; 1493215976Sjmallett uint64_t u2n_c_pe : 1; 1494215976Sjmallett uint64_t ltl_f_pe : 1; 1495215976Sjmallett uint64_t ltl_f_pf : 1; 1496215976Sjmallett uint64_t nd4o_rpe : 1; 1497215976Sjmallett uint64_t nd4o_rpf : 1; 1498215976Sjmallett uint64_t nd4o_dpe : 1; 1499215976Sjmallett uint64_t nd4o_dpf : 1; 1500215976Sjmallett uint64_t reserved_38_63 : 26; 1501215976Sjmallett#endif 1502215976Sjmallett } s; 1503215976Sjmallett struct cvmx_usbnx_int_enb_s cn30xx; 1504215976Sjmallett struct cvmx_usbnx_int_enb_s cn31xx; 1505215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx 1506215976Sjmallett { 1507215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1508215976Sjmallett uint64_t reserved_38_63 : 26; 1509215976Sjmallett uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1510215976Sjmallett register is asserted the USBN will assert an 1511215976Sjmallett interrupt. */ 1512215976Sjmallett uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1513215976Sjmallett register is asserted the USBN will assert an 1514215976Sjmallett interrupt. */ 1515215976Sjmallett uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1516215976Sjmallett register is asserted the USBN will assert an 1517215976Sjmallett interrupt. */ 1518215976Sjmallett uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1519215976Sjmallett register is asserted the USBN will assert an 1520215976Sjmallett interrupt. */ 1521215976Sjmallett uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1522215976Sjmallett register is asserted the USBN will assert an 1523215976Sjmallett interrupt. */ 1524215976Sjmallett uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1525215976Sjmallett register is asserted the USBN will assert an 1526215976Sjmallett interrupt. */ 1527215976Sjmallett uint64_t reserved_26_31 : 6; 1528215976Sjmallett uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1529215976Sjmallett register is asserted the USBN will assert an 1530215976Sjmallett interrupt. */ 1531215976Sjmallett uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1532215976Sjmallett register is asserted the USBN will assert an 1533215976Sjmallett interrupt. */ 1534215976Sjmallett uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1535215976Sjmallett register is asserted the USBN will assert an 1536215976Sjmallett interrupt. */ 1537215976Sjmallett uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1538215976Sjmallett register is asserted the USBN will assert an 1539215976Sjmallett interrupt. */ 1540215976Sjmallett uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1541215976Sjmallett register is asserted the USBN will assert an 1542215976Sjmallett interrupt. */ 1543215976Sjmallett uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1544215976Sjmallett register is asserted the USBN will assert an 1545215976Sjmallett interrupt. */ 1546215976Sjmallett uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1547215976Sjmallett register is asserted the USBN will assert an 1548215976Sjmallett interrupt. */ 1549215976Sjmallett uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1550215976Sjmallett register is asserted the USBN will assert an 1551215976Sjmallett interrupt. */ 1552215976Sjmallett uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1553215976Sjmallett register is asserted the USBN will assert an 1554215976Sjmallett interrupt. */ 1555215976Sjmallett uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1556215976Sjmallett register is asserted the USBN will assert an 1557215976Sjmallett interrupt. */ 1558215976Sjmallett uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1559215976Sjmallett register is asserted the USBN will assert an 1560215976Sjmallett interrupt. */ 1561215976Sjmallett uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1562215976Sjmallett register is asserted the USBN will assert an 1563215976Sjmallett interrupt. */ 1564215976Sjmallett uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1565215976Sjmallett register is asserted the USBN will assert an 1566215976Sjmallett interrupt. */ 1567215976Sjmallett uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1568215976Sjmallett register is asserted the USBN will assert an 1569215976Sjmallett interrupt. */ 1570215976Sjmallett uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1571215976Sjmallett register is asserted the USBN will assert an 1572215976Sjmallett interrupt. */ 1573215976Sjmallett uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1574215976Sjmallett register is asserted the USBN will assert an 1575215976Sjmallett interrupt. */ 1576215976Sjmallett uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1577215976Sjmallett register is asserted the USBN will assert an 1578215976Sjmallett interrupt. */ 1579215976Sjmallett uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1580215976Sjmallett register is asserted the USBN will assert an 1581215976Sjmallett interrupt. */ 1582215976Sjmallett uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1583215976Sjmallett register is asserted the USBN will assert an 1584215976Sjmallett interrupt. */ 1585215976Sjmallett uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1586215976Sjmallett register is asserted the USBN will assert an 1587215976Sjmallett interrupt. */ 1588215976Sjmallett uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1589215976Sjmallett register is asserted the USBN will assert an 1590215976Sjmallett interrupt. */ 1591215976Sjmallett uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1592215976Sjmallett register is asserted the USBN will assert an 1593215976Sjmallett interrupt. */ 1594215976Sjmallett uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1595215976Sjmallett register is asserted the USBN will assert an 1596215976Sjmallett interrupt. */ 1597215976Sjmallett uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1598215976Sjmallett register is asserted the USBN will assert an 1599215976Sjmallett interrupt. */ 1600215976Sjmallett uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1601215976Sjmallett register is asserted the USBN will assert an 1602215976Sjmallett interrupt. */ 1603215976Sjmallett uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1604215976Sjmallett register is asserted the USBN will assert an 1605215976Sjmallett interrupt. */ 1606215976Sjmallett#else 1607215976Sjmallett uint64_t pr_po_e : 1; 1608215976Sjmallett uint64_t pr_pu_f : 1; 1609215976Sjmallett uint64_t nr_po_e : 1; 1610215976Sjmallett uint64_t nr_pu_f : 1; 1611215976Sjmallett uint64_t lr_po_e : 1; 1612215976Sjmallett uint64_t lr_pu_f : 1; 1613215976Sjmallett uint64_t pt_po_e : 1; 1614215976Sjmallett uint64_t pt_pu_f : 1; 1615215976Sjmallett uint64_t nt_po_e : 1; 1616215976Sjmallett uint64_t nt_pu_f : 1; 1617215976Sjmallett uint64_t lt_po_e : 1; 1618215976Sjmallett uint64_t lt_pu_f : 1; 1619215976Sjmallett uint64_t dcred_e : 1; 1620215976Sjmallett uint64_t dcred_f : 1; 1621215976Sjmallett uint64_t l2c_s_e : 1; 1622215976Sjmallett uint64_t l2c_a_f : 1; 1623215976Sjmallett uint64_t l2_fi_e : 1; 1624215976Sjmallett uint64_t l2_fi_f : 1; 1625215976Sjmallett uint64_t rg_fi_e : 1; 1626215976Sjmallett uint64_t rg_fi_f : 1; 1627215976Sjmallett uint64_t rq_q2_f : 1; 1628215976Sjmallett uint64_t rq_q2_e : 1; 1629215976Sjmallett uint64_t rq_q3_f : 1; 1630215976Sjmallett uint64_t rq_q3_e : 1; 1631215976Sjmallett uint64_t uod_pe : 1; 1632215976Sjmallett uint64_t uod_pf : 1; 1633215976Sjmallett uint64_t reserved_26_31 : 6; 1634215976Sjmallett uint64_t ltl_f_pe : 1; 1635215976Sjmallett uint64_t ltl_f_pf : 1; 1636215976Sjmallett uint64_t nd4o_rpe : 1; 1637215976Sjmallett uint64_t nd4o_rpf : 1; 1638215976Sjmallett uint64_t nd4o_dpe : 1; 1639215976Sjmallett uint64_t nd4o_dpf : 1; 1640215976Sjmallett uint64_t reserved_38_63 : 26; 1641215976Sjmallett#endif 1642215976Sjmallett } cn50xx; 1643215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn52xx; 1644215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn52xxp1; 1645215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn56xx; 1646215976Sjmallett struct cvmx_usbnx_int_enb_cn50xx cn56xxp1; 1647215976Sjmallett}; 1648215976Sjmalletttypedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t; 1649215976Sjmallett 1650215976Sjmallett/** 1651215976Sjmallett * cvmx_usbn#_int_sum 1652215976Sjmallett * 1653215976Sjmallett * USBN_INT_SUM = USBN's Interrupt Summary Register 1654215976Sjmallett * 1655215976Sjmallett * Contains the diffrent interrupt summary bits of the USBN. 1656215976Sjmallett */ 1657215976Sjmallettunion cvmx_usbnx_int_sum 1658215976Sjmallett{ 1659215976Sjmallett uint64_t u64; 1660215976Sjmallett struct cvmx_usbnx_int_sum_s 1661215976Sjmallett { 1662215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1663215976Sjmallett uint64_t reserved_38_63 : 26; 1664215976Sjmallett uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1665215976Sjmallett uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1666215976Sjmallett uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1667215976Sjmallett uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1668215976Sjmallett uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1669215976Sjmallett uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1670215976Sjmallett uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */ 1671215976Sjmallett uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */ 1672215976Sjmallett uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */ 1673215976Sjmallett uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */ 1674215976Sjmallett uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */ 1675215976Sjmallett uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */ 1676215976Sjmallett uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1677215976Sjmallett uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1678215976Sjmallett uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1679215976Sjmallett uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1680215976Sjmallett uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1681215976Sjmallett uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1682215976Sjmallett uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1683215976Sjmallett uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1684215976Sjmallett uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1685215976Sjmallett uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1686215976Sjmallett uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1687215976Sjmallett uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1688215976Sjmallett uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1689215976Sjmallett uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1690215976Sjmallett uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1691215976Sjmallett uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1692215976Sjmallett uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1693215976Sjmallett uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1694215976Sjmallett uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1695215976Sjmallett uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1696215976Sjmallett uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1697215976Sjmallett uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1698215976Sjmallett uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1699215976Sjmallett uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1700215976Sjmallett uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1701215976Sjmallett uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1702215976Sjmallett#else 1703215976Sjmallett uint64_t pr_po_e : 1; 1704215976Sjmallett uint64_t pr_pu_f : 1; 1705215976Sjmallett uint64_t nr_po_e : 1; 1706215976Sjmallett uint64_t nr_pu_f : 1; 1707215976Sjmallett uint64_t lr_po_e : 1; 1708215976Sjmallett uint64_t lr_pu_f : 1; 1709215976Sjmallett uint64_t pt_po_e : 1; 1710215976Sjmallett uint64_t pt_pu_f : 1; 1711215976Sjmallett uint64_t nt_po_e : 1; 1712215976Sjmallett uint64_t nt_pu_f : 1; 1713215976Sjmallett uint64_t lt_po_e : 1; 1714215976Sjmallett uint64_t lt_pu_f : 1; 1715215976Sjmallett uint64_t dcred_e : 1; 1716215976Sjmallett uint64_t dcred_f : 1; 1717215976Sjmallett uint64_t l2c_s_e : 1; 1718215976Sjmallett uint64_t l2c_a_f : 1; 1719215976Sjmallett uint64_t lt_fi_e : 1; 1720215976Sjmallett uint64_t lt_fi_f : 1; 1721215976Sjmallett uint64_t rg_fi_e : 1; 1722215976Sjmallett uint64_t rg_fi_f : 1; 1723215976Sjmallett uint64_t rq_q2_f : 1; 1724215976Sjmallett uint64_t rq_q2_e : 1; 1725215976Sjmallett uint64_t rq_q3_f : 1; 1726215976Sjmallett uint64_t rq_q3_e : 1; 1727215976Sjmallett uint64_t uod_pe : 1; 1728215976Sjmallett uint64_t uod_pf : 1; 1729215976Sjmallett uint64_t n2u_pf : 1; 1730215976Sjmallett uint64_t n2u_pe : 1; 1731215976Sjmallett uint64_t u2n_d_pe : 1; 1732215976Sjmallett uint64_t u2n_d_pf : 1; 1733215976Sjmallett uint64_t u2n_c_pf : 1; 1734215976Sjmallett uint64_t u2n_c_pe : 1; 1735215976Sjmallett uint64_t ltl_f_pe : 1; 1736215976Sjmallett uint64_t ltl_f_pf : 1; 1737215976Sjmallett uint64_t nd4o_rpe : 1; 1738215976Sjmallett uint64_t nd4o_rpf : 1; 1739215976Sjmallett uint64_t nd4o_dpe : 1; 1740215976Sjmallett uint64_t nd4o_dpf : 1; 1741215976Sjmallett uint64_t reserved_38_63 : 26; 1742215976Sjmallett#endif 1743215976Sjmallett } s; 1744215976Sjmallett struct cvmx_usbnx_int_sum_s cn30xx; 1745215976Sjmallett struct cvmx_usbnx_int_sum_s cn31xx; 1746215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx 1747215976Sjmallett { 1748215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1749215976Sjmallett uint64_t reserved_38_63 : 26; 1750215976Sjmallett uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1751215976Sjmallett uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1752215976Sjmallett uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1753215976Sjmallett uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1754215976Sjmallett uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1755215976Sjmallett uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1756215976Sjmallett uint64_t reserved_26_31 : 6; 1757215976Sjmallett uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1758215976Sjmallett uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1759215976Sjmallett uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1760215976Sjmallett uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1761215976Sjmallett uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1762215976Sjmallett uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1763215976Sjmallett uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1764215976Sjmallett uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1765215976Sjmallett uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1766215976Sjmallett uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1767215976Sjmallett uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1768215976Sjmallett uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1769215976Sjmallett uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1770215976Sjmallett uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1771215976Sjmallett uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1772215976Sjmallett uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1773215976Sjmallett uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1774215976Sjmallett uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1775215976Sjmallett uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1776215976Sjmallett uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1777215976Sjmallett uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1778215976Sjmallett uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1779215976Sjmallett uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1780215976Sjmallett uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1781215976Sjmallett uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1782215976Sjmallett uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1783215976Sjmallett#else 1784215976Sjmallett uint64_t pr_po_e : 1; 1785215976Sjmallett uint64_t pr_pu_f : 1; 1786215976Sjmallett uint64_t nr_po_e : 1; 1787215976Sjmallett uint64_t nr_pu_f : 1; 1788215976Sjmallett uint64_t lr_po_e : 1; 1789215976Sjmallett uint64_t lr_pu_f : 1; 1790215976Sjmallett uint64_t pt_po_e : 1; 1791215976Sjmallett uint64_t pt_pu_f : 1; 1792215976Sjmallett uint64_t nt_po_e : 1; 1793215976Sjmallett uint64_t nt_pu_f : 1; 1794215976Sjmallett uint64_t lt_po_e : 1; 1795215976Sjmallett uint64_t lt_pu_f : 1; 1796215976Sjmallett uint64_t dcred_e : 1; 1797215976Sjmallett uint64_t dcred_f : 1; 1798215976Sjmallett uint64_t l2c_s_e : 1; 1799215976Sjmallett uint64_t l2c_a_f : 1; 1800215976Sjmallett uint64_t lt_fi_e : 1; 1801215976Sjmallett uint64_t lt_fi_f : 1; 1802215976Sjmallett uint64_t rg_fi_e : 1; 1803215976Sjmallett uint64_t rg_fi_f : 1; 1804215976Sjmallett uint64_t rq_q2_f : 1; 1805215976Sjmallett uint64_t rq_q2_e : 1; 1806215976Sjmallett uint64_t rq_q3_f : 1; 1807215976Sjmallett uint64_t rq_q3_e : 1; 1808215976Sjmallett uint64_t uod_pe : 1; 1809215976Sjmallett uint64_t uod_pf : 1; 1810215976Sjmallett uint64_t reserved_26_31 : 6; 1811215976Sjmallett uint64_t ltl_f_pe : 1; 1812215976Sjmallett uint64_t ltl_f_pf : 1; 1813215976Sjmallett uint64_t nd4o_rpe : 1; 1814215976Sjmallett uint64_t nd4o_rpf : 1; 1815215976Sjmallett uint64_t nd4o_dpe : 1; 1816215976Sjmallett uint64_t nd4o_dpf : 1; 1817215976Sjmallett uint64_t reserved_38_63 : 26; 1818215976Sjmallett#endif 1819215976Sjmallett } cn50xx; 1820215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn52xx; 1821215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn52xxp1; 1822215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn56xx; 1823215976Sjmallett struct cvmx_usbnx_int_sum_cn50xx cn56xxp1; 1824215976Sjmallett}; 1825215976Sjmalletttypedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t; 1826215976Sjmallett 1827215976Sjmallett/** 1828215976Sjmallett * cvmx_usbn#_usbp_ctl_status 1829215976Sjmallett * 1830215976Sjmallett * USBN_USBP_CTL_STATUS = USBP Control And Status Register 1831215976Sjmallett * 1832215976Sjmallett * Contains general control and status information for the USBN block. 1833215976Sjmallett */ 1834215976Sjmallettunion cvmx_usbnx_usbp_ctl_status 1835215976Sjmallett{ 1836215976Sjmallett uint64_t u64; 1837215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_s 1838215976Sjmallett { 1839215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1840215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 1841215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 1842215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 1843215976Sjmallett uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 1844215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 1845215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 1846215976Sjmallett uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 1847215976Sjmallett uint64_t otgdisable : 1; /**< OTG Block Disable */ 1848215976Sjmallett uint64_t portreset : 1; /**< Per_Port Reset */ 1849215976Sjmallett uint64_t drvvbus : 1; /**< Drive VBUS */ 1850215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 1851215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 1852215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 1853215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 1854215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 1855215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 1856215976Sjmallett Indicates an internal error was detected during 1857215976Sjmallett the BIST sequence. */ 1858215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 1859215976Sjmallett Presents either internaly generated signals or 1860215976Sjmallett test register contents, based upon the value of 1861215976Sjmallett test_data_out_sel. */ 1862215976Sjmallett uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 1863215976Sjmallett Normally should be set to zero. 1864215976Sjmallett When customers have no intent to use USB PHY 1865215976Sjmallett interface, they should: 1866215976Sjmallett - still provide 3.3V to USB_VDD33, and 1867215976Sjmallett - tie USB_REXT to 3.3V supply, and 1868215976Sjmallett - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 1869215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 1870215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 1871215976Sjmallett with byte-counts between packets. When set to 0 1872215976Sjmallett the L2C DMA address is incremented to the next 1873215976Sjmallett 4-byte aligned address after adding byte-count. */ 1874215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 1875215976Sjmallett set to '0' for operation. */ 1876215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 1877215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 1878215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 1879215976Sjmallett This signal enables the pull-down resistance on 1880215976Sjmallett the D+ line. '1' pull down-resistance is connected 1881215976Sjmallett to D+/ '0' pull down resistance is not connected 1882215976Sjmallett to D+. When an A/B device is acting as a host 1883215976Sjmallett (downstream-facing port), dp_pulldown and 1884215976Sjmallett dm_pulldown are enabled. This must not toggle 1885215976Sjmallett during normal opeartion. */ 1886215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 1887215976Sjmallett This signal enables the pull-down resistance on 1888215976Sjmallett the D- line. '1' pull down-resistance is connected 1889215976Sjmallett to D-. '0' pull down resistance is not connected 1890215976Sjmallett to D-. When an A/B device is acting as a host 1891215976Sjmallett (downstream-facing port), dp_pulldown and 1892215976Sjmallett dm_pulldown are enabled. This must not toggle 1893215976Sjmallett during normal opeartion. */ 1894215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 1895215976Sjmallett USB is acting as device. This field needs to be 1896215976Sjmallett set while the USB is in reset. */ 1897215976Sjmallett uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 1898215976Sjmallett Tunes the current supply and rise/fall output 1899215976Sjmallett times for high-speed operation. 1900215976Sjmallett [20:19] == 11: Current supply increased 1901215976Sjmallett approximately 9% 1902215976Sjmallett [20:19] == 10: Current supply increased 1903215976Sjmallett approximately 4.5% 1904215976Sjmallett [20:19] == 01: Design default. 1905215976Sjmallett [20:19] == 00: Current supply decreased 1906215976Sjmallett approximately 4.5% 1907215976Sjmallett [22:21] == 11: Rise and fall times are increased. 1908215976Sjmallett [22:21] == 10: Design default. 1909215976Sjmallett [22:21] == 01: Rise and fall times are decreased. 1910215976Sjmallett [22:21] == 00: Rise and fall times are decreased 1911215976Sjmallett further as compared to the 01 setting. */ 1912215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 1913215976Sjmallett Enables or disables bit stuffing on data[15:8] 1914215976Sjmallett when bit-stuffing is enabled. */ 1915215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 1916215976Sjmallett Enables or disables bit stuffing on data[7:0] 1917215976Sjmallett when bit-stuffing is enabled. */ 1918215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 1919215976Sjmallett '1': During data transmission the receive is 1920215976Sjmallett enabled. 1921215976Sjmallett '0': During data transmission the receive is 1922215976Sjmallett disabled. 1923215976Sjmallett Must be '0' for normal operation. */ 1924215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 1925215976Sjmallett '1' The PHY's analog_test pin is enabled for the 1926215976Sjmallett input and output of applicable analog test signals. 1927215976Sjmallett '0' THe analog_test pin is disabled. */ 1928215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 1929215976Sjmallett Used to activate BIST in the PHY. */ 1930215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 1931215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 1932215976Sjmallett are output. '0' internaly generated signals are 1933215976Sjmallett output. */ 1934215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 1935215976Sjmallett Specifies the register address for writing to or 1936215976Sjmallett reading from the PHY test interface register. */ 1937215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 1938215976Sjmallett This is a test bus. Data is present on [3:0], 1939215976Sjmallett and its corresponding select (enable) is present 1940215976Sjmallett on bits [7:4]. */ 1941215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 1942215976Sjmallett This is a test signal. When the USB Core is 1943215976Sjmallett powered up (not in Susned Mode), an automatic 1944215976Sjmallett tester can use this to disable phy_clock and 1945215976Sjmallett free_clk, then re-eanable them with an aligned 1946215976Sjmallett phase. 1947215976Sjmallett '1': The phy_clk and free_clk outputs are 1948215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 1949215976Sjmallett are available within a specific period after the 1950215976Sjmallett de-assertion. */ 1951215976Sjmallett#else 1952215976Sjmallett uint64_t ate_reset : 1; 1953215976Sjmallett uint64_t tdata_in : 8; 1954215976Sjmallett uint64_t taddr_in : 4; 1955215976Sjmallett uint64_t tdata_sel : 1; 1956215976Sjmallett uint64_t bist_enb : 1; 1957215976Sjmallett uint64_t vtest_enb : 1; 1958215976Sjmallett uint64_t loop_enb : 1; 1959215976Sjmallett uint64_t tx_bs_en : 1; 1960215976Sjmallett uint64_t tx_bs_enh : 1; 1961215976Sjmallett uint64_t tuning : 4; 1962215976Sjmallett uint64_t hst_mode : 1; 1963215976Sjmallett uint64_t dm_pulld : 1; 1964215976Sjmallett uint64_t dp_pulld : 1; 1965215976Sjmallett uint64_t tclk : 1; 1966215976Sjmallett uint64_t usbp_bist : 1; 1967215976Sjmallett uint64_t usbc_end : 1; 1968215976Sjmallett uint64_t dma_bmode : 1; 1969215976Sjmallett uint64_t txpreemphasistune : 1; 1970215976Sjmallett uint64_t siddq : 1; 1971215976Sjmallett uint64_t tdata_out : 4; 1972215976Sjmallett uint64_t bist_err : 1; 1973215976Sjmallett uint64_t bist_done : 1; 1974215976Sjmallett uint64_t hsbist : 1; 1975215976Sjmallett uint64_t fsbist : 1; 1976215976Sjmallett uint64_t lsbist : 1; 1977215976Sjmallett uint64_t drvvbus : 1; 1978215976Sjmallett uint64_t portreset : 1; 1979215976Sjmallett uint64_t otgdisable : 1; 1980215976Sjmallett uint64_t otgtune : 3; 1981215976Sjmallett uint64_t compdistune : 3; 1982215976Sjmallett uint64_t sqrxtune : 3; 1983215976Sjmallett uint64_t txhsxvtune : 2; 1984215976Sjmallett uint64_t txfslstune : 4; 1985215976Sjmallett uint64_t txvreftune : 4; 1986215976Sjmallett uint64_t txrisetune : 1; 1987215976Sjmallett#endif 1988215976Sjmallett } s; 1989215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn30xx 1990215976Sjmallett { 1991215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1992215976Sjmallett uint64_t reserved_38_63 : 26; 1993215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 1994215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 1995215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 1996215976Sjmallett Indicates an internal error was detected during 1997215976Sjmallett the BIST sequence. */ 1998215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 1999215976Sjmallett Presents either internaly generated signals or 2000215976Sjmallett test register contents, based upon the value of 2001215976Sjmallett test_data_out_sel. */ 2002215976Sjmallett uint64_t reserved_30_31 : 2; 2003215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2004215976Sjmallett with byte-counts between packets. When set to 0 2005215976Sjmallett the L2C DMA address is incremented to the next 2006215976Sjmallett 4-byte aligned address after adding byte-count. */ 2007215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2008215976Sjmallett set to '0' for operation. */ 2009215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2010215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2011215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2012215976Sjmallett This signal enables the pull-down resistance on 2013215976Sjmallett the D+ line. '1' pull down-resistance is connected 2014215976Sjmallett to D+/ '0' pull down resistance is not connected 2015215976Sjmallett to D+. When an A/B device is acting as a host 2016215976Sjmallett (downstream-facing port), dp_pulldown and 2017215976Sjmallett dm_pulldown are enabled. This must not toggle 2018215976Sjmallett during normal opeartion. */ 2019215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2020215976Sjmallett This signal enables the pull-down resistance on 2021215976Sjmallett the D- line. '1' pull down-resistance is connected 2022215976Sjmallett to D-. '0' pull down resistance is not connected 2023215976Sjmallett to D-. When an A/B device is acting as a host 2024215976Sjmallett (downstream-facing port), dp_pulldown and 2025215976Sjmallett dm_pulldown are enabled. This must not toggle 2026215976Sjmallett during normal opeartion. */ 2027215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2028215976Sjmallett USB is acting as device. This field needs to be 2029215976Sjmallett set while the USB is in reset. */ 2030215976Sjmallett uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 2031215976Sjmallett Tunes the current supply and rise/fall output 2032215976Sjmallett times for high-speed operation. 2033215976Sjmallett [20:19] == 11: Current supply increased 2034215976Sjmallett approximately 9% 2035215976Sjmallett [20:19] == 10: Current supply increased 2036215976Sjmallett approximately 4.5% 2037215976Sjmallett [20:19] == 01: Design default. 2038215976Sjmallett [20:19] == 00: Current supply decreased 2039215976Sjmallett approximately 4.5% 2040215976Sjmallett [22:21] == 11: Rise and fall times are increased. 2041215976Sjmallett [22:21] == 10: Design default. 2042215976Sjmallett [22:21] == 01: Rise and fall times are decreased. 2043215976Sjmallett [22:21] == 00: Rise and fall times are decreased 2044215976Sjmallett further as compared to the 01 setting. */ 2045215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2046215976Sjmallett Enables or disables bit stuffing on data[15:8] 2047215976Sjmallett when bit-stuffing is enabled. */ 2048215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2049215976Sjmallett Enables or disables bit stuffing on data[7:0] 2050215976Sjmallett when bit-stuffing is enabled. */ 2051215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2052215976Sjmallett '1': During data transmission the receive is 2053215976Sjmallett enabled. 2054215976Sjmallett '0': During data transmission the receive is 2055215976Sjmallett disabled. 2056215976Sjmallett Must be '0' for normal operation. */ 2057215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2058215976Sjmallett '1' The PHY's analog_test pin is enabled for the 2059215976Sjmallett input and output of applicable analog test signals. 2060215976Sjmallett '0' THe analog_test pin is disabled. */ 2061215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2062215976Sjmallett Used to activate BIST in the PHY. */ 2063215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 2064215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 2065215976Sjmallett are output. '0' internaly generated signals are 2066215976Sjmallett output. */ 2067215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2068215976Sjmallett Specifies the register address for writing to or 2069215976Sjmallett reading from the PHY test interface register. */ 2070215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2071215976Sjmallett This is a test bus. Data is present on [3:0], 2072215976Sjmallett and its corresponding select (enable) is present 2073215976Sjmallett on bits [7:4]. */ 2074215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2075215976Sjmallett This is a test signal. When the USB Core is 2076215976Sjmallett powered up (not in Susned Mode), an automatic 2077215976Sjmallett tester can use this to disable phy_clock and 2078215976Sjmallett free_clk, then re-eanable them with an aligned 2079215976Sjmallett phase. 2080215976Sjmallett '1': The phy_clk and free_clk outputs are 2081215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 2082215976Sjmallett are available within a specific period after the 2083215976Sjmallett de-assertion. */ 2084215976Sjmallett#else 2085215976Sjmallett uint64_t ate_reset : 1; 2086215976Sjmallett uint64_t tdata_in : 8; 2087215976Sjmallett uint64_t taddr_in : 4; 2088215976Sjmallett uint64_t tdata_sel : 1; 2089215976Sjmallett uint64_t bist_enb : 1; 2090215976Sjmallett uint64_t vtest_enb : 1; 2091215976Sjmallett uint64_t loop_enb : 1; 2092215976Sjmallett uint64_t tx_bs_en : 1; 2093215976Sjmallett uint64_t tx_bs_enh : 1; 2094215976Sjmallett uint64_t tuning : 4; 2095215976Sjmallett uint64_t hst_mode : 1; 2096215976Sjmallett uint64_t dm_pulld : 1; 2097215976Sjmallett uint64_t dp_pulld : 1; 2098215976Sjmallett uint64_t tclk : 1; 2099215976Sjmallett uint64_t usbp_bist : 1; 2100215976Sjmallett uint64_t usbc_end : 1; 2101215976Sjmallett uint64_t dma_bmode : 1; 2102215976Sjmallett uint64_t reserved_30_31 : 2; 2103215976Sjmallett uint64_t tdata_out : 4; 2104215976Sjmallett uint64_t bist_err : 1; 2105215976Sjmallett uint64_t bist_done : 1; 2106215976Sjmallett uint64_t reserved_38_63 : 26; 2107215976Sjmallett#endif 2108215976Sjmallett } cn30xx; 2109215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx; 2110215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn50xx 2111215976Sjmallett { 2112215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2113215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2114215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2115215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2116215976Sjmallett uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2117215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2118215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2119215976Sjmallett uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2120215976Sjmallett uint64_t otgdisable : 1; /**< OTG Block Disable */ 2121215976Sjmallett uint64_t portreset : 1; /**< Per_Port Reset */ 2122215976Sjmallett uint64_t drvvbus : 1; /**< Drive VBUS */ 2123215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2124215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2125215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2126215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 2127215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 2128215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 2129215976Sjmallett Indicates an internal error was detected during 2130215976Sjmallett the BIST sequence. */ 2131215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 2132215976Sjmallett Presents either internaly generated signals or 2133215976Sjmallett test register contents, based upon the value of 2134215976Sjmallett test_data_out_sel. */ 2135215976Sjmallett uint64_t reserved_31_31 : 1; 2136215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2137215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2138215976Sjmallett with byte-counts between packets. When set to 0 2139215976Sjmallett the L2C DMA address is incremented to the next 2140215976Sjmallett 4-byte aligned address after adding byte-count. */ 2141215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2142215976Sjmallett set to '0' for operation. */ 2143215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2144215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2145215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2146215976Sjmallett This signal enables the pull-down resistance on 2147215976Sjmallett the D+ line. '1' pull down-resistance is connected 2148215976Sjmallett to D+/ '0' pull down resistance is not connected 2149215976Sjmallett to D+. When an A/B device is acting as a host 2150215976Sjmallett (downstream-facing port), dp_pulldown and 2151215976Sjmallett dm_pulldown are enabled. This must not toggle 2152215976Sjmallett during normal opeartion. */ 2153215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2154215976Sjmallett This signal enables the pull-down resistance on 2155215976Sjmallett the D- line. '1' pull down-resistance is connected 2156215976Sjmallett to D-. '0' pull down resistance is not connected 2157215976Sjmallett to D-. When an A/B device is acting as a host 2158215976Sjmallett (downstream-facing port), dp_pulldown and 2159215976Sjmallett dm_pulldown are enabled. This must not toggle 2160215976Sjmallett during normal opeartion. */ 2161215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2162215976Sjmallett USB is acting as device. This field needs to be 2163215976Sjmallett set while the USB is in reset. */ 2164215976Sjmallett uint64_t reserved_19_22 : 4; 2165215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2166215976Sjmallett Enables or disables bit stuffing on data[15:8] 2167215976Sjmallett when bit-stuffing is enabled. */ 2168215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2169215976Sjmallett Enables or disables bit stuffing on data[7:0] 2170215976Sjmallett when bit-stuffing is enabled. */ 2171215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2172215976Sjmallett '1': During data transmission the receive is 2173215976Sjmallett enabled. 2174215976Sjmallett '0': During data transmission the receive is 2175215976Sjmallett disabled. 2176215976Sjmallett Must be '0' for normal operation. */ 2177215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2178215976Sjmallett '1' The PHY's analog_test pin is enabled for the 2179215976Sjmallett input and output of applicable analog test signals. 2180215976Sjmallett '0' THe analog_test pin is disabled. */ 2181215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2182215976Sjmallett Used to activate BIST in the PHY. */ 2183215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 2184215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 2185215976Sjmallett are output. '0' internaly generated signals are 2186215976Sjmallett output. */ 2187215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2188215976Sjmallett Specifies the register address for writing to or 2189215976Sjmallett reading from the PHY test interface register. */ 2190215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2191215976Sjmallett This is a test bus. Data is present on [3:0], 2192215976Sjmallett and its corresponding select (enable) is present 2193215976Sjmallett on bits [7:4]. */ 2194215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2195215976Sjmallett This is a test signal. When the USB Core is 2196215976Sjmallett powered up (not in Susned Mode), an automatic 2197215976Sjmallett tester can use this to disable phy_clock and 2198215976Sjmallett free_clk, then re-eanable them with an aligned 2199215976Sjmallett phase. 2200215976Sjmallett '1': The phy_clk and free_clk outputs are 2201215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 2202215976Sjmallett are available within a specific period after the 2203215976Sjmallett de-assertion. */ 2204215976Sjmallett#else 2205215976Sjmallett uint64_t ate_reset : 1; 2206215976Sjmallett uint64_t tdata_in : 8; 2207215976Sjmallett uint64_t taddr_in : 4; 2208215976Sjmallett uint64_t tdata_sel : 1; 2209215976Sjmallett uint64_t bist_enb : 1; 2210215976Sjmallett uint64_t vtest_enb : 1; 2211215976Sjmallett uint64_t loop_enb : 1; 2212215976Sjmallett uint64_t tx_bs_en : 1; 2213215976Sjmallett uint64_t tx_bs_enh : 1; 2214215976Sjmallett uint64_t reserved_19_22 : 4; 2215215976Sjmallett uint64_t hst_mode : 1; 2216215976Sjmallett uint64_t dm_pulld : 1; 2217215976Sjmallett uint64_t dp_pulld : 1; 2218215976Sjmallett uint64_t tclk : 1; 2219215976Sjmallett uint64_t usbp_bist : 1; 2220215976Sjmallett uint64_t usbc_end : 1; 2221215976Sjmallett uint64_t dma_bmode : 1; 2222215976Sjmallett uint64_t txpreemphasistune : 1; 2223215976Sjmallett uint64_t reserved_31_31 : 1; 2224215976Sjmallett uint64_t tdata_out : 4; 2225215976Sjmallett uint64_t bist_err : 1; 2226215976Sjmallett uint64_t bist_done : 1; 2227215976Sjmallett uint64_t hsbist : 1; 2228215976Sjmallett uint64_t fsbist : 1; 2229215976Sjmallett uint64_t lsbist : 1; 2230215976Sjmallett uint64_t drvvbus : 1; 2231215976Sjmallett uint64_t portreset : 1; 2232215976Sjmallett uint64_t otgdisable : 1; 2233215976Sjmallett uint64_t otgtune : 3; 2234215976Sjmallett uint64_t compdistune : 3; 2235215976Sjmallett uint64_t sqrxtune : 3; 2236215976Sjmallett uint64_t txhsxvtune : 2; 2237215976Sjmallett uint64_t txfslstune : 4; 2238215976Sjmallett uint64_t txvreftune : 4; 2239215976Sjmallett uint64_t txrisetune : 1; 2240215976Sjmallett#endif 2241215976Sjmallett } cn50xx; 2242215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn52xx 2243215976Sjmallett { 2244215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2245215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2246215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2247215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2248215976Sjmallett uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2249215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2250215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2251215976Sjmallett uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2252215976Sjmallett uint64_t otgdisable : 1; /**< OTG Block Disable */ 2253215976Sjmallett uint64_t portreset : 1; /**< Per_Port Reset */ 2254215976Sjmallett uint64_t drvvbus : 1; /**< Drive VBUS */ 2255215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2256215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2257215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2258215976Sjmallett uint64_t bist_done : 1; /**< PHY Bist Done. 2259215976Sjmallett Asserted at the end of the PHY BIST sequence. */ 2260215976Sjmallett uint64_t bist_err : 1; /**< PHY Bist Error. 2261215976Sjmallett Indicates an internal error was detected during 2262215976Sjmallett the BIST sequence. */ 2263215976Sjmallett uint64_t tdata_out : 4; /**< PHY Test Data Out. 2264215976Sjmallett Presents either internaly generated signals or 2265215976Sjmallett test register contents, based upon the value of 2266215976Sjmallett test_data_out_sel. */ 2267215976Sjmallett uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 2268215976Sjmallett Normally should be set to zero. 2269215976Sjmallett When customers have no intent to use USB PHY 2270215976Sjmallett interface, they should: 2271215976Sjmallett - still provide 3.3V to USB_VDD33, and 2272215976Sjmallett - tie USB_REXT to 3.3V supply, and 2273215976Sjmallett - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 2274215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2275215976Sjmallett uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2276215976Sjmallett with byte-counts between packets. When set to 0 2277215976Sjmallett the L2C DMA address is incremented to the next 2278215976Sjmallett 4-byte aligned address after adding byte-count. */ 2279215976Sjmallett uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2280215976Sjmallett set to '0' for operation. */ 2281215976Sjmallett uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2282215976Sjmallett uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2283215976Sjmallett uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2284215976Sjmallett This signal enables the pull-down resistance on 2285215976Sjmallett the D+ line. '1' pull down-resistance is connected 2286215976Sjmallett to D+/ '0' pull down resistance is not connected 2287215976Sjmallett to D+. When an A/B device is acting as a host 2288215976Sjmallett (downstream-facing port), dp_pulldown and 2289215976Sjmallett dm_pulldown are enabled. This must not toggle 2290215976Sjmallett during normal opeartion. */ 2291215976Sjmallett uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2292215976Sjmallett This signal enables the pull-down resistance on 2293215976Sjmallett the D- line. '1' pull down-resistance is connected 2294215976Sjmallett to D-. '0' pull down resistance is not connected 2295215976Sjmallett to D-. When an A/B device is acting as a host 2296215976Sjmallett (downstream-facing port), dp_pulldown and 2297215976Sjmallett dm_pulldown are enabled. This must not toggle 2298215976Sjmallett during normal opeartion. */ 2299215976Sjmallett uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2300215976Sjmallett USB is acting as device. This field needs to be 2301215976Sjmallett set while the USB is in reset. */ 2302215976Sjmallett uint64_t reserved_19_22 : 4; 2303215976Sjmallett uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2304215976Sjmallett Enables or disables bit stuffing on data[15:8] 2305215976Sjmallett when bit-stuffing is enabled. */ 2306215976Sjmallett uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2307215976Sjmallett Enables or disables bit stuffing on data[7:0] 2308215976Sjmallett when bit-stuffing is enabled. */ 2309215976Sjmallett uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2310215976Sjmallett '1': During data transmission the receive is 2311215976Sjmallett enabled. 2312215976Sjmallett '0': During data transmission the receive is 2313215976Sjmallett disabled. 2314215976Sjmallett Must be '0' for normal operation. */ 2315215976Sjmallett uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2316215976Sjmallett '1' The PHY's analog_test pin is enabled for the 2317215976Sjmallett input and output of applicable analog test signals. 2318215976Sjmallett '0' THe analog_test pin is disabled. */ 2319215976Sjmallett uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2320215976Sjmallett Used to activate BIST in the PHY. */ 2321215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data Out Select. 2322215976Sjmallett '1' test_data_out[3:0] (PHY) register contents 2323215976Sjmallett are output. '0' internaly generated signals are 2324215976Sjmallett output. */ 2325215976Sjmallett uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2326215976Sjmallett Specifies the register address for writing to or 2327215976Sjmallett reading from the PHY test interface register. */ 2328215976Sjmallett uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2329215976Sjmallett This is a test bus. Data is present on [3:0], 2330215976Sjmallett and its corresponding select (enable) is present 2331215976Sjmallett on bits [7:4]. */ 2332215976Sjmallett uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2333215976Sjmallett This is a test signal. When the USB Core is 2334215976Sjmallett powered up (not in Susned Mode), an automatic 2335215976Sjmallett tester can use this to disable phy_clock and 2336215976Sjmallett free_clk, then re-eanable them with an aligned 2337215976Sjmallett phase. 2338215976Sjmallett '1': The phy_clk and free_clk outputs are 2339215976Sjmallett disabled. "0": The phy_clock and free_clk outputs 2340215976Sjmallett are available within a specific period after the 2341215976Sjmallett de-assertion. */ 2342215976Sjmallett#else 2343215976Sjmallett uint64_t ate_reset : 1; 2344215976Sjmallett uint64_t tdata_in : 8; 2345215976Sjmallett uint64_t taddr_in : 4; 2346215976Sjmallett uint64_t tdata_sel : 1; 2347215976Sjmallett uint64_t bist_enb : 1; 2348215976Sjmallett uint64_t vtest_enb : 1; 2349215976Sjmallett uint64_t loop_enb : 1; 2350215976Sjmallett uint64_t tx_bs_en : 1; 2351215976Sjmallett uint64_t tx_bs_enh : 1; 2352215976Sjmallett uint64_t reserved_19_22 : 4; 2353215976Sjmallett uint64_t hst_mode : 1; 2354215976Sjmallett uint64_t dm_pulld : 1; 2355215976Sjmallett uint64_t dp_pulld : 1; 2356215976Sjmallett uint64_t tclk : 1; 2357215976Sjmallett uint64_t usbp_bist : 1; 2358215976Sjmallett uint64_t usbc_end : 1; 2359215976Sjmallett uint64_t dma_bmode : 1; 2360215976Sjmallett uint64_t txpreemphasistune : 1; 2361215976Sjmallett uint64_t siddq : 1; 2362215976Sjmallett uint64_t tdata_out : 4; 2363215976Sjmallett uint64_t bist_err : 1; 2364215976Sjmallett uint64_t bist_done : 1; 2365215976Sjmallett uint64_t hsbist : 1; 2366215976Sjmallett uint64_t fsbist : 1; 2367215976Sjmallett uint64_t lsbist : 1; 2368215976Sjmallett uint64_t drvvbus : 1; 2369215976Sjmallett uint64_t portreset : 1; 2370215976Sjmallett uint64_t otgdisable : 1; 2371215976Sjmallett uint64_t otgtune : 3; 2372215976Sjmallett uint64_t compdistune : 3; 2373215976Sjmallett uint64_t sqrxtune : 3; 2374215976Sjmallett uint64_t txhsxvtune : 2; 2375215976Sjmallett uint64_t txfslstune : 4; 2376215976Sjmallett uint64_t txvreftune : 4; 2377215976Sjmallett uint64_t txrisetune : 1; 2378215976Sjmallett#endif 2379215976Sjmallett } cn52xx; 2380215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1; 2381215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx; 2382215976Sjmallett struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1; 2383215976Sjmallett}; 2384215976Sjmalletttypedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t; 2385215976Sjmallett 2386215976Sjmallett#endif 2387