1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-usbcx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon usbcx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_USBCX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_USBCX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 64215976Sjmallett cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id) 72215976Sjmallett{ 73215976Sjmallett if (!( 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79215976Sjmallett cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull; 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id) 87215976Sjmallett{ 88215976Sjmallett if (!( 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 91215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 94215976Sjmallett cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull; 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id) 102215976Sjmallett{ 103215976Sjmallett if (!( 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109215976Sjmallett cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 121215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 122215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 123215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 124215976Sjmallett cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallettstatic inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id) 132215976Sjmallett{ 133215976Sjmallett if (!( 134215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 139215976Sjmallett cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallettstatic inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id) 147215976Sjmallett{ 148215976Sjmallett if (!( 149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154215976Sjmallett cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull; 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull) 159215976Sjmallett#endif 160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161215976Sjmallettstatic inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id) 162215976Sjmallett{ 163215976Sjmallett if (!( 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 166215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 169215976Sjmallett cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 183215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 184215976Sjmallett cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id) 192215976Sjmallett{ 193215976Sjmallett if (!( 194215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 196215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 197215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 198215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 199215976Sjmallett cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 200215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 201215976Sjmallett} 202215976Sjmallett#else 203215976Sjmallett#define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 204215976Sjmallett#endif 205215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206215976Sjmallettstatic inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id) 207215976Sjmallett{ 208215976Sjmallett if (!( 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214215976Sjmallett cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 226215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 229215976Sjmallett cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 241215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1)))) || 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))))) 244215976Sjmallett cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 245215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4; 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4) 249215976Sjmallett#endif 250215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251215976Sjmallettstatic inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id) 252215976Sjmallett{ 253215976Sjmallett if (!( 254215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259215976Sjmallett cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id); 260215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull; 261215976Sjmallett} 262215976Sjmallett#else 263215976Sjmallett#define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull) 264215976Sjmallett#endif 265215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266215976Sjmallettstatic inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id) 267215976Sjmallett{ 268215976Sjmallett if (!( 269215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274215976Sjmallett cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id); 275215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull; 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull) 279215976Sjmallett#endif 280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281215976Sjmallettstatic inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id) 282215976Sjmallett{ 283215976Sjmallett if (!( 284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289215976Sjmallett cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id); 290215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull; 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id) 297215976Sjmallett{ 298215976Sjmallett if (!( 299215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304215976Sjmallett cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id); 305215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull; 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id) 312215976Sjmallett{ 313215976Sjmallett if (!( 314215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 315215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 316215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 317215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 318215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 319215976Sjmallett cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id); 320215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull; 321215976Sjmallett} 322215976Sjmallett#else 323215976Sjmallett#define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull) 324215976Sjmallett#endif 325215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326215976Sjmallettstatic inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id) 327215976Sjmallett{ 328215976Sjmallett if (!( 329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 334215976Sjmallett cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull; 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallettstatic inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id) 342215976Sjmallett{ 343215976Sjmallett if (!( 344215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 349215976Sjmallett cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id); 350215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull; 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id) 357215976Sjmallett{ 358215976Sjmallett if (!( 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364215976Sjmallett cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull; 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallettstatic inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id) 372215976Sjmallett{ 373215976Sjmallett if (!( 374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 377215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379215976Sjmallett cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id) 387215976Sjmallett{ 388215976Sjmallett if (!( 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 390215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 391215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 392215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 393215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 394215976Sjmallett cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id); 395215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull; 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull) 399215976Sjmallett#endif 400215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401215976Sjmallettstatic inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id) 402215976Sjmallett{ 403215976Sjmallett if (!( 404215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 405215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 406215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 407215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 408215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 409215976Sjmallett cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id); 410215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull; 411215976Sjmallett} 412215976Sjmallett#else 413215976Sjmallett#define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull) 414215976Sjmallett#endif 415215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 416215976Sjmallettstatic inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id) 417215976Sjmallett{ 418215976Sjmallett if (!( 419215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 420215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 421215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 422215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 423215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 424215976Sjmallett cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id); 425215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull; 426215976Sjmallett} 427215976Sjmallett#else 428215976Sjmallett#define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull) 429215976Sjmallett#endif 430215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 431215976Sjmallettstatic inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id) 432215976Sjmallett{ 433215976Sjmallett if (!( 434215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 435215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 436215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 437215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 438215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 439215976Sjmallett cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id); 440215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull; 441215976Sjmallett} 442215976Sjmallett#else 443215976Sjmallett#define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull) 444215976Sjmallett#endif 445215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446215976Sjmallettstatic inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id) 447215976Sjmallett{ 448215976Sjmallett if (!( 449215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 450215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 451215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 452215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 453215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 454215976Sjmallett cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id); 455215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull; 456215976Sjmallett} 457215976Sjmallett#else 458215976Sjmallett#define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull) 459215976Sjmallett#endif 460215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 461215976Sjmallettstatic inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id) 462215976Sjmallett{ 463215976Sjmallett if (!( 464215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 465215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 466215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 467215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 468215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 469215976Sjmallett cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id); 470215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull; 471215976Sjmallett} 472215976Sjmallett#else 473215976Sjmallett#define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull) 474215976Sjmallett#endif 475215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476215976Sjmallettstatic inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id) 477215976Sjmallett{ 478215976Sjmallett if (!( 479215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 480215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 481215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 482215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 483215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 484215976Sjmallett cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id); 485215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull; 486215976Sjmallett} 487215976Sjmallett#else 488215976Sjmallett#define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull) 489215976Sjmallett#endif 490215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 491215976Sjmallettstatic inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id) 492215976Sjmallett{ 493215976Sjmallett if (!( 494215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 495215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 496215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 497215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 498215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 499215976Sjmallett cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id); 500215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull; 501215976Sjmallett} 502215976Sjmallett#else 503215976Sjmallett#define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull) 504215976Sjmallett#endif 505215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 506215976Sjmallettstatic inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id) 507215976Sjmallett{ 508215976Sjmallett if (!( 509215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 510215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 511215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 512215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 513215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 514215976Sjmallett cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id); 515215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull; 516215976Sjmallett} 517215976Sjmallett#else 518215976Sjmallett#define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull) 519215976Sjmallett#endif 520215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521215976Sjmallettstatic inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id) 522215976Sjmallett{ 523215976Sjmallett if (!( 524215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 525215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 526215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 527215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 528215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 529215976Sjmallett cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id); 530215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull; 531215976Sjmallett} 532215976Sjmallett#else 533215976Sjmallett#define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull) 534215976Sjmallett#endif 535215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536215976Sjmallettstatic inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id) 537215976Sjmallett{ 538215976Sjmallett if (!( 539215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 540215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 541215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 542215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 543215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 544215976Sjmallett cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id); 545215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull; 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallettstatic inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id) 552215976Sjmallett{ 553215976Sjmallett if (!( 554215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 555215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 556215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 557215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 558215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 559215976Sjmallett cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id); 560215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull; 561215976Sjmallett} 562215976Sjmallett#else 563215976Sjmallett#define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull) 564215976Sjmallett#endif 565215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566215976Sjmallettstatic inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id) 567215976Sjmallett{ 568215976Sjmallett if (!( 569215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 570215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 571215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 572215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 573215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 574215976Sjmallett cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id); 575215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull; 576215976Sjmallett} 577215976Sjmallett#else 578215976Sjmallett#define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull) 579215976Sjmallett#endif 580215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 581215976Sjmallettstatic inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id) 582215976Sjmallett{ 583215976Sjmallett if (!( 584215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 585215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 586215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 587215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 588215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 589215976Sjmallett cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id); 590215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull; 591215976Sjmallett} 592215976Sjmallett#else 593215976Sjmallett#define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull) 594215976Sjmallett#endif 595215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 596215976Sjmallettstatic inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id) 597215976Sjmallett{ 598215976Sjmallett if (!( 599215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 600215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 601215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 602215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 603215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 604215976Sjmallett cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id); 605215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull; 606215976Sjmallett} 607215976Sjmallett#else 608215976Sjmallett#define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull) 609215976Sjmallett#endif 610215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 611215976Sjmallettstatic inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id) 612215976Sjmallett{ 613215976Sjmallett if (!( 614215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 615215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 616215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 617215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 618215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 619215976Sjmallett cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id); 620215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull; 621215976Sjmallett} 622215976Sjmallett#else 623215976Sjmallett#define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull) 624215976Sjmallett#endif 625215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 626215976Sjmallettstatic inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id) 627215976Sjmallett{ 628215976Sjmallett if (!( 629215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 630215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 631215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 632215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 633215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 634215976Sjmallett cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id); 635215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull; 636215976Sjmallett} 637215976Sjmallett#else 638215976Sjmallett#define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull) 639215976Sjmallett#endif 640215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641215976Sjmallettstatic inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id) 642215976Sjmallett{ 643215976Sjmallett if (!( 644215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 645215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 646215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 647215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 648215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 649215976Sjmallett cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id); 650215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 651215976Sjmallett} 652215976Sjmallett#else 653215976Sjmallett#define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 654215976Sjmallett#endif 655215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 656215976Sjmallettstatic inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id) 657215976Sjmallett{ 658215976Sjmallett if (!( 659215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 660215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 661215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 662215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 663215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 664215976Sjmallett cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id); 665215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull; 666215976Sjmallett} 667215976Sjmallett#else 668215976Sjmallett#define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull) 669215976Sjmallett#endif 670215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 671215976Sjmallettstatic inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id) 672215976Sjmallett{ 673215976Sjmallett if (!( 674215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 675215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 676215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 677215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 678215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 679215976Sjmallett cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id); 680215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 681215976Sjmallett} 682215976Sjmallett#else 683215976Sjmallett#define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 684215976Sjmallett#endif 685215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 686215976Sjmallettstatic inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id) 687215976Sjmallett{ 688215976Sjmallett if (!( 689215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 690215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 691215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 692215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 693215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 694215976Sjmallett cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 695215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 696215976Sjmallett} 697215976Sjmallett#else 698215976Sjmallett#define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 699215976Sjmallett#endif 700215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 701215976Sjmallettstatic inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id) 702215976Sjmallett{ 703215976Sjmallett if (!( 704215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 705215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 706215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 707215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 708215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 709215976Sjmallett cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 710215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 711215976Sjmallett} 712215976Sjmallett#else 713215976Sjmallett#define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 714215976Sjmallett#endif 715215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716215976Sjmallettstatic inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id) 717215976Sjmallett{ 718215976Sjmallett if (!( 719215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 720215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 721215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 722215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 723215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 724215976Sjmallett cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 725215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 726215976Sjmallett} 727215976Sjmallett#else 728215976Sjmallett#define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 729215976Sjmallett#endif 730215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731215976Sjmallettstatic inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id) 732215976Sjmallett{ 733215976Sjmallett if (!( 734215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 735215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 736215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 737215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 738215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 739215976Sjmallett cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id); 740215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull; 741215976Sjmallett} 742215976Sjmallett#else 743215976Sjmallett#define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull) 744215976Sjmallett#endif 745215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 746215976Sjmallettstatic inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id) 747215976Sjmallett{ 748215976Sjmallett if (!( 749215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 750215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 751215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 752215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 753215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 754215976Sjmallett cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id); 755215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull; 756215976Sjmallett} 757215976Sjmallett#else 758215976Sjmallett#define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull) 759215976Sjmallett#endif 760215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 761215976Sjmallettstatic inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id) 762215976Sjmallett{ 763215976Sjmallett if (!( 764215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 765215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 766215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 767215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 768215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 769215976Sjmallett cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id); 770215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull; 771215976Sjmallett} 772215976Sjmallett#else 773215976Sjmallett#define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull) 774215976Sjmallett#endif 775215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776215976Sjmallettstatic inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id) 777215976Sjmallett{ 778215976Sjmallett if (!( 779215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 780215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 781215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 782215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 783215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 784215976Sjmallett cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id); 785215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull; 786215976Sjmallett} 787215976Sjmallett#else 788215976Sjmallett#define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull) 789215976Sjmallett#endif 790215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 791215976Sjmallettstatic inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id) 792215976Sjmallett{ 793215976Sjmallett if (!( 794215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 795215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 796215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 797215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 798215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 799215976Sjmallett cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id); 800215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull; 801215976Sjmallett} 802215976Sjmallett#else 803215976Sjmallett#define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull) 804215976Sjmallett#endif 805215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 806215976Sjmallettstatic inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id) 807215976Sjmallett{ 808215976Sjmallett if (!( 809215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 810215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 811215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 812215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 813215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 814215976Sjmallett cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id); 815215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096; 816215976Sjmallett} 817215976Sjmallett#else 818215976Sjmallett#define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096) 819215976Sjmallett#endif 820215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821215976Sjmallettstatic inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id) 822215976Sjmallett{ 823215976Sjmallett if (!( 824215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 825215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 826215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 827215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 828215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 829215976Sjmallett cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id); 830215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull; 831215976Sjmallett} 832215976Sjmallett#else 833215976Sjmallett#define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull) 834215976Sjmallett#endif 835215976Sjmallett 836215976Sjmallett/** 837215976Sjmallett * cvmx_usbc#_daint 838215976Sjmallett * 839215976Sjmallett * Device All Endpoints Interrupt Register (DAINT) 840215976Sjmallett * 841215976Sjmallett * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register 842215976Sjmallett * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints 843215976Sjmallett * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). 844215976Sjmallett * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 845215976Sjmallett * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt 846215976Sjmallett * bits are used. Bits in this register are set and cleared when the application sets and clears 847215976Sjmallett * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn). 848215976Sjmallett */ 849215976Sjmallettunion cvmx_usbcx_daint 850215976Sjmallett{ 851215976Sjmallett uint32_t u32; 852215976Sjmallett struct cvmx_usbcx_daint_s 853215976Sjmallett { 854215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 855215976Sjmallett uint32_t outepint : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt) 856215976Sjmallett One bit per OUT endpoint: 857215976Sjmallett Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */ 858215976Sjmallett uint32_t inepint : 16; /**< IN Endpoint Interrupt Bits (InEpInt) 859215976Sjmallett One bit per IN Endpoint: 860215976Sjmallett Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */ 861215976Sjmallett#else 862215976Sjmallett uint32_t inepint : 16; 863215976Sjmallett uint32_t outepint : 16; 864215976Sjmallett#endif 865215976Sjmallett } s; 866215976Sjmallett struct cvmx_usbcx_daint_s cn30xx; 867215976Sjmallett struct cvmx_usbcx_daint_s cn31xx; 868215976Sjmallett struct cvmx_usbcx_daint_s cn50xx; 869215976Sjmallett struct cvmx_usbcx_daint_s cn52xx; 870215976Sjmallett struct cvmx_usbcx_daint_s cn52xxp1; 871215976Sjmallett struct cvmx_usbcx_daint_s cn56xx; 872215976Sjmallett struct cvmx_usbcx_daint_s cn56xxp1; 873215976Sjmallett}; 874215976Sjmalletttypedef union cvmx_usbcx_daint cvmx_usbcx_daint_t; 875215976Sjmallett 876215976Sjmallett/** 877215976Sjmallett * cvmx_usbc#_daintmsk 878215976Sjmallett * 879215976Sjmallett * Device All Endpoints Interrupt Mask Register (DAINTMSK) 880215976Sjmallett * 881215976Sjmallett * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register 882215976Sjmallett * to interrupt the application when an event occurs on a device endpoint. However, the Device 883215976Sjmallett * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set. 884215976Sjmallett * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1 885215976Sjmallett */ 886215976Sjmallettunion cvmx_usbcx_daintmsk 887215976Sjmallett{ 888215976Sjmallett uint32_t u32; 889215976Sjmallett struct cvmx_usbcx_daintmsk_s 890215976Sjmallett { 891215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 892215976Sjmallett uint32_t outepmsk : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk) 893215976Sjmallett One per OUT Endpoint: 894215976Sjmallett Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */ 895215976Sjmallett uint32_t inepmsk : 16; /**< IN EP Interrupt Mask Bits (InEpMsk) 896215976Sjmallett One bit per IN Endpoint: 897215976Sjmallett Bit 0 for IN EP 0, bit 15 for IN EP 15 */ 898215976Sjmallett#else 899215976Sjmallett uint32_t inepmsk : 16; 900215976Sjmallett uint32_t outepmsk : 16; 901215976Sjmallett#endif 902215976Sjmallett } s; 903215976Sjmallett struct cvmx_usbcx_daintmsk_s cn30xx; 904215976Sjmallett struct cvmx_usbcx_daintmsk_s cn31xx; 905215976Sjmallett struct cvmx_usbcx_daintmsk_s cn50xx; 906215976Sjmallett struct cvmx_usbcx_daintmsk_s cn52xx; 907215976Sjmallett struct cvmx_usbcx_daintmsk_s cn52xxp1; 908215976Sjmallett struct cvmx_usbcx_daintmsk_s cn56xx; 909215976Sjmallett struct cvmx_usbcx_daintmsk_s cn56xxp1; 910215976Sjmallett}; 911215976Sjmalletttypedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t; 912215976Sjmallett 913215976Sjmallett/** 914215976Sjmallett * cvmx_usbc#_dcfg 915215976Sjmallett * 916215976Sjmallett * Device Configuration Register (DCFG) 917215976Sjmallett * 918215976Sjmallett * This register configures the core in Device mode after power-on or after certain control 919215976Sjmallett * commands or enumeration. Do not make changes to this register after initial programming. 920215976Sjmallett */ 921215976Sjmallettunion cvmx_usbcx_dcfg 922215976Sjmallett{ 923215976Sjmallett uint32_t u32; 924215976Sjmallett struct cvmx_usbcx_dcfg_s 925215976Sjmallett { 926215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 927215976Sjmallett uint32_t reserved_23_31 : 9; 928215976Sjmallett uint32_t epmiscnt : 5; /**< IN Endpoint Mismatch Count (EPMisCnt) 929215976Sjmallett The application programs this filed with a count that determines 930215976Sjmallett when the core generates an Endpoint Mismatch interrupt 931215976Sjmallett (GINTSTS.EPMis). The core loads this value into an internal 932215976Sjmallett counter and decrements it. The counter is reloaded whenever 933215976Sjmallett there is a match or when the counter expires. The width of this 934215976Sjmallett counter depends on the depth of the Token Queue. */ 935215976Sjmallett uint32_t reserved_13_17 : 5; 936215976Sjmallett uint32_t perfrint : 2; /**< Periodic Frame Interval (PerFrInt) 937215976Sjmallett Indicates the time within a (micro)frame at which the application 938215976Sjmallett must be notified using the End Of Periodic Frame Interrupt. This 939215976Sjmallett can be used to determine if all the isochronous traffic for that 940215976Sjmallett (micro)frame is complete. 941215976Sjmallett * 2'b00: 80% of the (micro)frame interval 942215976Sjmallett * 2'b01: 85% 943215976Sjmallett * 2'b10: 90% 944215976Sjmallett * 2'b11: 95% */ 945215976Sjmallett uint32_t devaddr : 7; /**< Device Address (DevAddr) 946215976Sjmallett The application must program this field after every SetAddress 947215976Sjmallett control command. */ 948215976Sjmallett uint32_t reserved_3_3 : 1; 949215976Sjmallett uint32_t nzstsouthshk : 1; /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) 950215976Sjmallett The application can use this field to select the handshake the 951215976Sjmallett core sends on receiving a nonzero-length data packet during 952215976Sjmallett the OUT transaction of a control transfer's Status stage. 953215976Sjmallett * 1'b1: Send a STALL handshake on a nonzero-length status 954215976Sjmallett OUT transaction and do not send the received OUT packet to 955215976Sjmallett the application. 956215976Sjmallett * 1'b0: Send the received OUT packet to the application (zero- 957215976Sjmallett length or nonzero-length) and send a handshake based on 958215976Sjmallett the NAK and STALL bits for the endpoint in the Device 959215976Sjmallett Endpoint Control register. */ 960215976Sjmallett uint32_t devspd : 2; /**< Device Speed (DevSpd) 961215976Sjmallett Indicates the speed at which the application requires the core to 962215976Sjmallett enumerate, or the maximum speed the application can support. 963215976Sjmallett However, the actual bus speed is determined only after the 964215976Sjmallett chirp sequence is completed, and is based on the speed of the 965215976Sjmallett USB host to which the core is connected. See "Device 966215976Sjmallett Initialization" on page 249 for details. 967215976Sjmallett * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) 968215976Sjmallett * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) 969215976Sjmallett * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If 970215976Sjmallett you select 6 MHz LS mode, you must do a soft reset. 971215976Sjmallett * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */ 972215976Sjmallett#else 973215976Sjmallett uint32_t devspd : 2; 974215976Sjmallett uint32_t nzstsouthshk : 1; 975215976Sjmallett uint32_t reserved_3_3 : 1; 976215976Sjmallett uint32_t devaddr : 7; 977215976Sjmallett uint32_t perfrint : 2; 978215976Sjmallett uint32_t reserved_13_17 : 5; 979215976Sjmallett uint32_t epmiscnt : 5; 980215976Sjmallett uint32_t reserved_23_31 : 9; 981215976Sjmallett#endif 982215976Sjmallett } s; 983215976Sjmallett struct cvmx_usbcx_dcfg_s cn30xx; 984215976Sjmallett struct cvmx_usbcx_dcfg_s cn31xx; 985215976Sjmallett struct cvmx_usbcx_dcfg_s cn50xx; 986215976Sjmallett struct cvmx_usbcx_dcfg_s cn52xx; 987215976Sjmallett struct cvmx_usbcx_dcfg_s cn52xxp1; 988215976Sjmallett struct cvmx_usbcx_dcfg_s cn56xx; 989215976Sjmallett struct cvmx_usbcx_dcfg_s cn56xxp1; 990215976Sjmallett}; 991215976Sjmalletttypedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t; 992215976Sjmallett 993215976Sjmallett/** 994215976Sjmallett * cvmx_usbc#_dctl 995215976Sjmallett * 996215976Sjmallett * Device Control Register (DCTL) 997215976Sjmallett * 998215976Sjmallett */ 999215976Sjmallettunion cvmx_usbcx_dctl 1000215976Sjmallett{ 1001215976Sjmallett uint32_t u32; 1002215976Sjmallett struct cvmx_usbcx_dctl_s 1003215976Sjmallett { 1004215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1005215976Sjmallett uint32_t reserved_12_31 : 20; 1006215976Sjmallett uint32_t pwronprgdone : 1; /**< Power-On Programming Done (PWROnPrgDone) 1007215976Sjmallett The application uses this bit to indicate that register 1008215976Sjmallett programming is completed after a wake-up from Power Down 1009215976Sjmallett mode. For more information, see "Device Mode Suspend and 1010215976Sjmallett Resume With Partial Power-Down" on page 357. */ 1011215976Sjmallett uint32_t cgoutnak : 1; /**< Clear Global OUT NAK (CGOUTNak) 1012215976Sjmallett A write to this field clears the Global OUT NAK. */ 1013215976Sjmallett uint32_t sgoutnak : 1; /**< Set Global OUT NAK (SGOUTNak) 1014215976Sjmallett A write to this field sets the Global OUT NAK. 1015215976Sjmallett The application uses this bit to send a NAK handshake on all 1016215976Sjmallett OUT endpoints. 1017215976Sjmallett The application should set the this bit only after making sure 1018215976Sjmallett that the Global OUT NAK Effective bit in the Core Interrupt 1019215976Sjmallett Register (GINTSTS.GOUTNakEff) is cleared. */ 1020215976Sjmallett uint32_t cgnpinnak : 1; /**< Clear Global Non-Periodic IN NAK (CGNPInNak) 1021215976Sjmallett A write to this field clears the Global Non-Periodic IN NAK. */ 1022215976Sjmallett uint32_t sgnpinnak : 1; /**< Set Global Non-Periodic IN NAK (SGNPInNak) 1023215976Sjmallett A write to this field sets the Global Non-Periodic IN NAK.The 1024215976Sjmallett application uses this bit to send a NAK handshake on all non- 1025215976Sjmallett periodic IN endpoints. The core can also set this bit when a 1026215976Sjmallett timeout condition is detected on a non-periodic endpoint. 1027215976Sjmallett The application should set this bit only after making sure that 1028215976Sjmallett the Global IN NAK Effective bit in the Core Interrupt Register 1029215976Sjmallett (GINTSTS.GINNakEff) is cleared. */ 1030215976Sjmallett uint32_t tstctl : 3; /**< Test Control (TstCtl) 1031215976Sjmallett * 3'b000: Test mode disabled 1032215976Sjmallett * 3'b001: Test_J mode 1033215976Sjmallett * 3'b010: Test_K mode 1034215976Sjmallett * 3'b011: Test_SE0_NAK mode 1035215976Sjmallett * 3'b100: Test_Packet mode 1036215976Sjmallett * 3'b101: Test_Force_Enable 1037215976Sjmallett * Others: Reserved */ 1038215976Sjmallett uint32_t goutnaksts : 1; /**< Global OUT NAK Status (GOUTNakSts) 1039215976Sjmallett * 1'b0: A handshake is sent based on the FIFO Status and the 1040215976Sjmallett NAK and STALL bit settings. 1041215976Sjmallett * 1'b1: No data is written to the RxFIFO, irrespective of space 1042215976Sjmallett availability. Sends a NAK handshake on all packets, except 1043215976Sjmallett on SETUP transactions. All isochronous OUT packets are 1044215976Sjmallett dropped. */ 1045215976Sjmallett uint32_t gnpinnaksts : 1; /**< Global Non-Periodic IN NAK Status (GNPINNakSts) 1046215976Sjmallett * 1'b0: A handshake is sent out based on the data availability 1047215976Sjmallett in the transmit FIFO. 1048215976Sjmallett * 1'b1: A NAK handshake is sent out on all non-periodic IN 1049215976Sjmallett endpoints, irrespective of the data availability in the transmit 1050215976Sjmallett FIFO. */ 1051215976Sjmallett uint32_t sftdiscon : 1; /**< Soft Disconnect (SftDiscon) 1052215976Sjmallett The application uses this bit to signal the O2P USB core to do a 1053215976Sjmallett soft disconnect. As long as this bit is set, the host will not see 1054215976Sjmallett that the device is connected, and the device will not receive 1055215976Sjmallett signals on the USB. The core stays in the disconnected state 1056215976Sjmallett until the application clears this bit. 1057215976Sjmallett The minimum duration for which the core must keep this bit set 1058215976Sjmallett is specified in Minimum Duration for Soft Disconnect . 1059215976Sjmallett * 1'b0: Normal operation. When this bit is cleared after a soft 1060215976Sjmallett disconnect, the core drives the phy_opmode_o signal on the 1061215976Sjmallett UTMI+ to 2'b00, which generates a device connect event to 1062215976Sjmallett the USB host. When the device is reconnected, the USB host 1063215976Sjmallett restarts device enumeration. 1064215976Sjmallett * 1'b1: The core drives the phy_opmode_o signal on the 1065215976Sjmallett UTMI+ to 2'b01, which generates a device disconnect event 1066215976Sjmallett to the USB host. */ 1067215976Sjmallett uint32_t rmtwkupsig : 1; /**< Remote Wakeup Signaling (RmtWkUpSig) 1068215976Sjmallett When the application sets this bit, the core initiates remote 1069215976Sjmallett signaling to wake up the USB host.The application must set this 1070215976Sjmallett bit to get the core out of Suspended state and must clear this bit 1071215976Sjmallett after the core comes out of Suspended state. */ 1072215976Sjmallett#else 1073215976Sjmallett uint32_t rmtwkupsig : 1; 1074215976Sjmallett uint32_t sftdiscon : 1; 1075215976Sjmallett uint32_t gnpinnaksts : 1; 1076215976Sjmallett uint32_t goutnaksts : 1; 1077215976Sjmallett uint32_t tstctl : 3; 1078215976Sjmallett uint32_t sgnpinnak : 1; 1079215976Sjmallett uint32_t cgnpinnak : 1; 1080215976Sjmallett uint32_t sgoutnak : 1; 1081215976Sjmallett uint32_t cgoutnak : 1; 1082215976Sjmallett uint32_t pwronprgdone : 1; 1083215976Sjmallett uint32_t reserved_12_31 : 20; 1084215976Sjmallett#endif 1085215976Sjmallett } s; 1086215976Sjmallett struct cvmx_usbcx_dctl_s cn30xx; 1087215976Sjmallett struct cvmx_usbcx_dctl_s cn31xx; 1088215976Sjmallett struct cvmx_usbcx_dctl_s cn50xx; 1089215976Sjmallett struct cvmx_usbcx_dctl_s cn52xx; 1090215976Sjmallett struct cvmx_usbcx_dctl_s cn52xxp1; 1091215976Sjmallett struct cvmx_usbcx_dctl_s cn56xx; 1092215976Sjmallett struct cvmx_usbcx_dctl_s cn56xxp1; 1093215976Sjmallett}; 1094215976Sjmalletttypedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t; 1095215976Sjmallett 1096215976Sjmallett/** 1097215976Sjmallett * cvmx_usbc#_diepctl# 1098215976Sjmallett * 1099215976Sjmallett * Device IN Endpoint-n Control Register (DIEPCTLn) 1100215976Sjmallett * 1101215976Sjmallett * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0. 1102215976Sjmallett */ 1103215976Sjmallettunion cvmx_usbcx_diepctlx 1104215976Sjmallett{ 1105215976Sjmallett uint32_t u32; 1106215976Sjmallett struct cvmx_usbcx_diepctlx_s 1107215976Sjmallett { 1108215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1109215976Sjmallett uint32_t epena : 1; /**< Endpoint Enable (EPEna) 1110215976Sjmallett Indicates that data is ready to be transmitted on the endpoint. 1111215976Sjmallett The core clears this bit before setting any of the following 1112215976Sjmallett interrupts on this endpoint: 1113215976Sjmallett * Endpoint Disabled 1114215976Sjmallett * Transfer Completed */ 1115215976Sjmallett uint32_t epdis : 1; /**< Endpoint Disable (EPDis) 1116215976Sjmallett The application sets this bit to stop transmitting data on an 1117215976Sjmallett endpoint, even before the transfer for that endpoint is complete. 1118215976Sjmallett The application must wait for the Endpoint Disabled interrupt 1119215976Sjmallett before treating the endpoint as disabled. The core clears this bit 1120215976Sjmallett before setting the Endpoint Disabled Interrupt. The application 1121215976Sjmallett should set this bit only if Endpoint Enable is already set for this 1122215976Sjmallett endpoint. */ 1123215976Sjmallett uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints: 1124215976Sjmallett Set DATA1 PID (SetD1PID) 1125215976Sjmallett Writing to this field sets the Endpoint Data Pid (DPID) field in 1126215976Sjmallett this register to DATA1. 1127215976Sjmallett For Isochronous endpoints: 1128215976Sjmallett Set Odd (micro)frame (SetOddFr) 1129215976Sjmallett Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1130215976Sjmallett field to odd (micro)frame. */ 1131215976Sjmallett uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints: 1132215976Sjmallett Writing to this field sets the Endpoint Data Pid (DPID) field in 1133215976Sjmallett this register to DATA0. 1134215976Sjmallett For Isochronous endpoints: 1135215976Sjmallett Set Odd (micro)frame (SetEvenFr) 1136215976Sjmallett Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1137215976Sjmallett field to even (micro)frame. */ 1138215976Sjmallett uint32_t snak : 1; /**< Set NAK (SNAK) 1139215976Sjmallett A write to this bit sets the NAK bit for the endpoint. 1140215976Sjmallett Using this bit, the application can control the transmission of 1141215976Sjmallett NAK handshakes on an endpoint. The core can also set this bit 1142215976Sjmallett for an endpoint after a SETUP packet is received on the 1143215976Sjmallett endpoint. */ 1144215976Sjmallett uint32_t cnak : 1; /**< Clear NAK (CNAK) 1145215976Sjmallett A write to this bit clears the NAK bit for the endpoint. */ 1146215976Sjmallett uint32_t txfnum : 4; /**< TxFIFO Number (TxFNum) 1147215976Sjmallett Non-periodic endpoints must set this bit to zero. Periodic 1148215976Sjmallett endpoints must map this to the corresponding Periodic TxFIFO 1149215976Sjmallett number. 1150215976Sjmallett * 4'h0: Non-Periodic TxFIFO 1151215976Sjmallett * Others: Specified Periodic TxFIFO number */ 1152215976Sjmallett uint32_t stall : 1; /**< STALL Handshake (Stall) 1153215976Sjmallett For non-control, non-isochronous endpoints: 1154215976Sjmallett The application sets this bit to stall all tokens from the USB host 1155215976Sjmallett to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or 1156215976Sjmallett Global OUT NAK is set along with this bit, the STALL bit takes 1157215976Sjmallett priority. Only the application can clear this bit, never the core. 1158215976Sjmallett For control endpoints: 1159215976Sjmallett The application can only set this bit, and the core clears it, when 1160215976Sjmallett a SETUP token i received for this endpoint. If a NAK bit, Global 1161215976Sjmallett Non-Periodic IN NAK, or Global OUT NAK is set along with this 1162215976Sjmallett bit, the STALL bit takes priority. Irrespective of this bit's setting, 1163215976Sjmallett the core always responds to SETUP data packets with an ACK handshake. */ 1164215976Sjmallett uint32_t reserved_20_20 : 1; 1165215976Sjmallett uint32_t eptype : 2; /**< Endpoint Type (EPType) 1166215976Sjmallett This is the transfer type supported by this logical endpoint. 1167215976Sjmallett * 2'b00: Control 1168215976Sjmallett * 2'b01: Isochronous 1169215976Sjmallett * 2'b10: Bulk 1170215976Sjmallett * 2'b11: Interrupt */ 1171215976Sjmallett uint32_t naksts : 1; /**< NAK Status (NAKSts) 1172215976Sjmallett Indicates the following: 1173215976Sjmallett * 1'b0: The core is transmitting non-NAK handshakes based 1174215976Sjmallett on the FIFO status 1175215976Sjmallett * 1'b1: The core is transmitting NAK handshakes on this 1176215976Sjmallett endpoint. 1177215976Sjmallett When either the application or the core sets this bit: 1178215976Sjmallett * For non-isochronous IN endpoints: The core stops 1179215976Sjmallett transmitting any data on an IN endpoint, even if data is 1180215976Sjmallett available in the TxFIFO. 1181215976Sjmallett * For isochronous IN endpoints: The core sends out a zero- 1182215976Sjmallett length data packet, even if data is available in the TxFIFO. 1183215976Sjmallett Irrespective of this bit's setting, the core always responds to 1184215976Sjmallett SETUP data packets with an ACK handshake. */ 1185215976Sjmallett uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints: 1186215976Sjmallett Endpoint Data PID (DPID) 1187215976Sjmallett Contains the PID of the packet to be received or transmitted on 1188215976Sjmallett this endpoint. The application should program the PID of the first 1189215976Sjmallett packet to be received or transmitted on this endpoint, after the 1190215976Sjmallett endpoint is activated. Applications use the SetD1PID and 1191215976Sjmallett SetD0PID fields of this register to program either DATA0 or 1192215976Sjmallett DATA1 PID. 1193215976Sjmallett * 1'b0: DATA0 1194215976Sjmallett * 1'b1: DATA1 1195215976Sjmallett For isochronous IN and OUT endpoints: 1196215976Sjmallett Even/Odd (Micro)Frame (EO_FrNum) 1197215976Sjmallett Indicates the (micro)frame number in which the core transmits/ 1198215976Sjmallett receives isochronous data for this endpoint. The application 1199215976Sjmallett should program the even/odd (micro) frame number in which it 1200215976Sjmallett intends to transmit/receive isochronous data for this endpoint 1201215976Sjmallett using the SetEvnFr and SetOddFr fields in this register. 1202215976Sjmallett * 1'b0: Even (micro)frame 1203215976Sjmallett * 1'b1: Odd (micro)frame */ 1204215976Sjmallett uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP) 1205215976Sjmallett Indicates whether this endpoint is active in the current 1206215976Sjmallett configuration and interface. The core clears this bit for all 1207215976Sjmallett endpoints (other than EP 0) after detecting a USB reset. After 1208215976Sjmallett receiving the SetConfiguration and SetInterface commands, the 1209215976Sjmallett application must program endpoint registers accordingly and set 1210215976Sjmallett this bit. */ 1211215976Sjmallett uint32_t nextep : 4; /**< Next Endpoint (NextEp) 1212215976Sjmallett Applies to non-periodic IN endpoints only. 1213215976Sjmallett Indicates the endpoint number to be fetched after the data for 1214215976Sjmallett the current endpoint is fetched. The core can access this field, 1215215976Sjmallett even when the Endpoint Enable (EPEna) bit is not set. This 1216215976Sjmallett field is not valid in Slave mode. */ 1217215976Sjmallett uint32_t mps : 11; /**< Maximum Packet Size (MPS) 1218215976Sjmallett Applies to IN and OUT endpoints. 1219215976Sjmallett The application must program this field with the maximum 1220215976Sjmallett packet size for the current logical endpoint. This value is in 1221215976Sjmallett bytes. */ 1222215976Sjmallett#else 1223215976Sjmallett uint32_t mps : 11; 1224215976Sjmallett uint32_t nextep : 4; 1225215976Sjmallett uint32_t usbactep : 1; 1226215976Sjmallett uint32_t dpid : 1; 1227215976Sjmallett uint32_t naksts : 1; 1228215976Sjmallett uint32_t eptype : 2; 1229215976Sjmallett uint32_t reserved_20_20 : 1; 1230215976Sjmallett uint32_t stall : 1; 1231215976Sjmallett uint32_t txfnum : 4; 1232215976Sjmallett uint32_t cnak : 1; 1233215976Sjmallett uint32_t snak : 1; 1234215976Sjmallett uint32_t setd0pid : 1; 1235215976Sjmallett uint32_t setd1pid : 1; 1236215976Sjmallett uint32_t epdis : 1; 1237215976Sjmallett uint32_t epena : 1; 1238215976Sjmallett#endif 1239215976Sjmallett } s; 1240215976Sjmallett struct cvmx_usbcx_diepctlx_s cn30xx; 1241215976Sjmallett struct cvmx_usbcx_diepctlx_s cn31xx; 1242215976Sjmallett struct cvmx_usbcx_diepctlx_s cn50xx; 1243215976Sjmallett struct cvmx_usbcx_diepctlx_s cn52xx; 1244215976Sjmallett struct cvmx_usbcx_diepctlx_s cn52xxp1; 1245215976Sjmallett struct cvmx_usbcx_diepctlx_s cn56xx; 1246215976Sjmallett struct cvmx_usbcx_diepctlx_s cn56xxp1; 1247215976Sjmallett}; 1248215976Sjmalletttypedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t; 1249215976Sjmallett 1250215976Sjmallett/** 1251215976Sjmallett * cvmx_usbc#_diepint# 1252215976Sjmallett * 1253215976Sjmallett * Device Endpoint-n Interrupt Register (DIEPINTn) 1254215976Sjmallett * 1255215976Sjmallett * This register indicates the status of an endpoint with respect to 1256215976Sjmallett * USB- and AHB-related events. The application must read this register 1257215976Sjmallett * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of 1258215976Sjmallett * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, 1259215976Sjmallett * respectively) is set. Before the application can read this register, 1260215976Sjmallett * it must first read the Device All Endpoints Interrupt (DAINT) register 1261215976Sjmallett * to get the exact endpoint number for the Device Endpoint-n Interrupt 1262215976Sjmallett * register. The application must clear the appropriate bit in this register 1263215976Sjmallett * to clear the corresponding bits in the DAINT and GINTSTS registers. 1264215976Sjmallett */ 1265215976Sjmallettunion cvmx_usbcx_diepintx 1266215976Sjmallett{ 1267215976Sjmallett uint32_t u32; 1268215976Sjmallett struct cvmx_usbcx_diepintx_s 1269215976Sjmallett { 1270215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1271215976Sjmallett uint32_t reserved_7_31 : 25; 1272215976Sjmallett uint32_t inepnakeff : 1; /**< IN Endpoint NAK Effective (INEPNakEff) 1273215976Sjmallett Applies to periodic IN endpoints only. 1274215976Sjmallett Indicates that the IN endpoint NAK bit set by the application has 1275215976Sjmallett taken effect in the core. This bit can be cleared when the 1276215976Sjmallett application clears the IN endpoint NAK by writing to 1277215976Sjmallett DIEPCTLn.CNAK. 1278215976Sjmallett This interrupt indicates that the core has sampled the NAK bit 1279215976Sjmallett set (either by the application or by the core). 1280215976Sjmallett This interrupt does not necessarily mean that a NAK handshake 1281215976Sjmallett is sent on the USB. A STALL bit takes priority over a NAK bit. */ 1282215976Sjmallett uint32_t intknepmis : 1; /**< IN Token Received with EP Mismatch (INTknEPMis) 1283215976Sjmallett Applies to non-periodic IN endpoints only. 1284215976Sjmallett Indicates that the data in the top of the non-periodic TxFIFO 1285215976Sjmallett belongs to an endpoint other than the one for which the IN 1286215976Sjmallett token was received. This interrupt is asserted on the endpoint 1287215976Sjmallett for which the IN token was received. */ 1288215976Sjmallett uint32_t intkntxfemp : 1; /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp) 1289215976Sjmallett Applies only to non-periodic IN endpoints. 1290215976Sjmallett Indicates that an IN token was received when the associated 1291215976Sjmallett TxFIFO (periodic/non-periodic) was empty. This interrupt is 1292215976Sjmallett asserted on the endpoint for which the IN token was received. */ 1293215976Sjmallett uint32_t timeout : 1; /**< Timeout Condition (TimeOUT) 1294215976Sjmallett Applies to non-isochronous IN endpoints only. 1295215976Sjmallett Indicates that the core has detected a timeout condition on the 1296215976Sjmallett USB for the last IN token on this endpoint. */ 1297215976Sjmallett uint32_t ahberr : 1; /**< AHB Error (AHBErr) 1298215976Sjmallett This is generated only in Internal DMA mode when there is an 1299215976Sjmallett AHB error during an AHB read/write. The application can read 1300215976Sjmallett the corresponding endpoint DMA address register to get the 1301215976Sjmallett error address. */ 1302215976Sjmallett uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld) 1303215976Sjmallett This bit indicates that the endpoint is disabled per the 1304215976Sjmallett application's request. */ 1305215976Sjmallett uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl) 1306215976Sjmallett Indicates that the programmed transfer is complete on the AHB 1307215976Sjmallett as well as on the USB, for this endpoint. */ 1308215976Sjmallett#else 1309215976Sjmallett uint32_t xfercompl : 1; 1310215976Sjmallett uint32_t epdisbld : 1; 1311215976Sjmallett uint32_t ahberr : 1; 1312215976Sjmallett uint32_t timeout : 1; 1313215976Sjmallett uint32_t intkntxfemp : 1; 1314215976Sjmallett uint32_t intknepmis : 1; 1315215976Sjmallett uint32_t inepnakeff : 1; 1316215976Sjmallett uint32_t reserved_7_31 : 25; 1317215976Sjmallett#endif 1318215976Sjmallett } s; 1319215976Sjmallett struct cvmx_usbcx_diepintx_s cn30xx; 1320215976Sjmallett struct cvmx_usbcx_diepintx_s cn31xx; 1321215976Sjmallett struct cvmx_usbcx_diepintx_s cn50xx; 1322215976Sjmallett struct cvmx_usbcx_diepintx_s cn52xx; 1323215976Sjmallett struct cvmx_usbcx_diepintx_s cn52xxp1; 1324215976Sjmallett struct cvmx_usbcx_diepintx_s cn56xx; 1325215976Sjmallett struct cvmx_usbcx_diepintx_s cn56xxp1; 1326215976Sjmallett}; 1327215976Sjmalletttypedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t; 1328215976Sjmallett 1329215976Sjmallett/** 1330215976Sjmallett * cvmx_usbc#_diepmsk 1331215976Sjmallett * 1332215976Sjmallett * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK) 1333215976Sjmallett * 1334215976Sjmallett * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers 1335215976Sjmallett * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt 1336215976Sjmallett * for a specific status in the DIEPINTn register can be masked by writing to the corresponding 1337215976Sjmallett * bit in this register. Status bits are masked by default. 1338215976Sjmallett * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1339215976Sjmallett */ 1340215976Sjmallettunion cvmx_usbcx_diepmsk 1341215976Sjmallett{ 1342215976Sjmallett uint32_t u32; 1343215976Sjmallett struct cvmx_usbcx_diepmsk_s 1344215976Sjmallett { 1345215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1346215976Sjmallett uint32_t reserved_7_31 : 25; 1347215976Sjmallett uint32_t inepnakeffmsk : 1; /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */ 1348215976Sjmallett uint32_t intknepmismsk : 1; /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */ 1349215976Sjmallett uint32_t intkntxfempmsk : 1; /**< IN Token Received When TxFIFO Empty Mask 1350215976Sjmallett (INTknTXFEmpMsk) */ 1351215976Sjmallett uint32_t timeoutmsk : 1; /**< Timeout Condition Mask (TimeOUTMsk) 1352215976Sjmallett (Non-isochronous endpoints) */ 1353215976Sjmallett uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */ 1354215976Sjmallett uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ 1355215976Sjmallett uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */ 1356215976Sjmallett#else 1357215976Sjmallett uint32_t xfercomplmsk : 1; 1358215976Sjmallett uint32_t epdisbldmsk : 1; 1359215976Sjmallett uint32_t ahberrmsk : 1; 1360215976Sjmallett uint32_t timeoutmsk : 1; 1361215976Sjmallett uint32_t intkntxfempmsk : 1; 1362215976Sjmallett uint32_t intknepmismsk : 1; 1363215976Sjmallett uint32_t inepnakeffmsk : 1; 1364215976Sjmallett uint32_t reserved_7_31 : 25; 1365215976Sjmallett#endif 1366215976Sjmallett } s; 1367215976Sjmallett struct cvmx_usbcx_diepmsk_s cn30xx; 1368215976Sjmallett struct cvmx_usbcx_diepmsk_s cn31xx; 1369215976Sjmallett struct cvmx_usbcx_diepmsk_s cn50xx; 1370215976Sjmallett struct cvmx_usbcx_diepmsk_s cn52xx; 1371215976Sjmallett struct cvmx_usbcx_diepmsk_s cn52xxp1; 1372215976Sjmallett struct cvmx_usbcx_diepmsk_s cn56xx; 1373215976Sjmallett struct cvmx_usbcx_diepmsk_s cn56xxp1; 1374215976Sjmallett}; 1375215976Sjmalletttypedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t; 1376215976Sjmallett 1377215976Sjmallett/** 1378215976Sjmallett * cvmx_usbc#_dieptsiz# 1379215976Sjmallett * 1380215976Sjmallett * Device Endpoint-n Transfer Size Register (DIEPTSIZn) 1381215976Sjmallett * 1382215976Sjmallett * The application must modify this register before enabling the endpoint. 1383215976Sjmallett * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), 1384215976Sjmallett * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. 1385215976Sjmallett * This register is used only for endpoints other than Endpoint 0. 1386215976Sjmallett */ 1387215976Sjmallettunion cvmx_usbcx_dieptsizx 1388215976Sjmallett{ 1389215976Sjmallett uint32_t u32; 1390215976Sjmallett struct cvmx_usbcx_dieptsizx_s 1391215976Sjmallett { 1392215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1393215976Sjmallett uint32_t reserved_31_31 : 1; 1394215976Sjmallett uint32_t mc : 2; /**< Multi Count (MC) 1395215976Sjmallett Applies to IN endpoints only. 1396215976Sjmallett For periodic IN endpoints, this field indicates the number of 1397215976Sjmallett packets that must be transmitted per microframe on the USB. 1398215976Sjmallett The core uses this field to calculate the data PID for 1399215976Sjmallett isochronous IN endpoints. 1400215976Sjmallett * 2'b01: 1 packet 1401215976Sjmallett * 2'b10: 2 packets 1402215976Sjmallett * 2'b11: 3 packets 1403215976Sjmallett For non-periodic IN endpoints, this field is valid only in Internal 1404215976Sjmallett DMA mode. It specifies the number of packets the core should 1405215976Sjmallett fetch for an IN endpoint before it switches to the endpoint 1406215976Sjmallett pointed to by the Next Endpoint field of the Device Endpoint-n 1407215976Sjmallett Control register (DIEPCTLn.NextEp) */ 1408215976Sjmallett uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 1409215976Sjmallett Indicates the total number of USB packets that constitute the 1410215976Sjmallett Transfer Size amount of data for this endpoint. 1411215976Sjmallett IN Endpoints: This field is decremented every time a packet 1412215976Sjmallett (maximum size or short packet) is read from the TxFIFO. */ 1413215976Sjmallett uint32_t xfersize : 19; /**< Transfer Size (XferSize) 1414215976Sjmallett This field contains the transfer size in bytes for the current 1415215976Sjmallett endpoint. 1416215976Sjmallett The core only interrupts the application after it has exhausted 1417215976Sjmallett the transfer size amount of data. The transfer size can be set to 1418215976Sjmallett the maximum packet size of the endpoint, to be interrupted at 1419215976Sjmallett the end of each packet. 1420215976Sjmallett IN Endpoints: The core decrements this field every time a 1421215976Sjmallett packet from the external memory is written to the TxFIFO. */ 1422215976Sjmallett#else 1423215976Sjmallett uint32_t xfersize : 19; 1424215976Sjmallett uint32_t pktcnt : 10; 1425215976Sjmallett uint32_t mc : 2; 1426215976Sjmallett uint32_t reserved_31_31 : 1; 1427215976Sjmallett#endif 1428215976Sjmallett } s; 1429215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn30xx; 1430215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn31xx; 1431215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn50xx; 1432215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn52xx; 1433215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn52xxp1; 1434215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn56xx; 1435215976Sjmallett struct cvmx_usbcx_dieptsizx_s cn56xxp1; 1436215976Sjmallett}; 1437215976Sjmalletttypedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t; 1438215976Sjmallett 1439215976Sjmallett/** 1440215976Sjmallett * cvmx_usbc#_doepctl# 1441215976Sjmallett * 1442215976Sjmallett * Device OUT Endpoint-n Control Register (DOEPCTLn) 1443215976Sjmallett * 1444215976Sjmallett * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0. 1445215976Sjmallett */ 1446215976Sjmallettunion cvmx_usbcx_doepctlx 1447215976Sjmallett{ 1448215976Sjmallett uint32_t u32; 1449215976Sjmallett struct cvmx_usbcx_doepctlx_s 1450215976Sjmallett { 1451215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1452215976Sjmallett uint32_t epena : 1; /**< Endpoint Enable (EPEna) 1453215976Sjmallett Indicates that the application has allocated the memory tp start 1454215976Sjmallett receiving data from the USB. 1455215976Sjmallett The core clears this bit before setting any of the following 1456215976Sjmallett interrupts on this endpoint: 1457215976Sjmallett * SETUP Phase Done 1458215976Sjmallett * Endpoint Disabled 1459215976Sjmallett * Transfer Completed 1460215976Sjmallett For control OUT endpoints in DMA mode, this bit must be set 1461215976Sjmallett to be able to transfer SETUP data packets in memory. */ 1462215976Sjmallett uint32_t epdis : 1; /**< Endpoint Disable (EPDis) 1463215976Sjmallett The application sets this bit to stop transmitting data on an 1464215976Sjmallett endpoint, even before the transfer for that endpoint is complete. 1465215976Sjmallett The application must wait for the Endpoint Disabled interrupt 1466215976Sjmallett before treating the endpoint as disabled. The core clears this bit 1467215976Sjmallett before setting the Endpoint Disabled Interrupt. The application 1468215976Sjmallett should set this bit only if Endpoint Enable is already set for this 1469215976Sjmallett endpoint. */ 1470215976Sjmallett uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints: 1471215976Sjmallett Set DATA1 PID (SetD1PID) 1472215976Sjmallett Writing to this field sets the Endpoint Data Pid (DPID) field in 1473215976Sjmallett this register to DATA1. 1474215976Sjmallett For Isochronous endpoints: 1475215976Sjmallett Set Odd (micro)frame (SetOddFr) 1476215976Sjmallett Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1477215976Sjmallett field to odd (micro)frame. */ 1478215976Sjmallett uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints: 1479215976Sjmallett Writing to this field sets the Endpoint Data Pid (DPID) field in 1480215976Sjmallett this register to DATA0. 1481215976Sjmallett For Isochronous endpoints: 1482215976Sjmallett Set Odd (micro)frame (SetEvenFr) 1483215976Sjmallett Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1484215976Sjmallett field to even (micro)frame. */ 1485215976Sjmallett uint32_t snak : 1; /**< Set NAK (SNAK) 1486215976Sjmallett A write to this bit sets the NAK bit for the endpoint. 1487215976Sjmallett Using this bit, the application can control the transmission of 1488215976Sjmallett NAK handshakes on an endpoint. The core can also set this bit 1489215976Sjmallett for an endpoint after a SETUP packet is received on the 1490215976Sjmallett endpoint. */ 1491215976Sjmallett uint32_t cnak : 1; /**< Clear NAK (CNAK) 1492215976Sjmallett A write to this bit clears the NAK bit for the endpoint. */ 1493215976Sjmallett uint32_t reserved_22_25 : 4; 1494215976Sjmallett uint32_t stall : 1; /**< STALL Handshake (Stall) 1495215976Sjmallett For non-control, non-isochronous endpoints: 1496215976Sjmallett The application sets this bit to stall all tokens from the USB host 1497215976Sjmallett to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or 1498215976Sjmallett Global OUT NAK is set along with this bit, the STALL bit takes 1499215976Sjmallett priority. Only the application can clear this bit, never the core. 1500215976Sjmallett For control endpoints: 1501215976Sjmallett The application can only set this bit, and the core clears it, when 1502215976Sjmallett a SETUP token i received for this endpoint. If a NAK bit, Global 1503215976Sjmallett Non-Periodic IN NAK, or Global OUT NAK is set along with this 1504215976Sjmallett bit, the STALL bit takes priority. Irrespective of this bit's setting, 1505215976Sjmallett the core always responds to SETUP data packets with an ACK handshake. */ 1506215976Sjmallett uint32_t snp : 1; /**< Snoop Mode (Snp) 1507215976Sjmallett This bit configures the endpoint to Snoop mode. In Snoop mode, 1508215976Sjmallett the core does not check the correctness of OUT packets before 1509215976Sjmallett transferring them to application memory. */ 1510215976Sjmallett uint32_t eptype : 2; /**< Endpoint Type (EPType) 1511215976Sjmallett This is the transfer type supported by this logical endpoint. 1512215976Sjmallett * 2'b00: Control 1513215976Sjmallett * 2'b01: Isochronous 1514215976Sjmallett * 2'b10: Bulk 1515215976Sjmallett * 2'b11: Interrupt */ 1516215976Sjmallett uint32_t naksts : 1; /**< NAK Status (NAKSts) 1517215976Sjmallett Indicates the following: 1518215976Sjmallett * 1'b0: The core is transmitting non-NAK handshakes based 1519215976Sjmallett on the FIFO status 1520215976Sjmallett * 1'b1: The core is transmitting NAK handshakes on this 1521215976Sjmallett endpoint. 1522215976Sjmallett When either the application or the core sets this bit: 1523215976Sjmallett * The core stops receiving any data on an OUT endpoint, even 1524215976Sjmallett if there is space in the RxFIFO to accomodate the incoming 1525215976Sjmallett packet. */ 1526215976Sjmallett uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints: 1527215976Sjmallett Endpoint Data PID (DPID) 1528215976Sjmallett Contains the PID of the packet to be received or transmitted on 1529215976Sjmallett this endpoint. The application should program the PID of the first 1530215976Sjmallett packet to be received or transmitted on this endpoint, after the 1531215976Sjmallett endpoint is activated. Applications use the SetD1PID and 1532215976Sjmallett SetD0PID fields of this register to program either DATA0 or 1533215976Sjmallett DATA1 PID. 1534215976Sjmallett * 1'b0: DATA0 1535215976Sjmallett * 1'b1: DATA1 1536215976Sjmallett For isochronous IN and OUT endpoints: 1537215976Sjmallett Even/Odd (Micro)Frame (EO_FrNum) 1538215976Sjmallett Indicates the (micro)frame number in which the core transmits/ 1539215976Sjmallett receives isochronous data for this endpoint. The application 1540215976Sjmallett should program the even/odd (micro) frame number in which it 1541215976Sjmallett intends to transmit/receive isochronous data for this endpoint 1542215976Sjmallett using the SetEvnFr and SetOddFr fields in this register. 1543215976Sjmallett * 1'b0: Even (micro)frame 1544215976Sjmallett * 1'b1: Odd (micro)frame */ 1545215976Sjmallett uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP) 1546215976Sjmallett Indicates whether this endpoint is active in the current 1547215976Sjmallett configuration and interface. The core clears this bit for all 1548215976Sjmallett endpoints (other than EP 0) after detecting a USB reset. After 1549215976Sjmallett receiving the SetConfiguration and SetInterface commands, the 1550215976Sjmallett application must program endpoint registers accordingly and set 1551215976Sjmallett this bit. */ 1552215976Sjmallett uint32_t reserved_11_14 : 4; 1553215976Sjmallett uint32_t mps : 11; /**< Maximum Packet Size (MPS) 1554215976Sjmallett Applies to IN and OUT endpoints. 1555215976Sjmallett The application must program this field with the maximum 1556215976Sjmallett packet size for the current logical endpoint. This value is in 1557215976Sjmallett bytes. */ 1558215976Sjmallett#else 1559215976Sjmallett uint32_t mps : 11; 1560215976Sjmallett uint32_t reserved_11_14 : 4; 1561215976Sjmallett uint32_t usbactep : 1; 1562215976Sjmallett uint32_t dpid : 1; 1563215976Sjmallett uint32_t naksts : 1; 1564215976Sjmallett uint32_t eptype : 2; 1565215976Sjmallett uint32_t snp : 1; 1566215976Sjmallett uint32_t stall : 1; 1567215976Sjmallett uint32_t reserved_22_25 : 4; 1568215976Sjmallett uint32_t cnak : 1; 1569215976Sjmallett uint32_t snak : 1; 1570215976Sjmallett uint32_t setd0pid : 1; 1571215976Sjmallett uint32_t setd1pid : 1; 1572215976Sjmallett uint32_t epdis : 1; 1573215976Sjmallett uint32_t epena : 1; 1574215976Sjmallett#endif 1575215976Sjmallett } s; 1576215976Sjmallett struct cvmx_usbcx_doepctlx_s cn30xx; 1577215976Sjmallett struct cvmx_usbcx_doepctlx_s cn31xx; 1578215976Sjmallett struct cvmx_usbcx_doepctlx_s cn50xx; 1579215976Sjmallett struct cvmx_usbcx_doepctlx_s cn52xx; 1580215976Sjmallett struct cvmx_usbcx_doepctlx_s cn52xxp1; 1581215976Sjmallett struct cvmx_usbcx_doepctlx_s cn56xx; 1582215976Sjmallett struct cvmx_usbcx_doepctlx_s cn56xxp1; 1583215976Sjmallett}; 1584215976Sjmalletttypedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t; 1585215976Sjmallett 1586215976Sjmallett/** 1587215976Sjmallett * cvmx_usbc#_doepint# 1588215976Sjmallett * 1589215976Sjmallett * Device Endpoint-n Interrupt Register (DOEPINTn) 1590215976Sjmallett * 1591215976Sjmallett * This register indicates the status of an endpoint with respect to USB- and AHB-related events. 1592215976Sjmallett * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints 1593215976Sjmallett * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) 1594215976Sjmallett * is set. Before the application can read this register, it must first read the Device All 1595215976Sjmallett * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n 1596215976Sjmallett * Interrupt register. The application must clear the appropriate bit in this register to clear the 1597215976Sjmallett * corresponding bits in the DAINT and GINTSTS registers. 1598215976Sjmallett */ 1599215976Sjmallettunion cvmx_usbcx_doepintx 1600215976Sjmallett{ 1601215976Sjmallett uint32_t u32; 1602215976Sjmallett struct cvmx_usbcx_doepintx_s 1603215976Sjmallett { 1604215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1605215976Sjmallett uint32_t reserved_5_31 : 27; 1606215976Sjmallett uint32_t outtknepdis : 1; /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis) 1607215976Sjmallett Applies only to control OUT endpoints. 1608215976Sjmallett Indicates that an OUT token was received when the endpoint 1609215976Sjmallett was not yet enabled. This interrupt is asserted on the endpoint 1610215976Sjmallett for which the OUT token was received. */ 1611215976Sjmallett uint32_t setup : 1; /**< SETUP Phase Done (SetUp) 1612215976Sjmallett Applies to control OUT endpoints only. 1613215976Sjmallett Indicates that the SETUP phase for the control endpoint is 1614215976Sjmallett complete and no more back-to-back SETUP packets were 1615215976Sjmallett received for the current control transfer. On this interrupt, the 1616215976Sjmallett application can decode the received SETUP data packet. */ 1617215976Sjmallett uint32_t ahberr : 1; /**< AHB Error (AHBErr) 1618215976Sjmallett This is generated only in Internal DMA mode when there is an 1619215976Sjmallett AHB error during an AHB read/write. The application can read 1620215976Sjmallett the corresponding endpoint DMA address register to get the 1621215976Sjmallett error address. */ 1622215976Sjmallett uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld) 1623215976Sjmallett This bit indicates that the endpoint is disabled per the 1624215976Sjmallett application's request. */ 1625215976Sjmallett uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl) 1626215976Sjmallett Indicates that the programmed transfer is complete on the AHB 1627215976Sjmallett as well as on the USB, for this endpoint. */ 1628215976Sjmallett#else 1629215976Sjmallett uint32_t xfercompl : 1; 1630215976Sjmallett uint32_t epdisbld : 1; 1631215976Sjmallett uint32_t ahberr : 1; 1632215976Sjmallett uint32_t setup : 1; 1633215976Sjmallett uint32_t outtknepdis : 1; 1634215976Sjmallett uint32_t reserved_5_31 : 27; 1635215976Sjmallett#endif 1636215976Sjmallett } s; 1637215976Sjmallett struct cvmx_usbcx_doepintx_s cn30xx; 1638215976Sjmallett struct cvmx_usbcx_doepintx_s cn31xx; 1639215976Sjmallett struct cvmx_usbcx_doepintx_s cn50xx; 1640215976Sjmallett struct cvmx_usbcx_doepintx_s cn52xx; 1641215976Sjmallett struct cvmx_usbcx_doepintx_s cn52xxp1; 1642215976Sjmallett struct cvmx_usbcx_doepintx_s cn56xx; 1643215976Sjmallett struct cvmx_usbcx_doepintx_s cn56xxp1; 1644215976Sjmallett}; 1645215976Sjmalletttypedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t; 1646215976Sjmallett 1647215976Sjmallett/** 1648215976Sjmallett * cvmx_usbc#_doepmsk 1649215976Sjmallett * 1650215976Sjmallett * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK) 1651215976Sjmallett * 1652215976Sjmallett * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers 1653215976Sjmallett * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt 1654215976Sjmallett * for a specific status in the DOEPINTn register can be masked by writing into the 1655215976Sjmallett * corresponding bit in this register. Status bits are masked by default. 1656215976Sjmallett * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1657215976Sjmallett */ 1658215976Sjmallettunion cvmx_usbcx_doepmsk 1659215976Sjmallett{ 1660215976Sjmallett uint32_t u32; 1661215976Sjmallett struct cvmx_usbcx_doepmsk_s 1662215976Sjmallett { 1663215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1664215976Sjmallett uint32_t reserved_5_31 : 27; 1665215976Sjmallett uint32_t outtknepdismsk : 1; /**< OUT Token Received when Endpoint Disabled Mask 1666215976Sjmallett (OUTTknEPdisMsk) 1667215976Sjmallett Applies to control OUT endpoints only. */ 1668215976Sjmallett uint32_t setupmsk : 1; /**< SETUP Phase Done Mask (SetUPMsk) 1669215976Sjmallett Applies to control endpoints only. */ 1670215976Sjmallett uint32_t ahberrmsk : 1; /**< AHB Error (AHBErrMsk) */ 1671215976Sjmallett uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ 1672215976Sjmallett uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */ 1673215976Sjmallett#else 1674215976Sjmallett uint32_t xfercomplmsk : 1; 1675215976Sjmallett uint32_t epdisbldmsk : 1; 1676215976Sjmallett uint32_t ahberrmsk : 1; 1677215976Sjmallett uint32_t setupmsk : 1; 1678215976Sjmallett uint32_t outtknepdismsk : 1; 1679215976Sjmallett uint32_t reserved_5_31 : 27; 1680215976Sjmallett#endif 1681215976Sjmallett } s; 1682215976Sjmallett struct cvmx_usbcx_doepmsk_s cn30xx; 1683215976Sjmallett struct cvmx_usbcx_doepmsk_s cn31xx; 1684215976Sjmallett struct cvmx_usbcx_doepmsk_s cn50xx; 1685215976Sjmallett struct cvmx_usbcx_doepmsk_s cn52xx; 1686215976Sjmallett struct cvmx_usbcx_doepmsk_s cn52xxp1; 1687215976Sjmallett struct cvmx_usbcx_doepmsk_s cn56xx; 1688215976Sjmallett struct cvmx_usbcx_doepmsk_s cn56xxp1; 1689215976Sjmallett}; 1690215976Sjmalletttypedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t; 1691215976Sjmallett 1692215976Sjmallett/** 1693215976Sjmallett * cvmx_usbc#_doeptsiz# 1694215976Sjmallett * 1695215976Sjmallett * Device Endpoint-n Transfer Size Register (DOEPTSIZn) 1696215976Sjmallett * 1697215976Sjmallett * The application must modify this register before enabling the endpoint. 1698215976Sjmallett * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control 1699215976Sjmallett * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application 1700215976Sjmallett * can only read this register once the core has cleared the Endpoint Enable bit. 1701215976Sjmallett * This register is used only for endpoints other than Endpoint 0. 1702215976Sjmallett */ 1703215976Sjmallettunion cvmx_usbcx_doeptsizx 1704215976Sjmallett{ 1705215976Sjmallett uint32_t u32; 1706215976Sjmallett struct cvmx_usbcx_doeptsizx_s 1707215976Sjmallett { 1708215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1709215976Sjmallett uint32_t reserved_31_31 : 1; 1710215976Sjmallett uint32_t mc : 2; /**< Multi Count (MC) 1711215976Sjmallett Received Data PID (RxDPID) 1712215976Sjmallett Applies to isochronous OUT endpoints only. 1713215976Sjmallett This is the data PID received in the last packet for this endpoint. 1714215976Sjmallett 2'b00: DATA0 1715215976Sjmallett 2'b01: DATA1 1716215976Sjmallett 2'b10: DATA2 1717215976Sjmallett 2'b11: MDATA 1718215976Sjmallett SETUP Packet Count (SUPCnt) 1719215976Sjmallett Applies to control OUT Endpoints only. 1720215976Sjmallett This field specifies the number of back-to-back SETUP data 1721215976Sjmallett packets the endpoint can receive. 1722215976Sjmallett 2'b01: 1 packet 1723215976Sjmallett 2'b10: 2 packets 1724215976Sjmallett 2'b11: 3 packets */ 1725215976Sjmallett uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 1726215976Sjmallett Indicates the total number of USB packets that constitute the 1727215976Sjmallett Transfer Size amount of data for this endpoint. 1728215976Sjmallett OUT Endpoints: This field is decremented every time a 1729215976Sjmallett packet (maximum size or short packet) is written to the 1730215976Sjmallett RxFIFO. */ 1731215976Sjmallett uint32_t xfersize : 19; /**< Transfer Size (XferSize) 1732215976Sjmallett This field contains the transfer size in bytes for the current 1733215976Sjmallett endpoint. 1734215976Sjmallett The core only interrupts the application after it has exhausted 1735215976Sjmallett the transfer size amount of data. The transfer size can be set to 1736215976Sjmallett the maximum packet size of the endpoint, to be interrupted at 1737215976Sjmallett the end of each packet. 1738215976Sjmallett OUT Endpoints: The core decrements this field every time a 1739215976Sjmallett packet is read from the RxFIFO and written to the external 1740215976Sjmallett memory. */ 1741215976Sjmallett#else 1742215976Sjmallett uint32_t xfersize : 19; 1743215976Sjmallett uint32_t pktcnt : 10; 1744215976Sjmallett uint32_t mc : 2; 1745215976Sjmallett uint32_t reserved_31_31 : 1; 1746215976Sjmallett#endif 1747215976Sjmallett } s; 1748215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn30xx; 1749215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn31xx; 1750215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn50xx; 1751215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn52xx; 1752215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn52xxp1; 1753215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn56xx; 1754215976Sjmallett struct cvmx_usbcx_doeptsizx_s cn56xxp1; 1755215976Sjmallett}; 1756215976Sjmalletttypedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t; 1757215976Sjmallett 1758215976Sjmallett/** 1759215976Sjmallett * cvmx_usbc#_dptxfsiz# 1760215976Sjmallett * 1761215976Sjmallett * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ) 1762215976Sjmallett * 1763215976Sjmallett * This register holds the memory start address of each periodic TxFIFO to implemented 1764215976Sjmallett * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint. 1765215976Sjmallett * This register is repeated for each periodic FIFO instantiated. 1766215976Sjmallett */ 1767215976Sjmallettunion cvmx_usbcx_dptxfsizx 1768215976Sjmallett{ 1769215976Sjmallett uint32_t u32; 1770215976Sjmallett struct cvmx_usbcx_dptxfsizx_s 1771215976Sjmallett { 1772215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1773215976Sjmallett uint32_t dptxfsize : 16; /**< Device Periodic TxFIFO Size (DPTxFSize) 1774215976Sjmallett This value is in terms of 32-bit words. 1775215976Sjmallett * Minimum value is 4 1776215976Sjmallett * Maximum value is 768 */ 1777215976Sjmallett uint32_t dptxfstaddr : 16; /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr) 1778215976Sjmallett Holds the start address in the RAM for this periodic FIFO. */ 1779215976Sjmallett#else 1780215976Sjmallett uint32_t dptxfstaddr : 16; 1781215976Sjmallett uint32_t dptxfsize : 16; 1782215976Sjmallett#endif 1783215976Sjmallett } s; 1784215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn30xx; 1785215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn31xx; 1786215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn50xx; 1787215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn52xx; 1788215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn52xxp1; 1789215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn56xx; 1790215976Sjmallett struct cvmx_usbcx_dptxfsizx_s cn56xxp1; 1791215976Sjmallett}; 1792215976Sjmalletttypedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t; 1793215976Sjmallett 1794215976Sjmallett/** 1795215976Sjmallett * cvmx_usbc#_dsts 1796215976Sjmallett * 1797215976Sjmallett * Device Status Register (DSTS) 1798215976Sjmallett * 1799215976Sjmallett * This register indicates the status of the core with respect to USB-related events. 1800215976Sjmallett * It must be read on interrupts from Device All Interrupts (DAINT) register. 1801215976Sjmallett */ 1802215976Sjmallettunion cvmx_usbcx_dsts 1803215976Sjmallett{ 1804215976Sjmallett uint32_t u32; 1805215976Sjmallett struct cvmx_usbcx_dsts_s 1806215976Sjmallett { 1807215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1808215976Sjmallett uint32_t reserved_22_31 : 10; 1809215976Sjmallett uint32_t soffn : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN) 1810215976Sjmallett When the core is operating at high speed, this field contains a 1811215976Sjmallett microframe number. When the core is operating at full or low 1812215976Sjmallett speed, this field contains a frame number. */ 1813215976Sjmallett uint32_t reserved_4_7 : 4; 1814215976Sjmallett uint32_t errticerr : 1; /**< Erratic Error (ErrticErr) 1815215976Sjmallett The core sets this bit to report any erratic errors 1816215976Sjmallett (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at 1817215976Sjmallett least 2 ms, due to PHY error) seen on the UTMI+. 1818215976Sjmallett Due to erratic errors, the O2P USB core goes into Suspended 1819215976Sjmallett state and an interrupt is generated to the application with Early 1820215976Sjmallett Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). 1821215976Sjmallett If the early suspend is asserted due to an erratic error, the 1822215976Sjmallett application can only perform a soft disconnect recover. */ 1823215976Sjmallett uint32_t enumspd : 2; /**< Enumerated Speed (EnumSpd) 1824215976Sjmallett Indicates the speed at which the O2P USB core has come up 1825215976Sjmallett after speed detection through a chirp sequence. 1826215976Sjmallett * 2'b00: High speed (PHY clock is running at 30 or 60 MHz) 1827215976Sjmallett * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz) 1828215976Sjmallett * 2'b10: Low speed (PHY clock is running at 6 MHz) 1829215976Sjmallett * 2'b11: Full speed (PHY clock is running at 48 MHz) 1830215976Sjmallett Low speed is not supported for devices using a UTMI+ PHY. */ 1831215976Sjmallett uint32_t suspsts : 1; /**< Suspend Status (SuspSts) 1832215976Sjmallett In Device mode, this bit is set as long as a Suspend condition is 1833215976Sjmallett detected on the USB. The core enters the Suspended state 1834215976Sjmallett when there is no activity on the phy_line_state_i signal for an 1835215976Sjmallett extended period of time. The core comes out of the suspend: 1836215976Sjmallett * When there is any activity on the phy_line_state_i signal 1837215976Sjmallett * When the application writes to the Remote Wakeup Signaling 1838215976Sjmallett bit in the Device Control register (DCTL.RmtWkUpSig). */ 1839215976Sjmallett#else 1840215976Sjmallett uint32_t suspsts : 1; 1841215976Sjmallett uint32_t enumspd : 2; 1842215976Sjmallett uint32_t errticerr : 1; 1843215976Sjmallett uint32_t reserved_4_7 : 4; 1844215976Sjmallett uint32_t soffn : 14; 1845215976Sjmallett uint32_t reserved_22_31 : 10; 1846215976Sjmallett#endif 1847215976Sjmallett } s; 1848215976Sjmallett struct cvmx_usbcx_dsts_s cn30xx; 1849215976Sjmallett struct cvmx_usbcx_dsts_s cn31xx; 1850215976Sjmallett struct cvmx_usbcx_dsts_s cn50xx; 1851215976Sjmallett struct cvmx_usbcx_dsts_s cn52xx; 1852215976Sjmallett struct cvmx_usbcx_dsts_s cn52xxp1; 1853215976Sjmallett struct cvmx_usbcx_dsts_s cn56xx; 1854215976Sjmallett struct cvmx_usbcx_dsts_s cn56xxp1; 1855215976Sjmallett}; 1856215976Sjmalletttypedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t; 1857215976Sjmallett 1858215976Sjmallett/** 1859215976Sjmallett * cvmx_usbc#_dtknqr1 1860215976Sjmallett * 1861215976Sjmallett * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1) 1862215976Sjmallett * 1863215976Sjmallett * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token 1864215976Sjmallett * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number. 1865215976Sjmallett * A read from this register returns the first 5 endpoint entries of the IN Token Sequence 1866215976Sjmallett * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest 1867215976Sjmallett * token is discarded. 1868215976Sjmallett */ 1869215976Sjmallettunion cvmx_usbcx_dtknqr1 1870215976Sjmallett{ 1871215976Sjmallett uint32_t u32; 1872215976Sjmallett struct cvmx_usbcx_dtknqr1_s 1873215976Sjmallett { 1874215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1875215976Sjmallett uint32_t eptkn : 24; /**< Endpoint Token (EPTkn) 1876215976Sjmallett Four bits per token represent the endpoint number of the token: 1877215976Sjmallett * Bits [31:28]: Endpoint number of Token 5 1878215976Sjmallett * Bits [27:24]: Endpoint number of Token 4 1879215976Sjmallett - ....... 1880215976Sjmallett * Bits [15:12]: Endpoint number of Token 1 1881215976Sjmallett * Bits [11:8]: Endpoint number of Token 0 */ 1882215976Sjmallett uint32_t wrapbit : 1; /**< Wrap Bit (WrapBit) 1883215976Sjmallett This bit is set when the write pointer wraps. It is cleared when 1884215976Sjmallett the learning queue is cleared. */ 1885215976Sjmallett uint32_t reserved_5_6 : 2; 1886215976Sjmallett uint32_t intknwptr : 5; /**< IN Token Queue Write Pointer (INTknWPtr) */ 1887215976Sjmallett#else 1888215976Sjmallett uint32_t intknwptr : 5; 1889215976Sjmallett uint32_t reserved_5_6 : 2; 1890215976Sjmallett uint32_t wrapbit : 1; 1891215976Sjmallett uint32_t eptkn : 24; 1892215976Sjmallett#endif 1893215976Sjmallett } s; 1894215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn30xx; 1895215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn31xx; 1896215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn50xx; 1897215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn52xx; 1898215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn52xxp1; 1899215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn56xx; 1900215976Sjmallett struct cvmx_usbcx_dtknqr1_s cn56xxp1; 1901215976Sjmallett}; 1902215976Sjmalletttypedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t; 1903215976Sjmallett 1904215976Sjmallett/** 1905215976Sjmallett * cvmx_usbc#_dtknqr2 1906215976Sjmallett * 1907215976Sjmallett * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2) 1908215976Sjmallett * 1909215976Sjmallett * A read from this register returns the next 8 endpoint entries of the learning queue. 1910215976Sjmallett */ 1911215976Sjmallettunion cvmx_usbcx_dtknqr2 1912215976Sjmallett{ 1913215976Sjmallett uint32_t u32; 1914215976Sjmallett struct cvmx_usbcx_dtknqr2_s 1915215976Sjmallett { 1916215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1917215976Sjmallett uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1918215976Sjmallett Four bits per token represent the endpoint number of the token: 1919215976Sjmallett * Bits [31:28]: Endpoint number of Token 13 1920215976Sjmallett * Bits [27:24]: Endpoint number of Token 12 1921215976Sjmallett - ....... 1922215976Sjmallett * Bits [7:4]: Endpoint number of Token 7 1923215976Sjmallett * Bits [3:0]: Endpoint number of Token 6 */ 1924215976Sjmallett#else 1925215976Sjmallett uint32_t eptkn : 32; 1926215976Sjmallett#endif 1927215976Sjmallett } s; 1928215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn30xx; 1929215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn31xx; 1930215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn50xx; 1931215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn52xx; 1932215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn52xxp1; 1933215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn56xx; 1934215976Sjmallett struct cvmx_usbcx_dtknqr2_s cn56xxp1; 1935215976Sjmallett}; 1936215976Sjmalletttypedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t; 1937215976Sjmallett 1938215976Sjmallett/** 1939215976Sjmallett * cvmx_usbc#_dtknqr3 1940215976Sjmallett * 1941215976Sjmallett * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3) 1942215976Sjmallett * 1943215976Sjmallett * A read from this register returns the next 8 endpoint entries of the learning queue. 1944215976Sjmallett */ 1945215976Sjmallettunion cvmx_usbcx_dtknqr3 1946215976Sjmallett{ 1947215976Sjmallett uint32_t u32; 1948215976Sjmallett struct cvmx_usbcx_dtknqr3_s 1949215976Sjmallett { 1950215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1951215976Sjmallett uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1952215976Sjmallett Four bits per token represent the endpoint number of the token: 1953215976Sjmallett * Bits [31:28]: Endpoint number of Token 21 1954215976Sjmallett * Bits [27:24]: Endpoint number of Token 20 1955215976Sjmallett - ....... 1956215976Sjmallett * Bits [7:4]: Endpoint number of Token 15 1957215976Sjmallett * Bits [3:0]: Endpoint number of Token 14 */ 1958215976Sjmallett#else 1959215976Sjmallett uint32_t eptkn : 32; 1960215976Sjmallett#endif 1961215976Sjmallett } s; 1962215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn30xx; 1963215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn31xx; 1964215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn50xx; 1965215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn52xx; 1966215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn52xxp1; 1967215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn56xx; 1968215976Sjmallett struct cvmx_usbcx_dtknqr3_s cn56xxp1; 1969215976Sjmallett}; 1970215976Sjmalletttypedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t; 1971215976Sjmallett 1972215976Sjmallett/** 1973215976Sjmallett * cvmx_usbc#_dtknqr4 1974215976Sjmallett * 1975215976Sjmallett * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4) 1976215976Sjmallett * 1977215976Sjmallett * A read from this register returns the last 8 endpoint entries of the learning queue. 1978215976Sjmallett */ 1979215976Sjmallettunion cvmx_usbcx_dtknqr4 1980215976Sjmallett{ 1981215976Sjmallett uint32_t u32; 1982215976Sjmallett struct cvmx_usbcx_dtknqr4_s 1983215976Sjmallett { 1984215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1985215976Sjmallett uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1986215976Sjmallett Four bits per token represent the endpoint number of the token: 1987215976Sjmallett * Bits [31:28]: Endpoint number of Token 29 1988215976Sjmallett * Bits [27:24]: Endpoint number of Token 28 1989215976Sjmallett - ....... 1990215976Sjmallett * Bits [7:4]: Endpoint number of Token 23 1991215976Sjmallett * Bits [3:0]: Endpoint number of Token 22 */ 1992215976Sjmallett#else 1993215976Sjmallett uint32_t eptkn : 32; 1994215976Sjmallett#endif 1995215976Sjmallett } s; 1996215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn30xx; 1997215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn31xx; 1998215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn50xx; 1999215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn52xx; 2000215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn52xxp1; 2001215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn56xx; 2002215976Sjmallett struct cvmx_usbcx_dtknqr4_s cn56xxp1; 2003215976Sjmallett}; 2004215976Sjmalletttypedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t; 2005215976Sjmallett 2006215976Sjmallett/** 2007215976Sjmallett * cvmx_usbc#_gahbcfg 2008215976Sjmallett * 2009215976Sjmallett * Core AHB Configuration Register (GAHBCFG) 2010215976Sjmallett * 2011215976Sjmallett * This register can be used to configure the core after power-on or a change in mode of operation. 2012215976Sjmallett * This register mainly contains AHB system-related configuration parameters. The AHB is the processor 2013215976Sjmallett * interface to the O2P USB core. In general, software need not know about this interface except to 2014215976Sjmallett * program the values as specified. 2015215976Sjmallett * 2016215976Sjmallett * The application must program this register as part of the O2P USB core initialization. 2017215976Sjmallett * Do not change this register after the initial programming. 2018215976Sjmallett */ 2019215976Sjmallettunion cvmx_usbcx_gahbcfg 2020215976Sjmallett{ 2021215976Sjmallett uint32_t u32; 2022215976Sjmallett struct cvmx_usbcx_gahbcfg_s 2023215976Sjmallett { 2024215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2025215976Sjmallett uint32_t reserved_9_31 : 23; 2026215976Sjmallett uint32_t ptxfemplvl : 1; /**< Periodic TxFIFO Empty Level (PTxFEmpLvl) 2027215976Sjmallett Software should set this bit to 0x1. 2028215976Sjmallett Indicates when the Periodic TxFIFO Empty Interrupt bit in the 2029215976Sjmallett Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This 2030215976Sjmallett bit is used only in Slave mode. 2031215976Sjmallett * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic 2032215976Sjmallett TxFIFO is half empty 2033215976Sjmallett * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic 2034215976Sjmallett TxFIFO is completely empty */ 2035215976Sjmallett uint32_t nptxfemplvl : 1; /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) 2036215976Sjmallett Software should set this bit to 0x1. 2037215976Sjmallett Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in 2038215976Sjmallett the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. 2039215976Sjmallett This bit is used only in Slave mode. 2040215976Sjmallett * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non- 2041215976Sjmallett Periodic TxFIFO is half empty 2042215976Sjmallett * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non- 2043215976Sjmallett Periodic TxFIFO is completely empty */ 2044215976Sjmallett uint32_t reserved_6_6 : 1; 2045215976Sjmallett uint32_t dmaen : 1; /**< DMA Enable (DMAEn) 2046215976Sjmallett * 1'b0: Core operates in Slave mode 2047215976Sjmallett * 1'b1: Core operates in a DMA mode */ 2048215976Sjmallett uint32_t hbstlen : 4; /**< Burst Length/Type (HBstLen) 2049215976Sjmallett This field has not effect and should be left as 0x0. */ 2050215976Sjmallett uint32_t glblintrmsk : 1; /**< Global Interrupt Mask (GlblIntrMsk) 2051215976Sjmallett Software should set this field to 0x1. 2052215976Sjmallett The application uses this bit to mask or unmask the interrupt 2053215976Sjmallett line assertion to itself. Irrespective of this bit's setting, the 2054215976Sjmallett interrupt status registers are updated by the core. 2055215976Sjmallett * 1'b0: Mask the interrupt assertion to the application. 2056215976Sjmallett * 1'b1: Unmask the interrupt assertion to the application. */ 2057215976Sjmallett#else 2058215976Sjmallett uint32_t glblintrmsk : 1; 2059215976Sjmallett uint32_t hbstlen : 4; 2060215976Sjmallett uint32_t dmaen : 1; 2061215976Sjmallett uint32_t reserved_6_6 : 1; 2062215976Sjmallett uint32_t nptxfemplvl : 1; 2063215976Sjmallett uint32_t ptxfemplvl : 1; 2064215976Sjmallett uint32_t reserved_9_31 : 23; 2065215976Sjmallett#endif 2066215976Sjmallett } s; 2067215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn30xx; 2068215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn31xx; 2069215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn50xx; 2070215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn52xx; 2071215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn52xxp1; 2072215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn56xx; 2073215976Sjmallett struct cvmx_usbcx_gahbcfg_s cn56xxp1; 2074215976Sjmallett}; 2075215976Sjmalletttypedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t; 2076215976Sjmallett 2077215976Sjmallett/** 2078215976Sjmallett * cvmx_usbc#_ghwcfg1 2079215976Sjmallett * 2080215976Sjmallett * User HW Config1 Register (GHWCFG1) 2081215976Sjmallett * 2082215976Sjmallett * This register contains the logical endpoint direction(s) of the O2P USB core. 2083215976Sjmallett */ 2084215976Sjmallettunion cvmx_usbcx_ghwcfg1 2085215976Sjmallett{ 2086215976Sjmallett uint32_t u32; 2087215976Sjmallett struct cvmx_usbcx_ghwcfg1_s 2088215976Sjmallett { 2089215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2090215976Sjmallett uint32_t epdir : 32; /**< Endpoint Direction (epdir) 2091215976Sjmallett Two bits per endpoint represent the direction. 2092215976Sjmallett * 2'b00: BIDIR (IN and OUT) endpoint 2093215976Sjmallett * 2'b01: IN endpoint 2094215976Sjmallett * 2'b10: OUT endpoint 2095215976Sjmallett * 2'b11: Reserved 2096215976Sjmallett Bits [31:30]: Endpoint 15 direction 2097215976Sjmallett Bits [29:28]: Endpoint 14 direction 2098215976Sjmallett - ... 2099215976Sjmallett Bits [3:2]: Endpoint 1 direction 2100215976Sjmallett Bits[1:0]: Endpoint 0 direction (always BIDIR) */ 2101215976Sjmallett#else 2102215976Sjmallett uint32_t epdir : 32; 2103215976Sjmallett#endif 2104215976Sjmallett } s; 2105215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn30xx; 2106215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn31xx; 2107215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn50xx; 2108215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn52xx; 2109215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn52xxp1; 2110215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn56xx; 2111215976Sjmallett struct cvmx_usbcx_ghwcfg1_s cn56xxp1; 2112215976Sjmallett}; 2113215976Sjmalletttypedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t; 2114215976Sjmallett 2115215976Sjmallett/** 2116215976Sjmallett * cvmx_usbc#_ghwcfg2 2117215976Sjmallett * 2118215976Sjmallett * User HW Config2 Register (GHWCFG2) 2119215976Sjmallett * 2120215976Sjmallett * This register contains configuration options of the O2P USB core. 2121215976Sjmallett */ 2122215976Sjmallettunion cvmx_usbcx_ghwcfg2 2123215976Sjmallett{ 2124215976Sjmallett uint32_t u32; 2125215976Sjmallett struct cvmx_usbcx_ghwcfg2_s 2126215976Sjmallett { 2127215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2128215976Sjmallett uint32_t reserved_31_31 : 1; 2129215976Sjmallett uint32_t tknqdepth : 5; /**< Device Mode IN Token Sequence Learning Queue Depth 2130215976Sjmallett (TknQDepth) 2131215976Sjmallett Range: 0-30 */ 2132215976Sjmallett uint32_t ptxqdepth : 2; /**< Host Mode Periodic Request Queue Depth (PTxQDepth) 2133215976Sjmallett * 2'b00: 2 2134215976Sjmallett * 2'b01: 4 2135215976Sjmallett * 2'b10: 8 2136215976Sjmallett * Others: Reserved */ 2137215976Sjmallett uint32_t nptxqdepth : 2; /**< Non-Periodic Request Queue Depth (NPTxQDepth) 2138215976Sjmallett * 2'b00: 2 2139215976Sjmallett * 2'b01: 4 2140215976Sjmallett * 2'b10: 8 2141215976Sjmallett * Others: Reserved */ 2142215976Sjmallett uint32_t reserved_20_21 : 2; 2143215976Sjmallett uint32_t dynfifosizing : 1; /**< Dynamic FIFO Sizing Enabled (DynFifoSizing) 2144215976Sjmallett * 1'b0: No 2145215976Sjmallett * 1'b1: Yes */ 2146215976Sjmallett uint32_t periosupport : 1; /**< Periodic OUT Channels Supported in Host Mode 2147215976Sjmallett (PerioSupport) 2148215976Sjmallett * 1'b0: No 2149215976Sjmallett * 1'b1: Yes */ 2150215976Sjmallett uint32_t numhstchnl : 4; /**< Number of Host Channels (NumHstChnl) 2151215976Sjmallett Indicates the number of host channels supported by the core in 2152215976Sjmallett Host mode. The range of this field is 0-15: 0 specifies 1 2153215976Sjmallett channel, 15 specifies 16 channels. */ 2154215976Sjmallett uint32_t numdeveps : 4; /**< Number of Device Endpoints (NumDevEps) 2155215976Sjmallett Indicates the number of device endpoints supported by the core 2156215976Sjmallett in Device mode in addition to control endpoint 0. The range of 2157215976Sjmallett this field is 1-15. */ 2158215976Sjmallett uint32_t fsphytype : 2; /**< Full-Speed PHY Interface Type (FSPhyType) 2159215976Sjmallett * 2'b00: Full-speed interface not supported 2160215976Sjmallett * 2'b01: Dedicated full-speed interface 2161215976Sjmallett * 2'b10: FS pins shared with UTMI+ pins 2162215976Sjmallett * 2'b11: FS pins shared with ULPI pins */ 2163215976Sjmallett uint32_t hsphytype : 2; /**< High-Speed PHY Interface Type (HSPhyType) 2164215976Sjmallett * 2'b00: High-Speed interface not supported 2165215976Sjmallett * 2'b01: UTMI+ 2166215976Sjmallett * 2'b10: ULPI 2167215976Sjmallett * 2'b11: UTMI+ and ULPI */ 2168215976Sjmallett uint32_t singpnt : 1; /**< Point-to-Point (SingPnt) 2169215976Sjmallett * 1'b0: Multi-point application 2170215976Sjmallett * 1'b1: Single-point application */ 2171215976Sjmallett uint32_t otgarch : 2; /**< Architecture (OtgArch) 2172215976Sjmallett * 2'b00: Slave-Only 2173215976Sjmallett * 2'b01: External DMA 2174215976Sjmallett * 2'b10: Internal DMA 2175215976Sjmallett * Others: Reserved */ 2176215976Sjmallett uint32_t otgmode : 3; /**< Mode of Operation (OtgMode) 2177215976Sjmallett * 3'b000: HNP- and SRP-Capable OTG (Host & Device) 2178215976Sjmallett * 3'b001: SRP-Capable OTG (Host & Device) 2179215976Sjmallett * 3'b010: Non-HNP and Non-SRP Capable OTG (Host & 2180215976Sjmallett Device) 2181215976Sjmallett * 3'b011: SRP-Capable Device 2182215976Sjmallett * 3'b100: Non-OTG Device 2183215976Sjmallett * 3'b101: SRP-Capable Host 2184215976Sjmallett * 3'b110: Non-OTG Host 2185215976Sjmallett * Others: Reserved */ 2186215976Sjmallett#else 2187215976Sjmallett uint32_t otgmode : 3; 2188215976Sjmallett uint32_t otgarch : 2; 2189215976Sjmallett uint32_t singpnt : 1; 2190215976Sjmallett uint32_t hsphytype : 2; 2191215976Sjmallett uint32_t fsphytype : 2; 2192215976Sjmallett uint32_t numdeveps : 4; 2193215976Sjmallett uint32_t numhstchnl : 4; 2194215976Sjmallett uint32_t periosupport : 1; 2195215976Sjmallett uint32_t dynfifosizing : 1; 2196215976Sjmallett uint32_t reserved_20_21 : 2; 2197215976Sjmallett uint32_t nptxqdepth : 2; 2198215976Sjmallett uint32_t ptxqdepth : 2; 2199215976Sjmallett uint32_t tknqdepth : 5; 2200215976Sjmallett uint32_t reserved_31_31 : 1; 2201215976Sjmallett#endif 2202215976Sjmallett } s; 2203215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn30xx; 2204215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn31xx; 2205215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn50xx; 2206215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn52xx; 2207215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn52xxp1; 2208215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn56xx; 2209215976Sjmallett struct cvmx_usbcx_ghwcfg2_s cn56xxp1; 2210215976Sjmallett}; 2211215976Sjmalletttypedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t; 2212215976Sjmallett 2213215976Sjmallett/** 2214215976Sjmallett * cvmx_usbc#_ghwcfg3 2215215976Sjmallett * 2216215976Sjmallett * User HW Config3 Register (GHWCFG3) 2217215976Sjmallett * 2218215976Sjmallett * This register contains the configuration options of the O2P USB core. 2219215976Sjmallett */ 2220215976Sjmallettunion cvmx_usbcx_ghwcfg3 2221215976Sjmallett{ 2222215976Sjmallett uint32_t u32; 2223215976Sjmallett struct cvmx_usbcx_ghwcfg3_s 2224215976Sjmallett { 2225215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2226215976Sjmallett uint32_t dfifodepth : 16; /**< DFIFO Depth (DfifoDepth) 2227215976Sjmallett This value is in terms of 32-bit words. 2228215976Sjmallett * Minimum value is 32 2229215976Sjmallett * Maximum value is 32768 */ 2230215976Sjmallett uint32_t reserved_13_15 : 3; 2231215976Sjmallett uint32_t ahbphysync : 1; /**< AHB and PHY Synchronous (AhbPhySync) 2232215976Sjmallett Indicates whether AHB and PHY clocks are synchronous to 2233215976Sjmallett each other. 2234215976Sjmallett * 1'b0: No 2235215976Sjmallett * 1'b1: Yes 2236215976Sjmallett This bit is tied to 1. */ 2237215976Sjmallett uint32_t rsttype : 1; /**< Reset Style for Clocked always Blocks in RTL (RstType) 2238215976Sjmallett * 1'b0: Asynchronous reset is used in the core 2239215976Sjmallett * 1'b1: Synchronous reset is used in the core */ 2240215976Sjmallett uint32_t optfeature : 1; /**< Optional Features Removed (OptFeature) 2241215976Sjmallett Indicates whether the User ID register, GPIO interface ports, 2242215976Sjmallett and SOF toggle and counter ports were removed for gate count 2243215976Sjmallett optimization. */ 2244215976Sjmallett uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support 2245215976Sjmallett * 1'b0: Vendor Control Interface is not available on the core. 2246215976Sjmallett * 1'b1: Vendor Control Interface is available. */ 2247215976Sjmallett uint32_t i2c_selection : 1; /**< I2C Selection 2248215976Sjmallett * 1'b0: I2C Interface is not available on the core. 2249215976Sjmallett * 1'b1: I2C Interface is available on the core. */ 2250215976Sjmallett uint32_t otgen : 1; /**< OTG Function Enabled (OtgEn) 2251215976Sjmallett The application uses this bit to indicate the O2P USB core's 2252215976Sjmallett OTG capabilities. 2253215976Sjmallett * 1'b0: Not OTG capable 2254215976Sjmallett * 1'b1: OTG Capable */ 2255215976Sjmallett uint32_t pktsizewidth : 3; /**< Width of Packet Size Counters (PktSizeWidth) 2256215976Sjmallett * 3'b000: 4 bits 2257215976Sjmallett * 3'b001: 5 bits 2258215976Sjmallett * 3'b010: 6 bits 2259215976Sjmallett * 3'b011: 7 bits 2260215976Sjmallett * 3'b100: 8 bits 2261215976Sjmallett * 3'b101: 9 bits 2262215976Sjmallett * 3'b110: 10 bits 2263215976Sjmallett * Others: Reserved */ 2264215976Sjmallett uint32_t xfersizewidth : 4; /**< Width of Transfer Size Counters (XferSizeWidth) 2265215976Sjmallett * 4'b0000: 11 bits 2266215976Sjmallett * 4'b0001: 12 bits 2267215976Sjmallett - ... 2268215976Sjmallett * 4'b1000: 19 bits 2269215976Sjmallett * Others: Reserved */ 2270215976Sjmallett#else 2271215976Sjmallett uint32_t xfersizewidth : 4; 2272215976Sjmallett uint32_t pktsizewidth : 3; 2273215976Sjmallett uint32_t otgen : 1; 2274215976Sjmallett uint32_t i2c_selection : 1; 2275215976Sjmallett uint32_t vendor_control_interface_support : 1; 2276215976Sjmallett uint32_t optfeature : 1; 2277215976Sjmallett uint32_t rsttype : 1; 2278215976Sjmallett uint32_t ahbphysync : 1; 2279215976Sjmallett uint32_t reserved_13_15 : 3; 2280215976Sjmallett uint32_t dfifodepth : 16; 2281215976Sjmallett#endif 2282215976Sjmallett } s; 2283215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn30xx; 2284215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn31xx; 2285215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn50xx; 2286215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn52xx; 2287215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn52xxp1; 2288215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn56xx; 2289215976Sjmallett struct cvmx_usbcx_ghwcfg3_s cn56xxp1; 2290215976Sjmallett}; 2291215976Sjmalletttypedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t; 2292215976Sjmallett 2293215976Sjmallett/** 2294215976Sjmallett * cvmx_usbc#_ghwcfg4 2295215976Sjmallett * 2296215976Sjmallett * User HW Config4 Register (GHWCFG4) 2297215976Sjmallett * 2298215976Sjmallett * This register contains the configuration options of the O2P USB core. 2299215976Sjmallett */ 2300215976Sjmallettunion cvmx_usbcx_ghwcfg4 2301215976Sjmallett{ 2302215976Sjmallett uint32_t u32; 2303215976Sjmallett struct cvmx_usbcx_ghwcfg4_s 2304215976Sjmallett { 2305215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2306215976Sjmallett uint32_t reserved_30_31 : 2; 2307215976Sjmallett uint32_t numdevmodinend : 4; /**< Enable dedicatd transmit FIFO for device IN endpoints. */ 2308215976Sjmallett uint32_t endedtrfifo : 1; /**< Enable dedicatd transmit FIFO for device IN endpoints. */ 2309215976Sjmallett uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr) 2310215976Sjmallett * 1'b0: No filter 2311215976Sjmallett * 1'b1: Filter */ 2312215976Sjmallett uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr) 2313215976Sjmallett * 1'b0: No filter 2314215976Sjmallett * 1'b1: Filter */ 2315215976Sjmallett uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr) 2316215976Sjmallett * 1'b0: No filter 2317215976Sjmallett * 1'b1: Filter */ 2318215976Sjmallett uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr) 2319215976Sjmallett * 1'b0: No filter 2320215976Sjmallett * 1'b1: Filter */ 2321215976Sjmallett uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr) 2322215976Sjmallett * 1'b0: No filter 2323215976Sjmallett * 1'b1: Filter */ 2324215976Sjmallett uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to 2325215976Sjmallett Endpoint 0 (NumCtlEps) 2326215976Sjmallett Range: 1-15 */ 2327215976Sjmallett uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 2328215976Sjmallett (PhyDataWidth) 2329215976Sjmallett When a ULPI PHY is used, an internal wrapper converts ULPI 2330215976Sjmallett to UTMI+. 2331215976Sjmallett * 2'b00: 8 bits 2332215976Sjmallett * 2'b01: 16 bits 2333215976Sjmallett * 2'b10: 8/16 bits, software selectable 2334215976Sjmallett * Others: Reserved */ 2335215976Sjmallett uint32_t reserved_6_13 : 8; 2336215976Sjmallett uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 2337215976Sjmallett * 1'b0: No 2338215976Sjmallett * 1'b1: Yes */ 2339215976Sjmallett uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt) 2340215976Sjmallett * 1'b0: No 2341215976Sjmallett * 1'b1: Yes */ 2342215976Sjmallett uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints 2343215976Sjmallett (NumDevPerioEps) 2344215976Sjmallett Range: 0-15 */ 2345215976Sjmallett#else 2346215976Sjmallett uint32_t numdevperioeps : 4; 2347215976Sjmallett uint32_t enablepwropt : 1; 2348215976Sjmallett uint32_t ahbfreq : 1; 2349215976Sjmallett uint32_t reserved_6_13 : 8; 2350215976Sjmallett uint32_t phydatawidth : 2; 2351215976Sjmallett uint32_t numctleps : 4; 2352215976Sjmallett uint32_t iddgfltr : 1; 2353215976Sjmallett uint32_t vbusvalidfltr : 1; 2354215976Sjmallett uint32_t avalidfltr : 1; 2355215976Sjmallett uint32_t bvalidfltr : 1; 2356215976Sjmallett uint32_t sessendfltr : 1; 2357215976Sjmallett uint32_t endedtrfifo : 1; 2358215976Sjmallett uint32_t numdevmodinend : 4; 2359215976Sjmallett uint32_t reserved_30_31 : 2; 2360215976Sjmallett#endif 2361215976Sjmallett } s; 2362215976Sjmallett struct cvmx_usbcx_ghwcfg4_cn30xx 2363215976Sjmallett { 2364215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2365215976Sjmallett uint32_t reserved_25_31 : 7; 2366215976Sjmallett uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr) 2367215976Sjmallett * 1'b0: No filter 2368215976Sjmallett * 1'b1: Filter */ 2369215976Sjmallett uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr) 2370215976Sjmallett * 1'b0: No filter 2371215976Sjmallett * 1'b1: Filter */ 2372215976Sjmallett uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr) 2373215976Sjmallett * 1'b0: No filter 2374215976Sjmallett * 1'b1: Filter */ 2375215976Sjmallett uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr) 2376215976Sjmallett * 1'b0: No filter 2377215976Sjmallett * 1'b1: Filter */ 2378215976Sjmallett uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr) 2379215976Sjmallett * 1'b0: No filter 2380215976Sjmallett * 1'b1: Filter */ 2381215976Sjmallett uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to 2382215976Sjmallett Endpoint 0 (NumCtlEps) 2383215976Sjmallett Range: 1-15 */ 2384215976Sjmallett uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 2385215976Sjmallett (PhyDataWidth) 2386215976Sjmallett When a ULPI PHY is used, an internal wrapper converts ULPI 2387215976Sjmallett to UTMI+. 2388215976Sjmallett * 2'b00: 8 bits 2389215976Sjmallett * 2'b01: 16 bits 2390215976Sjmallett * 2'b10: 8/16 bits, software selectable 2391215976Sjmallett * Others: Reserved */ 2392215976Sjmallett uint32_t reserved_6_13 : 8; 2393215976Sjmallett uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 2394215976Sjmallett * 1'b0: No 2395215976Sjmallett * 1'b1: Yes */ 2396215976Sjmallett uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt) 2397215976Sjmallett * 1'b0: No 2398215976Sjmallett * 1'b1: Yes */ 2399215976Sjmallett uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints 2400215976Sjmallett (NumDevPerioEps) 2401215976Sjmallett Range: 0-15 */ 2402215976Sjmallett#else 2403215976Sjmallett uint32_t numdevperioeps : 4; 2404215976Sjmallett uint32_t enablepwropt : 1; 2405215976Sjmallett uint32_t ahbfreq : 1; 2406215976Sjmallett uint32_t reserved_6_13 : 8; 2407215976Sjmallett uint32_t phydatawidth : 2; 2408215976Sjmallett uint32_t numctleps : 4; 2409215976Sjmallett uint32_t iddgfltr : 1; 2410215976Sjmallett uint32_t vbusvalidfltr : 1; 2411215976Sjmallett uint32_t avalidfltr : 1; 2412215976Sjmallett uint32_t bvalidfltr : 1; 2413215976Sjmallett uint32_t sessendfltr : 1; 2414215976Sjmallett uint32_t reserved_25_31 : 7; 2415215976Sjmallett#endif 2416215976Sjmallett } cn30xx; 2417215976Sjmallett struct cvmx_usbcx_ghwcfg4_cn30xx cn31xx; 2418215976Sjmallett struct cvmx_usbcx_ghwcfg4_s cn50xx; 2419215976Sjmallett struct cvmx_usbcx_ghwcfg4_s cn52xx; 2420215976Sjmallett struct cvmx_usbcx_ghwcfg4_s cn52xxp1; 2421215976Sjmallett struct cvmx_usbcx_ghwcfg4_s cn56xx; 2422215976Sjmallett struct cvmx_usbcx_ghwcfg4_s cn56xxp1; 2423215976Sjmallett}; 2424215976Sjmalletttypedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t; 2425215976Sjmallett 2426215976Sjmallett/** 2427215976Sjmallett * cvmx_usbc#_gintmsk 2428215976Sjmallett * 2429215976Sjmallett * Core Interrupt Mask Register (GINTMSK) 2430215976Sjmallett * 2431215976Sjmallett * This register works with the Core Interrupt register to interrupt the application. 2432215976Sjmallett * When an interrupt bit is masked, the interrupt associated with that bit will not be generated. 2433215976Sjmallett * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set. 2434215976Sjmallett * Mask interrupt: 1'b0, Unmask interrupt: 1'b1 2435215976Sjmallett */ 2436215976Sjmallettunion cvmx_usbcx_gintmsk 2437215976Sjmallett{ 2438215976Sjmallett uint32_t u32; 2439215976Sjmallett struct cvmx_usbcx_gintmsk_s 2440215976Sjmallett { 2441215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2442215976Sjmallett uint32_t wkupintmsk : 1; /**< Resume/Remote Wakeup Detected Interrupt Mask 2443215976Sjmallett (WkUpIntMsk) */ 2444215976Sjmallett uint32_t sessreqintmsk : 1; /**< Session Request/New Session Detected Interrupt Mask 2445215976Sjmallett (SessReqIntMsk) */ 2446215976Sjmallett uint32_t disconnintmsk : 1; /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */ 2447215976Sjmallett uint32_t conidstschngmsk : 1; /**< Connector ID Status Change Mask (ConIDStsChngMsk) */ 2448215976Sjmallett uint32_t reserved_27_27 : 1; 2449215976Sjmallett uint32_t ptxfempmsk : 1; /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */ 2450215976Sjmallett uint32_t hchintmsk : 1; /**< Host Channels Interrupt Mask (HChIntMsk) */ 2451215976Sjmallett uint32_t prtintmsk : 1; /**< Host Port Interrupt Mask (PrtIntMsk) */ 2452215976Sjmallett uint32_t reserved_23_23 : 1; 2453215976Sjmallett uint32_t fetsuspmsk : 1; /**< Data Fetch Suspended Mask (FetSuspMsk) */ 2454215976Sjmallett uint32_t incomplpmsk : 1; /**< Incomplete Periodic Transfer Mask (incomplPMsk) 2455215976Sjmallett Incomplete Isochronous OUT Transfer Mask 2456215976Sjmallett (incompISOOUTMsk) */ 2457215976Sjmallett uint32_t incompisoinmsk : 1; /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */ 2458215976Sjmallett uint32_t oepintmsk : 1; /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */ 2459215976Sjmallett uint32_t inepintmsk : 1; /**< IN Endpoints Interrupt Mask (INEPIntMsk) */ 2460215976Sjmallett uint32_t epmismsk : 1; /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */ 2461215976Sjmallett uint32_t reserved_16_16 : 1; 2462215976Sjmallett uint32_t eopfmsk : 1; /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */ 2463215976Sjmallett uint32_t isooutdropmsk : 1; /**< Isochronous OUT Packet Dropped Interrupt Mask 2464215976Sjmallett (ISOOutDropMsk) */ 2465215976Sjmallett uint32_t enumdonemsk : 1; /**< Enumeration Done Mask (EnumDoneMsk) */ 2466215976Sjmallett uint32_t usbrstmsk : 1; /**< USB Reset Mask (USBRstMsk) */ 2467215976Sjmallett uint32_t usbsuspmsk : 1; /**< USB Suspend Mask (USBSuspMsk) */ 2468215976Sjmallett uint32_t erlysuspmsk : 1; /**< Early Suspend Mask (ErlySuspMsk) */ 2469215976Sjmallett uint32_t i2cint : 1; /**< I2C Interrupt Mask (I2CINT) */ 2470215976Sjmallett uint32_t ulpickintmsk : 1; /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk) 2471215976Sjmallett I2C Carkit Interrupt Mask (I2CCKINTMsk) */ 2472215976Sjmallett uint32_t goutnakeffmsk : 1; /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */ 2473215976Sjmallett uint32_t ginnakeffmsk : 1; /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */ 2474215976Sjmallett uint32_t nptxfempmsk : 1; /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */ 2475215976Sjmallett uint32_t rxflvlmsk : 1; /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */ 2476215976Sjmallett uint32_t sofmsk : 1; /**< Start of (micro)Frame Mask (SofMsk) */ 2477215976Sjmallett uint32_t otgintmsk : 1; /**< OTG Interrupt Mask (OTGIntMsk) */ 2478215976Sjmallett uint32_t modemismsk : 1; /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */ 2479215976Sjmallett uint32_t reserved_0_0 : 1; 2480215976Sjmallett#else 2481215976Sjmallett uint32_t reserved_0_0 : 1; 2482215976Sjmallett uint32_t modemismsk : 1; 2483215976Sjmallett uint32_t otgintmsk : 1; 2484215976Sjmallett uint32_t sofmsk : 1; 2485215976Sjmallett uint32_t rxflvlmsk : 1; 2486215976Sjmallett uint32_t nptxfempmsk : 1; 2487215976Sjmallett uint32_t ginnakeffmsk : 1; 2488215976Sjmallett uint32_t goutnakeffmsk : 1; 2489215976Sjmallett uint32_t ulpickintmsk : 1; 2490215976Sjmallett uint32_t i2cint : 1; 2491215976Sjmallett uint32_t erlysuspmsk : 1; 2492215976Sjmallett uint32_t usbsuspmsk : 1; 2493215976Sjmallett uint32_t usbrstmsk : 1; 2494215976Sjmallett uint32_t enumdonemsk : 1; 2495215976Sjmallett uint32_t isooutdropmsk : 1; 2496215976Sjmallett uint32_t eopfmsk : 1; 2497215976Sjmallett uint32_t reserved_16_16 : 1; 2498215976Sjmallett uint32_t epmismsk : 1; 2499215976Sjmallett uint32_t inepintmsk : 1; 2500215976Sjmallett uint32_t oepintmsk : 1; 2501215976Sjmallett uint32_t incompisoinmsk : 1; 2502215976Sjmallett uint32_t incomplpmsk : 1; 2503215976Sjmallett uint32_t fetsuspmsk : 1; 2504215976Sjmallett uint32_t reserved_23_23 : 1; 2505215976Sjmallett uint32_t prtintmsk : 1; 2506215976Sjmallett uint32_t hchintmsk : 1; 2507215976Sjmallett uint32_t ptxfempmsk : 1; 2508215976Sjmallett uint32_t reserved_27_27 : 1; 2509215976Sjmallett uint32_t conidstschngmsk : 1; 2510215976Sjmallett uint32_t disconnintmsk : 1; 2511215976Sjmallett uint32_t sessreqintmsk : 1; 2512215976Sjmallett uint32_t wkupintmsk : 1; 2513215976Sjmallett#endif 2514215976Sjmallett } s; 2515215976Sjmallett struct cvmx_usbcx_gintmsk_s cn30xx; 2516215976Sjmallett struct cvmx_usbcx_gintmsk_s cn31xx; 2517215976Sjmallett struct cvmx_usbcx_gintmsk_s cn50xx; 2518215976Sjmallett struct cvmx_usbcx_gintmsk_s cn52xx; 2519215976Sjmallett struct cvmx_usbcx_gintmsk_s cn52xxp1; 2520215976Sjmallett struct cvmx_usbcx_gintmsk_s cn56xx; 2521215976Sjmallett struct cvmx_usbcx_gintmsk_s cn56xxp1; 2522215976Sjmallett}; 2523215976Sjmalletttypedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t; 2524215976Sjmallett 2525215976Sjmallett/** 2526215976Sjmallett * cvmx_usbc#_gintsts 2527215976Sjmallett * 2528215976Sjmallett * Core Interrupt Register (GINTSTS) 2529215976Sjmallett * 2530215976Sjmallett * This register interrupts the application for system-level events in the current mode of operation 2531215976Sjmallett * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode, 2532215976Sjmallett * while others are valid in Device mode only. This register also indicates the current mode of operation. 2533215976Sjmallett * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit. 2534215976Sjmallett * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these 2535215976Sjmallett * interrupts, FIFO interrupt conditions are cleared automatically. 2536215976Sjmallett */ 2537215976Sjmallettunion cvmx_usbcx_gintsts 2538215976Sjmallett{ 2539215976Sjmallett uint32_t u32; 2540215976Sjmallett struct cvmx_usbcx_gintsts_s 2541215976Sjmallett { 2542215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2543215976Sjmallett uint32_t wkupint : 1; /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt) 2544215976Sjmallett In Device mode, this interrupt is asserted when a resume is 2545215976Sjmallett detected on the USB. In Host mode, this interrupt is asserted 2546215976Sjmallett when a remote wakeup is detected on the USB. 2547215976Sjmallett For more information on how to use this interrupt, see "Partial 2548215976Sjmallett Power-Down and Clock Gating Programming Model" on 2549215976Sjmallett page 353. */ 2550215976Sjmallett uint32_t sessreqint : 1; /**< Session Request/New Session Detected Interrupt (SessReqInt) 2551215976Sjmallett In Host mode, this interrupt is asserted when a session request 2552215976Sjmallett is detected from the device. In Device mode, this interrupt is 2553215976Sjmallett asserted when the utmiotg_bvalid signal goes high. 2554215976Sjmallett For more information on how to use this interrupt, see "Partial 2555215976Sjmallett Power-Down and Clock Gating Programming Model" on 2556215976Sjmallett page 353. */ 2557215976Sjmallett uint32_t disconnint : 1; /**< Disconnect Detected Interrupt (DisconnInt) 2558215976Sjmallett Asserted when a device disconnect is detected. */ 2559215976Sjmallett uint32_t conidstschng : 1; /**< Connector ID Status Change (ConIDStsChng) 2560215976Sjmallett The core sets this bit when there is a change in connector ID 2561215976Sjmallett status. */ 2562215976Sjmallett uint32_t reserved_27_27 : 1; 2563215976Sjmallett uint32_t ptxfemp : 1; /**< Periodic TxFIFO Empty (PTxFEmp) 2564215976Sjmallett Asserted when the Periodic Transmit FIFO is either half or 2565215976Sjmallett completely empty and there is space for at least one entry to be 2566215976Sjmallett written in the Periodic Request Queue. The half or completely 2567215976Sjmallett empty status is determined by the Periodic TxFIFO Empty Level 2568215976Sjmallett bit in the Core AHB Configuration register 2569215976Sjmallett (GAHBCFG.PTxFEmpLvl). */ 2570215976Sjmallett uint32_t hchint : 1; /**< Host Channels Interrupt (HChInt) 2571215976Sjmallett The core sets this bit to indicate that an interrupt is pending on 2572215976Sjmallett one of the channels of the core (in Host mode). The application 2573215976Sjmallett must read the Host All Channels Interrupt (HAINT) register to 2574215976Sjmallett determine the exact number of the channel on which the 2575215976Sjmallett interrupt occurred, and then read the corresponding Host 2576215976Sjmallett Channel-n Interrupt (HCINTn) register to determine the exact 2577215976Sjmallett cause of the interrupt. The application must clear the 2578215976Sjmallett appropriate status bit in the HCINTn register to clear this bit. */ 2579215976Sjmallett uint32_t prtint : 1; /**< Host Port Interrupt (PrtInt) 2580215976Sjmallett The core sets this bit to indicate a change in port status of one 2581215976Sjmallett of the O2P USB core ports in Host mode. The application must 2582215976Sjmallett read the Host Port Control and Status (HPRT) register to 2583215976Sjmallett determine the exact event that caused this interrupt. The 2584215976Sjmallett application must clear the appropriate status bit in the Host Port 2585215976Sjmallett Control and Status register to clear this bit. */ 2586215976Sjmallett uint32_t reserved_23_23 : 1; 2587215976Sjmallett uint32_t fetsusp : 1; /**< Data Fetch Suspended (FetSusp) 2588215976Sjmallett This interrupt is valid only in DMA mode. This interrupt indicates 2589215976Sjmallett that the core has stopped fetching data for IN endpoints due to 2590215976Sjmallett the unavailability of TxFIFO space or Request Queue space. 2591215976Sjmallett This interrupt is used by the application for an endpoint 2592215976Sjmallett mismatch algorithm. */ 2593215976Sjmallett uint32_t incomplp : 1; /**< Incomplete Periodic Transfer (incomplP) 2594215976Sjmallett In Host mode, the core sets this interrupt bit when there are 2595215976Sjmallett incomplete periodic transactions still pending which are 2596215976Sjmallett scheduled for the current microframe. 2597215976Sjmallett Incomplete Isochronous OUT Transfer (incompISOOUT) 2598215976Sjmallett The Device mode, the core sets this interrupt to indicate that 2599215976Sjmallett there is at least one isochronous OUT endpoint on which the 2600215976Sjmallett transfer is not completed in the current microframe. This 2601215976Sjmallett interrupt is asserted along with the End of Periodic Frame 2602215976Sjmallett Interrupt (EOPF) bit in this register. */ 2603215976Sjmallett uint32_t incompisoin : 1; /**< Incomplete Isochronous IN Transfer (incompISOIN) 2604215976Sjmallett The core sets this interrupt to indicate that there is at least one 2605215976Sjmallett isochronous IN endpoint on which the transfer is not completed 2606215976Sjmallett in the current microframe. This interrupt is asserted along with 2607215976Sjmallett the End of Periodic Frame Interrupt (EOPF) bit in this register. */ 2608215976Sjmallett uint32_t oepint : 1; /**< OUT Endpoints Interrupt (OEPInt) 2609215976Sjmallett The core sets this bit to indicate that an interrupt is pending on 2610215976Sjmallett one of the OUT endpoints of the core (in Device mode). The 2611215976Sjmallett application must read the Device All Endpoints Interrupt 2612215976Sjmallett (DAINT) register to determine the exact number of the OUT 2613215976Sjmallett endpoint on which the interrupt occurred, and then read the 2614215976Sjmallett corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) 2615215976Sjmallett register to determine the exact cause of the interrupt. The 2616215976Sjmallett application must clear the appropriate status bit in the 2617215976Sjmallett corresponding DOEPINTn register to clear this bit. */ 2618215976Sjmallett uint32_t iepint : 1; /**< IN Endpoints Interrupt (IEPInt) 2619215976Sjmallett The core sets this bit to indicate that an interrupt is pending on 2620215976Sjmallett one of the IN endpoints of the core (in Device mode). The 2621215976Sjmallett application must read the Device All Endpoints Interrupt 2622215976Sjmallett (DAINT) register to determine the exact number of the IN 2623215976Sjmallett endpoint on which the interrupt occurred, and then read the 2624215976Sjmallett corresponding Device IN Endpoint-n Interrupt (DIEPINTn) 2625215976Sjmallett register to determine the exact cause of the interrupt. The 2626215976Sjmallett application must clear the appropriate status bit in the 2627215976Sjmallett corresponding DIEPINTn register to clear this bit. */ 2628215976Sjmallett uint32_t epmis : 1; /**< Endpoint Mismatch Interrupt (EPMis) 2629215976Sjmallett Indicates that an IN token has been received for a non-periodic 2630215976Sjmallett endpoint, but the data for another endpoint is present in the top 2631215976Sjmallett of the Non-Periodic Transmit FIFO and the IN endpoint 2632215976Sjmallett mismatch count programmed by the application has expired. */ 2633215976Sjmallett uint32_t reserved_16_16 : 1; 2634215976Sjmallett uint32_t eopf : 1; /**< End of Periodic Frame Interrupt (EOPF) 2635215976Sjmallett Indicates that the period specified in the Periodic Frame Interval 2636215976Sjmallett field of the Device Configuration register (DCFG.PerFrInt) has 2637215976Sjmallett been reached in the current microframe. */ 2638215976Sjmallett uint32_t isooutdrop : 1; /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) 2639215976Sjmallett The core sets this bit when it fails to write an isochronous OUT 2640215976Sjmallett packet into the RxFIFO because the RxFIFO doesn't have 2641215976Sjmallett enough space to accommodate a maximum packet size packet 2642215976Sjmallett for the isochronous OUT endpoint. */ 2643215976Sjmallett uint32_t enumdone : 1; /**< Enumeration Done (EnumDone) 2644215976Sjmallett The core sets this bit to indicate that speed enumeration is 2645215976Sjmallett complete. The application must read the Device Status (DSTS) 2646215976Sjmallett register to obtain the enumerated speed. */ 2647215976Sjmallett uint32_t usbrst : 1; /**< USB Reset (USBRst) 2648215976Sjmallett The core sets this bit to indicate that a reset is detected on the 2649215976Sjmallett USB. */ 2650215976Sjmallett uint32_t usbsusp : 1; /**< USB Suspend (USBSusp) 2651215976Sjmallett The core sets this bit to indicate that a suspend was detected 2652215976Sjmallett on the USB. The core enters the Suspended state when there 2653215976Sjmallett is no activity on the phy_line_state_i signal for an extended 2654215976Sjmallett period of time. */ 2655215976Sjmallett uint32_t erlysusp : 1; /**< Early Suspend (ErlySusp) 2656215976Sjmallett The core sets this bit to indicate that an Idle state has been 2657215976Sjmallett detected on the USB for 3 ms. */ 2658215976Sjmallett uint32_t i2cint : 1; /**< I2C Interrupt (I2CINT) 2659215976Sjmallett This bit is always 0x0. */ 2660215976Sjmallett uint32_t ulpickint : 1; /**< ULPI Carkit Interrupt (ULPICKINT) 2661215976Sjmallett This bit is always 0x0. */ 2662215976Sjmallett uint32_t goutnakeff : 1; /**< Global OUT NAK Effective (GOUTNakEff) 2663215976Sjmallett Indicates that the Set Global OUT NAK bit in the Device Control 2664215976Sjmallett register (DCTL.SGOUTNak), set by the application, has taken 2665215976Sjmallett effect in the core. This bit can be cleared by writing the Clear 2666215976Sjmallett Global OUT NAK bit in the Device Control register 2667215976Sjmallett (DCTL.CGOUTNak). */ 2668215976Sjmallett uint32_t ginnakeff : 1; /**< Global IN Non-Periodic NAK Effective (GINNakEff) 2669215976Sjmallett Indicates that the Set Global Non-Periodic IN NAK bit in the 2670215976Sjmallett Device Control register (DCTL.SGNPInNak), set by the 2671215976Sjmallett application, has taken effect in the core. That is, the core has 2672215976Sjmallett sampled the Global IN NAK bit set by the application. This bit 2673215976Sjmallett can be cleared by clearing the Clear Global Non-Periodic IN 2674215976Sjmallett NAK bit in the Device Control register (DCTL.CGNPInNak). 2675215976Sjmallett This interrupt does not necessarily mean that a NAK handshake 2676215976Sjmallett is sent out on the USB. The STALL bit takes precedence over 2677215976Sjmallett the NAK bit. */ 2678215976Sjmallett uint32_t nptxfemp : 1; /**< Non-Periodic TxFIFO Empty (NPTxFEmp) 2679215976Sjmallett This interrupt is asserted when the Non-Periodic TxFIFO is 2680215976Sjmallett either half or completely empty, and there is space for at least 2681215976Sjmallett one entry to be written to the Non-Periodic Transmit Request 2682215976Sjmallett Queue. The half or completely empty status is determined by 2683215976Sjmallett the Non-Periodic TxFIFO Empty Level bit in the Core AHB 2684215976Sjmallett Configuration register (GAHBCFG.NPTxFEmpLvl). */ 2685215976Sjmallett uint32_t rxflvl : 1; /**< RxFIFO Non-Empty (RxFLvl) 2686215976Sjmallett Indicates that there is at least one packet pending to be read 2687215976Sjmallett from the RxFIFO. */ 2688215976Sjmallett uint32_t sof : 1; /**< Start of (micro)Frame (Sof) 2689215976Sjmallett In Host mode, the core sets this bit to indicate that an SOF 2690215976Sjmallett (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the 2691215976Sjmallett USB. The application must write a 1 to this bit to clear the 2692215976Sjmallett interrupt. 2693215976Sjmallett In Device mode, in the core sets this bit to indicate that an SOF 2694215976Sjmallett token has been received on the USB. The application can read 2695215976Sjmallett the Device Status register to get the current (micro)frame 2696215976Sjmallett number. This interrupt is seen only when the core is operating 2697215976Sjmallett at either HS or FS. */ 2698215976Sjmallett uint32_t otgint : 1; /**< OTG Interrupt (OTGInt) 2699215976Sjmallett The core sets this bit to indicate an OTG protocol event. The 2700215976Sjmallett application must read the OTG Interrupt Status (GOTGINT) 2701215976Sjmallett register to determine the exact event that caused this interrupt. 2702215976Sjmallett The application must clear the appropriate status bit in the 2703215976Sjmallett GOTGINT register to clear this bit. */ 2704215976Sjmallett uint32_t modemis : 1; /**< Mode Mismatch Interrupt (ModeMis) 2705215976Sjmallett The core sets this bit when the application is trying to access: 2706215976Sjmallett * A Host mode register, when the core is operating in Device 2707215976Sjmallett mode 2708215976Sjmallett * A Device mode register, when the core is operating in Host 2709215976Sjmallett mode 2710215976Sjmallett The register access is completed on the AHB with an OKAY 2711215976Sjmallett response, but is ignored by the core internally and doesn't 2712215976Sjmallett affect the operation of the core. */ 2713215976Sjmallett uint32_t curmod : 1; /**< Current Mode of Operation (CurMod) 2714215976Sjmallett Indicates the current mode of operation. 2715215976Sjmallett * 1'b0: Device mode 2716215976Sjmallett * 1'b1: Host mode */ 2717215976Sjmallett#else 2718215976Sjmallett uint32_t curmod : 1; 2719215976Sjmallett uint32_t modemis : 1; 2720215976Sjmallett uint32_t otgint : 1; 2721215976Sjmallett uint32_t sof : 1; 2722215976Sjmallett uint32_t rxflvl : 1; 2723215976Sjmallett uint32_t nptxfemp : 1; 2724215976Sjmallett uint32_t ginnakeff : 1; 2725215976Sjmallett uint32_t goutnakeff : 1; 2726215976Sjmallett uint32_t ulpickint : 1; 2727215976Sjmallett uint32_t i2cint : 1; 2728215976Sjmallett uint32_t erlysusp : 1; 2729215976Sjmallett uint32_t usbsusp : 1; 2730215976Sjmallett uint32_t usbrst : 1; 2731215976Sjmallett uint32_t enumdone : 1; 2732215976Sjmallett uint32_t isooutdrop : 1; 2733215976Sjmallett uint32_t eopf : 1; 2734215976Sjmallett uint32_t reserved_16_16 : 1; 2735215976Sjmallett uint32_t epmis : 1; 2736215976Sjmallett uint32_t iepint : 1; 2737215976Sjmallett uint32_t oepint : 1; 2738215976Sjmallett uint32_t incompisoin : 1; 2739215976Sjmallett uint32_t incomplp : 1; 2740215976Sjmallett uint32_t fetsusp : 1; 2741215976Sjmallett uint32_t reserved_23_23 : 1; 2742215976Sjmallett uint32_t prtint : 1; 2743215976Sjmallett uint32_t hchint : 1; 2744215976Sjmallett uint32_t ptxfemp : 1; 2745215976Sjmallett uint32_t reserved_27_27 : 1; 2746215976Sjmallett uint32_t conidstschng : 1; 2747215976Sjmallett uint32_t disconnint : 1; 2748215976Sjmallett uint32_t sessreqint : 1; 2749215976Sjmallett uint32_t wkupint : 1; 2750215976Sjmallett#endif 2751215976Sjmallett } s; 2752215976Sjmallett struct cvmx_usbcx_gintsts_s cn30xx; 2753215976Sjmallett struct cvmx_usbcx_gintsts_s cn31xx; 2754215976Sjmallett struct cvmx_usbcx_gintsts_s cn50xx; 2755215976Sjmallett struct cvmx_usbcx_gintsts_s cn52xx; 2756215976Sjmallett struct cvmx_usbcx_gintsts_s cn52xxp1; 2757215976Sjmallett struct cvmx_usbcx_gintsts_s cn56xx; 2758215976Sjmallett struct cvmx_usbcx_gintsts_s cn56xxp1; 2759215976Sjmallett}; 2760215976Sjmalletttypedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t; 2761215976Sjmallett 2762215976Sjmallett/** 2763215976Sjmallett * cvmx_usbc#_gnptxfsiz 2764215976Sjmallett * 2765215976Sjmallett * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ) 2766215976Sjmallett * 2767215976Sjmallett * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO. 2768215976Sjmallett */ 2769215976Sjmallettunion cvmx_usbcx_gnptxfsiz 2770215976Sjmallett{ 2771215976Sjmallett uint32_t u32; 2772215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s 2773215976Sjmallett { 2774215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2775215976Sjmallett uint32_t nptxfdep : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep) 2776215976Sjmallett This value is in terms of 32-bit words. 2777215976Sjmallett Minimum value is 16 2778215976Sjmallett Maximum value is 32768 */ 2779215976Sjmallett uint32_t nptxfstaddr : 16; /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr) 2780215976Sjmallett This field contains the memory start address for Non-Periodic 2781215976Sjmallett Transmit FIFO RAM. */ 2782215976Sjmallett#else 2783215976Sjmallett uint32_t nptxfstaddr : 16; 2784215976Sjmallett uint32_t nptxfdep : 16; 2785215976Sjmallett#endif 2786215976Sjmallett } s; 2787215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn30xx; 2788215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn31xx; 2789215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn50xx; 2790215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn52xx; 2791215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn52xxp1; 2792215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn56xx; 2793215976Sjmallett struct cvmx_usbcx_gnptxfsiz_s cn56xxp1; 2794215976Sjmallett}; 2795215976Sjmalletttypedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t; 2796215976Sjmallett 2797215976Sjmallett/** 2798215976Sjmallett * cvmx_usbc#_gnptxsts 2799215976Sjmallett * 2800215976Sjmallett * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) 2801215976Sjmallett * 2802215976Sjmallett * This read-only register contains the free space information for the Non-Periodic TxFIFO and 2803215976Sjmallett * the Non-Periodic Transmit Request Queue 2804215976Sjmallett */ 2805215976Sjmallettunion cvmx_usbcx_gnptxsts 2806215976Sjmallett{ 2807215976Sjmallett uint32_t u32; 2808215976Sjmallett struct cvmx_usbcx_gnptxsts_s 2809215976Sjmallett { 2810215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2811215976Sjmallett uint32_t reserved_31_31 : 1; 2812215976Sjmallett uint32_t nptxqtop : 7; /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop) 2813215976Sjmallett Entry in the Non-Periodic Tx Request Queue that is currently 2814215976Sjmallett being processed by the MAC. 2815215976Sjmallett * Bits [30:27]: Channel/endpoint number 2816215976Sjmallett * Bits [26:25]: 2817215976Sjmallett - 2'b00: IN/OUT token 2818215976Sjmallett - 2'b01: Zero-length transmit packet (device IN/host OUT) 2819215976Sjmallett - 2'b10: PING/CSPLIT token 2820215976Sjmallett - 2'b11: Channel halt command 2821215976Sjmallett * Bit [24]: Terminate (last entry for selected channel/endpoint) */ 2822215976Sjmallett uint32_t nptxqspcavail : 8; /**< Non-Periodic Transmit Request Queue Space Available 2823215976Sjmallett (NPTxQSpcAvail) 2824215976Sjmallett Indicates the amount of free space available in the Non- 2825215976Sjmallett Periodic Transmit Request Queue. This queue holds both IN 2826215976Sjmallett and OUT requests in Host mode. Device mode has only IN 2827215976Sjmallett requests. 2828215976Sjmallett * 8'h0: Non-Periodic Transmit Request Queue is full 2829215976Sjmallett * 8'h1: 1 location available 2830215976Sjmallett * 8'h2: 2 locations available 2831215976Sjmallett * n: n locations available (0..8) 2832215976Sjmallett * Others: Reserved */ 2833215976Sjmallett uint32_t nptxfspcavail : 16; /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail) 2834215976Sjmallett Indicates the amount of free space available in the Non- 2835215976Sjmallett Periodic TxFIFO. 2836215976Sjmallett Values are in terms of 32-bit words. 2837215976Sjmallett * 16'h0: Non-Periodic TxFIFO is full 2838215976Sjmallett * 16'h1: 1 word available 2839215976Sjmallett * 16'h2: 2 words available 2840215976Sjmallett * 16'hn: n words available (where 0..32768) 2841215976Sjmallett * 16'h8000: 32768 words available 2842215976Sjmallett * Others: Reserved */ 2843215976Sjmallett#else 2844215976Sjmallett uint32_t nptxfspcavail : 16; 2845215976Sjmallett uint32_t nptxqspcavail : 8; 2846215976Sjmallett uint32_t nptxqtop : 7; 2847215976Sjmallett uint32_t reserved_31_31 : 1; 2848215976Sjmallett#endif 2849215976Sjmallett } s; 2850215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn30xx; 2851215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn31xx; 2852215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn50xx; 2853215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn52xx; 2854215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn52xxp1; 2855215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn56xx; 2856215976Sjmallett struct cvmx_usbcx_gnptxsts_s cn56xxp1; 2857215976Sjmallett}; 2858215976Sjmalletttypedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t; 2859215976Sjmallett 2860215976Sjmallett/** 2861215976Sjmallett * cvmx_usbc#_gotgctl 2862215976Sjmallett * 2863215976Sjmallett * OTG Control and Status Register (GOTGCTL) 2864215976Sjmallett * 2865215976Sjmallett * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.: 2866215976Sjmallett */ 2867215976Sjmallettunion cvmx_usbcx_gotgctl 2868215976Sjmallett{ 2869215976Sjmallett uint32_t u32; 2870215976Sjmallett struct cvmx_usbcx_gotgctl_s 2871215976Sjmallett { 2872215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2873215976Sjmallett uint32_t reserved_20_31 : 12; 2874215976Sjmallett uint32_t bsesvld : 1; /**< B-Session Valid (BSesVld) 2875215976Sjmallett Valid only when O2P USB core is configured as a USB device. 2876215976Sjmallett Indicates the Device mode transceiver status. 2877215976Sjmallett * 1'b0: B-session is not valid. 2878215976Sjmallett * 1'b1: B-session is valid. */ 2879215976Sjmallett uint32_t asesvld : 1; /**< A-Session Valid (ASesVld) 2880215976Sjmallett Valid only when O2P USB core is configured as a USB host. 2881215976Sjmallett Indicates the Host mode transceiver status. 2882215976Sjmallett * 1'b0: A-session is not valid 2883215976Sjmallett * 1'b1: A-session is valid */ 2884215976Sjmallett uint32_t dbnctime : 1; /**< Long/Short Debounce Time (DbncTime) 2885215976Sjmallett In the present version of the core this bit will only read as '0'. */ 2886215976Sjmallett uint32_t conidsts : 1; /**< Connector ID Status (ConIDSts) 2887215976Sjmallett Indicates the connector ID status on a connect event. 2888215976Sjmallett * 1'b0: The O2P USB core is in A-device mode 2889215976Sjmallett * 1'b1: The O2P USB core is in B-device mode */ 2890215976Sjmallett uint32_t reserved_12_15 : 4; 2891215976Sjmallett uint32_t devhnpen : 1; /**< Device HNP Enabled (DevHNPEn) 2892215976Sjmallett Since O2P USB core is not HNP capable this bit is 0x0. */ 2893215976Sjmallett uint32_t hstsethnpen : 1; /**< Host Set HNP Enable (HstSetHNPEn) 2894215976Sjmallett Since O2P USB core is not HNP capable this bit is 0x0. */ 2895215976Sjmallett uint32_t hnpreq : 1; /**< HNP Request (HNPReq) 2896215976Sjmallett Since O2P USB core is not HNP capable this bit is 0x0. */ 2897215976Sjmallett uint32_t hstnegscs : 1; /**< Host Negotiation Success (HstNegScs) 2898215976Sjmallett Since O2P USB core is not HNP capable this bit is 0x0. */ 2899215976Sjmallett uint32_t reserved_2_7 : 6; 2900215976Sjmallett uint32_t sesreq : 1; /**< Session Request (SesReq) 2901215976Sjmallett Since O2P USB core is not SRP capable this bit is 0x0. */ 2902215976Sjmallett uint32_t sesreqscs : 1; /**< Session Request Success (SesReqScs) 2903215976Sjmallett Since O2P USB core is not SRP capable this bit is 0x0. */ 2904215976Sjmallett#else 2905215976Sjmallett uint32_t sesreqscs : 1; 2906215976Sjmallett uint32_t sesreq : 1; 2907215976Sjmallett uint32_t reserved_2_7 : 6; 2908215976Sjmallett uint32_t hstnegscs : 1; 2909215976Sjmallett uint32_t hnpreq : 1; 2910215976Sjmallett uint32_t hstsethnpen : 1; 2911215976Sjmallett uint32_t devhnpen : 1; 2912215976Sjmallett uint32_t reserved_12_15 : 4; 2913215976Sjmallett uint32_t conidsts : 1; 2914215976Sjmallett uint32_t dbnctime : 1; 2915215976Sjmallett uint32_t asesvld : 1; 2916215976Sjmallett uint32_t bsesvld : 1; 2917215976Sjmallett uint32_t reserved_20_31 : 12; 2918215976Sjmallett#endif 2919215976Sjmallett } s; 2920215976Sjmallett struct cvmx_usbcx_gotgctl_s cn30xx; 2921215976Sjmallett struct cvmx_usbcx_gotgctl_s cn31xx; 2922215976Sjmallett struct cvmx_usbcx_gotgctl_s cn50xx; 2923215976Sjmallett struct cvmx_usbcx_gotgctl_s cn52xx; 2924215976Sjmallett struct cvmx_usbcx_gotgctl_s cn52xxp1; 2925215976Sjmallett struct cvmx_usbcx_gotgctl_s cn56xx; 2926215976Sjmallett struct cvmx_usbcx_gotgctl_s cn56xxp1; 2927215976Sjmallett}; 2928215976Sjmalletttypedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t; 2929215976Sjmallett 2930215976Sjmallett/** 2931215976Sjmallett * cvmx_usbc#_gotgint 2932215976Sjmallett * 2933215976Sjmallett * OTG Interrupt Register (GOTGINT) 2934215976Sjmallett * 2935215976Sjmallett * The application reads this register whenever there is an OTG interrupt and clears the bits in this register 2936215976Sjmallett * to clear the OTG interrupt. It is shown in Interrupt .: 2937215976Sjmallett */ 2938215976Sjmallettunion cvmx_usbcx_gotgint 2939215976Sjmallett{ 2940215976Sjmallett uint32_t u32; 2941215976Sjmallett struct cvmx_usbcx_gotgint_s 2942215976Sjmallett { 2943215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2944215976Sjmallett uint32_t reserved_20_31 : 12; 2945215976Sjmallett uint32_t dbncedone : 1; /**< Debounce Done (DbnceDone) 2946215976Sjmallett In the present version of the code this bit is tied to '0'. */ 2947215976Sjmallett uint32_t adevtoutchg : 1; /**< A-Device Timeout Change (ADevTOUTChg) 2948215976Sjmallett Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2949215976Sjmallett uint32_t hstnegdet : 1; /**< Host Negotiation Detected (HstNegDet) 2950215976Sjmallett Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2951215976Sjmallett uint32_t reserved_10_16 : 7; 2952215976Sjmallett uint32_t hstnegsucstschng : 1; /**< Host Negotiation Success Status Change (HstNegSucStsChng) 2953215976Sjmallett Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2954215976Sjmallett uint32_t sesreqsucstschng : 1; /**< Session Request Success Status Change 2955215976Sjmallett Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2956215976Sjmallett uint32_t reserved_3_7 : 5; 2957215976Sjmallett uint32_t sesenddet : 1; /**< Session End Detected (SesEndDet) 2958215976Sjmallett Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2959215976Sjmallett uint32_t reserved_0_1 : 2; 2960215976Sjmallett#else 2961215976Sjmallett uint32_t reserved_0_1 : 2; 2962215976Sjmallett uint32_t sesenddet : 1; 2963215976Sjmallett uint32_t reserved_3_7 : 5; 2964215976Sjmallett uint32_t sesreqsucstschng : 1; 2965215976Sjmallett uint32_t hstnegsucstschng : 1; 2966215976Sjmallett uint32_t reserved_10_16 : 7; 2967215976Sjmallett uint32_t hstnegdet : 1; 2968215976Sjmallett uint32_t adevtoutchg : 1; 2969215976Sjmallett uint32_t dbncedone : 1; 2970215976Sjmallett uint32_t reserved_20_31 : 12; 2971215976Sjmallett#endif 2972215976Sjmallett } s; 2973215976Sjmallett struct cvmx_usbcx_gotgint_s cn30xx; 2974215976Sjmallett struct cvmx_usbcx_gotgint_s cn31xx; 2975215976Sjmallett struct cvmx_usbcx_gotgint_s cn50xx; 2976215976Sjmallett struct cvmx_usbcx_gotgint_s cn52xx; 2977215976Sjmallett struct cvmx_usbcx_gotgint_s cn52xxp1; 2978215976Sjmallett struct cvmx_usbcx_gotgint_s cn56xx; 2979215976Sjmallett struct cvmx_usbcx_gotgint_s cn56xxp1; 2980215976Sjmallett}; 2981215976Sjmalletttypedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t; 2982215976Sjmallett 2983215976Sjmallett/** 2984215976Sjmallett * cvmx_usbc#_grstctl 2985215976Sjmallett * 2986215976Sjmallett * Core Reset Register (GRSTCTL) 2987215976Sjmallett * 2988215976Sjmallett * The application uses this register to reset various hardware features inside the core. 2989215976Sjmallett */ 2990215976Sjmallettunion cvmx_usbcx_grstctl 2991215976Sjmallett{ 2992215976Sjmallett uint32_t u32; 2993215976Sjmallett struct cvmx_usbcx_grstctl_s 2994215976Sjmallett { 2995215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2996215976Sjmallett uint32_t ahbidle : 1; /**< AHB Master Idle (AHBIdle) 2997215976Sjmallett Indicates that the AHB Master State Machine is in the IDLE 2998215976Sjmallett condition. */ 2999215976Sjmallett uint32_t dmareq : 1; /**< DMA Request Signal (DMAReq) 3000215976Sjmallett Indicates that the DMA request is in progress. Used for debug. */ 3001215976Sjmallett uint32_t reserved_11_29 : 19; 3002215976Sjmallett uint32_t txfnum : 5; /**< TxFIFO Number (TxFNum) 3003215976Sjmallett This is the FIFO number that must be flushed using the TxFIFO 3004215976Sjmallett Flush bit. This field must not be changed until the core clears 3005215976Sjmallett the TxFIFO Flush bit. 3006215976Sjmallett * 5'h0: Non-Periodic TxFIFO flush 3007215976Sjmallett * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic 3008215976Sjmallett TxFIFO flush in Host mode 3009215976Sjmallett * 5'h2: Periodic TxFIFO 2 flush in Device mode 3010215976Sjmallett - ... 3011215976Sjmallett * 5'hF: Periodic TxFIFO 15 flush in Device mode 3012215976Sjmallett * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the 3013215976Sjmallett core */ 3014215976Sjmallett uint32_t txfflsh : 1; /**< TxFIFO Flush (TxFFlsh) 3015215976Sjmallett This bit selectively flushes a single or all transmit FIFOs, but 3016215976Sjmallett cannot do so if the core is in the midst of a transaction. 3017215976Sjmallett The application must only write this bit after checking that the 3018215976Sjmallett core is neither writing to the TxFIFO nor reading from the 3019215976Sjmallett TxFIFO. 3020215976Sjmallett The application must wait until the core clears this bit before 3021215976Sjmallett performing any operations. This bit takes 8 clocks (of phy_clk or 3022215976Sjmallett hclk, whichever is slower) to clear. */ 3023215976Sjmallett uint32_t rxfflsh : 1; /**< RxFIFO Flush (RxFFlsh) 3024215976Sjmallett The application can flush the entire RxFIFO using this bit, but 3025215976Sjmallett must first ensure that the core is not in the middle of a 3026215976Sjmallett transaction. 3027215976Sjmallett The application must only write to this bit after checking that the 3028215976Sjmallett core is neither reading from the RxFIFO nor writing to the 3029215976Sjmallett RxFIFO. 3030215976Sjmallett The application must wait until the bit is cleared before 3031215976Sjmallett performing any other operations. This bit will take 8 clocks 3032215976Sjmallett (slowest of PHY or AHB clock) to clear. */ 3033215976Sjmallett uint32_t intknqflsh : 1; /**< IN Token Sequence Learning Queue Flush (INTknQFlsh) 3034215976Sjmallett The application writes this bit to flush the IN Token Sequence 3035215976Sjmallett Learning Queue. */ 3036215976Sjmallett uint32_t frmcntrrst : 1; /**< Host Frame Counter Reset (FrmCntrRst) 3037215976Sjmallett The application writes this bit to reset the (micro)frame number 3038215976Sjmallett counter inside the core. When the (micro)frame counter is reset, 3039215976Sjmallett the subsequent SOF sent out by the core will have a 3040215976Sjmallett (micro)frame number of 0. */ 3041215976Sjmallett uint32_t hsftrst : 1; /**< HClk Soft Reset (HSftRst) 3042215976Sjmallett The application uses this bit to flush the control logic in the AHB 3043215976Sjmallett Clock domain. Only AHB Clock Domain pipelines are reset. 3044215976Sjmallett * FIFOs are not flushed with this bit. 3045215976Sjmallett * All state machines in the AHB clock domain are reset to the 3046215976Sjmallett Idle state after terminating the transactions on the AHB, 3047215976Sjmallett following the protocol. 3048215976Sjmallett * CSR control bits used by the AHB clock domain state 3049215976Sjmallett machines are cleared. 3050215976Sjmallett * To clear this interrupt, status mask bits that control the 3051215976Sjmallett interrupt status and are generated by the AHB clock domain 3052215976Sjmallett state machine are cleared. 3053215976Sjmallett * Because interrupt status bits are not cleared, the application 3054215976Sjmallett can get the status of any core events that occurred after it set 3055215976Sjmallett this bit. 3056215976Sjmallett This is a self-clearing bit that the core clears after all necessary 3057215976Sjmallett logic is reset in the core. This may take several clocks, 3058215976Sjmallett depending on the core's current state. */ 3059215976Sjmallett uint32_t csftrst : 1; /**< Core Soft Reset (CSftRst) 3060215976Sjmallett Resets the hclk and phy_clock domains as follows: 3061215976Sjmallett * Clears the interrupts and all the CSR registers except the 3062215976Sjmallett following register bits: 3063215976Sjmallett - PCGCCTL.RstPdwnModule 3064215976Sjmallett - PCGCCTL.GateHclk 3065215976Sjmallett - PCGCCTL.PwrClmp 3066215976Sjmallett - PCGCCTL.StopPPhyLPwrClkSelclk 3067215976Sjmallett - GUSBCFG.PhyLPwrClkSel 3068215976Sjmallett - GUSBCFG.DDRSel 3069215976Sjmallett - GUSBCFG.PHYSel 3070215976Sjmallett - GUSBCFG.FSIntf 3071215976Sjmallett - GUSBCFG.ULPI_UTMI_Sel 3072215976Sjmallett - GUSBCFG.PHYIf 3073215976Sjmallett - HCFG.FSLSPclkSel 3074215976Sjmallett - DCFG.DevSpd 3075215976Sjmallett * All module state machines (except the AHB Slave Unit) are 3076215976Sjmallett reset to the IDLE state, and all the transmit FIFOs and the 3077215976Sjmallett receive FIFO are flushed. 3078215976Sjmallett * Any transactions on the AHB Master are terminated as soon 3079215976Sjmallett as possible, after gracefully completing the last data phase of 3080215976Sjmallett an AHB transfer. Any transactions on the USB are terminated 3081215976Sjmallett immediately. 3082215976Sjmallett The application can write to this bit any time it wants to reset 3083215976Sjmallett the core. This is a self-clearing bit and the core clears this bit 3084215976Sjmallett after all the necessary logic is reset in the core, which may take 3085215976Sjmallett several clocks, depending on the current state of the core. 3086215976Sjmallett Once this bit is cleared software should wait at least 3 PHY 3087215976Sjmallett clocks before doing any access to the PHY domain 3088215976Sjmallett (synchronization delay). Software should also should check that 3089215976Sjmallett bit 31 of this register is 1 (AHB Master is IDLE) before starting 3090215976Sjmallett any operation. 3091215976Sjmallett Typically software reset is used during software development 3092215976Sjmallett and also when you dynamically change the PHY selection bits 3093215976Sjmallett in the USB configuration registers listed above. When you 3094215976Sjmallett change the PHY, the corresponding clock for the PHY is 3095215976Sjmallett selected and used in the PHY domain. Once a new clock is 3096215976Sjmallett selected, the PHY domain has to be reset for proper operation. */ 3097215976Sjmallett#else 3098215976Sjmallett uint32_t csftrst : 1; 3099215976Sjmallett uint32_t hsftrst : 1; 3100215976Sjmallett uint32_t frmcntrrst : 1; 3101215976Sjmallett uint32_t intknqflsh : 1; 3102215976Sjmallett uint32_t rxfflsh : 1; 3103215976Sjmallett uint32_t txfflsh : 1; 3104215976Sjmallett uint32_t txfnum : 5; 3105215976Sjmallett uint32_t reserved_11_29 : 19; 3106215976Sjmallett uint32_t dmareq : 1; 3107215976Sjmallett uint32_t ahbidle : 1; 3108215976Sjmallett#endif 3109215976Sjmallett } s; 3110215976Sjmallett struct cvmx_usbcx_grstctl_s cn30xx; 3111215976Sjmallett struct cvmx_usbcx_grstctl_s cn31xx; 3112215976Sjmallett struct cvmx_usbcx_grstctl_s cn50xx; 3113215976Sjmallett struct cvmx_usbcx_grstctl_s cn52xx; 3114215976Sjmallett struct cvmx_usbcx_grstctl_s cn52xxp1; 3115215976Sjmallett struct cvmx_usbcx_grstctl_s cn56xx; 3116215976Sjmallett struct cvmx_usbcx_grstctl_s cn56xxp1; 3117215976Sjmallett}; 3118215976Sjmalletttypedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t; 3119215976Sjmallett 3120215976Sjmallett/** 3121215976Sjmallett * cvmx_usbc#_grxfsiz 3122215976Sjmallett * 3123215976Sjmallett * Receive FIFO Size Register (GRXFSIZ) 3124215976Sjmallett * 3125215976Sjmallett * The application can program the RAM size that must be allocated to the RxFIFO. 3126215976Sjmallett */ 3127215976Sjmallettunion cvmx_usbcx_grxfsiz 3128215976Sjmallett{ 3129215976Sjmallett uint32_t u32; 3130215976Sjmallett struct cvmx_usbcx_grxfsiz_s 3131215976Sjmallett { 3132215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3133215976Sjmallett uint32_t reserved_16_31 : 16; 3134215976Sjmallett uint32_t rxfdep : 16; /**< RxFIFO Depth (RxFDep) 3135215976Sjmallett This value is in terms of 32-bit words. 3136215976Sjmallett * Minimum value is 16 3137215976Sjmallett * Maximum value is 32768 */ 3138215976Sjmallett#else 3139215976Sjmallett uint32_t rxfdep : 16; 3140215976Sjmallett uint32_t reserved_16_31 : 16; 3141215976Sjmallett#endif 3142215976Sjmallett } s; 3143215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn30xx; 3144215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn31xx; 3145215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn50xx; 3146215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn52xx; 3147215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn52xxp1; 3148215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn56xx; 3149215976Sjmallett struct cvmx_usbcx_grxfsiz_s cn56xxp1; 3150215976Sjmallett}; 3151215976Sjmalletttypedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t; 3152215976Sjmallett 3153215976Sjmallett/** 3154215976Sjmallett * cvmx_usbc#_grxstspd 3155215976Sjmallett * 3156215976Sjmallett * Receive Status Debug Read Register, Device Mode (GRXSTSPD) 3157215976Sjmallett * 3158215976Sjmallett * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO. 3159215976Sjmallett * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSPH instead. 3160215976Sjmallett * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core. 3161215976Sjmallett * The offset difference shown in this document is for software clarity and is actually ignored by the 3162215976Sjmallett * hardware. 3163215976Sjmallett */ 3164215976Sjmallettunion cvmx_usbcx_grxstspd 3165215976Sjmallett{ 3166215976Sjmallett uint32_t u32; 3167215976Sjmallett struct cvmx_usbcx_grxstspd_s 3168215976Sjmallett { 3169215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3170215976Sjmallett uint32_t reserved_25_31 : 7; 3171215976Sjmallett uint32_t fn : 4; /**< Frame Number (FN) 3172215976Sjmallett This is the least significant 4 bits of the (micro)frame number in 3173215976Sjmallett which the packet is received on the USB. This field is supported 3174215976Sjmallett only when the isochronous OUT endpoints are supported. */ 3175215976Sjmallett uint32_t pktsts : 4; /**< Packet Status (PktSts) 3176215976Sjmallett Indicates the status of the received packet 3177215976Sjmallett * 4'b0001: Glogal OUT NAK (triggers an interrupt) 3178215976Sjmallett * 4'b0010: OUT data packet received 3179215976Sjmallett * 4'b0100: SETUP transaction completed (triggers an interrupt) 3180215976Sjmallett * 4'b0110: SETUP data packet received 3181215976Sjmallett * Others: Reserved */ 3182215976Sjmallett uint32_t dpid : 2; /**< Data PID (DPID) 3183215976Sjmallett * 2'b00: DATA0 3184215976Sjmallett * 2'b10: DATA1 3185215976Sjmallett * 2'b01: DATA2 3186215976Sjmallett * 2'b11: MDATA */ 3187215976Sjmallett uint32_t bcnt : 11; /**< Byte Count (BCnt) 3188215976Sjmallett Indicates the byte count of the received data packet */ 3189215976Sjmallett uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3190215976Sjmallett Indicates the endpoint number to which the current received 3191215976Sjmallett packet belongs. */ 3192215976Sjmallett#else 3193215976Sjmallett uint32_t epnum : 4; 3194215976Sjmallett uint32_t bcnt : 11; 3195215976Sjmallett uint32_t dpid : 2; 3196215976Sjmallett uint32_t pktsts : 4; 3197215976Sjmallett uint32_t fn : 4; 3198215976Sjmallett uint32_t reserved_25_31 : 7; 3199215976Sjmallett#endif 3200215976Sjmallett } s; 3201215976Sjmallett struct cvmx_usbcx_grxstspd_s cn30xx; 3202215976Sjmallett struct cvmx_usbcx_grxstspd_s cn31xx; 3203215976Sjmallett struct cvmx_usbcx_grxstspd_s cn50xx; 3204215976Sjmallett struct cvmx_usbcx_grxstspd_s cn52xx; 3205215976Sjmallett struct cvmx_usbcx_grxstspd_s cn52xxp1; 3206215976Sjmallett struct cvmx_usbcx_grxstspd_s cn56xx; 3207215976Sjmallett struct cvmx_usbcx_grxstspd_s cn56xxp1; 3208215976Sjmallett}; 3209215976Sjmalletttypedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t; 3210215976Sjmallett 3211215976Sjmallett/** 3212215976Sjmallett * cvmx_usbc#_grxstsph 3213215976Sjmallett * 3214215976Sjmallett * Receive Status Read and Pop Register, Host Mode (GRXSTSPH) 3215215976Sjmallett * 3216215976Sjmallett * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO. 3217215976Sjmallett * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSPD instead. 3218215976Sjmallett * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core. 3219215976Sjmallett * The offset difference shown in this document is for software clarity and is actually ignored by the 3220215976Sjmallett * hardware. 3221215976Sjmallett */ 3222215976Sjmallettunion cvmx_usbcx_grxstsph 3223215976Sjmallett{ 3224215976Sjmallett uint32_t u32; 3225215976Sjmallett struct cvmx_usbcx_grxstsph_s 3226215976Sjmallett { 3227215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3228215976Sjmallett uint32_t reserved_21_31 : 11; 3229215976Sjmallett uint32_t pktsts : 4; /**< Packet Status (PktSts) 3230215976Sjmallett Indicates the status of the received packet 3231215976Sjmallett * 4'b0010: IN data packet received 3232215976Sjmallett * 4'b0011: IN transfer completed (triggers an interrupt) 3233215976Sjmallett * 4'b0101: Data toggle error (triggers an interrupt) 3234215976Sjmallett * 4'b0111: Channel halted (triggers an interrupt) 3235215976Sjmallett * Others: Reserved */ 3236215976Sjmallett uint32_t dpid : 2; /**< Data PID (DPID) 3237215976Sjmallett * 2'b00: DATA0 3238215976Sjmallett * 2'b10: DATA1 3239215976Sjmallett * 2'b01: DATA2 3240215976Sjmallett * 2'b11: MDATA */ 3241215976Sjmallett uint32_t bcnt : 11; /**< Byte Count (BCnt) 3242215976Sjmallett Indicates the byte count of the received IN data packet */ 3243215976Sjmallett uint32_t chnum : 4; /**< Channel Number (ChNum) 3244215976Sjmallett Indicates the channel number to which the current received 3245215976Sjmallett packet belongs. */ 3246215976Sjmallett#else 3247215976Sjmallett uint32_t chnum : 4; 3248215976Sjmallett uint32_t bcnt : 11; 3249215976Sjmallett uint32_t dpid : 2; 3250215976Sjmallett uint32_t pktsts : 4; 3251215976Sjmallett uint32_t reserved_21_31 : 11; 3252215976Sjmallett#endif 3253215976Sjmallett } s; 3254215976Sjmallett struct cvmx_usbcx_grxstsph_s cn30xx; 3255215976Sjmallett struct cvmx_usbcx_grxstsph_s cn31xx; 3256215976Sjmallett struct cvmx_usbcx_grxstsph_s cn50xx; 3257215976Sjmallett struct cvmx_usbcx_grxstsph_s cn52xx; 3258215976Sjmallett struct cvmx_usbcx_grxstsph_s cn52xxp1; 3259215976Sjmallett struct cvmx_usbcx_grxstsph_s cn56xx; 3260215976Sjmallett struct cvmx_usbcx_grxstsph_s cn56xxp1; 3261215976Sjmallett}; 3262215976Sjmalletttypedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t; 3263215976Sjmallett 3264215976Sjmallett/** 3265215976Sjmallett * cvmx_usbc#_grxstsrd 3266215976Sjmallett * 3267215976Sjmallett * Receive Status Debug Read Register, Device Mode (GRXSTSRD) 3268215976Sjmallett * 3269215976Sjmallett * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. 3270215976Sjmallett * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSRH instead. 3271215976Sjmallett * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core. 3272215976Sjmallett * The offset difference shown in this document is for software clarity and is actually ignored by the 3273215976Sjmallett * hardware. 3274215976Sjmallett */ 3275215976Sjmallettunion cvmx_usbcx_grxstsrd 3276215976Sjmallett{ 3277215976Sjmallett uint32_t u32; 3278215976Sjmallett struct cvmx_usbcx_grxstsrd_s 3279215976Sjmallett { 3280215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3281215976Sjmallett uint32_t reserved_25_31 : 7; 3282215976Sjmallett uint32_t fn : 4; /**< Frame Number (FN) 3283215976Sjmallett This is the least significant 4 bits of the (micro)frame number in 3284215976Sjmallett which the packet is received on the USB. This field is supported 3285215976Sjmallett only when the isochronous OUT endpoints are supported. */ 3286215976Sjmallett uint32_t pktsts : 4; /**< Packet Status (PktSts) 3287215976Sjmallett Indicates the status of the received packet 3288215976Sjmallett * 4'b0001: Glogal OUT NAK (triggers an interrupt) 3289215976Sjmallett * 4'b0010: OUT data packet received 3290215976Sjmallett * 4'b0100: SETUP transaction completed (triggers an interrupt) 3291215976Sjmallett * 4'b0110: SETUP data packet received 3292215976Sjmallett * Others: Reserved */ 3293215976Sjmallett uint32_t dpid : 2; /**< Data PID (DPID) 3294215976Sjmallett * 2'b00: DATA0 3295215976Sjmallett * 2'b10: DATA1 3296215976Sjmallett * 2'b01: DATA2 3297215976Sjmallett * 2'b11: MDATA */ 3298215976Sjmallett uint32_t bcnt : 11; /**< Byte Count (BCnt) 3299215976Sjmallett Indicates the byte count of the received data packet */ 3300215976Sjmallett uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3301215976Sjmallett Indicates the endpoint number to which the current received 3302215976Sjmallett packet belongs. */ 3303215976Sjmallett#else 3304215976Sjmallett uint32_t epnum : 4; 3305215976Sjmallett uint32_t bcnt : 11; 3306215976Sjmallett uint32_t dpid : 2; 3307215976Sjmallett uint32_t pktsts : 4; 3308215976Sjmallett uint32_t fn : 4; 3309215976Sjmallett uint32_t reserved_25_31 : 7; 3310215976Sjmallett#endif 3311215976Sjmallett } s; 3312215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn30xx; 3313215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn31xx; 3314215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn50xx; 3315215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn52xx; 3316215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn52xxp1; 3317215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn56xx; 3318215976Sjmallett struct cvmx_usbcx_grxstsrd_s cn56xxp1; 3319215976Sjmallett}; 3320215976Sjmalletttypedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t; 3321215976Sjmallett 3322215976Sjmallett/** 3323215976Sjmallett * cvmx_usbc#_grxstsrh 3324215976Sjmallett * 3325215976Sjmallett * Receive Status Debug Read Register, Host Mode (GRXSTSRH) 3326215976Sjmallett * 3327215976Sjmallett * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. 3328215976Sjmallett * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSRD instead. 3329215976Sjmallett * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core. 3330215976Sjmallett * The offset difference shown in this document is for software clarity and is actually ignored by the 3331215976Sjmallett * hardware. 3332215976Sjmallett */ 3333215976Sjmallettunion cvmx_usbcx_grxstsrh 3334215976Sjmallett{ 3335215976Sjmallett uint32_t u32; 3336215976Sjmallett struct cvmx_usbcx_grxstsrh_s 3337215976Sjmallett { 3338215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3339215976Sjmallett uint32_t reserved_21_31 : 11; 3340215976Sjmallett uint32_t pktsts : 4; /**< Packet Status (PktSts) 3341215976Sjmallett Indicates the status of the received packet 3342215976Sjmallett * 4'b0010: IN data packet received 3343215976Sjmallett * 4'b0011: IN transfer completed (triggers an interrupt) 3344215976Sjmallett * 4'b0101: Data toggle error (triggers an interrupt) 3345215976Sjmallett * 4'b0111: Channel halted (triggers an interrupt) 3346215976Sjmallett * Others: Reserved */ 3347215976Sjmallett uint32_t dpid : 2; /**< Data PID (DPID) 3348215976Sjmallett * 2'b00: DATA0 3349215976Sjmallett * 2'b10: DATA1 3350215976Sjmallett * 2'b01: DATA2 3351215976Sjmallett * 2'b11: MDATA */ 3352215976Sjmallett uint32_t bcnt : 11; /**< Byte Count (BCnt) 3353215976Sjmallett Indicates the byte count of the received IN data packet */ 3354215976Sjmallett uint32_t chnum : 4; /**< Channel Number (ChNum) 3355215976Sjmallett Indicates the channel number to which the current received 3356215976Sjmallett packet belongs. */ 3357215976Sjmallett#else 3358215976Sjmallett uint32_t chnum : 4; 3359215976Sjmallett uint32_t bcnt : 11; 3360215976Sjmallett uint32_t dpid : 2; 3361215976Sjmallett uint32_t pktsts : 4; 3362215976Sjmallett uint32_t reserved_21_31 : 11; 3363215976Sjmallett#endif 3364215976Sjmallett } s; 3365215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn30xx; 3366215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn31xx; 3367215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn50xx; 3368215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn52xx; 3369215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn52xxp1; 3370215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn56xx; 3371215976Sjmallett struct cvmx_usbcx_grxstsrh_s cn56xxp1; 3372215976Sjmallett}; 3373215976Sjmalletttypedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t; 3374215976Sjmallett 3375215976Sjmallett/** 3376215976Sjmallett * cvmx_usbc#_gsnpsid 3377215976Sjmallett * 3378215976Sjmallett * Synopsys ID Register (GSNPSID) 3379215976Sjmallett * 3380215976Sjmallett * This is a read-only register that contains the release number of the core being used. 3381215976Sjmallett */ 3382215976Sjmallettunion cvmx_usbcx_gsnpsid 3383215976Sjmallett{ 3384215976Sjmallett uint32_t u32; 3385215976Sjmallett struct cvmx_usbcx_gsnpsid_s 3386215976Sjmallett { 3387215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3388215976Sjmallett uint32_t synopsysid : 32; /**< 0x4F54\<version\>A, release number of the core being used. 3389215976Sjmallett 0x4F54220A => pass1.x, 0x4F54240A => pass2.x */ 3390215976Sjmallett#else 3391215976Sjmallett uint32_t synopsysid : 32; 3392215976Sjmallett#endif 3393215976Sjmallett } s; 3394215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn30xx; 3395215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn31xx; 3396215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn50xx; 3397215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn52xx; 3398215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn52xxp1; 3399215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn56xx; 3400215976Sjmallett struct cvmx_usbcx_gsnpsid_s cn56xxp1; 3401215976Sjmallett}; 3402215976Sjmalletttypedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t; 3403215976Sjmallett 3404215976Sjmallett/** 3405215976Sjmallett * cvmx_usbc#_gusbcfg 3406215976Sjmallett * 3407215976Sjmallett * Core USB Configuration Register (GUSBCFG) 3408215976Sjmallett * 3409215976Sjmallett * This register can be used to configure the core after power-on or a changing to Host mode or Device mode. 3410215976Sjmallett * It contains USB and USB-PHY related configuration parameters. The application must program this register 3411215976Sjmallett * before starting any transactions on either the AHB or the USB. 3412215976Sjmallett * Do not make changes to this register after the initial programming. 3413215976Sjmallett */ 3414215976Sjmallettunion cvmx_usbcx_gusbcfg 3415215976Sjmallett{ 3416215976Sjmallett uint32_t u32; 3417215976Sjmallett struct cvmx_usbcx_gusbcfg_s 3418215976Sjmallett { 3419215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3420215976Sjmallett uint32_t reserved_17_31 : 15; 3421215976Sjmallett uint32_t otgi2csel : 1; /**< UTMIFS or I2C Interface Select (OtgI2CSel) 3422215976Sjmallett This bit is always 0x0. */ 3423215976Sjmallett uint32_t phylpwrclksel : 1; /**< PHY Low-Power Clock Select (PhyLPwrClkSel) 3424215976Sjmallett Software should set this bit to 0x0. 3425215976Sjmallett Selects either 480-MHz or 48-MHz (low-power) PHY mode. In 3426215976Sjmallett FS and LS modes, the PHY can usually operate on a 48-MHz 3427215976Sjmallett clock to save power. 3428215976Sjmallett * 1'b0: 480-MHz Internal PLL clock 3429215976Sjmallett * 1'b1: 48-MHz External Clock 3430215976Sjmallett In 480 MHz mode, the UTMI interface operates at either 60 or 3431215976Sjmallett 30-MHz, depending upon whether 8- or 16-bit data width is 3432215976Sjmallett selected. In 48-MHz mode, the UTMI interface operates at 48 3433215976Sjmallett MHz in FS mode and at either 48 or 6 MHz in LS mode 3434215976Sjmallett (depending on the PHY vendor). 3435215976Sjmallett This bit drives the utmi_fsls_low_power core output signal, and 3436215976Sjmallett is valid only for UTMI+ PHYs. */ 3437215976Sjmallett uint32_t reserved_14_14 : 1; 3438215976Sjmallett uint32_t usbtrdtim : 4; /**< USB Turnaround Time (USBTrdTim) 3439215976Sjmallett Sets the turnaround time in PHY clocks. 3440215976Sjmallett Specifies the response time for a MAC request to the Packet 3441215976Sjmallett FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). 3442215976Sjmallett This must be programmed to 0x5. */ 3443215976Sjmallett uint32_t hnpcap : 1; /**< HNP-Capable (HNPCap) 3444215976Sjmallett This bit is always 0x0. */ 3445215976Sjmallett uint32_t srpcap : 1; /**< SRP-Capable (SRPCap) 3446215976Sjmallett This bit is always 0x0. */ 3447215976Sjmallett uint32_t ddrsel : 1; /**< ULPI DDR Select (DDRSel) 3448215976Sjmallett Software should set this bit to 0x0. */ 3449215976Sjmallett uint32_t physel : 1; /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial 3450215976Sjmallett Software should set this bit to 0x0. */ 3451215976Sjmallett uint32_t fsintf : 1; /**< Full-Speed Serial Interface Select (FSIntf) 3452215976Sjmallett Software should set this bit to 0x0. */ 3453215976Sjmallett uint32_t ulpi_utmi_sel : 1; /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel) 3454215976Sjmallett This bit is always 0x0. */ 3455215976Sjmallett uint32_t phyif : 1; /**< PHY Interface (PHYIf) 3456215976Sjmallett This bit is always 0x1. */ 3457215976Sjmallett uint32_t toutcal : 3; /**< HS/FS Timeout Calibration (TOutCal) 3458215976Sjmallett The number of PHY clocks that the application programs in this 3459215976Sjmallett field is added to the high-speed/full-speed interpacket timeout 3460215976Sjmallett duration in the core to account for any additional delays 3461215976Sjmallett introduced by the PHY. This may be required, since the delay 3462215976Sjmallett introduced by the PHY in generating the linestate condition may 3463215976Sjmallett vary from one PHY to another. 3464215976Sjmallett The USB standard timeout value for high-speed operation is 3465215976Sjmallett 736 to 816 (inclusive) bit times. The USB standard timeout 3466215976Sjmallett value for full-speed operation is 16 to 18 (inclusive) bit times. 3467215976Sjmallett The application must program this field based on the speed of 3468215976Sjmallett enumeration. The number of bit times added per PHY clock are: 3469215976Sjmallett High-speed operation: 3470215976Sjmallett * One 30-MHz PHY clock = 16 bit times 3471215976Sjmallett * One 60-MHz PHY clock = 8 bit times 3472215976Sjmallett Full-speed operation: 3473215976Sjmallett * One 30-MHz PHY clock = 0.4 bit times 3474215976Sjmallett * One 60-MHz PHY clock = 0.2 bit times 3475215976Sjmallett * One 48-MHz PHY clock = 0.25 bit times */ 3476215976Sjmallett#else 3477215976Sjmallett uint32_t toutcal : 3; 3478215976Sjmallett uint32_t phyif : 1; 3479215976Sjmallett uint32_t ulpi_utmi_sel : 1; 3480215976Sjmallett uint32_t fsintf : 1; 3481215976Sjmallett uint32_t physel : 1; 3482215976Sjmallett uint32_t ddrsel : 1; 3483215976Sjmallett uint32_t srpcap : 1; 3484215976Sjmallett uint32_t hnpcap : 1; 3485215976Sjmallett uint32_t usbtrdtim : 4; 3486215976Sjmallett uint32_t reserved_14_14 : 1; 3487215976Sjmallett uint32_t phylpwrclksel : 1; 3488215976Sjmallett uint32_t otgi2csel : 1; 3489215976Sjmallett uint32_t reserved_17_31 : 15; 3490215976Sjmallett#endif 3491215976Sjmallett } s; 3492215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn30xx; 3493215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn31xx; 3494215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn50xx; 3495215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn52xx; 3496215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn52xxp1; 3497215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn56xx; 3498215976Sjmallett struct cvmx_usbcx_gusbcfg_s cn56xxp1; 3499215976Sjmallett}; 3500215976Sjmalletttypedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t; 3501215976Sjmallett 3502215976Sjmallett/** 3503215976Sjmallett * cvmx_usbc#_haint 3504215976Sjmallett * 3505215976Sjmallett * Host All Channels Interrupt Register (HAINT) 3506215976Sjmallett * 3507215976Sjmallett * When a significant event occurs on a channel, the Host All Channels Interrupt register 3508215976Sjmallett * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt 3509215976Sjmallett * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per 3510215976Sjmallett * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the 3511215976Sjmallett * application sets and clears bits in the corresponding Host Channel-n Interrupt register. 3512215976Sjmallett */ 3513215976Sjmallettunion cvmx_usbcx_haint 3514215976Sjmallett{ 3515215976Sjmallett uint32_t u32; 3516215976Sjmallett struct cvmx_usbcx_haint_s 3517215976Sjmallett { 3518215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3519215976Sjmallett uint32_t reserved_16_31 : 16; 3520215976Sjmallett uint32_t haint : 16; /**< Channel Interrupts (HAINT) 3521215976Sjmallett One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */ 3522215976Sjmallett#else 3523215976Sjmallett uint32_t haint : 16; 3524215976Sjmallett uint32_t reserved_16_31 : 16; 3525215976Sjmallett#endif 3526215976Sjmallett } s; 3527215976Sjmallett struct cvmx_usbcx_haint_s cn30xx; 3528215976Sjmallett struct cvmx_usbcx_haint_s cn31xx; 3529215976Sjmallett struct cvmx_usbcx_haint_s cn50xx; 3530215976Sjmallett struct cvmx_usbcx_haint_s cn52xx; 3531215976Sjmallett struct cvmx_usbcx_haint_s cn52xxp1; 3532215976Sjmallett struct cvmx_usbcx_haint_s cn56xx; 3533215976Sjmallett struct cvmx_usbcx_haint_s cn56xxp1; 3534215976Sjmallett}; 3535215976Sjmalletttypedef union cvmx_usbcx_haint cvmx_usbcx_haint_t; 3536215976Sjmallett 3537215976Sjmallett/** 3538215976Sjmallett * cvmx_usbc#_haintmsk 3539215976Sjmallett * 3540215976Sjmallett * Host All Channels Interrupt Mask Register (HAINTMSK) 3541215976Sjmallett * 3542215976Sjmallett * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt 3543215976Sjmallett * register to interrupt the application when an event occurs on a channel. There is one 3544215976Sjmallett * interrupt mask bit per channel, up to a maximum of 16 bits. 3545215976Sjmallett * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 3546215976Sjmallett */ 3547215976Sjmallettunion cvmx_usbcx_haintmsk 3548215976Sjmallett{ 3549215976Sjmallett uint32_t u32; 3550215976Sjmallett struct cvmx_usbcx_haintmsk_s 3551215976Sjmallett { 3552215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3553215976Sjmallett uint32_t reserved_16_31 : 16; 3554215976Sjmallett uint32_t haintmsk : 16; /**< Channel Interrupt Mask (HAINTMsk) 3555215976Sjmallett One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */ 3556215976Sjmallett#else 3557215976Sjmallett uint32_t haintmsk : 16; 3558215976Sjmallett uint32_t reserved_16_31 : 16; 3559215976Sjmallett#endif 3560215976Sjmallett } s; 3561215976Sjmallett struct cvmx_usbcx_haintmsk_s cn30xx; 3562215976Sjmallett struct cvmx_usbcx_haintmsk_s cn31xx; 3563215976Sjmallett struct cvmx_usbcx_haintmsk_s cn50xx; 3564215976Sjmallett struct cvmx_usbcx_haintmsk_s cn52xx; 3565215976Sjmallett struct cvmx_usbcx_haintmsk_s cn52xxp1; 3566215976Sjmallett struct cvmx_usbcx_haintmsk_s cn56xx; 3567215976Sjmallett struct cvmx_usbcx_haintmsk_s cn56xxp1; 3568215976Sjmallett}; 3569215976Sjmalletttypedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t; 3570215976Sjmallett 3571215976Sjmallett/** 3572215976Sjmallett * cvmx_usbc#_hcchar# 3573215976Sjmallett * 3574215976Sjmallett * Host Channel-n Characteristics Register (HCCHAR) 3575215976Sjmallett * 3576215976Sjmallett */ 3577215976Sjmallettunion cvmx_usbcx_hccharx 3578215976Sjmallett{ 3579215976Sjmallett uint32_t u32; 3580215976Sjmallett struct cvmx_usbcx_hccharx_s 3581215976Sjmallett { 3582215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3583215976Sjmallett uint32_t chena : 1; /**< Channel Enable (ChEna) 3584215976Sjmallett This field is set by the application and cleared by the OTG host. 3585215976Sjmallett * 1'b0: Channel disabled 3586215976Sjmallett * 1'b1: Channel enabled */ 3587215976Sjmallett uint32_t chdis : 1; /**< Channel Disable (ChDis) 3588215976Sjmallett The application sets this bit to stop transmitting/receiving data 3589215976Sjmallett on a channel, even before the transfer for that channel is 3590215976Sjmallett complete. The application must wait for the Channel Disabled 3591215976Sjmallett interrupt before treating the channel as disabled. */ 3592215976Sjmallett uint32_t oddfrm : 1; /**< Odd Frame (OddFrm) 3593215976Sjmallett This field is set (reset) by the application to indicate that the 3594215976Sjmallett OTG host must perform a transfer in an odd (micro)frame. This 3595215976Sjmallett field is applicable for only periodic (isochronous and interrupt) 3596215976Sjmallett transactions. 3597215976Sjmallett * 1'b0: Even (micro)frame 3598215976Sjmallett * 1'b1: Odd (micro)frame */ 3599215976Sjmallett uint32_t devaddr : 7; /**< Device Address (DevAddr) 3600215976Sjmallett This field selects the specific device serving as the data source 3601215976Sjmallett or sink. */ 3602215976Sjmallett uint32_t ec : 2; /**< Multi Count (MC) / Error Count (EC) 3603215976Sjmallett When the Split Enable bit of the Host Channel-n Split Control 3604215976Sjmallett register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates 3605215976Sjmallett to the host the number of transactions that should be executed 3606215976Sjmallett per microframe for this endpoint. 3607215976Sjmallett * 2'b00: Reserved. This field yields undefined results. 3608215976Sjmallett * 2'b01: 1 transaction 3609215976Sjmallett * 2'b10: 2 transactions to be issued for this endpoint per 3610215976Sjmallett microframe 3611215976Sjmallett * 2'b11: 3 transactions to be issued for this endpoint per 3612215976Sjmallett microframe 3613215976Sjmallett When HCSPLTn.SpltEna is set (1'b1), this field indicates the 3614215976Sjmallett number of immediate retries to be performed for a periodic split 3615215976Sjmallett transactions on transaction errors. This field must be set to at 3616215976Sjmallett least 2'b01. */ 3617215976Sjmallett uint32_t eptype : 2; /**< Endpoint Type (EPType) 3618215976Sjmallett Indicates the transfer type selected. 3619215976Sjmallett * 2'b00: Control 3620215976Sjmallett * 2'b01: Isochronous 3621215976Sjmallett * 2'b10: Bulk 3622215976Sjmallett * 2'b11: Interrupt */ 3623215976Sjmallett uint32_t lspddev : 1; /**< Low-Speed Device (LSpdDev) 3624215976Sjmallett This field is set by the application to indicate that this channel is 3625215976Sjmallett communicating to a low-speed device. */ 3626215976Sjmallett uint32_t reserved_16_16 : 1; 3627215976Sjmallett uint32_t epdir : 1; /**< Endpoint Direction (EPDir) 3628215976Sjmallett Indicates whether the transaction is IN or OUT. 3629215976Sjmallett * 1'b0: OUT 3630215976Sjmallett * 1'b1: IN */ 3631215976Sjmallett uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3632215976Sjmallett Indicates the endpoint number on the device serving as the 3633215976Sjmallett data source or sink. */ 3634215976Sjmallett uint32_t mps : 11; /**< Maximum Packet Size (MPS) 3635215976Sjmallett Indicates the maximum packet size of the associated endpoint. */ 3636215976Sjmallett#else 3637215976Sjmallett uint32_t mps : 11; 3638215976Sjmallett uint32_t epnum : 4; 3639215976Sjmallett uint32_t epdir : 1; 3640215976Sjmallett uint32_t reserved_16_16 : 1; 3641215976Sjmallett uint32_t lspddev : 1; 3642215976Sjmallett uint32_t eptype : 2; 3643215976Sjmallett uint32_t ec : 2; 3644215976Sjmallett uint32_t devaddr : 7; 3645215976Sjmallett uint32_t oddfrm : 1; 3646215976Sjmallett uint32_t chdis : 1; 3647215976Sjmallett uint32_t chena : 1; 3648215976Sjmallett#endif 3649215976Sjmallett } s; 3650215976Sjmallett struct cvmx_usbcx_hccharx_s cn30xx; 3651215976Sjmallett struct cvmx_usbcx_hccharx_s cn31xx; 3652215976Sjmallett struct cvmx_usbcx_hccharx_s cn50xx; 3653215976Sjmallett struct cvmx_usbcx_hccharx_s cn52xx; 3654215976Sjmallett struct cvmx_usbcx_hccharx_s cn52xxp1; 3655215976Sjmallett struct cvmx_usbcx_hccharx_s cn56xx; 3656215976Sjmallett struct cvmx_usbcx_hccharx_s cn56xxp1; 3657215976Sjmallett}; 3658215976Sjmalletttypedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t; 3659215976Sjmallett 3660215976Sjmallett/** 3661215976Sjmallett * cvmx_usbc#_hcfg 3662215976Sjmallett * 3663215976Sjmallett * Host Configuration Register (HCFG) 3664215976Sjmallett * 3665215976Sjmallett * This register configures the core after power-on. Do not make changes to this register after initializing the host. 3666215976Sjmallett */ 3667215976Sjmallettunion cvmx_usbcx_hcfg 3668215976Sjmallett{ 3669215976Sjmallett uint32_t u32; 3670215976Sjmallett struct cvmx_usbcx_hcfg_s 3671215976Sjmallett { 3672215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3673215976Sjmallett uint32_t reserved_3_31 : 29; 3674215976Sjmallett uint32_t fslssupp : 1; /**< FS- and LS-Only Support (FSLSSupp) 3675215976Sjmallett The application uses this bit to control the core's enumeration 3676215976Sjmallett speed. Using this bit, the application can make the core 3677215976Sjmallett enumerate as a FS host, even if the connected device supports 3678215976Sjmallett HS traffic. Do not make changes to this field after initial 3679215976Sjmallett programming. 3680215976Sjmallett * 1'b0: HS/FS/LS, based on the maximum speed supported by 3681215976Sjmallett the connected device 3682215976Sjmallett * 1'b1: FS/LS-only, even if the connected device can support HS */ 3683215976Sjmallett uint32_t fslspclksel : 2; /**< FS/LS PHY Clock Select (FSLSPclkSel) 3684215976Sjmallett When the core is in FS Host mode 3685215976Sjmallett * 2'b00: PHY clock is running at 30/60 MHz 3686215976Sjmallett * 2'b01: PHY clock is running at 48 MHz 3687215976Sjmallett * Others: Reserved 3688215976Sjmallett When the core is in LS Host mode 3689215976Sjmallett * 2'b00: PHY clock is running at 30/60 MHz. When the 3690215976Sjmallett UTMI+/ULPI PHY Low Power mode is not selected, use 3691215976Sjmallett 30/60 MHz. 3692215976Sjmallett * 2'b01: PHY clock is running at 48 MHz. When the UTMI+ 3693215976Sjmallett PHY Low Power mode is selected, use 48MHz if the PHY 3694215976Sjmallett supplies a 48 MHz clock during LS mode. 3695215976Sjmallett * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, 3696215976Sjmallett use 6 MHz when the UTMI+ PHY Low Power mode is 3697215976Sjmallett selected and the PHY supplies a 6 MHz clock during LS 3698215976Sjmallett mode. If you select a 6 MHz clock during LS mode, you must 3699215976Sjmallett do a soft reset. 3700215976Sjmallett * 2'b11: Reserved */ 3701215976Sjmallett#else 3702215976Sjmallett uint32_t fslspclksel : 2; 3703215976Sjmallett uint32_t fslssupp : 1; 3704215976Sjmallett uint32_t reserved_3_31 : 29; 3705215976Sjmallett#endif 3706215976Sjmallett } s; 3707215976Sjmallett struct cvmx_usbcx_hcfg_s cn30xx; 3708215976Sjmallett struct cvmx_usbcx_hcfg_s cn31xx; 3709215976Sjmallett struct cvmx_usbcx_hcfg_s cn50xx; 3710215976Sjmallett struct cvmx_usbcx_hcfg_s cn52xx; 3711215976Sjmallett struct cvmx_usbcx_hcfg_s cn52xxp1; 3712215976Sjmallett struct cvmx_usbcx_hcfg_s cn56xx; 3713215976Sjmallett struct cvmx_usbcx_hcfg_s cn56xxp1; 3714215976Sjmallett}; 3715215976Sjmalletttypedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t; 3716215976Sjmallett 3717215976Sjmallett/** 3718215976Sjmallett * cvmx_usbc#_hcint# 3719215976Sjmallett * 3720215976Sjmallett * Host Channel-n Interrupt Register (HCINT) 3721215976Sjmallett * 3722215976Sjmallett * This register indicates the status of a channel with respect to USB- and AHB-related events. 3723215976Sjmallett * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt 3724215976Sjmallett * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read 3725215976Sjmallett * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n 3726215976Sjmallett * Interrupt register. The application must clear the appropriate bit in this register to clear the 3727215976Sjmallett * corresponding bits in the HAINT and GINTSTS registers. 3728215976Sjmallett */ 3729215976Sjmallettunion cvmx_usbcx_hcintx 3730215976Sjmallett{ 3731215976Sjmallett uint32_t u32; 3732215976Sjmallett struct cvmx_usbcx_hcintx_s 3733215976Sjmallett { 3734215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3735215976Sjmallett uint32_t reserved_11_31 : 21; 3736215976Sjmallett uint32_t datatglerr : 1; /**< Data Toggle Error (DataTglErr) */ 3737215976Sjmallett uint32_t frmovrun : 1; /**< Frame Overrun (FrmOvrun) */ 3738215976Sjmallett uint32_t bblerr : 1; /**< Babble Error (BblErr) */ 3739215976Sjmallett uint32_t xacterr : 1; /**< Transaction Error (XactErr) */ 3740215976Sjmallett uint32_t nyet : 1; /**< NYET Response Received Interrupt (NYET) */ 3741215976Sjmallett uint32_t ack : 1; /**< ACK Response Received Interrupt (ACK) */ 3742215976Sjmallett uint32_t nak : 1; /**< NAK Response Received Interrupt (NAK) */ 3743215976Sjmallett uint32_t stall : 1; /**< STALL Response Received Interrupt (STALL) */ 3744215976Sjmallett uint32_t ahberr : 1; /**< This bit is always 0x0. */ 3745215976Sjmallett uint32_t chhltd : 1; /**< Channel Halted (ChHltd) 3746215976Sjmallett Indicates the transfer completed abnormally either because of 3747215976Sjmallett any USB transaction error or in response to disable request by 3748215976Sjmallett the application. */ 3749215976Sjmallett uint32_t xfercompl : 1; /**< Transfer Completed (XferCompl) 3750215976Sjmallett Transfer completed normally without any errors. */ 3751215976Sjmallett#else 3752215976Sjmallett uint32_t xfercompl : 1; 3753215976Sjmallett uint32_t chhltd : 1; 3754215976Sjmallett uint32_t ahberr : 1; 3755215976Sjmallett uint32_t stall : 1; 3756215976Sjmallett uint32_t nak : 1; 3757215976Sjmallett uint32_t ack : 1; 3758215976Sjmallett uint32_t nyet : 1; 3759215976Sjmallett uint32_t xacterr : 1; 3760215976Sjmallett uint32_t bblerr : 1; 3761215976Sjmallett uint32_t frmovrun : 1; 3762215976Sjmallett uint32_t datatglerr : 1; 3763215976Sjmallett uint32_t reserved_11_31 : 21; 3764215976Sjmallett#endif 3765215976Sjmallett } s; 3766215976Sjmallett struct cvmx_usbcx_hcintx_s cn30xx; 3767215976Sjmallett struct cvmx_usbcx_hcintx_s cn31xx; 3768215976Sjmallett struct cvmx_usbcx_hcintx_s cn50xx; 3769215976Sjmallett struct cvmx_usbcx_hcintx_s cn52xx; 3770215976Sjmallett struct cvmx_usbcx_hcintx_s cn52xxp1; 3771215976Sjmallett struct cvmx_usbcx_hcintx_s cn56xx; 3772215976Sjmallett struct cvmx_usbcx_hcintx_s cn56xxp1; 3773215976Sjmallett}; 3774215976Sjmalletttypedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t; 3775215976Sjmallett 3776215976Sjmallett/** 3777215976Sjmallett * cvmx_usbc#_hcintmsk# 3778215976Sjmallett * 3779215976Sjmallett * Host Channel-n Interrupt Mask Register (HCINTMSKn) 3780215976Sjmallett * 3781215976Sjmallett * This register reflects the mask for each channel status described in the previous section. 3782215976Sjmallett * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 3783215976Sjmallett */ 3784215976Sjmallettunion cvmx_usbcx_hcintmskx 3785215976Sjmallett{ 3786215976Sjmallett uint32_t u32; 3787215976Sjmallett struct cvmx_usbcx_hcintmskx_s 3788215976Sjmallett { 3789215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3790215976Sjmallett uint32_t reserved_11_31 : 21; 3791215976Sjmallett uint32_t datatglerrmsk : 1; /**< Data Toggle Error Mask (DataTglErrMsk) */ 3792215976Sjmallett uint32_t frmovrunmsk : 1; /**< Frame Overrun Mask (FrmOvrunMsk) */ 3793215976Sjmallett uint32_t bblerrmsk : 1; /**< Babble Error Mask (BblErrMsk) */ 3794215976Sjmallett uint32_t xacterrmsk : 1; /**< Transaction Error Mask (XactErrMsk) */ 3795215976Sjmallett uint32_t nyetmsk : 1; /**< NYET Response Received Interrupt Mask (NyetMsk) */ 3796215976Sjmallett uint32_t ackmsk : 1; /**< ACK Response Received Interrupt Mask (AckMsk) */ 3797215976Sjmallett uint32_t nakmsk : 1; /**< NAK Response Received Interrupt Mask (NakMsk) */ 3798215976Sjmallett uint32_t stallmsk : 1; /**< STALL Response Received Interrupt Mask (StallMsk) */ 3799215976Sjmallett uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */ 3800215976Sjmallett uint32_t chhltdmsk : 1; /**< Channel Halted Mask (ChHltdMsk) */ 3801215976Sjmallett uint32_t xfercomplmsk : 1; /**< Transfer Completed Mask (XferComplMsk) */ 3802215976Sjmallett#else 3803215976Sjmallett uint32_t xfercomplmsk : 1; 3804215976Sjmallett uint32_t chhltdmsk : 1; 3805215976Sjmallett uint32_t ahberrmsk : 1; 3806215976Sjmallett uint32_t stallmsk : 1; 3807215976Sjmallett uint32_t nakmsk : 1; 3808215976Sjmallett uint32_t ackmsk : 1; 3809215976Sjmallett uint32_t nyetmsk : 1; 3810215976Sjmallett uint32_t xacterrmsk : 1; 3811215976Sjmallett uint32_t bblerrmsk : 1; 3812215976Sjmallett uint32_t frmovrunmsk : 1; 3813215976Sjmallett uint32_t datatglerrmsk : 1; 3814215976Sjmallett uint32_t reserved_11_31 : 21; 3815215976Sjmallett#endif 3816215976Sjmallett } s; 3817215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn30xx; 3818215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn31xx; 3819215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn50xx; 3820215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn52xx; 3821215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn52xxp1; 3822215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn56xx; 3823215976Sjmallett struct cvmx_usbcx_hcintmskx_s cn56xxp1; 3824215976Sjmallett}; 3825215976Sjmalletttypedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t; 3826215976Sjmallett 3827215976Sjmallett/** 3828215976Sjmallett * cvmx_usbc#_hcsplt# 3829215976Sjmallett * 3830215976Sjmallett * Host Channel-n Split Control Register (HCSPLT) 3831215976Sjmallett * 3832215976Sjmallett */ 3833215976Sjmallettunion cvmx_usbcx_hcspltx 3834215976Sjmallett{ 3835215976Sjmallett uint32_t u32; 3836215976Sjmallett struct cvmx_usbcx_hcspltx_s 3837215976Sjmallett { 3838215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3839215976Sjmallett uint32_t spltena : 1; /**< Split Enable (SpltEna) 3840215976Sjmallett The application sets this field to indicate that this channel is 3841215976Sjmallett enabled to perform split transactions. */ 3842215976Sjmallett uint32_t reserved_17_30 : 14; 3843215976Sjmallett uint32_t compsplt : 1; /**< Do Complete Split (CompSplt) 3844215976Sjmallett The application sets this field to request the OTG host to 3845215976Sjmallett perform a complete split transaction. */ 3846215976Sjmallett uint32_t xactpos : 2; /**< Transaction Position (XactPos) 3847215976Sjmallett This field is used to determine whether to send all, first, middle, 3848215976Sjmallett or last payloads with each OUT transaction. 3849215976Sjmallett * 2'b11: All. This is the entire data payload is of this transaction 3850215976Sjmallett (which is less than or equal to 188 bytes). 3851215976Sjmallett * 2'b10: Begin. This is the first data payload of this transaction 3852215976Sjmallett (which is larger than 188 bytes). 3853215976Sjmallett * 2'b00: Mid. This is the middle payload of this transaction 3854215976Sjmallett (which is larger than 188 bytes). 3855215976Sjmallett * 2'b01: End. This is the last payload of this transaction (which 3856215976Sjmallett is larger than 188 bytes). */ 3857215976Sjmallett uint32_t hubaddr : 7; /**< Hub Address (HubAddr) 3858215976Sjmallett This field holds the device address of the transaction 3859215976Sjmallett translator's hub. */ 3860215976Sjmallett uint32_t prtaddr : 7; /**< Port Address (PrtAddr) 3861215976Sjmallett This field is the port number of the recipient transaction 3862215976Sjmallett translator. */ 3863215976Sjmallett#else 3864215976Sjmallett uint32_t prtaddr : 7; 3865215976Sjmallett uint32_t hubaddr : 7; 3866215976Sjmallett uint32_t xactpos : 2; 3867215976Sjmallett uint32_t compsplt : 1; 3868215976Sjmallett uint32_t reserved_17_30 : 14; 3869215976Sjmallett uint32_t spltena : 1; 3870215976Sjmallett#endif 3871215976Sjmallett } s; 3872215976Sjmallett struct cvmx_usbcx_hcspltx_s cn30xx; 3873215976Sjmallett struct cvmx_usbcx_hcspltx_s cn31xx; 3874215976Sjmallett struct cvmx_usbcx_hcspltx_s cn50xx; 3875215976Sjmallett struct cvmx_usbcx_hcspltx_s cn52xx; 3876215976Sjmallett struct cvmx_usbcx_hcspltx_s cn52xxp1; 3877215976Sjmallett struct cvmx_usbcx_hcspltx_s cn56xx; 3878215976Sjmallett struct cvmx_usbcx_hcspltx_s cn56xxp1; 3879215976Sjmallett}; 3880215976Sjmalletttypedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t; 3881215976Sjmallett 3882215976Sjmallett/** 3883215976Sjmallett * cvmx_usbc#_hctsiz# 3884215976Sjmallett * 3885215976Sjmallett * Host Channel-n Transfer Size Register (HCTSIZ) 3886215976Sjmallett * 3887215976Sjmallett */ 3888215976Sjmallettunion cvmx_usbcx_hctsizx 3889215976Sjmallett{ 3890215976Sjmallett uint32_t u32; 3891215976Sjmallett struct cvmx_usbcx_hctsizx_s 3892215976Sjmallett { 3893215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3894215976Sjmallett uint32_t dopng : 1; /**< Do Ping (DoPng) 3895215976Sjmallett Setting this field to 1 directs the host to do PING protocol. */ 3896215976Sjmallett uint32_t pid : 2; /**< PID (Pid) 3897215976Sjmallett The application programs this field with the type of PID to use 3898215976Sjmallett for the initial transaction. The host will maintain this field for the 3899215976Sjmallett rest of the transfer. 3900215976Sjmallett * 2'b00: DATA0 3901215976Sjmallett * 2'b01: DATA2 3902215976Sjmallett * 2'b10: DATA1 3903215976Sjmallett * 2'b11: MDATA (non-control)/SETUP (control) */ 3904215976Sjmallett uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 3905215976Sjmallett This field is programmed by the application with the expected 3906215976Sjmallett number of packets to be transmitted (OUT) or received (IN). 3907215976Sjmallett The host decrements this count on every successful 3908215976Sjmallett transmission or reception of an OUT/IN packet. Once this count 3909215976Sjmallett reaches zero, the application is interrupted to indicate normal 3910215976Sjmallett completion. */ 3911215976Sjmallett uint32_t xfersize : 19; /**< Transfer Size (XferSize) 3912215976Sjmallett For an OUT, this field is the number of data bytes the host will 3913215976Sjmallett send during the transfer. 3914215976Sjmallett For an IN, this field is the buffer size that the application has 3915215976Sjmallett reserved for the transfer. The application is expected to 3916215976Sjmallett program this field as an integer multiple of the maximum packet 3917215976Sjmallett size for IN transactions (periodic and non-periodic). */ 3918215976Sjmallett#else 3919215976Sjmallett uint32_t xfersize : 19; 3920215976Sjmallett uint32_t pktcnt : 10; 3921215976Sjmallett uint32_t pid : 2; 3922215976Sjmallett uint32_t dopng : 1; 3923215976Sjmallett#endif 3924215976Sjmallett } s; 3925215976Sjmallett struct cvmx_usbcx_hctsizx_s cn30xx; 3926215976Sjmallett struct cvmx_usbcx_hctsizx_s cn31xx; 3927215976Sjmallett struct cvmx_usbcx_hctsizx_s cn50xx; 3928215976Sjmallett struct cvmx_usbcx_hctsizx_s cn52xx; 3929215976Sjmallett struct cvmx_usbcx_hctsizx_s cn52xxp1; 3930215976Sjmallett struct cvmx_usbcx_hctsizx_s cn56xx; 3931215976Sjmallett struct cvmx_usbcx_hctsizx_s cn56xxp1; 3932215976Sjmallett}; 3933215976Sjmalletttypedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t; 3934215976Sjmallett 3935215976Sjmallett/** 3936215976Sjmallett * cvmx_usbc#_hfir 3937215976Sjmallett * 3938215976Sjmallett * Host Frame Interval Register (HFIR) 3939215976Sjmallett * 3940215976Sjmallett * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated. 3941215976Sjmallett */ 3942215976Sjmallettunion cvmx_usbcx_hfir 3943215976Sjmallett{ 3944215976Sjmallett uint32_t u32; 3945215976Sjmallett struct cvmx_usbcx_hfir_s 3946215976Sjmallett { 3947215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3948215976Sjmallett uint32_t reserved_16_31 : 16; 3949215976Sjmallett uint32_t frint : 16; /**< Frame Interval (FrInt) 3950215976Sjmallett The value that the application programs to this field specifies 3951215976Sjmallett the interval between two consecutive SOFs (FS) or micro- 3952215976Sjmallett SOFs (HS) or Keep-Alive tokens (HS). This field contains the 3953215976Sjmallett number of PHY clocks that constitute the required frame 3954215976Sjmallett interval. The default value set in this field for a FS operation 3955215976Sjmallett when the PHY clock frequency is 60 MHz. The application can 3956215976Sjmallett write a value to this register only after the Port Enable bit of 3957215976Sjmallett the Host Port Control and Status register (HPRT.PrtEnaPort) 3958215976Sjmallett has been set. If no value is programmed, the core calculates 3959215976Sjmallett the value based on the PHY clock specified in the FS/LS PHY 3960215976Sjmallett Clock Select field of the Host Configuration register 3961215976Sjmallett (HCFG.FSLSPclkSel). Do not change the value of this field 3962215976Sjmallett after the initial configuration. 3963215976Sjmallett * 125 us (PHY clock frequency for HS) 3964215976Sjmallett * 1 ms (PHY clock frequency for FS/LS) */ 3965215976Sjmallett#else 3966215976Sjmallett uint32_t frint : 16; 3967215976Sjmallett uint32_t reserved_16_31 : 16; 3968215976Sjmallett#endif 3969215976Sjmallett } s; 3970215976Sjmallett struct cvmx_usbcx_hfir_s cn30xx; 3971215976Sjmallett struct cvmx_usbcx_hfir_s cn31xx; 3972215976Sjmallett struct cvmx_usbcx_hfir_s cn50xx; 3973215976Sjmallett struct cvmx_usbcx_hfir_s cn52xx; 3974215976Sjmallett struct cvmx_usbcx_hfir_s cn52xxp1; 3975215976Sjmallett struct cvmx_usbcx_hfir_s cn56xx; 3976215976Sjmallett struct cvmx_usbcx_hfir_s cn56xxp1; 3977215976Sjmallett}; 3978215976Sjmalletttypedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t; 3979215976Sjmallett 3980215976Sjmallett/** 3981215976Sjmallett * cvmx_usbc#_hfnum 3982215976Sjmallett * 3983215976Sjmallett * Host Frame Number/Frame Time Remaining Register (HFNUM) 3984215976Sjmallett * 3985215976Sjmallett * This register indicates the current frame number. 3986215976Sjmallett * It also indicates the time remaining (in terms of the number of PHY clocks) 3987215976Sjmallett * in the current (micro)frame. 3988215976Sjmallett */ 3989215976Sjmallettunion cvmx_usbcx_hfnum 3990215976Sjmallett{ 3991215976Sjmallett uint32_t u32; 3992215976Sjmallett struct cvmx_usbcx_hfnum_s 3993215976Sjmallett { 3994215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3995215976Sjmallett uint32_t frrem : 16; /**< Frame Time Remaining (FrRem) 3996215976Sjmallett Indicates the amount of time remaining in the current 3997215976Sjmallett microframe (HS) or frame (FS/LS), in terms of PHY clocks. 3998215976Sjmallett This field decrements on each PHY clock. When it reaches 3999215976Sjmallett zero, this field is reloaded with the value in the Frame Interval 4000215976Sjmallett register and a new SOF is transmitted on the USB. */ 4001215976Sjmallett uint32_t frnum : 16; /**< Frame Number (FrNum) 4002215976Sjmallett This field increments when a new SOF is transmitted on the 4003215976Sjmallett USB, and is reset to 0 when it reaches 16'h3FFF. */ 4004215976Sjmallett#else 4005215976Sjmallett uint32_t frnum : 16; 4006215976Sjmallett uint32_t frrem : 16; 4007215976Sjmallett#endif 4008215976Sjmallett } s; 4009215976Sjmallett struct cvmx_usbcx_hfnum_s cn30xx; 4010215976Sjmallett struct cvmx_usbcx_hfnum_s cn31xx; 4011215976Sjmallett struct cvmx_usbcx_hfnum_s cn50xx; 4012215976Sjmallett struct cvmx_usbcx_hfnum_s cn52xx; 4013215976Sjmallett struct cvmx_usbcx_hfnum_s cn52xxp1; 4014215976Sjmallett struct cvmx_usbcx_hfnum_s cn56xx; 4015215976Sjmallett struct cvmx_usbcx_hfnum_s cn56xxp1; 4016215976Sjmallett}; 4017215976Sjmalletttypedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t; 4018215976Sjmallett 4019215976Sjmallett/** 4020215976Sjmallett * cvmx_usbc#_hprt 4021215976Sjmallett * 4022215976Sjmallett * Host Port Control and Status Register (HPRT) 4023215976Sjmallett * 4024215976Sjmallett * This register is available in both Host and Device modes. 4025215976Sjmallett * Currently, the OTG Host supports only one port. 4026215976Sjmallett * A single register holds USB port-related information such as USB reset, enable, suspend, resume, 4027215976Sjmallett * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an 4028215976Sjmallett * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt 4029215976Sjmallett * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear 4030215976Sjmallett * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit 4031215976Sjmallett * to clear the interrupt. 4032215976Sjmallett */ 4033215976Sjmallettunion cvmx_usbcx_hprt 4034215976Sjmallett{ 4035215976Sjmallett uint32_t u32; 4036215976Sjmallett struct cvmx_usbcx_hprt_s 4037215976Sjmallett { 4038215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4039215976Sjmallett uint32_t reserved_19_31 : 13; 4040215976Sjmallett uint32_t prtspd : 2; /**< Port Speed (PrtSpd) 4041215976Sjmallett Indicates the speed of the device attached to this port. 4042215976Sjmallett * 2'b00: High speed 4043215976Sjmallett * 2'b01: Full speed 4044215976Sjmallett * 2'b10: Low speed 4045215976Sjmallett * 2'b11: Reserved */ 4046215976Sjmallett uint32_t prttstctl : 4; /**< Port Test Control (PrtTstCtl) 4047215976Sjmallett The application writes a nonzero value to this field to put 4048215976Sjmallett the port into a Test mode, and the corresponding pattern is 4049215976Sjmallett signaled on the port. 4050215976Sjmallett * 4'b0000: Test mode disabled 4051215976Sjmallett * 4'b0001: Test_J mode 4052215976Sjmallett * 4'b0010: Test_K mode 4053215976Sjmallett * 4'b0011: Test_SE0_NAK mode 4054215976Sjmallett * 4'b0100: Test_Packet mode 4055215976Sjmallett * 4'b0101: Test_Force_Enable 4056215976Sjmallett * Others: Reserved 4057215976Sjmallett PrtSpd must be zero (i.e. the interface must be in high-speed 4058215976Sjmallett mode) to use the PrtTstCtl test modes. */ 4059215976Sjmallett uint32_t prtpwr : 1; /**< Port Power (PrtPwr) 4060215976Sjmallett The application uses this field to control power to this port, 4061215976Sjmallett and the core clears this bit on an overcurrent condition. 4062215976Sjmallett * 1'b0: Power off 4063215976Sjmallett * 1'b1: Power on */ 4064215976Sjmallett uint32_t prtlnsts : 2; /**< Port Line Status (PrtLnSts) 4065215976Sjmallett Indicates the current logic level USB data lines 4066215976Sjmallett * Bit [10]: Logic level of D- 4067215976Sjmallett * Bit [11]: Logic level of D+ */ 4068215976Sjmallett uint32_t reserved_9_9 : 1; 4069215976Sjmallett uint32_t prtrst : 1; /**< Port Reset (PrtRst) 4070215976Sjmallett When the application sets this bit, a reset sequence is 4071215976Sjmallett started on this port. The application must time the reset 4072215976Sjmallett period and clear this bit after the reset sequence is 4073215976Sjmallett complete. 4074215976Sjmallett * 1'b0: Port not in reset 4075215976Sjmallett * 1'b1: Port in reset 4076215976Sjmallett The application must leave this bit set for at least a 4077215976Sjmallett minimum duration mentioned below to start a reset on the 4078215976Sjmallett port. The application can leave it set for another 10 ms in 4079215976Sjmallett addition to the required minimum duration, before clearing 4080215976Sjmallett the bit, even though there is no maximum limit set by the 4081215976Sjmallett USB standard. 4082215976Sjmallett * High speed: 50 ms 4083215976Sjmallett * Full speed/Low speed: 10 ms */ 4084215976Sjmallett uint32_t prtsusp : 1; /**< Port Suspend (PrtSusp) 4085215976Sjmallett The application sets this bit to put this port in Suspend 4086215976Sjmallett mode. The core only stops sending SOFs when this is set. 4087215976Sjmallett To stop the PHY clock, the application must set the Port 4088215976Sjmallett Clock Stop bit, which will assert the suspend input pin of 4089215976Sjmallett the PHY. 4090215976Sjmallett The read value of this bit reflects the current suspend 4091215976Sjmallett status of the port. This bit is cleared by the core after a 4092215976Sjmallett remote wakeup signal is detected or the application sets 4093215976Sjmallett the Port Reset bit or Port Resume bit in this register or the 4094215976Sjmallett Resume/Remote Wakeup Detected Interrupt bit or 4095215976Sjmallett Disconnect Detected Interrupt bit in the Core Interrupt 4096215976Sjmallett register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, 4097215976Sjmallett respectively). 4098215976Sjmallett * 1'b0: Port not in Suspend mode 4099215976Sjmallett * 1'b1: Port in Suspend mode */ 4100215976Sjmallett uint32_t prtres : 1; /**< Port Resume (PrtRes) 4101215976Sjmallett The application sets this bit to drive resume signaling on 4102215976Sjmallett the port. The core continues to drive the resume signal 4103215976Sjmallett until the application clears this bit. 4104215976Sjmallett If the core detects a USB remote wakeup sequence, as 4105215976Sjmallett indicated by the Port Resume/Remote Wakeup Detected 4106215976Sjmallett Interrupt bit of the Core Interrupt register 4107215976Sjmallett (GINTSTS.WkUpInt), the core starts driving resume 4108215976Sjmallett signaling without application intervention and clears this bit 4109215976Sjmallett when it detects a disconnect condition. The read value of 4110215976Sjmallett this bit indicates whether the core is currently driving 4111215976Sjmallett resume signaling. 4112215976Sjmallett * 1'b0: No resume driven 4113215976Sjmallett * 1'b1: Resume driven */ 4114215976Sjmallett uint32_t prtovrcurrchng : 1; /**< Port Overcurrent Change (PrtOvrCurrChng) 4115215976Sjmallett The core sets this bit when the status of the Port 4116215976Sjmallett Overcurrent Active bit (bit 4) in this register changes. */ 4117215976Sjmallett uint32_t prtovrcurract : 1; /**< Port Overcurrent Active (PrtOvrCurrAct) 4118215976Sjmallett Indicates the overcurrent condition of the port. 4119215976Sjmallett * 1'b0: No overcurrent condition 4120215976Sjmallett * 1'b1: Overcurrent condition */ 4121215976Sjmallett uint32_t prtenchng : 1; /**< Port Enable/Disable Change (PrtEnChng) 4122215976Sjmallett The core sets this bit when the status of the Port Enable bit 4123215976Sjmallett [2] of this register changes. */ 4124215976Sjmallett uint32_t prtena : 1; /**< Port Enable (PrtEna) 4125215976Sjmallett A port is enabled only by the core after a reset sequence, 4126215976Sjmallett and is disabled by an overcurrent condition, a disconnect 4127215976Sjmallett condition, or by the application clearing this bit. The 4128215976Sjmallett application cannot set this bit by a register write. It can only 4129215976Sjmallett clear it to disable the port. This bit does not trigger any 4130215976Sjmallett interrupt to the application. 4131215976Sjmallett * 1'b0: Port disabled 4132215976Sjmallett * 1'b1: Port enabled */ 4133215976Sjmallett uint32_t prtconndet : 1; /**< Port Connect Detected (PrtConnDet) 4134215976Sjmallett The core sets this bit when a device connection is detected 4135215976Sjmallett to trigger an interrupt to the application using the Host Port 4136215976Sjmallett Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). 4137215976Sjmallett The application must write a 1 to this bit to clear the 4138215976Sjmallett interrupt. */ 4139215976Sjmallett uint32_t prtconnsts : 1; /**< Port Connect Status (PrtConnSts) 4140215976Sjmallett * 0: No device is attached to the port. 4141215976Sjmallett * 1: A device is attached to the port. */ 4142215976Sjmallett#else 4143215976Sjmallett uint32_t prtconnsts : 1; 4144215976Sjmallett uint32_t prtconndet : 1; 4145215976Sjmallett uint32_t prtena : 1; 4146215976Sjmallett uint32_t prtenchng : 1; 4147215976Sjmallett uint32_t prtovrcurract : 1; 4148215976Sjmallett uint32_t prtovrcurrchng : 1; 4149215976Sjmallett uint32_t prtres : 1; 4150215976Sjmallett uint32_t prtsusp : 1; 4151215976Sjmallett uint32_t prtrst : 1; 4152215976Sjmallett uint32_t reserved_9_9 : 1; 4153215976Sjmallett uint32_t prtlnsts : 2; 4154215976Sjmallett uint32_t prtpwr : 1; 4155215976Sjmallett uint32_t prttstctl : 4; 4156215976Sjmallett uint32_t prtspd : 2; 4157215976Sjmallett uint32_t reserved_19_31 : 13; 4158215976Sjmallett#endif 4159215976Sjmallett } s; 4160215976Sjmallett struct cvmx_usbcx_hprt_s cn30xx; 4161215976Sjmallett struct cvmx_usbcx_hprt_s cn31xx; 4162215976Sjmallett struct cvmx_usbcx_hprt_s cn50xx; 4163215976Sjmallett struct cvmx_usbcx_hprt_s cn52xx; 4164215976Sjmallett struct cvmx_usbcx_hprt_s cn52xxp1; 4165215976Sjmallett struct cvmx_usbcx_hprt_s cn56xx; 4166215976Sjmallett struct cvmx_usbcx_hprt_s cn56xxp1; 4167215976Sjmallett}; 4168215976Sjmalletttypedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t; 4169215976Sjmallett 4170215976Sjmallett/** 4171215976Sjmallett * cvmx_usbc#_hptxfsiz 4172215976Sjmallett * 4173215976Sjmallett * Host Periodic Transmit FIFO Size Register (HPTXFSIZ) 4174215976Sjmallett * 4175215976Sjmallett * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311. 4176215976Sjmallett */ 4177215976Sjmallettunion cvmx_usbcx_hptxfsiz 4178215976Sjmallett{ 4179215976Sjmallett uint32_t u32; 4180215976Sjmallett struct cvmx_usbcx_hptxfsiz_s 4181215976Sjmallett { 4182215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4183215976Sjmallett uint32_t ptxfsize : 16; /**< Host Periodic TxFIFO Depth (PTxFSize) 4184215976Sjmallett This value is in terms of 32-bit words. 4185215976Sjmallett * Minimum value is 16 4186215976Sjmallett * Maximum value is 32768 */ 4187215976Sjmallett uint32_t ptxfstaddr : 16; /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */ 4188215976Sjmallett#else 4189215976Sjmallett uint32_t ptxfstaddr : 16; 4190215976Sjmallett uint32_t ptxfsize : 16; 4191215976Sjmallett#endif 4192215976Sjmallett } s; 4193215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn30xx; 4194215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn31xx; 4195215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn50xx; 4196215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn52xx; 4197215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn52xxp1; 4198215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn56xx; 4199215976Sjmallett struct cvmx_usbcx_hptxfsiz_s cn56xxp1; 4200215976Sjmallett}; 4201215976Sjmalletttypedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t; 4202215976Sjmallett 4203215976Sjmallett/** 4204215976Sjmallett * cvmx_usbc#_hptxsts 4205215976Sjmallett * 4206215976Sjmallett * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS) 4207215976Sjmallett * 4208215976Sjmallett * This read-only register contains the free space information for the Periodic TxFIFO and 4209215976Sjmallett * the Periodic Transmit Request Queue 4210215976Sjmallett */ 4211215976Sjmallettunion cvmx_usbcx_hptxsts 4212215976Sjmallett{ 4213215976Sjmallett uint32_t u32; 4214215976Sjmallett struct cvmx_usbcx_hptxsts_s 4215215976Sjmallett { 4216215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4217215976Sjmallett uint32_t ptxqtop : 8; /**< Top of the Periodic Transmit Request Queue (PTxQTop) 4218215976Sjmallett This indicates the entry in the Periodic Tx Request Queue that 4219215976Sjmallett is currently being processes by the MAC. 4220215976Sjmallett This register is used for debugging. 4221215976Sjmallett * Bit [31]: Odd/Even (micro)frame 4222215976Sjmallett - 1'b0: send in even (micro)frame 4223215976Sjmallett - 1'b1: send in odd (micro)frame 4224215976Sjmallett * Bits [30:27]: Channel/endpoint number 4225215976Sjmallett * Bits [26:25]: Type 4226215976Sjmallett - 2'b00: IN/OUT 4227215976Sjmallett - 2'b01: Zero-length packet 4228215976Sjmallett - 2'b10: CSPLIT 4229215976Sjmallett - 2'b11: Disable channel command 4230215976Sjmallett * Bit [24]: Terminate (last entry for the selected 4231215976Sjmallett channel/endpoint) */ 4232215976Sjmallett uint32_t ptxqspcavail : 8; /**< Periodic Transmit Request Queue Space Available 4233215976Sjmallett (PTxQSpcAvail) 4234215976Sjmallett Indicates the number of free locations available to be written in 4235215976Sjmallett the Periodic Transmit Request Queue. This queue holds both 4236215976Sjmallett IN and OUT requests. 4237215976Sjmallett * 8'h0: Periodic Transmit Request Queue is full 4238215976Sjmallett * 8'h1: 1 location available 4239215976Sjmallett * 8'h2: 2 locations available 4240215976Sjmallett * n: n locations available (0..8) 4241215976Sjmallett * Others: Reserved */ 4242215976Sjmallett uint32_t ptxfspcavail : 16; /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail) 4243215976Sjmallett Indicates the number of free locations available to be written to 4244215976Sjmallett in the Periodic TxFIFO. 4245215976Sjmallett Values are in terms of 32-bit words 4246215976Sjmallett * 16'h0: Periodic TxFIFO is full 4247215976Sjmallett * 16'h1: 1 word available 4248215976Sjmallett * 16'h2: 2 words available 4249215976Sjmallett * 16'hn: n words available (where 0..32768) 4250215976Sjmallett * 16'h8000: 32768 words available 4251215976Sjmallett * Others: Reserved */ 4252215976Sjmallett#else 4253215976Sjmallett uint32_t ptxfspcavail : 16; 4254215976Sjmallett uint32_t ptxqspcavail : 8; 4255215976Sjmallett uint32_t ptxqtop : 8; 4256215976Sjmallett#endif 4257215976Sjmallett } s; 4258215976Sjmallett struct cvmx_usbcx_hptxsts_s cn30xx; 4259215976Sjmallett struct cvmx_usbcx_hptxsts_s cn31xx; 4260215976Sjmallett struct cvmx_usbcx_hptxsts_s cn50xx; 4261215976Sjmallett struct cvmx_usbcx_hptxsts_s cn52xx; 4262215976Sjmallett struct cvmx_usbcx_hptxsts_s cn52xxp1; 4263215976Sjmallett struct cvmx_usbcx_hptxsts_s cn56xx; 4264215976Sjmallett struct cvmx_usbcx_hptxsts_s cn56xxp1; 4265215976Sjmallett}; 4266215976Sjmalletttypedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t; 4267215976Sjmallett 4268215976Sjmallett/** 4269215976Sjmallett * cvmx_usbc#_nptxdfifo# 4270215976Sjmallett * 4271215976Sjmallett * NPTX Data Fifo (NPTXDFIFO) 4272215976Sjmallett * 4273215976Sjmallett * A slave mode application uses this register to access the Tx FIFO for channel n. 4274215976Sjmallett */ 4275215976Sjmallettunion cvmx_usbcx_nptxdfifox 4276215976Sjmallett{ 4277215976Sjmallett uint32_t u32; 4278215976Sjmallett struct cvmx_usbcx_nptxdfifox_s 4279215976Sjmallett { 4280215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4281215976Sjmallett uint32_t data : 32; /**< Reserved */ 4282215976Sjmallett#else 4283215976Sjmallett uint32_t data : 32; 4284215976Sjmallett#endif 4285215976Sjmallett } s; 4286215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn30xx; 4287215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn31xx; 4288215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn50xx; 4289215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn52xx; 4290215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn52xxp1; 4291215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn56xx; 4292215976Sjmallett struct cvmx_usbcx_nptxdfifox_s cn56xxp1; 4293215976Sjmallett}; 4294215976Sjmalletttypedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t; 4295215976Sjmallett 4296215976Sjmallett/** 4297215976Sjmallett * cvmx_usbc#_pcgcctl 4298215976Sjmallett * 4299215976Sjmallett * Power and Clock Gating Control Register (PCGCCTL) 4300215976Sjmallett * 4301215976Sjmallett * The application can use this register to control the core's power-down and clock gating features. 4302215976Sjmallett */ 4303215976Sjmallettunion cvmx_usbcx_pcgcctl 4304215976Sjmallett{ 4305215976Sjmallett uint32_t u32; 4306215976Sjmallett struct cvmx_usbcx_pcgcctl_s 4307215976Sjmallett { 4308215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4309215976Sjmallett uint32_t reserved_5_31 : 27; 4310215976Sjmallett uint32_t physuspended : 1; /**< PHY Suspended. (PhySuspended) 4311215976Sjmallett Indicates that the PHY has been suspended. After the 4312215976Sjmallett application sets the Stop Pclk bit (bit 0), this bit is updated once 4313215976Sjmallett the PHY is suspended. 4314215976Sjmallett Since the UTMI+ PHY suspend is controlled through a port, the 4315215976Sjmallett UTMI+ PHY is suspended immediately after Stop Pclk is set. 4316215976Sjmallett However, the ULPI PHY takes a few clocks to suspend, 4317215976Sjmallett because the suspend information is conveyed through the ULPI 4318215976Sjmallett protocol to the ULPI PHY. */ 4319215976Sjmallett uint32_t rstpdwnmodule : 1; /**< Reset Power-Down Modules (RstPdwnModule) 4320215976Sjmallett This bit is valid only in Partial Power-Down mode. The 4321215976Sjmallett application sets this bit when the power is turned off. The 4322215976Sjmallett application clears this bit after the power is turned on and the 4323215976Sjmallett PHY clock is up. */ 4324215976Sjmallett uint32_t pwrclmp : 1; /**< Power Clamp (PwrClmp) 4325215976Sjmallett This bit is only valid in Partial Power-Down mode. The 4326215976Sjmallett application sets this bit before the power is turned off to clamp 4327215976Sjmallett the signals between the power-on modules and the power-off 4328215976Sjmallett modules. The application clears the bit to disable the clamping 4329215976Sjmallett before the power is turned on. */ 4330215976Sjmallett uint32_t gatehclk : 1; /**< Gate Hclk (GateHclk) 4331215976Sjmallett The application sets this bit to gate hclk to modules other than 4332215976Sjmallett the AHB Slave and Master and wakeup logic when the USB is 4333215976Sjmallett suspended or the session is not valid. The application clears 4334215976Sjmallett this bit when the USB is resumed or a new session starts. */ 4335215976Sjmallett uint32_t stoppclk : 1; /**< Stop Pclk (StopPclk) 4336215976Sjmallett The application sets this bit to stop the PHY clock (phy_clk) 4337215976Sjmallett when the USB is suspended, the session is not valid, or the 4338215976Sjmallett device is disconnected. The application clears this bit when the 4339215976Sjmallett USB is resumed or a new session starts. */ 4340215976Sjmallett#else 4341215976Sjmallett uint32_t stoppclk : 1; 4342215976Sjmallett uint32_t gatehclk : 1; 4343215976Sjmallett uint32_t pwrclmp : 1; 4344215976Sjmallett uint32_t rstpdwnmodule : 1; 4345215976Sjmallett uint32_t physuspended : 1; 4346215976Sjmallett uint32_t reserved_5_31 : 27; 4347215976Sjmallett#endif 4348215976Sjmallett } s; 4349215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn30xx; 4350215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn31xx; 4351215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn50xx; 4352215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn52xx; 4353215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn52xxp1; 4354215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn56xx; 4355215976Sjmallett struct cvmx_usbcx_pcgcctl_s cn56xxp1; 4356215976Sjmallett}; 4357215976Sjmalletttypedef union cvmx_usbcx_pcgcctl cvmx_usbcx_pcgcctl_t; 4358215976Sjmallett 4359215976Sjmallett#endif 4360