1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-uctlx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon uctlx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_UCTLX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_UCTLX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 60215976Sjmallett cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F0000A0ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallettstatic inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id) 68215976Sjmallett{ 69215976Sjmallett if (!( 70215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 71215976Sjmallett cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000000ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallettstatic inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id) 79215976Sjmallett{ 80215976Sjmallett if (!( 81215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 82215976Sjmallett cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000080ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallettstatic inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id) 90215976Sjmallett{ 91215976Sjmallett if (!( 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 93215976Sjmallett cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F0000A8ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id) 101215976Sjmallett{ 102215976Sjmallett if (!( 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 104215976Sjmallett cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000090ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallettstatic inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id) 112215976Sjmallett{ 113215976Sjmallett if (!( 114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 115215976Sjmallett cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000030ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallettstatic inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id) 123215976Sjmallett{ 124215976Sjmallett if (!( 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 126215976Sjmallett cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000028ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallettstatic inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id) 134215976Sjmallett{ 135215976Sjmallett if (!( 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 137215976Sjmallett cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000020ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallettstatic inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id) 145215976Sjmallett{ 146215976Sjmallett if (!( 147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 148215976Sjmallett cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000088ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallettstatic inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id) 156215976Sjmallett{ 157215976Sjmallett if (!( 158215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 159215976Sjmallett cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000098ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallettstatic inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id) 167215976Sjmallett{ 168215976Sjmallett if (!( 169215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 170215976Sjmallett cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000038ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallettstatic inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id) 178215976Sjmallett{ 179215976Sjmallett if (!( 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 181215976Sjmallett cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000008ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull)) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0)))))) 192215976Sjmallett cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8; 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8) 197215976Sjmallett#endif 198215976Sjmallett 199215976Sjmallett/** 200215976Sjmallett * cvmx_uctl#_bist_status 201215976Sjmallett * 202215976Sjmallett * UCTL_BIST_STATUS = UCTL Bist Status 203215976Sjmallett * 204215976Sjmallett * Results from BIST runs of UCTL's memories. 205215976Sjmallett */ 206215976Sjmallettunion cvmx_uctlx_bist_status 207215976Sjmallett{ 208215976Sjmallett uint64_t u64; 209215976Sjmallett struct cvmx_uctlx_bist_status_s 210215976Sjmallett { 211215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 212215976Sjmallett uint64_t reserved_6_63 : 58; 213215976Sjmallett uint64_t data_bis : 1; /**< UAHC EHCI Data Ram Bist Status */ 214215976Sjmallett uint64_t desc_bis : 1; /**< UAHC EHCI Descriptor Ram Bist Status */ 215215976Sjmallett uint64_t erbm_bis : 1; /**< UCTL EHCI Read Buffer Memory Bist Status */ 216215976Sjmallett uint64_t orbm_bis : 1; /**< UCTL OHCI Read Buffer Memory Bist Status */ 217215976Sjmallett uint64_t wrbm_bis : 1; /**< UCTL Write Buffer Memory Bist Sta */ 218215976Sjmallett uint64_t ppaf_bis : 1; /**< PP Access FIFO Memory Bist Status */ 219215976Sjmallett#else 220215976Sjmallett uint64_t ppaf_bis : 1; 221215976Sjmallett uint64_t wrbm_bis : 1; 222215976Sjmallett uint64_t orbm_bis : 1; 223215976Sjmallett uint64_t erbm_bis : 1; 224215976Sjmallett uint64_t desc_bis : 1; 225215976Sjmallett uint64_t data_bis : 1; 226215976Sjmallett uint64_t reserved_6_63 : 58; 227215976Sjmallett#endif 228215976Sjmallett } s; 229215976Sjmallett struct cvmx_uctlx_bist_status_s cn63xx; 230215976Sjmallett struct cvmx_uctlx_bist_status_s cn63xxp1; 231215976Sjmallett}; 232215976Sjmalletttypedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t; 233215976Sjmallett 234215976Sjmallett/** 235215976Sjmallett * cvmx_uctl#_clk_rst_ctl 236215976Sjmallett * 237215976Sjmallett * CLK_RST_CTL = Clock and Reset Control Reigster 238215976Sjmallett * This register controls the frequceny of hclk and resets for hclk and phy clocks. It also controls Simulation modes and Bists. 239215976Sjmallett */ 240215976Sjmallettunion cvmx_uctlx_clk_rst_ctl 241215976Sjmallett{ 242215976Sjmallett uint64_t u64; 243215976Sjmallett struct cvmx_uctlx_clk_rst_ctl_s 244215976Sjmallett { 245215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 246215976Sjmallett uint64_t reserved_25_63 : 39; 247215976Sjmallett uint64_t clear_bist : 1; /**< Clear BIST on the HCLK memories */ 248215976Sjmallett uint64_t start_bist : 1; /**< Starts BIST on the HCLK memories during 0-to-1 249215976Sjmallett transition. */ 250215976Sjmallett uint64_t ehci_sm : 1; /**< Only set it during simulation time. When set to 1, 251215976Sjmallett this bit sets the PHY in a non-driving mode so the 252215976Sjmallett EHCI can detect device connection. 253215976Sjmallett Note: it must not be set to 1, during normal 254215976Sjmallett operation. */ 255215976Sjmallett uint64_t ohci_clkcktrst : 1; /**< Clear clock reset. Active low. OHCI initial reset 256215976Sjmallett signal for the DPLL block. This is only needed by 257215976Sjmallett simulation. The duration of the reset in simulation 258215976Sjmallett must be the same as HRST. 259215976Sjmallett Note: it must be set to 1 during normal operation. */ 260215976Sjmallett uint64_t ohci_sm : 1; /**< OHCI Simulation Mode. It selects the counter value 261215976Sjmallett for simulation or real time for 1 ms. 262215976Sjmallett - 0: counter full 1ms; 1: simulation time. */ 263215976Sjmallett uint64_t ohci_susp_lgcy : 1; /**< OHCI Clock Control Signal. Note: This bit must be 264215976Sjmallett set to 0 if the OHCI 48/12Mhz clocks must be 265215976Sjmallett suspended when the EHCI and OHCI controllers are 266215976Sjmallett not active. */ 267215976Sjmallett uint64_t app_start_clk : 1; /**< OHCI Clock Control Signal. When the OHCI clocks are 268215976Sjmallett suspended, the system has to assert this signal to 269215976Sjmallett start the clocks (12 and 48 Mhz). */ 270215976Sjmallett uint64_t o_clkdiv_rst : 1; /**< OHCI 12Mhz clock divider reset. Active low. When 271215976Sjmallett set to 0, divider is held in reset. 272215976Sjmallett The reset to the divider is also asserted when core 273215976Sjmallett reset is asserted. */ 274215976Sjmallett uint64_t h_clkdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV */ 275215976Sjmallett uint64_t h_clkdiv_rst : 1; /**< Host clock divider reset. Active low. When set to 0, 276215976Sjmallett divider is held in reset. This must be set to 0 277215976Sjmallett before change H_DIV0 and H_DIV1. 278215976Sjmallett The reset to the divider is also asserted when core 279215976Sjmallett reset is asserted. */ 280215976Sjmallett uint64_t h_clkdiv_en : 1; /**< Hclk enable. When set to 1, the hclk is gernerated. */ 281215976Sjmallett uint64_t o_clkdiv_en : 1; /**< OHCI 48Mhz/12MHz clock enable. When set to 1, the 282215976Sjmallett clocks are gernerated. */ 283215976Sjmallett uint64_t h_div : 4; /**< The hclk frequency is sclk frequency divided by 284215976Sjmallett H_DIV. The maximum frequency of hclk is 200Mhz. 285215976Sjmallett The minimum frequency of hclk is no less than the 286215976Sjmallett UTMI clock frequency which is 60Mhz. After writing a 287215976Sjmallett value to this field, the software should read the 288215976Sjmallett field for the value written. The [H_ENABLE] field of 289215976Sjmallett this register should not be set until after this 290215976Sjmallett field is set and then read. 291215976Sjmallett Only the following values are valid: 292215976Sjmallett 1, 2, 3, 4, 6, 8, 12. 293215976Sjmallett All other values are reserved and will be coded as 294215976Sjmallett following: 295215976Sjmallett 0 -> 1 296215976Sjmallett 5 -> 4 297215976Sjmallett 7 -> 6 298215976Sjmallett 9,10,11 -> 8 299215976Sjmallett 13,14,15 -> 12 */ 300215976Sjmallett uint64_t p_refclk_sel : 2; /**< PHY PLL Reference Clock Select. 301215976Sjmallett - 00: uses 12Mhz crystal at USB_XO and USB_XI; 302215976Sjmallett - 01: uses 12/24/48Mhz 2.5V clock source at USB_XO. 303215976Sjmallett USB_XI should be tied to GND. 304215976Sjmallett 1x: Reserved. */ 305215976Sjmallett uint64_t p_refclk_div : 2; /**< PHY Reference Clock Frequency Select. 306215976Sjmallett - 00: 12MHz, 01: 24Mhz, 10: 48Mhz, 11: Reserved. 307215976Sjmallett Note: This value must be set during POR is active. 308215976Sjmallett If a crystal is used as a reference clock,this field 309215976Sjmallett must be set to 12 MHz. Values 01 and 10 are reserved 310215976Sjmallett when a crystal is used. */ 311215976Sjmallett uint64_t reserved_4_4 : 1; 312215976Sjmallett uint64_t p_com_on : 1; /**< PHY Common Block Power-Down Control. 313215976Sjmallett - 1: The XO, Bias, and PLL blocks are powered down in 314215976Sjmallett Suspend mode. 315215976Sjmallett - 0: The XO, Bias, and PLL blocks remain powered in 316215976Sjmallett suspend mode. 317215976Sjmallett Note: This bit must be set to 0 during POR is active 318215976Sjmallett in current design. */ 319215976Sjmallett uint64_t p_por : 1; /**< Power on reset for PHY. Resets all the PHY's 320215976Sjmallett registers and state machines. */ 321215976Sjmallett uint64_t p_prst : 1; /**< PHY Clock Reset. The is the value for phy_rst_n, 322215976Sjmallett utmi_rst_n[1] and utmi_rst_n[0]. It is synchronized 323215976Sjmallett to each clock domain to generate the corresponding 324215976Sjmallett reset signal. This should not be set to 1 until the 325215976Sjmallett time it takes for six clock cycles (HCLK and 326215976Sjmallett PHY CLK, which ever is slower) has passed. */ 327215976Sjmallett uint64_t hrst : 1; /**< Host Clock Reset. This is the value for hreset_n. 328215976Sjmallett This should not be set to 1 until 12ms after PHY CLK 329215976Sjmallett is stable. */ 330215976Sjmallett#else 331215976Sjmallett uint64_t hrst : 1; 332215976Sjmallett uint64_t p_prst : 1; 333215976Sjmallett uint64_t p_por : 1; 334215976Sjmallett uint64_t p_com_on : 1; 335215976Sjmallett uint64_t reserved_4_4 : 1; 336215976Sjmallett uint64_t p_refclk_div : 2; 337215976Sjmallett uint64_t p_refclk_sel : 2; 338215976Sjmallett uint64_t h_div : 4; 339215976Sjmallett uint64_t o_clkdiv_en : 1; 340215976Sjmallett uint64_t h_clkdiv_en : 1; 341215976Sjmallett uint64_t h_clkdiv_rst : 1; 342215976Sjmallett uint64_t h_clkdiv_byp : 1; 343215976Sjmallett uint64_t o_clkdiv_rst : 1; 344215976Sjmallett uint64_t app_start_clk : 1; 345215976Sjmallett uint64_t ohci_susp_lgcy : 1; 346215976Sjmallett uint64_t ohci_sm : 1; 347215976Sjmallett uint64_t ohci_clkcktrst : 1; 348215976Sjmallett uint64_t ehci_sm : 1; 349215976Sjmallett uint64_t start_bist : 1; 350215976Sjmallett uint64_t clear_bist : 1; 351215976Sjmallett uint64_t reserved_25_63 : 39; 352215976Sjmallett#endif 353215976Sjmallett } s; 354215976Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn63xx; 355215976Sjmallett struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1; 356215976Sjmallett}; 357215976Sjmalletttypedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t; 358215976Sjmallett 359215976Sjmallett/** 360215976Sjmallett * cvmx_uctl#_ehci_ctl 361215976Sjmallett * 362215976Sjmallett * UCTL_EHCI_CTL = UCTL EHCI Control Register 363215976Sjmallett * This register controls the general behavior of UCTL EHCI datapath. 364215976Sjmallett */ 365215976Sjmallettunion cvmx_uctlx_ehci_ctl 366215976Sjmallett{ 367215976Sjmallett uint64_t u64; 368215976Sjmallett struct cvmx_uctlx_ehci_ctl_s 369215976Sjmallett { 370215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 371215976Sjmallett uint64_t reserved_20_63 : 44; 372215976Sjmallett uint64_t desc_rbm : 1; /**< Descriptor Read Burst Mode on AHB bus 373215976Sjmallett - 1: A read burst can be interruprted after 16 AHB 374215976Sjmallett clock cycle 375215976Sjmallett - 0: A read burst will not be interrupted until it 376215976Sjmallett finishes or no more data available */ 377215976Sjmallett uint64_t reg_nb : 1; /**< 1: EHCI register access will not be blocked by EHCI 378215976Sjmallett buffer/descriptor access on AHB 379215976Sjmallett - 0: Buffer/descriptor and register access will be 380215976Sjmallett mutually exclusive */ 381215976Sjmallett uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor 382215976Sjmallett store commands to L2C. */ 383215976Sjmallett uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer 384215976Sjmallett store commands to L2C. */ 385215976Sjmallett uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store 386215976Sjmallett command to L2C. */ 387215976Sjmallett uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */ 388215976Sjmallett uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C. 389215976Sjmallett IN: A-B-C-D-E-F-G-H 390215976Sjmallett OUT0: A-B-C-D-E-F-G-H 391215976Sjmallett OUT1: H-G-F-E-D-C-B-A 392215976Sjmallett OUT2: D-C-B-A-H-G-F-E 393215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 394215976Sjmallett uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C. 395215976Sjmallett IN: A-B-C-D-E-F-G-H 396215976Sjmallett OUT0: A-B-C-D-E-F-G-H 397215976Sjmallett OUT1: H-G-F-E-D-C-B-A 398215976Sjmallett OUT2: D-C-B-A-H-G-F-E 399215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 400215976Sjmallett uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1, 401215976Sjmallett for a 32-bit NCB I/O register access, the address 402215976Sjmallett offset will be flipped between 0x4 and 0x0. */ 403215976Sjmallett uint64_t ehci_64b_addr_en : 1; /**< EHCI AHB Master 64-bit Addressing Enable. 404215976Sjmallett - 1: enable ehci 64-bit addressing mode; 405215976Sjmallett - 0: disable ehci 64-bit addressing mode. 406215976Sjmallett When ehci 64-bit addressing mode is disabled, 407215976Sjmallett UCTL_EHCI_CTL[L2C_ADDR_MSB] is used as the address 408215976Sjmallett bit[39:32]. */ 409215976Sjmallett uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C 410215976Sjmallett for ehci whenUCTL_EHCI_CFG[EHCI_64B_ADDR_EN=0]). */ 411215976Sjmallett#else 412215976Sjmallett uint64_t l2c_addr_msb : 8; 413215976Sjmallett uint64_t ehci_64b_addr_en : 1; 414215976Sjmallett uint64_t inv_reg_a2 : 1; 415215976Sjmallett uint64_t l2c_desc_emod : 2; 416215976Sjmallett uint64_t l2c_buff_emod : 2; 417215976Sjmallett uint64_t l2c_stt : 1; 418215976Sjmallett uint64_t l2c_0pag : 1; 419215976Sjmallett uint64_t l2c_bc : 1; 420215976Sjmallett uint64_t l2c_dc : 1; 421215976Sjmallett uint64_t reg_nb : 1; 422215976Sjmallett uint64_t desc_rbm : 1; 423215976Sjmallett uint64_t reserved_20_63 : 44; 424215976Sjmallett#endif 425215976Sjmallett } s; 426215976Sjmallett struct cvmx_uctlx_ehci_ctl_s cn63xx; 427215976Sjmallett struct cvmx_uctlx_ehci_ctl_s cn63xxp1; 428215976Sjmallett}; 429215976Sjmalletttypedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t; 430215976Sjmallett 431215976Sjmallett/** 432215976Sjmallett * cvmx_uctl#_ehci_fla 433215976Sjmallett * 434215976Sjmallett * UCTL_EHCI_FLA = UCTL EHCI Frame Length Adjument Register 435215976Sjmallett * This register configures the EHCI Frame Length Adjustment. 436215976Sjmallett */ 437215976Sjmallettunion cvmx_uctlx_ehci_fla 438215976Sjmallett{ 439215976Sjmallett uint64_t u64; 440215976Sjmallett struct cvmx_uctlx_ehci_fla_s 441215976Sjmallett { 442215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 443215976Sjmallett uint64_t reserved_6_63 : 58; 444215976Sjmallett uint64_t fla : 6; /**< EHCI Frame Length Adjustment. This feature 445215976Sjmallett adjusts any offset from the clock source that drives 446215976Sjmallett the uSOF counter. The default value is 32(0x20), 447215976Sjmallett which gives an SOF cycle time of 60,0000 (each 448215976Sjmallett microframe has 60,000 bit times). 449215976Sjmallett Note: keep this value to 0x20 (decimal 32) for no 450215976Sjmallett offset. */ 451215976Sjmallett#else 452215976Sjmallett uint64_t fla : 6; 453215976Sjmallett uint64_t reserved_6_63 : 58; 454215976Sjmallett#endif 455215976Sjmallett } s; 456215976Sjmallett struct cvmx_uctlx_ehci_fla_s cn63xx; 457215976Sjmallett struct cvmx_uctlx_ehci_fla_s cn63xxp1; 458215976Sjmallett}; 459215976Sjmalletttypedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t; 460215976Sjmallett 461215976Sjmallett/** 462215976Sjmallett * cvmx_uctl#_erto_ctl 463215976Sjmallett * 464215976Sjmallett * UCTL_ERTO_CTL = UCTL EHCI Readbuffer TimeOut Control Register 465215976Sjmallett * This register controls timeout for EHCI Readbuffer. 466215976Sjmallett */ 467215976Sjmallettunion cvmx_uctlx_erto_ctl 468215976Sjmallett{ 469215976Sjmallett uint64_t u64; 470215976Sjmallett struct cvmx_uctlx_erto_ctl_s 471215976Sjmallett { 472215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 473215976Sjmallett uint64_t reserved_32_63 : 32; 474215976Sjmallett uint64_t to_val : 27; /**< Read buffer timeout value 475215976Sjmallett (value 0 means timeout disabled) */ 476215976Sjmallett uint64_t reserved_0_4 : 5; 477215976Sjmallett#else 478215976Sjmallett uint64_t reserved_0_4 : 5; 479215976Sjmallett uint64_t to_val : 27; 480215976Sjmallett uint64_t reserved_32_63 : 32; 481215976Sjmallett#endif 482215976Sjmallett } s; 483215976Sjmallett struct cvmx_uctlx_erto_ctl_s cn63xx; 484215976Sjmallett struct cvmx_uctlx_erto_ctl_s cn63xxp1; 485215976Sjmallett}; 486215976Sjmalletttypedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t; 487215976Sjmallett 488215976Sjmallett/** 489215976Sjmallett * cvmx_uctl#_if_ena 490215976Sjmallett * 491215976Sjmallett * UCTL_IF_ENA = UCTL Interface Enable Register 492215976Sjmallett * 493215976Sjmallett * Register to enable the uctl interface clock. 494215976Sjmallett */ 495215976Sjmallettunion cvmx_uctlx_if_ena 496215976Sjmallett{ 497215976Sjmallett uint64_t u64; 498215976Sjmallett struct cvmx_uctlx_if_ena_s 499215976Sjmallett { 500215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 501215976Sjmallett uint64_t reserved_1_63 : 63; 502215976Sjmallett uint64_t en : 1; /**< Turns on the USB UCTL interface clock */ 503215976Sjmallett#else 504215976Sjmallett uint64_t en : 1; 505215976Sjmallett uint64_t reserved_1_63 : 63; 506215976Sjmallett#endif 507215976Sjmallett } s; 508215976Sjmallett struct cvmx_uctlx_if_ena_s cn63xx; 509215976Sjmallett struct cvmx_uctlx_if_ena_s cn63xxp1; 510215976Sjmallett}; 511215976Sjmalletttypedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t; 512215976Sjmallett 513215976Sjmallett/** 514215976Sjmallett * cvmx_uctl#_int_ena 515215976Sjmallett * 516215976Sjmallett * UCTL_INT_ENA = UCTL Interrupt Enable Register 517215976Sjmallett * 518215976Sjmallett * Register to enable individual interrupt source in corresponding to UCTL_INT_REG 519215976Sjmallett */ 520215976Sjmallettunion cvmx_uctlx_int_ena 521215976Sjmallett{ 522215976Sjmallett uint64_t u64; 523215976Sjmallett struct cvmx_uctlx_int_ena_s 524215976Sjmallett { 525215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 526215976Sjmallett uint64_t reserved_8_63 : 56; 527215976Sjmallett uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error */ 528215976Sjmallett uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error */ 529215976Sjmallett uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */ 530215976Sjmallett uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */ 531215976Sjmallett uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */ 532215976Sjmallett uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */ 533215976Sjmallett uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */ 534215976Sjmallett uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */ 535215976Sjmallett#else 536215976Sjmallett uint64_t pp_psh_f : 1; 537215976Sjmallett uint64_t er_psh_f : 1; 538215976Sjmallett uint64_t or_psh_f : 1; 539215976Sjmallett uint64_t cf_psh_f : 1; 540215976Sjmallett uint64_t wb_psh_f : 1; 541215976Sjmallett uint64_t wb_pop_e : 1; 542215976Sjmallett uint64_t oc_ovf_e : 1; 543215976Sjmallett uint64_t ec_ovf_e : 1; 544215976Sjmallett uint64_t reserved_8_63 : 56; 545215976Sjmallett#endif 546215976Sjmallett } s; 547215976Sjmallett struct cvmx_uctlx_int_ena_s cn63xx; 548215976Sjmallett struct cvmx_uctlx_int_ena_s cn63xxp1; 549215976Sjmallett}; 550215976Sjmalletttypedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t; 551215976Sjmallett 552215976Sjmallett/** 553215976Sjmallett * cvmx_uctl#_int_reg 554215976Sjmallett * 555215976Sjmallett * UCTL_INT_REG = UCTL Interrupt Register 556215976Sjmallett * 557215976Sjmallett * Summary of different bits of RSL interrupt status. 558215976Sjmallett */ 559215976Sjmallettunion cvmx_uctlx_int_reg 560215976Sjmallett{ 561215976Sjmallett uint64_t u64; 562215976Sjmallett struct cvmx_uctlx_int_reg_s 563215976Sjmallett { 564215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 565215976Sjmallett uint64_t reserved_8_63 : 56; 566215976Sjmallett uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error 567215976Sjmallett When the error happenes, the whole NCB system needs 568215976Sjmallett to be reset. */ 569215976Sjmallett uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error 570215976Sjmallett When the error happenes, the whole NCB system needs 571215976Sjmallett to be reset. */ 572215976Sjmallett uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */ 573215976Sjmallett uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */ 574215976Sjmallett uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */ 575215976Sjmallett uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */ 576215976Sjmallett uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */ 577215976Sjmallett uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */ 578215976Sjmallett#else 579215976Sjmallett uint64_t pp_psh_f : 1; 580215976Sjmallett uint64_t er_psh_f : 1; 581215976Sjmallett uint64_t or_psh_f : 1; 582215976Sjmallett uint64_t cf_psh_f : 1; 583215976Sjmallett uint64_t wb_psh_f : 1; 584215976Sjmallett uint64_t wb_pop_e : 1; 585215976Sjmallett uint64_t oc_ovf_e : 1; 586215976Sjmallett uint64_t ec_ovf_e : 1; 587215976Sjmallett uint64_t reserved_8_63 : 56; 588215976Sjmallett#endif 589215976Sjmallett } s; 590215976Sjmallett struct cvmx_uctlx_int_reg_s cn63xx; 591215976Sjmallett struct cvmx_uctlx_int_reg_s cn63xxp1; 592215976Sjmallett}; 593215976Sjmalletttypedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t; 594215976Sjmallett 595215976Sjmallett/** 596215976Sjmallett * cvmx_uctl#_ohci_ctl 597215976Sjmallett * 598215976Sjmallett * RSL registers starting from 0x10 can be accessed only after hclk is active and hreset is deasserted. 599215976Sjmallett * 600215976Sjmallett * UCTL_OHCI_CTL = UCTL OHCI Control Register 601215976Sjmallett * This register controls the general behavior of UCTL OHCI datapath. 602215976Sjmallett */ 603215976Sjmallettunion cvmx_uctlx_ohci_ctl 604215976Sjmallett{ 605215976Sjmallett uint64_t u64; 606215976Sjmallett struct cvmx_uctlx_ohci_ctl_s 607215976Sjmallett { 608215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 609215976Sjmallett uint64_t reserved_19_63 : 45; 610215976Sjmallett uint64_t reg_nb : 1; /**< 1: OHCI register access will not be blocked by EHCI 611215976Sjmallett buffer/descriptor access on AHB 612215976Sjmallett - 0: Buffer/descriptor and register access will be 613215976Sjmallett mutually exclusive */ 614215976Sjmallett uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor 615215976Sjmallett store commands to L2C. */ 616215976Sjmallett uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer 617215976Sjmallett store commands to L2C. */ 618215976Sjmallett uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store 619215976Sjmallett command to L2C. */ 620215976Sjmallett uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */ 621215976Sjmallett uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C. 622215976Sjmallett IN: A-B-C-D-E-F-G-H 623215976Sjmallett OUT0: A-B-C-D-E-F-G-H 624215976Sjmallett OUT1: H-G-F-E-D-C-B-A 625215976Sjmallett OUT2: D-C-B-A-H-G-F-E 626215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 627215976Sjmallett uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C. 628215976Sjmallett IN: A-B-C-D-E-F-G-H 629215976Sjmallett OUT0: A-B-C-D-E-F-G-H 630215976Sjmallett OUT1: H-G-F-E-D-C-B-A 631215976Sjmallett OUT2: D-C-B-A-H-G-F-E 632215976Sjmallett OUT3: E-F-G-H-A-B-C-D */ 633215976Sjmallett uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1, 634215976Sjmallett for a 32-bit NCB I/O register access, the address 635215976Sjmallett offset will be flipped between 0x4 and 0x0. */ 636215976Sjmallett uint64_t reserved_8_8 : 1; 637215976Sjmallett uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C 638215976Sjmallett for ohci. */ 639215976Sjmallett#else 640215976Sjmallett uint64_t l2c_addr_msb : 8; 641215976Sjmallett uint64_t reserved_8_8 : 1; 642215976Sjmallett uint64_t inv_reg_a2 : 1; 643215976Sjmallett uint64_t l2c_desc_emod : 2; 644215976Sjmallett uint64_t l2c_buff_emod : 2; 645215976Sjmallett uint64_t l2c_stt : 1; 646215976Sjmallett uint64_t l2c_0pag : 1; 647215976Sjmallett uint64_t l2c_bc : 1; 648215976Sjmallett uint64_t l2c_dc : 1; 649215976Sjmallett uint64_t reg_nb : 1; 650215976Sjmallett uint64_t reserved_19_63 : 45; 651215976Sjmallett#endif 652215976Sjmallett } s; 653215976Sjmallett struct cvmx_uctlx_ohci_ctl_s cn63xx; 654215976Sjmallett struct cvmx_uctlx_ohci_ctl_s cn63xxp1; 655215976Sjmallett}; 656215976Sjmalletttypedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t; 657215976Sjmallett 658215976Sjmallett/** 659215976Sjmallett * cvmx_uctl#_orto_ctl 660215976Sjmallett * 661215976Sjmallett * UCTL_ORTO_CTL = UCTL OHCI Readbuffer TimeOut Control Register 662215976Sjmallett * This register controls timeout for OHCI Readbuffer. 663215976Sjmallett */ 664215976Sjmallettunion cvmx_uctlx_orto_ctl 665215976Sjmallett{ 666215976Sjmallett uint64_t u64; 667215976Sjmallett struct cvmx_uctlx_orto_ctl_s 668215976Sjmallett { 669215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 670215976Sjmallett uint64_t reserved_32_63 : 32; 671215976Sjmallett uint64_t to_val : 24; /**< Read buffer timeout value 672215976Sjmallett (value 0 means timeout disabled) */ 673215976Sjmallett uint64_t reserved_0_7 : 8; 674215976Sjmallett#else 675215976Sjmallett uint64_t reserved_0_7 : 8; 676215976Sjmallett uint64_t to_val : 24; 677215976Sjmallett uint64_t reserved_32_63 : 32; 678215976Sjmallett#endif 679215976Sjmallett } s; 680215976Sjmallett struct cvmx_uctlx_orto_ctl_s cn63xx; 681215976Sjmallett struct cvmx_uctlx_orto_ctl_s cn63xxp1; 682215976Sjmallett}; 683215976Sjmalletttypedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t; 684215976Sjmallett 685215976Sjmallett/** 686215976Sjmallett * cvmx_uctl#_ppaf_wm 687215976Sjmallett * 688215976Sjmallett * UCTL_PPAF_WM = UCTL PP Access FIFO WaterMark Register 689215976Sjmallett * 690215976Sjmallett * Register to set PP access FIFO full watermark. 691215976Sjmallett */ 692215976Sjmallettunion cvmx_uctlx_ppaf_wm 693215976Sjmallett{ 694215976Sjmallett uint64_t u64; 695215976Sjmallett struct cvmx_uctlx_ppaf_wm_s 696215976Sjmallett { 697215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 698215976Sjmallett uint64_t reserved_5_63 : 59; 699215976Sjmallett uint64_t wm : 5; /**< Number of entries when PP Access FIFO will assert 700215976Sjmallett full (back pressure) */ 701215976Sjmallett#else 702215976Sjmallett uint64_t wm : 5; 703215976Sjmallett uint64_t reserved_5_63 : 59; 704215976Sjmallett#endif 705215976Sjmallett } s; 706215976Sjmallett struct cvmx_uctlx_ppaf_wm_s cn63xx; 707215976Sjmallett struct cvmx_uctlx_ppaf_wm_s cn63xxp1; 708215976Sjmallett}; 709215976Sjmalletttypedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t; 710215976Sjmallett 711215976Sjmallett/** 712215976Sjmallett * cvmx_uctl#_uphy_ctl_status 713215976Sjmallett * 714215976Sjmallett * UPHY_CTL_STATUS = USB PHY Control and Status Reigster 715215976Sjmallett * This register controls the USB PHY test and Bist. 716215976Sjmallett */ 717215976Sjmallettunion cvmx_uctlx_uphy_ctl_status 718215976Sjmallett{ 719215976Sjmallett uint64_t u64; 720215976Sjmallett struct cvmx_uctlx_uphy_ctl_status_s 721215976Sjmallett { 722215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 723215976Sjmallett uint64_t reserved_10_63 : 54; 724215976Sjmallett uint64_t bist_done : 1; /**< PHY BIST DONE. Asserted at the end of the PHY BIST 725215976Sjmallett sequence. */ 726215976Sjmallett uint64_t bist_err : 1; /**< PHY BIST Error. Valid when BIST_ENB is high. 727215976Sjmallett Indicates an internal error was detected during the 728215976Sjmallett BIST sequence. */ 729215976Sjmallett uint64_t hsbist : 1; /**< High-Speed BIST Enable */ 730215976Sjmallett uint64_t fsbist : 1; /**< Full-Speed BIST Enable */ 731215976Sjmallett uint64_t lsbist : 1; /**< Low-Speed BIST Enable */ 732215976Sjmallett uint64_t siddq : 1; /**< Drives the PHY SIDDQ input. Normally should be set 733215976Sjmallett to zero. Customers not using USB PHY interface 734215976Sjmallett should do the following: 735215976Sjmallett Provide 3.3V to USB_VDD33 Tie USB_REXT to 3.3V 736215976Sjmallett supply and Set SIDDQ to 1. */ 737215976Sjmallett uint64_t vtest_en : 1; /**< Analog Test Pin Enable. 738215976Sjmallett 1 = The PHY's ANALOG _TEST pin is enabled for the 739215976Sjmallett input and output of applicable analog test 740215976Sjmallett signals. 741215976Sjmallett 0 = The ANALOG_TEST pin is disabled. */ 742215976Sjmallett uint64_t uphy_bist : 1; /**< When set to 1, it makes sure that during PHY BIST, 743215976Sjmallett utmi_txvld == 0. */ 744215976Sjmallett uint64_t bist_en : 1; /**< PHY BIST ENABLE */ 745215976Sjmallett uint64_t ate_reset : 1; /**< Reset Input from ATE. This is a test signal. When 746215976Sjmallett the USB core is powered up (not in suspend mode), an 747215976Sjmallett automatic tester can use this to disable PHYCLOCK 748215976Sjmallett and FREECLK, then re-enable them with an aligned 749215976Sjmallett phase. 750215976Sjmallett - 1: PHYCLOCKs and FREECLK outputs are disable. 751215976Sjmallett - 0: PHYCLOCKs and FREECLK are available within a 752215976Sjmallett specific period after ATERESET is de-asserted. */ 753215976Sjmallett#else 754215976Sjmallett uint64_t ate_reset : 1; 755215976Sjmallett uint64_t bist_en : 1; 756215976Sjmallett uint64_t uphy_bist : 1; 757215976Sjmallett uint64_t vtest_en : 1; 758215976Sjmallett uint64_t siddq : 1; 759215976Sjmallett uint64_t lsbist : 1; 760215976Sjmallett uint64_t fsbist : 1; 761215976Sjmallett uint64_t hsbist : 1; 762215976Sjmallett uint64_t bist_err : 1; 763215976Sjmallett uint64_t bist_done : 1; 764215976Sjmallett uint64_t reserved_10_63 : 54; 765215976Sjmallett#endif 766215976Sjmallett } s; 767215976Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn63xx; 768215976Sjmallett struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1; 769215976Sjmallett}; 770215976Sjmalletttypedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t; 771215976Sjmallett 772215976Sjmallett/** 773215976Sjmallett * cvmx_uctl#_uphy_port#_ctl_status 774215976Sjmallett * 775215976Sjmallett * UPHY_PORTX_CTL_STATUS = USB PHY Port X Control and Status Reigsters 776215976Sjmallett * This register controls the each port of the USB PHY. 777215976Sjmallett */ 778215976Sjmallettunion cvmx_uctlx_uphy_portx_ctl_status 779215976Sjmallett{ 780215976Sjmallett uint64_t u64; 781215976Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s 782215976Sjmallett { 783215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 784215976Sjmallett uint64_t reserved_43_63 : 21; 785215976Sjmallett uint64_t tdata_out : 4; /**< PHY test data out. Presents either interlly 786215976Sjmallett generated signals or test register contenets, based 787215976Sjmallett upon the value of TDATA_SEL */ 788215976Sjmallett uint64_t txbiststuffenh : 1; /**< High-Byte Transmit Bit-Stuffing Enable. It must be 789215976Sjmallett set to 1'b1 in normal operation. */ 790215976Sjmallett uint64_t txbiststuffen : 1; /**< Low-Byte Transmit Bit-Stuffing Enable. It must be 791215976Sjmallett set to 1'b1 in normal operation. */ 792215976Sjmallett uint64_t dmpulldown : 1; /**< D- Pull-Down Resistor Enable. It must be set to 1'b1 793215976Sjmallett in normal operation. */ 794215976Sjmallett uint64_t dppulldown : 1; /**< D+ Pull-Down Resistor Enable. It must be set to 1'b1 795215976Sjmallett in normal operation. */ 796215976Sjmallett uint64_t vbusvldext : 1; /**< In host mode, this input is not used and can be tied 797215976Sjmallett to 1'b0. */ 798215976Sjmallett uint64_t portreset : 1; /**< Per-port reset */ 799215976Sjmallett uint64_t txhsvxtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 800215976Sjmallett uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 801215976Sjmallett uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 802215976Sjmallett uint64_t txpreemphasistune : 1; /**< HS transmitter pre-emphasis enable. */ 803215976Sjmallett uint64_t txfslstune : 4; /**< FS/LS Source Impedance Adjustment */ 804215976Sjmallett uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 805215976Sjmallett uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 806215976Sjmallett uint64_t loop_en : 1; /**< Port Loop back Test Enable 807215976Sjmallett - 1: During data transmission, the receive logic is 808215976Sjmallett enabled 809215976Sjmallett - 0: During data transmission, the receive logic is 810215976Sjmallett disabled */ 811215976Sjmallett uint64_t tclk : 1; /**< PHY port test clock, used to load TDATA_IN to the 812215976Sjmallett UPHY. */ 813215976Sjmallett uint64_t tdata_sel : 1; /**< Test Data out select 814215976Sjmallett - 1: Mode-defined test register contents are output 815215976Sjmallett - 0: internally generated signals are output */ 816215976Sjmallett uint64_t taddr_in : 4; /**< Mode address for test interface. Specifies the 817215976Sjmallett register address for writing to or reading from the 818215976Sjmallett PHY test interface register. */ 819215976Sjmallett uint64_t tdata_in : 8; /**< Internal testing Register input data and select. 820215976Sjmallett This is a test bus. Data presents on [3:0] and the 821215976Sjmallett corresponding select (enable) presents on bits[7:4]. */ 822215976Sjmallett#else 823215976Sjmallett uint64_t tdata_in : 8; 824215976Sjmallett uint64_t taddr_in : 4; 825215976Sjmallett uint64_t tdata_sel : 1; 826215976Sjmallett uint64_t tclk : 1; 827215976Sjmallett uint64_t loop_en : 1; 828215976Sjmallett uint64_t compdistune : 3; 829215976Sjmallett uint64_t sqrxtune : 3; 830215976Sjmallett uint64_t txfslstune : 4; 831215976Sjmallett uint64_t txpreemphasistune : 1; 832215976Sjmallett uint64_t txrisetune : 1; 833215976Sjmallett uint64_t txvreftune : 4; 834215976Sjmallett uint64_t txhsvxtune : 2; 835215976Sjmallett uint64_t portreset : 1; 836215976Sjmallett uint64_t vbusvldext : 1; 837215976Sjmallett uint64_t dppulldown : 1; 838215976Sjmallett uint64_t dmpulldown : 1; 839215976Sjmallett uint64_t txbiststuffen : 1; 840215976Sjmallett uint64_t txbiststuffenh : 1; 841215976Sjmallett uint64_t tdata_out : 4; 842215976Sjmallett uint64_t reserved_43_63 : 21; 843215976Sjmallett#endif 844215976Sjmallett } s; 845215976Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx; 846215976Sjmallett struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1; 847215976Sjmallett}; 848215976Sjmalletttypedef union cvmx_uctlx_uphy_portx_ctl_status cvmx_uctlx_uphy_portx_ctl_status_t; 849215976Sjmallett 850215976Sjmallett#endif 851