1210284Sjmallett/***********************license start*************** 2215990Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18215990Sjmallett * * Neither the name of Cavium Networks nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215990Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Support library for the hardware work queue timers. 50210284Sjmallett * 51215990Sjmallett * <hr>$Revision: 49448 $<hr> 52210284Sjmallett */ 53210284Sjmallett#include "executive-config.h" 54210284Sjmallett#include "cvmx-config.h" 55210284Sjmallett#include "cvmx.h" 56210284Sjmallett#include "cvmx-sysinfo.h" 57210284Sjmallett#include "cvmx-tim.h" 58210284Sjmallett#include "cvmx-bootmem.h" 59210284Sjmallett 60215990Sjmallett/* CSR typedefs have been moved to cvmx-tim-defs.h */ 61210284Sjmallett 62210284Sjmallett/** 63210284Sjmallett * Global structure holding the state of all timers. 64210284Sjmallett */ 65210284SjmallettCVMX_SHARED cvmx_tim_t cvmx_tim; 66210284Sjmallett 67210284Sjmallett 68210284Sjmallett#ifdef CVMX_ENABLE_TIMER_FUNCTIONS 69210284Sjmallett/** 70210284Sjmallett * Setup a timer for use. Must be called before the timer 71210284Sjmallett * can be used. 72210284Sjmallett * 73210284Sjmallett * @param tick Time between each bucket in microseconds. This must not be 74210284Sjmallett * smaller than 1024/(clock frequency in MHz). 75210284Sjmallett * @param max_ticks The maximum number of ticks the timer must be able 76210284Sjmallett * to schedule in the future. There are guaranteed to be enough 77210284Sjmallett * timer buckets such that: 78210284Sjmallett * number of buckets >= max_ticks. 79210284Sjmallett * @return Zero on success. Negative on error. Failures are possible 80210284Sjmallett * if the number of buckets needed is too large or memory 81210284Sjmallett * allocation fails for creating the buckets. 82210284Sjmallett */ 83210284Sjmallettint cvmx_tim_setup(uint64_t tick, uint64_t max_ticks) 84210284Sjmallett{ 85210284Sjmallett cvmx_tim_mem_ring0_t config_ring0; 86210284Sjmallett cvmx_tim_mem_ring1_t config_ring1; 87210284Sjmallett uint64_t timer_id; 88210284Sjmallett int error = -1; 89215990Sjmallett uint64_t tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM); 90210284Sjmallett uint64_t hw_tick_ns; 91210284Sjmallett uint64_t hw_tick_ns_allowed; 92210284Sjmallett uint64_t tick_ns = 1000 * tick; 93210284Sjmallett int i; 94210284Sjmallett uint32_t temp; 95210284Sjmallett 96210284Sjmallett /* for the simulator */ 97215990Sjmallett if (tim_clock_hz == 0) 98215990Sjmallett tim_clock_hz = 333000000; 99210284Sjmallett 100215990Sjmallett hw_tick_ns = 1024 * 1000000000ull / tim_clock_hz; 101215990Sjmallett /* 102215990Sjmallett * Double the minimal allowed tick to 2 * HW tick. tick between 103215990Sjmallett * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval 104210284Sjmallett * to zero, or 1024 cycles. This is not enough time for the timer unit 105215990Sjmallett * to fetch the bucket data, Resulting in timer ring error interrupt 106215990Sjmallett * be always generated. Avoid such setting in software. 107210284Sjmallett */ 108215990Sjmallett hw_tick_ns_allowed = hw_tick_ns * 2; 109210284Sjmallett 110210284Sjmallett /* Make sure the timers are stopped */ 111210284Sjmallett cvmx_tim_stop(); 112210284Sjmallett 113210284Sjmallett /* Reinitialize out timer state */ 114210284Sjmallett memset(&cvmx_tim, 0, sizeof(cvmx_tim)); 115210284Sjmallett 116215990Sjmallett 117210284Sjmallett if ((tick_ns < (hw_tick_ns_allowed)) || (tick_ns > 4194304 * hw_tick_ns)) 118210284Sjmallett { 119215990Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than" 120215990Sjmallett " the minimal ticks allowed by hardware %lu(ns)\n", 121210284Sjmallett tick_ns, hw_tick_ns_allowed); 122210284Sjmallett return error; 123210284Sjmallett } 124210284Sjmallett 125210284Sjmallett for (i=2; i<20; i++) 126210284Sjmallett { 127210284Sjmallett if (tick_ns < (hw_tick_ns << i)) 128210284Sjmallett break; 129210284Sjmallett } 130210284Sjmallett 131210284Sjmallett cvmx_tim.max_ticks = (uint32_t)max_ticks; 132210284Sjmallett cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10); 133215990Sjmallett cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000; 134210284Sjmallett 135210284Sjmallett temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift; 136210284Sjmallett 137210284Sjmallett /* round up to nearest power of 2 */ 138210284Sjmallett temp -= 1; 139210284Sjmallett temp = temp | (temp >> 1); 140210284Sjmallett temp = temp | (temp >> 2); 141210284Sjmallett temp = temp | (temp >> 4); 142210284Sjmallett temp = temp | (temp >> 8); 143210284Sjmallett temp = temp | (temp >> 16); 144210284Sjmallett cvmx_tim.num_buckets = temp + 1; 145210284Sjmallett 146210284Sjmallett /* ensure input params fall into permitted ranges */ 147210284Sjmallett if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576) 148210284Sjmallett { 149215990Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n"); 150210284Sjmallett return error; 151210284Sjmallett } 152210284Sjmallett 153210284Sjmallett /* Allocate the timer buckets from hardware addressable memory */ 154210284Sjmallett cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets 155210284Sjmallett * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE); 156210284Sjmallett if (cvmx_tim.bucket == NULL) 157210284Sjmallett { 158215990Sjmallett cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n"); 159210284Sjmallett return error; 160210284Sjmallett } 161210284Sjmallett memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t)); 162210284Sjmallett 163210284Sjmallett cvmx_tim.start_time = 0; 164210284Sjmallett 165210284Sjmallett /* Loop through all timers */ 166210284Sjmallett for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++) 167210284Sjmallett { 168210284Sjmallett cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets; 169210284Sjmallett /* Tell the hardware where about the bucket array */ 170210284Sjmallett config_ring0.u64 = 0; 171210284Sjmallett config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5; 172210284Sjmallett config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1; 173210284Sjmallett config_ring0.s.ring = timer_id; 174210284Sjmallett cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64); 175210284Sjmallett 176210284Sjmallett /* Tell the hardware the size of each chunk block in pointers */ 177210284Sjmallett config_ring1.u64 = 0; 178210284Sjmallett config_ring1.s.enable = 1; 179210284Sjmallett config_ring1.s.pool = CVMX_FPA_TIMER_POOL; 180210284Sjmallett config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8; 181210284Sjmallett config_ring1.s.interval = (1 << (cvmx_tim.bucket_shift - 10)) - 1; 182210284Sjmallett config_ring1.s.ring = timer_id; 183210284Sjmallett cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64); 184210284Sjmallett } 185210284Sjmallett 186210284Sjmallett return 0; 187210284Sjmallett} 188210284Sjmallett#endif 189210284Sjmallett 190210284Sjmallett/** 191210284Sjmallett * Start the hardware timer processing 192210284Sjmallett */ 193210284Sjmallettvoid cvmx_tim_start(void) 194210284Sjmallett{ 195210284Sjmallett cvmx_tim_control_t control; 196210284Sjmallett 197210284Sjmallett control.u64 = 0; 198210284Sjmallett control.s.enable_dwb = 1; 199210284Sjmallett control.s.enable_timers = 1; 200210284Sjmallett 201210284Sjmallett /* Remember when we started the timers */ 202215990Sjmallett cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM); 203210284Sjmallett cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); 204210284Sjmallett} 205210284Sjmallett 206210284Sjmallett 207210284Sjmallett/** 208210284Sjmallett * Stop the hardware timer processing. Timers stay configured. 209210284Sjmallett */ 210210284Sjmallettvoid cvmx_tim_stop(void) 211210284Sjmallett{ 212210284Sjmallett cvmx_tim_control_t control; 213210284Sjmallett control.u64 = 0; 214210284Sjmallett control.s.enable_dwb = 0; 215210284Sjmallett control.s.enable_timers = 0; 216210284Sjmallett cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); 217210284Sjmallett} 218210284Sjmallett 219210284Sjmallett 220210284Sjmallett/** 221210284Sjmallett * Stop the timer. After this the timer must be setup again 222210284Sjmallett * before use. 223210284Sjmallett */ 224210284Sjmallett#ifdef CVMX_ENABLE_TIMER_FUNCTIONS 225210284Sjmallettvoid cvmx_tim_shutdown(void) 226210284Sjmallett{ 227210284Sjmallett uint32_t bucket; 228210284Sjmallett uint64_t timer_id; 229210284Sjmallett uint64_t entries_per_chunk; 230210284Sjmallett 231210284Sjmallett /* Make sure the timers are stopped */ 232210284Sjmallett cvmx_tim_stop(); 233210284Sjmallett 234210284Sjmallett entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1; 235210284Sjmallett 236210284Sjmallett /* Now walk all buckets freeing the chunks */ 237210284Sjmallett for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++) 238210284Sjmallett { 239210284Sjmallett for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++) 240210284Sjmallett { 241210284Sjmallett uint64_t chunk_addr; 242210284Sjmallett uint64_t next_chunk_addr; 243210284Sjmallett cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket; 244210284Sjmallett CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */ 245210284Sjmallett 246210284Sjmallett /* Each bucket contains a list of chunks */ 247210284Sjmallett chunk_addr = bucket_ptr->first_chunk_addr; 248210284Sjmallett while (bucket_ptr->num_entries) 249210284Sjmallett { 250210284Sjmallett#ifdef DEBUG 251210284Sjmallett cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr)); 252210284Sjmallett#endif 253210284Sjmallett /* Read next chunk pointer from end of the current chunk */ 254210284Sjmallett next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8)); 255210284Sjmallett 256210284Sjmallett cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0); 257210284Sjmallett chunk_addr = next_chunk_addr; 258210284Sjmallett if (bucket_ptr->num_entries > entries_per_chunk) 259210284Sjmallett bucket_ptr->num_entries -= entries_per_chunk; 260210284Sjmallett else 261210284Sjmallett bucket_ptr->num_entries = 0; 262210284Sjmallett } 263210284Sjmallett } 264210284Sjmallett } 265210284Sjmallett} 266210284Sjmallett 267210284Sjmallett#endif 268