1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-rnm-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon rnm. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_RNM_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_RNM_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) 56215976Sjmallett#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) 57215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 58215976Sjmallett#define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC() 59215976Sjmallettstatic inline uint64_t CVMX_RNM_EER_DBG_FUNC(void) 60215976Sjmallett{ 61215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 62215976Sjmallett cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n"); 63215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180040000018ull); 64215976Sjmallett} 65215976Sjmallett#else 66215976Sjmallett#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) 67215976Sjmallett#endif 68215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69215976Sjmallett#define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC() 70215976Sjmallettstatic inline uint64_t CVMX_RNM_EER_KEY_FUNC(void) 71215976Sjmallett{ 72215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 73215976Sjmallett cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n"); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180040000010ull); 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull)) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallett#define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC() 81215976Sjmallettstatic inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void) 82215976Sjmallett{ 83215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 84215976Sjmallett cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n"); 85215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180040000020ull); 86215976Sjmallett} 87215976Sjmallett#else 88215976Sjmallett#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull)) 89215976Sjmallett#endif 90215976Sjmallett 91215976Sjmallett/** 92215976Sjmallett * cvmx_rnm_bist_status 93215976Sjmallett * 94215976Sjmallett * RNM_BIST_STATUS = RNM's BIST Status Register 95215976Sjmallett * 96215976Sjmallett * The RNM's Memory Bist Status register. 97215976Sjmallett */ 98215976Sjmallettunion cvmx_rnm_bist_status 99215976Sjmallett{ 100215976Sjmallett uint64_t u64; 101215976Sjmallett struct cvmx_rnm_bist_status_s 102215976Sjmallett { 103215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 104215976Sjmallett uint64_t reserved_2_63 : 62; 105215976Sjmallett uint64_t rrc : 1; /**< Status of RRC block bist. */ 106215976Sjmallett uint64_t mem : 1; /**< Status of MEM block bist. */ 107215976Sjmallett#else 108215976Sjmallett uint64_t mem : 1; 109215976Sjmallett uint64_t rrc : 1; 110215976Sjmallett uint64_t reserved_2_63 : 62; 111215976Sjmallett#endif 112215976Sjmallett } s; 113215976Sjmallett struct cvmx_rnm_bist_status_s cn30xx; 114215976Sjmallett struct cvmx_rnm_bist_status_s cn31xx; 115215976Sjmallett struct cvmx_rnm_bist_status_s cn38xx; 116215976Sjmallett struct cvmx_rnm_bist_status_s cn38xxp2; 117215976Sjmallett struct cvmx_rnm_bist_status_s cn50xx; 118215976Sjmallett struct cvmx_rnm_bist_status_s cn52xx; 119215976Sjmallett struct cvmx_rnm_bist_status_s cn52xxp1; 120215976Sjmallett struct cvmx_rnm_bist_status_s cn56xx; 121215976Sjmallett struct cvmx_rnm_bist_status_s cn56xxp1; 122215976Sjmallett struct cvmx_rnm_bist_status_s cn58xx; 123215976Sjmallett struct cvmx_rnm_bist_status_s cn58xxp1; 124215976Sjmallett struct cvmx_rnm_bist_status_s cn63xx; 125215976Sjmallett struct cvmx_rnm_bist_status_s cn63xxp1; 126215976Sjmallett}; 127215976Sjmalletttypedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t; 128215976Sjmallett 129215976Sjmallett/** 130215976Sjmallett * cvmx_rnm_ctl_status 131215976Sjmallett * 132215976Sjmallett * RNM_CTL_STATUS = RNM's Control/Status Register 133215976Sjmallett * 134215976Sjmallett * The RNM's interrupt enable register. 135215976Sjmallett */ 136215976Sjmallettunion cvmx_rnm_ctl_status 137215976Sjmallett{ 138215976Sjmallett uint64_t u64; 139215976Sjmallett struct cvmx_rnm_ctl_status_s 140215976Sjmallett { 141215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 142215976Sjmallett uint64_t reserved_11_63 : 53; 143215976Sjmallett uint64_t eer_lck : 1; /**< Encryption enable register locked */ 144215976Sjmallett uint64_t eer_val : 1; /**< Dormant encryption key match */ 145215976Sjmallett uint64_t ent_sel : 4; /**< ? */ 146215976Sjmallett uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 147215976Sjmallett uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 148215976Sjmallett uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 149215976Sjmallett logic. */ 150215976Sjmallett uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 151215976Sjmallett uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 152215976Sjmallett#else 153215976Sjmallett uint64_t ent_en : 1; 154215976Sjmallett uint64_t rng_en : 1; 155215976Sjmallett uint64_t rnm_rst : 1; 156215976Sjmallett uint64_t rng_rst : 1; 157215976Sjmallett uint64_t exp_ent : 1; 158215976Sjmallett uint64_t ent_sel : 4; 159215976Sjmallett uint64_t eer_val : 1; 160215976Sjmallett uint64_t eer_lck : 1; 161215976Sjmallett uint64_t reserved_11_63 : 53; 162215976Sjmallett#endif 163215976Sjmallett } s; 164215976Sjmallett struct cvmx_rnm_ctl_status_cn30xx 165215976Sjmallett { 166215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 167215976Sjmallett uint64_t reserved_4_63 : 60; 168215976Sjmallett uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 169215976Sjmallett uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 170215976Sjmallett logic. */ 171215976Sjmallett uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 172215976Sjmallett uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 173215976Sjmallett#else 174215976Sjmallett uint64_t ent_en : 1; 175215976Sjmallett uint64_t rng_en : 1; 176215976Sjmallett uint64_t rnm_rst : 1; 177215976Sjmallett uint64_t rng_rst : 1; 178215976Sjmallett uint64_t reserved_4_63 : 60; 179215976Sjmallett#endif 180215976Sjmallett } cn30xx; 181215976Sjmallett struct cvmx_rnm_ctl_status_cn30xx cn31xx; 182215976Sjmallett struct cvmx_rnm_ctl_status_cn30xx cn38xx; 183215976Sjmallett struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; 184215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx 185215976Sjmallett { 186215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 187215976Sjmallett uint64_t reserved_9_63 : 55; 188215976Sjmallett uint64_t ent_sel : 4; /**< ? */ 189215976Sjmallett uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 190215976Sjmallett uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 191215976Sjmallett uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 192215976Sjmallett logic. */ 193215976Sjmallett uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 194215976Sjmallett uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 195215976Sjmallett#else 196215976Sjmallett uint64_t ent_en : 1; 197215976Sjmallett uint64_t rng_en : 1; 198215976Sjmallett uint64_t rnm_rst : 1; 199215976Sjmallett uint64_t rng_rst : 1; 200215976Sjmallett uint64_t exp_ent : 1; 201215976Sjmallett uint64_t ent_sel : 4; 202215976Sjmallett uint64_t reserved_9_63 : 55; 203215976Sjmallett#endif 204215976Sjmallett } cn50xx; 205215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx cn52xx; 206215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; 207215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx cn56xx; 208215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; 209215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx cn58xx; 210215976Sjmallett struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; 211215976Sjmallett struct cvmx_rnm_ctl_status_s cn63xx; 212215976Sjmallett struct cvmx_rnm_ctl_status_s cn63xxp1; 213215976Sjmallett}; 214215976Sjmalletttypedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t; 215215976Sjmallett 216215976Sjmallett/** 217215976Sjmallett * cvmx_rnm_eer_dbg 218215976Sjmallett * 219215976Sjmallett * RNM_EER_DBG = RNM's Encryption enable debug register 220215976Sjmallett * 221215976Sjmallett * The RNM's Encryption enable debug register 222215976Sjmallett */ 223215976Sjmallettunion cvmx_rnm_eer_dbg 224215976Sjmallett{ 225215976Sjmallett uint64_t u64; 226215976Sjmallett struct cvmx_rnm_eer_dbg_s 227215976Sjmallett { 228215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 229215976Sjmallett uint64_t dat : 64; /**< Dormant encryption debug info. */ 230215976Sjmallett#else 231215976Sjmallett uint64_t dat : 64; 232215976Sjmallett#endif 233215976Sjmallett } s; 234215976Sjmallett struct cvmx_rnm_eer_dbg_s cn63xx; 235215976Sjmallett struct cvmx_rnm_eer_dbg_s cn63xxp1; 236215976Sjmallett}; 237215976Sjmalletttypedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t; 238215976Sjmallett 239215976Sjmallett/** 240215976Sjmallett * cvmx_rnm_eer_key 241215976Sjmallett * 242215976Sjmallett * RNM_EER_KEY = RNM's Encryption enable register 243215976Sjmallett * 244215976Sjmallett * The RNM's Encryption enable register 245215976Sjmallett */ 246215976Sjmallettunion cvmx_rnm_eer_key 247215976Sjmallett{ 248215976Sjmallett uint64_t u64; 249215976Sjmallett struct cvmx_rnm_eer_key_s 250215976Sjmallett { 251215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 252215976Sjmallett uint64_t key : 64; /**< Dormant encryption key. If dormant crypto is fuse 253215976Sjmallett enabled, crypto can be enable by writing this 254215976Sjmallett register with the correct key. */ 255215976Sjmallett#else 256215976Sjmallett uint64_t key : 64; 257215976Sjmallett#endif 258215976Sjmallett } s; 259215976Sjmallett struct cvmx_rnm_eer_key_s cn63xx; 260215976Sjmallett struct cvmx_rnm_eer_key_s cn63xxp1; 261215976Sjmallett}; 262215976Sjmalletttypedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t; 263215976Sjmallett 264215976Sjmallett/** 265215976Sjmallett * cvmx_rnm_serial_num 266215976Sjmallett * 267215976Sjmallett * RNM_SERIAL_NUM = RNM's fuse serial number register 268215976Sjmallett * 269215976Sjmallett * The RNM's fuse serial number register 270215976Sjmallett * 271215976Sjmallett * Notes: 272215976Sjmallett * Added RNM_SERIAL_NUM in pass 2.0 273215976Sjmallett * 274215976Sjmallett */ 275215976Sjmallettunion cvmx_rnm_serial_num 276215976Sjmallett{ 277215976Sjmallett uint64_t u64; 278215976Sjmallett struct cvmx_rnm_serial_num_s 279215976Sjmallett { 280215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 281215976Sjmallett uint64_t dat : 64; /**< Dormant encryption serial number */ 282215976Sjmallett#else 283215976Sjmallett uint64_t dat : 64; 284215976Sjmallett#endif 285215976Sjmallett } s; 286215976Sjmallett struct cvmx_rnm_serial_num_s cn63xx; 287215976Sjmallett}; 288215976Sjmalletttypedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t; 289215976Sjmallett 290215976Sjmallett#endif 291