1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-rad-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon rad. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_RAD_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_RAD_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60215976Sjmallett cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070001000ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71215976Sjmallett cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070001008ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82215976Sjmallett cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070001010ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93215976Sjmallett cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000080ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 104215976Sjmallett cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000008ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180070000008ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_CTL_FUNC(void) 113215976Sjmallett{ 114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115215976Sjmallett cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000000ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_RAD_REG_CTL (CVMX_ADD_IO_SEG(0x0001180070000000ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void) 124215976Sjmallett{ 125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000100ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_RAD_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070000100ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void) 135215976Sjmallett{ 136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 137215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000108ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_RAD_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070000108ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallett#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC() 145215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void) 146215976Sjmallett{ 147215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 148215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n"); 149215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000150ull); 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_RAD_REG_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180070000150ull)) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallett#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC() 156215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void) 157215976Sjmallett{ 158215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 159215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n"); 160215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000158ull); 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_RAD_REG_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180070000158ull)) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallett#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC() 167215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void) 168215976Sjmallett{ 169215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 170215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n"); 171215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000160ull); 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_RAD_REG_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180070000160ull)) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallett#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC() 178215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void) 179215976Sjmallett{ 180215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 181215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n"); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000110ull); 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_RAD_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070000110ull)) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallett#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC() 189215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void) 190215976Sjmallett{ 191215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 192215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n"); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000118ull); 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_RAD_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180070000118ull)) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallett#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC() 200215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void) 201215976Sjmallett{ 202215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 203215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n"); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000120ull); 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_RAD_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180070000120ull)) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallett#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC() 211215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void) 212215976Sjmallett{ 213215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 214215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n"); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000128ull); 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_RAD_REG_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180070000128ull)) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallett#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC() 222215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void) 223215976Sjmallett{ 224215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 225215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n"); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000130ull); 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_RAD_REG_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180070000130ull)) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallett#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC() 233215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void) 234215976Sjmallett{ 235215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 236215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n"); 237215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000138ull); 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_RAD_REG_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180070000138ull)) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallett#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC() 244215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void) 245215976Sjmallett{ 246215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 247215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n"); 248215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000140ull); 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_RAD_REG_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180070000140ull)) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallett#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC() 255215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void) 256215976Sjmallett{ 257215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 258215976Sjmallett cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n"); 259215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000148ull); 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_RAD_REG_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180070000148ull)) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallett#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC() 266215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void) 267215976Sjmallett{ 268215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 269215976Sjmallett cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n"); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000088ull); 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_RAD_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180070000088ull)) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallett#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC() 277215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void) 278215976Sjmallett{ 279215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 280215976Sjmallett cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n"); 281215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000090ull); 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_RAD_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180070000090ull)) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallett#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC() 288215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void) 289215976Sjmallett{ 290215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 291215976Sjmallett cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n"); 292215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000010ull); 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_RAD_REG_POLYNOMIAL (CVMX_ADD_IO_SEG(0x0001180070000010ull)) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallett#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC() 299215976Sjmallettstatic inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void) 300215976Sjmallett{ 301215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 302215976Sjmallett cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n"); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180070000018ull); 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_RAD_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180070000018ull)) 307215976Sjmallett#endif 308215976Sjmallett 309215976Sjmallett/** 310215976Sjmallett * cvmx_rad_mem_debug0 311215976Sjmallett * 312215976Sjmallett * Notes: 313215976Sjmallett * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 314215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 315215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 316215976Sjmallett */ 317215976Sjmallettunion cvmx_rad_mem_debug0 318215976Sjmallett{ 319215976Sjmallett uint64_t u64; 320215976Sjmallett struct cvmx_rad_mem_debug0_s 321215976Sjmallett { 322215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 323215976Sjmallett uint64_t iword : 64; /**< IWord */ 324215976Sjmallett#else 325215976Sjmallett uint64_t iword : 64; 326215976Sjmallett#endif 327215976Sjmallett } s; 328215976Sjmallett struct cvmx_rad_mem_debug0_s cn52xx; 329215976Sjmallett struct cvmx_rad_mem_debug0_s cn52xxp1; 330215976Sjmallett struct cvmx_rad_mem_debug0_s cn56xx; 331215976Sjmallett struct cvmx_rad_mem_debug0_s cn56xxp1; 332215976Sjmallett struct cvmx_rad_mem_debug0_s cn63xx; 333215976Sjmallett struct cvmx_rad_mem_debug0_s cn63xxp1; 334215976Sjmallett}; 335215976Sjmalletttypedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t; 336215976Sjmallett 337215976Sjmallett/** 338215976Sjmallett * cvmx_rad_mem_debug1 339215976Sjmallett * 340215976Sjmallett * Notes: 341215976Sjmallett * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 342215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 343215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 344215976Sjmallett */ 345215976Sjmallettunion cvmx_rad_mem_debug1 346215976Sjmallett{ 347215976Sjmallett uint64_t u64; 348215976Sjmallett struct cvmx_rad_mem_debug1_s 349215976Sjmallett { 350215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 351215976Sjmallett uint64_t p_dat : 64; /**< P data */ 352215976Sjmallett#else 353215976Sjmallett uint64_t p_dat : 64; 354215976Sjmallett#endif 355215976Sjmallett } s; 356215976Sjmallett struct cvmx_rad_mem_debug1_s cn52xx; 357215976Sjmallett struct cvmx_rad_mem_debug1_s cn52xxp1; 358215976Sjmallett struct cvmx_rad_mem_debug1_s cn56xx; 359215976Sjmallett struct cvmx_rad_mem_debug1_s cn56xxp1; 360215976Sjmallett struct cvmx_rad_mem_debug1_s cn63xx; 361215976Sjmallett struct cvmx_rad_mem_debug1_s cn63xxp1; 362215976Sjmallett}; 363215976Sjmalletttypedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t; 364215976Sjmallett 365215976Sjmallett/** 366215976Sjmallett * cvmx_rad_mem_debug2 367215976Sjmallett * 368215976Sjmallett * Notes: 369215976Sjmallett * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 370215976Sjmallett * CSR read operations to this address can be performed. A read of any entry that has not been 371215976Sjmallett * previously written is illegal and will result in unpredictable CSR read data. 372215976Sjmallett */ 373215976Sjmallettunion cvmx_rad_mem_debug2 374215976Sjmallett{ 375215976Sjmallett uint64_t u64; 376215976Sjmallett struct cvmx_rad_mem_debug2_s 377215976Sjmallett { 378215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 379215976Sjmallett uint64_t q_dat : 64; /**< Q data */ 380215976Sjmallett#else 381215976Sjmallett uint64_t q_dat : 64; 382215976Sjmallett#endif 383215976Sjmallett } s; 384215976Sjmallett struct cvmx_rad_mem_debug2_s cn52xx; 385215976Sjmallett struct cvmx_rad_mem_debug2_s cn52xxp1; 386215976Sjmallett struct cvmx_rad_mem_debug2_s cn56xx; 387215976Sjmallett struct cvmx_rad_mem_debug2_s cn56xxp1; 388215976Sjmallett struct cvmx_rad_mem_debug2_s cn63xx; 389215976Sjmallett struct cvmx_rad_mem_debug2_s cn63xxp1; 390215976Sjmallett}; 391215976Sjmalletttypedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t; 392215976Sjmallett 393215976Sjmallett/** 394215976Sjmallett * cvmx_rad_reg_bist_result 395215976Sjmallett * 396215976Sjmallett * Notes: 397215976Sjmallett * Access to the internal BiST results 398215976Sjmallett * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 399215976Sjmallett */ 400215976Sjmallettunion cvmx_rad_reg_bist_result 401215976Sjmallett{ 402215976Sjmallett uint64_t u64; 403215976Sjmallett struct cvmx_rad_reg_bist_result_s 404215976Sjmallett { 405215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 406215976Sjmallett uint64_t reserved_6_63 : 58; 407215976Sjmallett uint64_t sta : 1; /**< BiST result of the STA memories */ 408215976Sjmallett uint64_t ncb_oub : 1; /**< BiST result of the NCB_OUB memories */ 409215976Sjmallett uint64_t ncb_inb : 2; /**< BiST result of the NCB_INB memories */ 410215976Sjmallett uint64_t dat : 2; /**< BiST result of the DAT memories */ 411215976Sjmallett#else 412215976Sjmallett uint64_t dat : 2; 413215976Sjmallett uint64_t ncb_inb : 2; 414215976Sjmallett uint64_t ncb_oub : 1; 415215976Sjmallett uint64_t sta : 1; 416215976Sjmallett uint64_t reserved_6_63 : 58; 417215976Sjmallett#endif 418215976Sjmallett } s; 419215976Sjmallett struct cvmx_rad_reg_bist_result_s cn52xx; 420215976Sjmallett struct cvmx_rad_reg_bist_result_s cn52xxp1; 421215976Sjmallett struct cvmx_rad_reg_bist_result_s cn56xx; 422215976Sjmallett struct cvmx_rad_reg_bist_result_s cn56xxp1; 423215976Sjmallett struct cvmx_rad_reg_bist_result_s cn63xx; 424215976Sjmallett struct cvmx_rad_reg_bist_result_s cn63xxp1; 425215976Sjmallett}; 426215976Sjmalletttypedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t; 427215976Sjmallett 428215976Sjmallett/** 429215976Sjmallett * cvmx_rad_reg_cmd_buf 430215976Sjmallett * 431215976Sjmallett * Notes: 432215976Sjmallett * Sets the command buffer parameters 433215976Sjmallett * The size of the command buffer segments is measured in uint64s. The pool specifies 1 of 8 free 434215976Sjmallett * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next 435215976Sjmallett * pointer each time that the command buffer segment is exhausted. 436215976Sjmallett */ 437215976Sjmallettunion cvmx_rad_reg_cmd_buf 438215976Sjmallett{ 439215976Sjmallett uint64_t u64; 440215976Sjmallett struct cvmx_rad_reg_cmd_buf_s 441215976Sjmallett { 442215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 443215976Sjmallett uint64_t reserved_58_63 : 6; 444215976Sjmallett uint64_t dwb : 9; /**< Number of DontWriteBacks */ 445215976Sjmallett uint64_t pool : 3; /**< Free list used to free command buffer segments */ 446215976Sjmallett uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 447215976Sjmallett uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 448215976Sjmallett#else 449215976Sjmallett uint64_t ptr : 33; 450215976Sjmallett uint64_t size : 13; 451215976Sjmallett uint64_t pool : 3; 452215976Sjmallett uint64_t dwb : 9; 453215976Sjmallett uint64_t reserved_58_63 : 6; 454215976Sjmallett#endif 455215976Sjmallett } s; 456215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn52xx; 457215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn52xxp1; 458215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn56xx; 459215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn56xxp1; 460215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn63xx; 461215976Sjmallett struct cvmx_rad_reg_cmd_buf_s cn63xxp1; 462215976Sjmallett}; 463215976Sjmalletttypedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t; 464215976Sjmallett 465215976Sjmallett/** 466215976Sjmallett * cvmx_rad_reg_ctl 467215976Sjmallett * 468215976Sjmallett * Notes: 469215976Sjmallett * MAX_READ is a throttle to control NCB usage. Values >8 are illegal. 470215976Sjmallett * 471215976Sjmallett */ 472215976Sjmallettunion cvmx_rad_reg_ctl 473215976Sjmallett{ 474215976Sjmallett uint64_t u64; 475215976Sjmallett struct cvmx_rad_reg_ctl_s 476215976Sjmallett { 477215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 478215976Sjmallett uint64_t reserved_6_63 : 58; 479215976Sjmallett uint64_t max_read : 4; /**< Maximum number of outstanding data read commands */ 480215976Sjmallett uint64_t store_le : 1; /**< Force STORE0 byte write address to little endian */ 481215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse (lasts for 4 cycles) */ 482215976Sjmallett#else 483215976Sjmallett uint64_t reset : 1; 484215976Sjmallett uint64_t store_le : 1; 485215976Sjmallett uint64_t max_read : 4; 486215976Sjmallett uint64_t reserved_6_63 : 58; 487215976Sjmallett#endif 488215976Sjmallett } s; 489215976Sjmallett struct cvmx_rad_reg_ctl_s cn52xx; 490215976Sjmallett struct cvmx_rad_reg_ctl_s cn52xxp1; 491215976Sjmallett struct cvmx_rad_reg_ctl_s cn56xx; 492215976Sjmallett struct cvmx_rad_reg_ctl_s cn56xxp1; 493215976Sjmallett struct cvmx_rad_reg_ctl_s cn63xx; 494215976Sjmallett struct cvmx_rad_reg_ctl_s cn63xxp1; 495215976Sjmallett}; 496215976Sjmalletttypedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t; 497215976Sjmallett 498215976Sjmallett/** 499215976Sjmallett * cvmx_rad_reg_debug0 500215976Sjmallett */ 501215976Sjmallettunion cvmx_rad_reg_debug0 502215976Sjmallett{ 503215976Sjmallett uint64_t u64; 504215976Sjmallett struct cvmx_rad_reg_debug0_s 505215976Sjmallett { 506215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 507215976Sjmallett uint64_t reserved_57_63 : 7; 508215976Sjmallett uint64_t loop : 25; /**< Loop offset */ 509215976Sjmallett uint64_t reserved_22_31 : 10; 510215976Sjmallett uint64_t iridx : 6; /**< IWords read index */ 511215976Sjmallett uint64_t reserved_14_15 : 2; 512215976Sjmallett uint64_t iwidx : 6; /**< IWords write index */ 513215976Sjmallett uint64_t owordqv : 1; /**< Valid for OWORDQ */ 514215976Sjmallett uint64_t owordpv : 1; /**< Valid for OWORDP */ 515215976Sjmallett uint64_t commit : 1; /**< Waiting for write commit */ 516215976Sjmallett uint64_t state : 5; /**< Main state */ 517215976Sjmallett#else 518215976Sjmallett uint64_t state : 5; 519215976Sjmallett uint64_t commit : 1; 520215976Sjmallett uint64_t owordpv : 1; 521215976Sjmallett uint64_t owordqv : 1; 522215976Sjmallett uint64_t iwidx : 6; 523215976Sjmallett uint64_t reserved_14_15 : 2; 524215976Sjmallett uint64_t iridx : 6; 525215976Sjmallett uint64_t reserved_22_31 : 10; 526215976Sjmallett uint64_t loop : 25; 527215976Sjmallett uint64_t reserved_57_63 : 7; 528215976Sjmallett#endif 529215976Sjmallett } s; 530215976Sjmallett struct cvmx_rad_reg_debug0_s cn52xx; 531215976Sjmallett struct cvmx_rad_reg_debug0_s cn52xxp1; 532215976Sjmallett struct cvmx_rad_reg_debug0_s cn56xx; 533215976Sjmallett struct cvmx_rad_reg_debug0_s cn56xxp1; 534215976Sjmallett struct cvmx_rad_reg_debug0_s cn63xx; 535215976Sjmallett struct cvmx_rad_reg_debug0_s cn63xxp1; 536215976Sjmallett}; 537215976Sjmalletttypedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t; 538215976Sjmallett 539215976Sjmallett/** 540215976Sjmallett * cvmx_rad_reg_debug1 541215976Sjmallett */ 542215976Sjmallettunion cvmx_rad_reg_debug1 543215976Sjmallett{ 544215976Sjmallett uint64_t u64; 545215976Sjmallett struct cvmx_rad_reg_debug1_s 546215976Sjmallett { 547215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 548215976Sjmallett uint64_t cword : 64; /**< CWord */ 549215976Sjmallett#else 550215976Sjmallett uint64_t cword : 64; 551215976Sjmallett#endif 552215976Sjmallett } s; 553215976Sjmallett struct cvmx_rad_reg_debug1_s cn52xx; 554215976Sjmallett struct cvmx_rad_reg_debug1_s cn52xxp1; 555215976Sjmallett struct cvmx_rad_reg_debug1_s cn56xx; 556215976Sjmallett struct cvmx_rad_reg_debug1_s cn56xxp1; 557215976Sjmallett struct cvmx_rad_reg_debug1_s cn63xx; 558215976Sjmallett struct cvmx_rad_reg_debug1_s cn63xxp1; 559215976Sjmallett}; 560215976Sjmalletttypedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t; 561215976Sjmallett 562215976Sjmallett/** 563215976Sjmallett * cvmx_rad_reg_debug10 564215976Sjmallett */ 565215976Sjmallettunion cvmx_rad_reg_debug10 566215976Sjmallett{ 567215976Sjmallett uint64_t u64; 568215976Sjmallett struct cvmx_rad_reg_debug10_s 569215976Sjmallett { 570215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 571215976Sjmallett uint64_t flags : 8; /**< OCTL flags */ 572215976Sjmallett uint64_t size : 16; /**< OCTL size (bytes) */ 573215976Sjmallett uint64_t ptr : 40; /**< OCTL pointer */ 574215976Sjmallett#else 575215976Sjmallett uint64_t ptr : 40; 576215976Sjmallett uint64_t size : 16; 577215976Sjmallett uint64_t flags : 8; 578215976Sjmallett#endif 579215976Sjmallett } s; 580215976Sjmallett struct cvmx_rad_reg_debug10_s cn52xx; 581215976Sjmallett struct cvmx_rad_reg_debug10_s cn52xxp1; 582215976Sjmallett struct cvmx_rad_reg_debug10_s cn56xx; 583215976Sjmallett struct cvmx_rad_reg_debug10_s cn56xxp1; 584215976Sjmallett struct cvmx_rad_reg_debug10_s cn63xx; 585215976Sjmallett struct cvmx_rad_reg_debug10_s cn63xxp1; 586215976Sjmallett}; 587215976Sjmalletttypedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t; 588215976Sjmallett 589215976Sjmallett/** 590215976Sjmallett * cvmx_rad_reg_debug11 591215976Sjmallett */ 592215976Sjmallettunion cvmx_rad_reg_debug11 593215976Sjmallett{ 594215976Sjmallett uint64_t u64; 595215976Sjmallett struct cvmx_rad_reg_debug11_s 596215976Sjmallett { 597215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 598215976Sjmallett uint64_t reserved_13_63 : 51; 599215976Sjmallett uint64_t q : 1; /**< OCTL q flag */ 600215976Sjmallett uint64_t p : 1; /**< OCTL p flag */ 601215976Sjmallett uint64_t wc : 1; /**< OCTL write commit flag */ 602215976Sjmallett uint64_t eod : 1; /**< OCTL eod flag */ 603215976Sjmallett uint64_t sod : 1; /**< OCTL sod flag */ 604215976Sjmallett uint64_t index : 8; /**< OCTL index */ 605215976Sjmallett#else 606215976Sjmallett uint64_t index : 8; 607215976Sjmallett uint64_t sod : 1; 608215976Sjmallett uint64_t eod : 1; 609215976Sjmallett uint64_t wc : 1; 610215976Sjmallett uint64_t p : 1; 611215976Sjmallett uint64_t q : 1; 612215976Sjmallett uint64_t reserved_13_63 : 51; 613215976Sjmallett#endif 614215976Sjmallett } s; 615215976Sjmallett struct cvmx_rad_reg_debug11_s cn52xx; 616215976Sjmallett struct cvmx_rad_reg_debug11_s cn52xxp1; 617215976Sjmallett struct cvmx_rad_reg_debug11_s cn56xx; 618215976Sjmallett struct cvmx_rad_reg_debug11_s cn56xxp1; 619215976Sjmallett struct cvmx_rad_reg_debug11_s cn63xx; 620215976Sjmallett struct cvmx_rad_reg_debug11_s cn63xxp1; 621215976Sjmallett}; 622215976Sjmalletttypedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t; 623215976Sjmallett 624215976Sjmallett/** 625215976Sjmallett * cvmx_rad_reg_debug12 626215976Sjmallett */ 627215976Sjmallettunion cvmx_rad_reg_debug12 628215976Sjmallett{ 629215976Sjmallett uint64_t u64; 630215976Sjmallett struct cvmx_rad_reg_debug12_s 631215976Sjmallett { 632215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 633215976Sjmallett uint64_t reserved_15_63 : 49; 634215976Sjmallett uint64_t asserts : 15; /**< Various assertion checks */ 635215976Sjmallett#else 636215976Sjmallett uint64_t asserts : 15; 637215976Sjmallett uint64_t reserved_15_63 : 49; 638215976Sjmallett#endif 639215976Sjmallett } s; 640215976Sjmallett struct cvmx_rad_reg_debug12_s cn52xx; 641215976Sjmallett struct cvmx_rad_reg_debug12_s cn52xxp1; 642215976Sjmallett struct cvmx_rad_reg_debug12_s cn56xx; 643215976Sjmallett struct cvmx_rad_reg_debug12_s cn56xxp1; 644215976Sjmallett struct cvmx_rad_reg_debug12_s cn63xx; 645215976Sjmallett struct cvmx_rad_reg_debug12_s cn63xxp1; 646215976Sjmallett}; 647215976Sjmalletttypedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t; 648215976Sjmallett 649215976Sjmallett/** 650215976Sjmallett * cvmx_rad_reg_debug2 651215976Sjmallett */ 652215976Sjmallettunion cvmx_rad_reg_debug2 653215976Sjmallett{ 654215976Sjmallett uint64_t u64; 655215976Sjmallett struct cvmx_rad_reg_debug2_s 656215976Sjmallett { 657215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 658215976Sjmallett uint64_t owordp : 64; /**< OWordP */ 659215976Sjmallett#else 660215976Sjmallett uint64_t owordp : 64; 661215976Sjmallett#endif 662215976Sjmallett } s; 663215976Sjmallett struct cvmx_rad_reg_debug2_s cn52xx; 664215976Sjmallett struct cvmx_rad_reg_debug2_s cn52xxp1; 665215976Sjmallett struct cvmx_rad_reg_debug2_s cn56xx; 666215976Sjmallett struct cvmx_rad_reg_debug2_s cn56xxp1; 667215976Sjmallett struct cvmx_rad_reg_debug2_s cn63xx; 668215976Sjmallett struct cvmx_rad_reg_debug2_s cn63xxp1; 669215976Sjmallett}; 670215976Sjmalletttypedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t; 671215976Sjmallett 672215976Sjmallett/** 673215976Sjmallett * cvmx_rad_reg_debug3 674215976Sjmallett */ 675215976Sjmallettunion cvmx_rad_reg_debug3 676215976Sjmallett{ 677215976Sjmallett uint64_t u64; 678215976Sjmallett struct cvmx_rad_reg_debug3_s 679215976Sjmallett { 680215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 681215976Sjmallett uint64_t owordq : 64; /**< OWordQ */ 682215976Sjmallett#else 683215976Sjmallett uint64_t owordq : 64; 684215976Sjmallett#endif 685215976Sjmallett } s; 686215976Sjmallett struct cvmx_rad_reg_debug3_s cn52xx; 687215976Sjmallett struct cvmx_rad_reg_debug3_s cn52xxp1; 688215976Sjmallett struct cvmx_rad_reg_debug3_s cn56xx; 689215976Sjmallett struct cvmx_rad_reg_debug3_s cn56xxp1; 690215976Sjmallett struct cvmx_rad_reg_debug3_s cn63xx; 691215976Sjmallett struct cvmx_rad_reg_debug3_s cn63xxp1; 692215976Sjmallett}; 693215976Sjmalletttypedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t; 694215976Sjmallett 695215976Sjmallett/** 696215976Sjmallett * cvmx_rad_reg_debug4 697215976Sjmallett */ 698215976Sjmallettunion cvmx_rad_reg_debug4 699215976Sjmallett{ 700215976Sjmallett uint64_t u64; 701215976Sjmallett struct cvmx_rad_reg_debug4_s 702215976Sjmallett { 703215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 704215976Sjmallett uint64_t rword : 64; /**< RWord */ 705215976Sjmallett#else 706215976Sjmallett uint64_t rword : 64; 707215976Sjmallett#endif 708215976Sjmallett } s; 709215976Sjmallett struct cvmx_rad_reg_debug4_s cn52xx; 710215976Sjmallett struct cvmx_rad_reg_debug4_s cn52xxp1; 711215976Sjmallett struct cvmx_rad_reg_debug4_s cn56xx; 712215976Sjmallett struct cvmx_rad_reg_debug4_s cn56xxp1; 713215976Sjmallett struct cvmx_rad_reg_debug4_s cn63xx; 714215976Sjmallett struct cvmx_rad_reg_debug4_s cn63xxp1; 715215976Sjmallett}; 716215976Sjmalletttypedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t; 717215976Sjmallett 718215976Sjmallett/** 719215976Sjmallett * cvmx_rad_reg_debug5 720215976Sjmallett */ 721215976Sjmallettunion cvmx_rad_reg_debug5 722215976Sjmallett{ 723215976Sjmallett uint64_t u64; 724215976Sjmallett struct cvmx_rad_reg_debug5_s 725215976Sjmallett { 726215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 727215976Sjmallett uint64_t reserved_53_63 : 11; 728215976Sjmallett uint64_t niropc7 : 3; /**< NCBI ropc (stage7 grant) */ 729215976Sjmallett uint64_t nirque7 : 2; /**< NCBI rque (stage7 grant) */ 730215976Sjmallett uint64_t nirval7 : 5; /**< NCBI rval (stage7 grant) */ 731215976Sjmallett uint64_t niropc6 : 3; /**< NCBI ropc (stage6 arb) */ 732215976Sjmallett uint64_t nirque6 : 2; /**< NCBI rque (stage6 arb) */ 733215976Sjmallett uint64_t nirarb6 : 1; /**< NCBI rarb (stage6 arb) */ 734215976Sjmallett uint64_t nirval6 : 5; /**< NCBI rval (stage6 arb) */ 735215976Sjmallett uint64_t niridx1 : 4; /**< NCBI ridx1 */ 736215976Sjmallett uint64_t niwidx1 : 4; /**< NCBI widx1 */ 737215976Sjmallett uint64_t niridx0 : 4; /**< NCBI ridx0 */ 738215976Sjmallett uint64_t niwidx0 : 4; /**< NCBI widx0 */ 739215976Sjmallett uint64_t wccreds : 2; /**< WC credits */ 740215976Sjmallett uint64_t fpacreds : 2; /**< POW credits */ 741215976Sjmallett uint64_t reserved_10_11 : 2; 742215976Sjmallett uint64_t powcreds : 2; /**< POW credits */ 743215976Sjmallett uint64_t n1creds : 4; /**< NCBI1 credits */ 744215976Sjmallett uint64_t n0creds : 4; /**< NCBI0 credits */ 745215976Sjmallett#else 746215976Sjmallett uint64_t n0creds : 4; 747215976Sjmallett uint64_t n1creds : 4; 748215976Sjmallett uint64_t powcreds : 2; 749215976Sjmallett uint64_t reserved_10_11 : 2; 750215976Sjmallett uint64_t fpacreds : 2; 751215976Sjmallett uint64_t wccreds : 2; 752215976Sjmallett uint64_t niwidx0 : 4; 753215976Sjmallett uint64_t niridx0 : 4; 754215976Sjmallett uint64_t niwidx1 : 4; 755215976Sjmallett uint64_t niridx1 : 4; 756215976Sjmallett uint64_t nirval6 : 5; 757215976Sjmallett uint64_t nirarb6 : 1; 758215976Sjmallett uint64_t nirque6 : 2; 759215976Sjmallett uint64_t niropc6 : 3; 760215976Sjmallett uint64_t nirval7 : 5; 761215976Sjmallett uint64_t nirque7 : 2; 762215976Sjmallett uint64_t niropc7 : 3; 763215976Sjmallett uint64_t reserved_53_63 : 11; 764215976Sjmallett#endif 765215976Sjmallett } s; 766215976Sjmallett struct cvmx_rad_reg_debug5_s cn52xx; 767215976Sjmallett struct cvmx_rad_reg_debug5_s cn52xxp1; 768215976Sjmallett struct cvmx_rad_reg_debug5_s cn56xx; 769215976Sjmallett struct cvmx_rad_reg_debug5_s cn56xxp1; 770215976Sjmallett struct cvmx_rad_reg_debug5_s cn63xx; 771215976Sjmallett struct cvmx_rad_reg_debug5_s cn63xxp1; 772215976Sjmallett}; 773215976Sjmalletttypedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t; 774215976Sjmallett 775215976Sjmallett/** 776215976Sjmallett * cvmx_rad_reg_debug6 777215976Sjmallett */ 778215976Sjmallettunion cvmx_rad_reg_debug6 779215976Sjmallett{ 780215976Sjmallett uint64_t u64; 781215976Sjmallett struct cvmx_rad_reg_debug6_s 782215976Sjmallett { 783215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 784215976Sjmallett uint64_t cnt : 8; /**< CCTL count[7:0] (bytes) */ 785215976Sjmallett uint64_t size : 16; /**< CCTL size (bytes) */ 786215976Sjmallett uint64_t ptr : 40; /**< CCTL pointer */ 787215976Sjmallett#else 788215976Sjmallett uint64_t ptr : 40; 789215976Sjmallett uint64_t size : 16; 790215976Sjmallett uint64_t cnt : 8; 791215976Sjmallett#endif 792215976Sjmallett } s; 793215976Sjmallett struct cvmx_rad_reg_debug6_s cn52xx; 794215976Sjmallett struct cvmx_rad_reg_debug6_s cn52xxp1; 795215976Sjmallett struct cvmx_rad_reg_debug6_s cn56xx; 796215976Sjmallett struct cvmx_rad_reg_debug6_s cn56xxp1; 797215976Sjmallett struct cvmx_rad_reg_debug6_s cn63xx; 798215976Sjmallett struct cvmx_rad_reg_debug6_s cn63xxp1; 799215976Sjmallett}; 800215976Sjmalletttypedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t; 801215976Sjmallett 802215976Sjmallett/** 803215976Sjmallett * cvmx_rad_reg_debug7 804215976Sjmallett */ 805215976Sjmallettunion cvmx_rad_reg_debug7 806215976Sjmallett{ 807215976Sjmallett uint64_t u64; 808215976Sjmallett struct cvmx_rad_reg_debug7_s 809215976Sjmallett { 810215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 811215976Sjmallett uint64_t reserved_15_63 : 49; 812215976Sjmallett uint64_t cnt : 15; /**< CCTL count[22:8] (bytes) */ 813215976Sjmallett#else 814215976Sjmallett uint64_t cnt : 15; 815215976Sjmallett uint64_t reserved_15_63 : 49; 816215976Sjmallett#endif 817215976Sjmallett } s; 818215976Sjmallett struct cvmx_rad_reg_debug7_s cn52xx; 819215976Sjmallett struct cvmx_rad_reg_debug7_s cn52xxp1; 820215976Sjmallett struct cvmx_rad_reg_debug7_s cn56xx; 821215976Sjmallett struct cvmx_rad_reg_debug7_s cn56xxp1; 822215976Sjmallett struct cvmx_rad_reg_debug7_s cn63xx; 823215976Sjmallett struct cvmx_rad_reg_debug7_s cn63xxp1; 824215976Sjmallett}; 825215976Sjmalletttypedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t; 826215976Sjmallett 827215976Sjmallett/** 828215976Sjmallett * cvmx_rad_reg_debug8 829215976Sjmallett */ 830215976Sjmallettunion cvmx_rad_reg_debug8 831215976Sjmallett{ 832215976Sjmallett uint64_t u64; 833215976Sjmallett struct cvmx_rad_reg_debug8_s 834215976Sjmallett { 835215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 836215976Sjmallett uint64_t flags : 8; /**< ICTL flags */ 837215976Sjmallett uint64_t size : 16; /**< ICTL size (bytes) */ 838215976Sjmallett uint64_t ptr : 40; /**< ICTL pointer */ 839215976Sjmallett#else 840215976Sjmallett uint64_t ptr : 40; 841215976Sjmallett uint64_t size : 16; 842215976Sjmallett uint64_t flags : 8; 843215976Sjmallett#endif 844215976Sjmallett } s; 845215976Sjmallett struct cvmx_rad_reg_debug8_s cn52xx; 846215976Sjmallett struct cvmx_rad_reg_debug8_s cn52xxp1; 847215976Sjmallett struct cvmx_rad_reg_debug8_s cn56xx; 848215976Sjmallett struct cvmx_rad_reg_debug8_s cn56xxp1; 849215976Sjmallett struct cvmx_rad_reg_debug8_s cn63xx; 850215976Sjmallett struct cvmx_rad_reg_debug8_s cn63xxp1; 851215976Sjmallett}; 852215976Sjmalletttypedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t; 853215976Sjmallett 854215976Sjmallett/** 855215976Sjmallett * cvmx_rad_reg_debug9 856215976Sjmallett */ 857215976Sjmallettunion cvmx_rad_reg_debug9 858215976Sjmallett{ 859215976Sjmallett uint64_t u64; 860215976Sjmallett struct cvmx_rad_reg_debug9_s 861215976Sjmallett { 862215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 863215976Sjmallett uint64_t reserved_20_63 : 44; 864215976Sjmallett uint64_t eod : 1; /**< ICTL eod flag */ 865215976Sjmallett uint64_t ini : 1; /**< ICTL init flag */ 866215976Sjmallett uint64_t q : 1; /**< ICTL q enable */ 867215976Sjmallett uint64_t p : 1; /**< ICTL p enable */ 868215976Sjmallett uint64_t mul : 8; /**< ICTL multiplier */ 869215976Sjmallett uint64_t index : 8; /**< ICTL index */ 870215976Sjmallett#else 871215976Sjmallett uint64_t index : 8; 872215976Sjmallett uint64_t mul : 8; 873215976Sjmallett uint64_t p : 1; 874215976Sjmallett uint64_t q : 1; 875215976Sjmallett uint64_t ini : 1; 876215976Sjmallett uint64_t eod : 1; 877215976Sjmallett uint64_t reserved_20_63 : 44; 878215976Sjmallett#endif 879215976Sjmallett } s; 880215976Sjmallett struct cvmx_rad_reg_debug9_s cn52xx; 881215976Sjmallett struct cvmx_rad_reg_debug9_s cn52xxp1; 882215976Sjmallett struct cvmx_rad_reg_debug9_s cn56xx; 883215976Sjmallett struct cvmx_rad_reg_debug9_s cn56xxp1; 884215976Sjmallett struct cvmx_rad_reg_debug9_s cn63xx; 885215976Sjmallett struct cvmx_rad_reg_debug9_s cn63xxp1; 886215976Sjmallett}; 887215976Sjmalletttypedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t; 888215976Sjmallett 889215976Sjmallett/** 890215976Sjmallett * cvmx_rad_reg_error 891215976Sjmallett */ 892215976Sjmallettunion cvmx_rad_reg_error 893215976Sjmallett{ 894215976Sjmallett uint64_t u64; 895215976Sjmallett struct cvmx_rad_reg_error_s 896215976Sjmallett { 897215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 898215976Sjmallett uint64_t reserved_1_63 : 63; 899215976Sjmallett uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 900215976Sjmallett#else 901215976Sjmallett uint64_t doorbell : 1; 902215976Sjmallett uint64_t reserved_1_63 : 63; 903215976Sjmallett#endif 904215976Sjmallett } s; 905215976Sjmallett struct cvmx_rad_reg_error_s cn52xx; 906215976Sjmallett struct cvmx_rad_reg_error_s cn52xxp1; 907215976Sjmallett struct cvmx_rad_reg_error_s cn56xx; 908215976Sjmallett struct cvmx_rad_reg_error_s cn56xxp1; 909215976Sjmallett struct cvmx_rad_reg_error_s cn63xx; 910215976Sjmallett struct cvmx_rad_reg_error_s cn63xxp1; 911215976Sjmallett}; 912215976Sjmalletttypedef union cvmx_rad_reg_error cvmx_rad_reg_error_t; 913215976Sjmallett 914215976Sjmallett/** 915215976Sjmallett * cvmx_rad_reg_int_mask 916215976Sjmallett * 917215976Sjmallett * Notes: 918215976Sjmallett * When a mask bit is set, the corresponding interrupt is enabled. 919215976Sjmallett * 920215976Sjmallett */ 921215976Sjmallettunion cvmx_rad_reg_int_mask 922215976Sjmallett{ 923215976Sjmallett uint64_t u64; 924215976Sjmallett struct cvmx_rad_reg_int_mask_s 925215976Sjmallett { 926215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 927215976Sjmallett uint64_t reserved_1_63 : 63; 928215976Sjmallett uint64_t doorbell : 1; /**< Bit mask corresponding to RAD_REG_ERROR[0] above */ 929215976Sjmallett#else 930215976Sjmallett uint64_t doorbell : 1; 931215976Sjmallett uint64_t reserved_1_63 : 63; 932215976Sjmallett#endif 933215976Sjmallett } s; 934215976Sjmallett struct cvmx_rad_reg_int_mask_s cn52xx; 935215976Sjmallett struct cvmx_rad_reg_int_mask_s cn52xxp1; 936215976Sjmallett struct cvmx_rad_reg_int_mask_s cn56xx; 937215976Sjmallett struct cvmx_rad_reg_int_mask_s cn56xxp1; 938215976Sjmallett struct cvmx_rad_reg_int_mask_s cn63xx; 939215976Sjmallett struct cvmx_rad_reg_int_mask_s cn63xxp1; 940215976Sjmallett}; 941215976Sjmalletttypedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t; 942215976Sjmallett 943215976Sjmallett/** 944215976Sjmallett * cvmx_rad_reg_polynomial 945215976Sjmallett * 946215976Sjmallett * Notes: 947215976Sjmallett * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0. 948215976Sjmallett * 949215976Sjmallett */ 950215976Sjmallettunion cvmx_rad_reg_polynomial 951215976Sjmallett{ 952215976Sjmallett uint64_t u64; 953215976Sjmallett struct cvmx_rad_reg_polynomial_s 954215976Sjmallett { 955215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 956215976Sjmallett uint64_t reserved_8_63 : 56; 957215976Sjmallett uint64_t coeffs : 8; /**< coefficients of GF(2^8) irreducible polynomial */ 958215976Sjmallett#else 959215976Sjmallett uint64_t coeffs : 8; 960215976Sjmallett uint64_t reserved_8_63 : 56; 961215976Sjmallett#endif 962215976Sjmallett } s; 963215976Sjmallett struct cvmx_rad_reg_polynomial_s cn52xx; 964215976Sjmallett struct cvmx_rad_reg_polynomial_s cn52xxp1; 965215976Sjmallett struct cvmx_rad_reg_polynomial_s cn56xx; 966215976Sjmallett struct cvmx_rad_reg_polynomial_s cn56xxp1; 967215976Sjmallett struct cvmx_rad_reg_polynomial_s cn63xx; 968215976Sjmallett struct cvmx_rad_reg_polynomial_s cn63xxp1; 969215976Sjmallett}; 970215976Sjmalletttypedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t; 971215976Sjmallett 972215976Sjmallett/** 973215976Sjmallett * cvmx_rad_reg_read_idx 974215976Sjmallett * 975215976Sjmallett * Notes: 976215976Sjmallett * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 977215976Sjmallett * as memories. The names of these CSRs begin with the prefix "RAD_MEM_". 978215976Sjmallett * IDX[15:0] is the read index. INC[15:0] is an increment that is added to IDX[15:0] after any CSR read. 979215976Sjmallett * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 980215976Sjmallett * contents of a CSR memory can be read with consecutive CSR read commands. 981215976Sjmallett */ 982215976Sjmallettunion cvmx_rad_reg_read_idx 983215976Sjmallett{ 984215976Sjmallett uint64_t u64; 985215976Sjmallett struct cvmx_rad_reg_read_idx_s 986215976Sjmallett { 987215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 988215976Sjmallett uint64_t reserved_32_63 : 32; 989215976Sjmallett uint64_t inc : 16; /**< Increment to add to current index for next index */ 990215976Sjmallett uint64_t index : 16; /**< Index to use for next memory CSR read */ 991215976Sjmallett#else 992215976Sjmallett uint64_t index : 16; 993215976Sjmallett uint64_t inc : 16; 994215976Sjmallett uint64_t reserved_32_63 : 32; 995215976Sjmallett#endif 996215976Sjmallett } s; 997215976Sjmallett struct cvmx_rad_reg_read_idx_s cn52xx; 998215976Sjmallett struct cvmx_rad_reg_read_idx_s cn52xxp1; 999215976Sjmallett struct cvmx_rad_reg_read_idx_s cn56xx; 1000215976Sjmallett struct cvmx_rad_reg_read_idx_s cn56xxp1; 1001215976Sjmallett struct cvmx_rad_reg_read_idx_s cn63xx; 1002215976Sjmallett struct cvmx_rad_reg_read_idx_s cn63xxp1; 1003215976Sjmallett}; 1004215976Sjmalletttypedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t; 1005215976Sjmallett 1006215976Sjmallett#endif 1007