1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pow-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pow. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_POW_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_POW_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull)) 56215976Sjmallett#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull)) 57215976Sjmallett#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull)) 58215976Sjmallett#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull)) 59215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 60215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset) 61215976Sjmallett{ 62215976Sjmallett if (!( 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 64215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 65215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 66215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 67215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 68215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 69215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 70215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 71215976Sjmallett cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8; 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8) 76215976Sjmallett#endif 77215976Sjmallett#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull)) 78215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 79215976Sjmallett#define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC() 80215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_INT_FUNC(void) 81215976Sjmallett{ 82215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 83215976Sjmallett cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n"); 84215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000238ull); 85215976Sjmallett} 86215976Sjmallett#else 87215976Sjmallett#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull)) 88215976Sjmallett#endif 89215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90215976Sjmallett#define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC() 91215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void) 92215976Sjmallett{ 93215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 94215976Sjmallett cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n"); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000240ull); 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull)) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset) 102215976Sjmallett{ 103215976Sjmallett if (!( 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 106215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 107215976Sjmallett cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset); 108215976Sjmallett return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8; 109215976Sjmallett} 110215976Sjmallett#else 111215976Sjmallett#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8) 112215976Sjmallett#endif 113215976Sjmallett#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull)) 114215976Sjmallett#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull)) 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallett#define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC() 117215976Sjmallettstatic inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void) 118215976Sjmallett{ 119215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 120215976Sjmallett cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n"); 121215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000230ull); 122215976Sjmallett} 123215976Sjmallett#else 124215976Sjmallett#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull)) 125215976Sjmallett#endif 126215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 127215976Sjmallettstatic inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset) 128215976Sjmallett{ 129215976Sjmallett if (!( 130215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 132215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 133215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 134215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 138215976Sjmallett cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset); 139215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8; 140215976Sjmallett} 141215976Sjmallett#else 142215976Sjmallett#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8) 143215976Sjmallett#endif 144215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 145215976Sjmallettstatic inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset) 146215976Sjmallett{ 147215976Sjmallett if (!( 148215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 153215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 154215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 156215976Sjmallett cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset); 157215976Sjmallett return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8; 158215976Sjmallett} 159215976Sjmallett#else 160215976Sjmallett#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8) 161215976Sjmallett#endif 162215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 163215976Sjmallettstatic inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset) 164215976Sjmallett{ 165215976Sjmallett if (!( 166215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 169215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 170215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 171215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 172215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 173215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 174215976Sjmallett cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset); 175215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8; 176215976Sjmallett} 177215976Sjmallett#else 178215976Sjmallett#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8) 179215976Sjmallett#endif 180215976Sjmallett#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull)) 181215976Sjmallett#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull)) 182215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 183215976Sjmallettstatic inline uint64_t CVMX_POW_WA_PCX(unsigned long offset) 184215976Sjmallett{ 185215976Sjmallett if (!( 186215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 187215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 188215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 189215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 190215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 192215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 193215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 194215976Sjmallett cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset); 195215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8; 196215976Sjmallett} 197215976Sjmallett#else 198215976Sjmallett#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8) 199215976Sjmallett#endif 200215976Sjmallett#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull)) 201215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 202215976Sjmallettstatic inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset) 203215976Sjmallett{ 204215976Sjmallett if (!( 205215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 206215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 207215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 208215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 211215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))))) 213215976Sjmallett cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset); 214215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8; 215215976Sjmallett} 216215976Sjmallett#else 217215976Sjmallett#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8) 218215976Sjmallett#endif 219215976Sjmallett#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull)) 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 226215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 230215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 231215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))))) 232215976Sjmallett cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset); 233215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8; 234215976Sjmallett} 235215976Sjmallett#else 236215976Sjmallett#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8) 237215976Sjmallett#endif 238215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 239215976Sjmallettstatic inline uint64_t CVMX_POW_WS_PCX(unsigned long offset) 240215976Sjmallett{ 241215976Sjmallett if (!( 242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 244215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 245215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 247215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 248215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 249215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))))) 250215976Sjmallett cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset); 251215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8; 252215976Sjmallett} 253215976Sjmallett#else 254215976Sjmallett#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8) 255215976Sjmallett#endif 256215976Sjmallett 257215976Sjmallett/** 258215976Sjmallett * cvmx_pow_bist_stat 259215976Sjmallett * 260215976Sjmallett * POW_BIST_STAT = POW BIST Status Register 261215976Sjmallett * 262215976Sjmallett * Contains the BIST status for the POW memories ('0' = pass, '1' = fail). 263215976Sjmallett * 264215976Sjmallett * Also contains the BIST status for the PP's. Each bit in the PP field is the OR of all BIST 265215976Sjmallett * results for the corresponding physical PP ('0' = pass, '1' = fail). 266215976Sjmallett */ 267215976Sjmallettunion cvmx_pow_bist_stat 268215976Sjmallett{ 269215976Sjmallett uint64_t u64; 270215976Sjmallett struct cvmx_pow_bist_stat_s 271215976Sjmallett { 272215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 273215976Sjmallett uint64_t reserved_32_63 : 32; 274215976Sjmallett uint64_t pp : 16; /**< Physical PP BIST status */ 275215976Sjmallett uint64_t reserved_0_15 : 16; 276215976Sjmallett#else 277215976Sjmallett uint64_t reserved_0_15 : 16; 278215976Sjmallett uint64_t pp : 16; 279215976Sjmallett uint64_t reserved_32_63 : 32; 280215976Sjmallett#endif 281215976Sjmallett } s; 282215976Sjmallett struct cvmx_pow_bist_stat_cn30xx 283215976Sjmallett { 284215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 285215976Sjmallett uint64_t reserved_17_63 : 47; 286215976Sjmallett uint64_t pp : 1; /**< Physical PP BIST status */ 287215976Sjmallett uint64_t reserved_9_15 : 7; 288215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 289215976Sjmallett uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */ 290215976Sjmallett uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */ 291215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 292215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 293215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 294215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 295215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 296215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 297215976Sjmallett#else 298215976Sjmallett uint64_t adr : 1; 299215976Sjmallett uint64_t pend : 1; 300215976Sjmallett uint64_t nbr0 : 1; 301215976Sjmallett uint64_t nbr1 : 1; 302215976Sjmallett uint64_t fidx : 1; 303215976Sjmallett uint64_t index : 1; 304215976Sjmallett uint64_t nbt0 : 1; 305215976Sjmallett uint64_t nbt1 : 1; 306215976Sjmallett uint64_t cam : 1; 307215976Sjmallett uint64_t reserved_9_15 : 7; 308215976Sjmallett uint64_t pp : 1; 309215976Sjmallett uint64_t reserved_17_63 : 47; 310215976Sjmallett#endif 311215976Sjmallett } cn30xx; 312215976Sjmallett struct cvmx_pow_bist_stat_cn31xx 313215976Sjmallett { 314215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 315215976Sjmallett uint64_t reserved_18_63 : 46; 316215976Sjmallett uint64_t pp : 2; /**< Physical PP BIST status */ 317215976Sjmallett uint64_t reserved_9_15 : 7; 318215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 319215976Sjmallett uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */ 320215976Sjmallett uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */ 321215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 322215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 323215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 324215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 325215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 326215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 327215976Sjmallett#else 328215976Sjmallett uint64_t adr : 1; 329215976Sjmallett uint64_t pend : 1; 330215976Sjmallett uint64_t nbr0 : 1; 331215976Sjmallett uint64_t nbr1 : 1; 332215976Sjmallett uint64_t fidx : 1; 333215976Sjmallett uint64_t index : 1; 334215976Sjmallett uint64_t nbt0 : 1; 335215976Sjmallett uint64_t nbt1 : 1; 336215976Sjmallett uint64_t cam : 1; 337215976Sjmallett uint64_t reserved_9_15 : 7; 338215976Sjmallett uint64_t pp : 2; 339215976Sjmallett uint64_t reserved_18_63 : 46; 340215976Sjmallett#endif 341215976Sjmallett } cn31xx; 342215976Sjmallett struct cvmx_pow_bist_stat_cn38xx 343215976Sjmallett { 344215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 345215976Sjmallett uint64_t reserved_32_63 : 32; 346215976Sjmallett uint64_t pp : 16; /**< Physical PP BIST status */ 347215976Sjmallett uint64_t reserved_10_15 : 6; 348215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 349215976Sjmallett uint64_t nbt : 1; /**< NCB transmitter memory BIST status */ 350215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 351215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 352215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 353215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 354215976Sjmallett uint64_t pend1 : 1; /**< Pending switch memory 1 BIST status */ 355215976Sjmallett uint64_t pend0 : 1; /**< Pending switch memory 0 BIST status */ 356215976Sjmallett uint64_t adr1 : 1; /**< Address memory 1 BIST status */ 357215976Sjmallett uint64_t adr0 : 1; /**< Address memory 0 BIST status */ 358215976Sjmallett#else 359215976Sjmallett uint64_t adr0 : 1; 360215976Sjmallett uint64_t adr1 : 1; 361215976Sjmallett uint64_t pend0 : 1; 362215976Sjmallett uint64_t pend1 : 1; 363215976Sjmallett uint64_t nbr0 : 1; 364215976Sjmallett uint64_t nbr1 : 1; 365215976Sjmallett uint64_t fidx : 1; 366215976Sjmallett uint64_t index : 1; 367215976Sjmallett uint64_t nbt : 1; 368215976Sjmallett uint64_t cam : 1; 369215976Sjmallett uint64_t reserved_10_15 : 6; 370215976Sjmallett uint64_t pp : 16; 371215976Sjmallett uint64_t reserved_32_63 : 32; 372215976Sjmallett#endif 373215976Sjmallett } cn38xx; 374215976Sjmallett struct cvmx_pow_bist_stat_cn38xx cn38xxp2; 375215976Sjmallett struct cvmx_pow_bist_stat_cn31xx cn50xx; 376215976Sjmallett struct cvmx_pow_bist_stat_cn52xx 377215976Sjmallett { 378215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 379215976Sjmallett uint64_t reserved_20_63 : 44; 380215976Sjmallett uint64_t pp : 4; /**< Physical PP BIST status */ 381215976Sjmallett uint64_t reserved_9_15 : 7; 382215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 383215976Sjmallett uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */ 384215976Sjmallett uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */ 385215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 386215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 387215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 388215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 389215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 390215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 391215976Sjmallett#else 392215976Sjmallett uint64_t adr : 1; 393215976Sjmallett uint64_t pend : 1; 394215976Sjmallett uint64_t nbr0 : 1; 395215976Sjmallett uint64_t nbr1 : 1; 396215976Sjmallett uint64_t fidx : 1; 397215976Sjmallett uint64_t index : 1; 398215976Sjmallett uint64_t nbt0 : 1; 399215976Sjmallett uint64_t nbt1 : 1; 400215976Sjmallett uint64_t cam : 1; 401215976Sjmallett uint64_t reserved_9_15 : 7; 402215976Sjmallett uint64_t pp : 4; 403215976Sjmallett uint64_t reserved_20_63 : 44; 404215976Sjmallett#endif 405215976Sjmallett } cn52xx; 406215976Sjmallett struct cvmx_pow_bist_stat_cn52xx cn52xxp1; 407215976Sjmallett struct cvmx_pow_bist_stat_cn56xx 408215976Sjmallett { 409215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 410215976Sjmallett uint64_t reserved_28_63 : 36; 411215976Sjmallett uint64_t pp : 12; /**< Physical PP BIST status */ 412215976Sjmallett uint64_t reserved_10_15 : 6; 413215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 414215976Sjmallett uint64_t nbt : 1; /**< NCB transmitter memory BIST status */ 415215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 416215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 417215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 418215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 419215976Sjmallett uint64_t pend1 : 1; /**< Pending switch memory 1 BIST status */ 420215976Sjmallett uint64_t pend0 : 1; /**< Pending switch memory 0 BIST status */ 421215976Sjmallett uint64_t adr1 : 1; /**< Address memory 1 BIST status */ 422215976Sjmallett uint64_t adr0 : 1; /**< Address memory 0 BIST status */ 423215976Sjmallett#else 424215976Sjmallett uint64_t adr0 : 1; 425215976Sjmallett uint64_t adr1 : 1; 426215976Sjmallett uint64_t pend0 : 1; 427215976Sjmallett uint64_t pend1 : 1; 428215976Sjmallett uint64_t nbr0 : 1; 429215976Sjmallett uint64_t nbr1 : 1; 430215976Sjmallett uint64_t fidx : 1; 431215976Sjmallett uint64_t index : 1; 432215976Sjmallett uint64_t nbt : 1; 433215976Sjmallett uint64_t cam : 1; 434215976Sjmallett uint64_t reserved_10_15 : 6; 435215976Sjmallett uint64_t pp : 12; 436215976Sjmallett uint64_t reserved_28_63 : 36; 437215976Sjmallett#endif 438215976Sjmallett } cn56xx; 439215976Sjmallett struct cvmx_pow_bist_stat_cn56xx cn56xxp1; 440215976Sjmallett struct cvmx_pow_bist_stat_cn38xx cn58xx; 441215976Sjmallett struct cvmx_pow_bist_stat_cn38xx cn58xxp1; 442215976Sjmallett struct cvmx_pow_bist_stat_cn63xx 443215976Sjmallett { 444215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 445215976Sjmallett uint64_t reserved_22_63 : 42; 446215976Sjmallett uint64_t pp : 6; /**< Physical PP BIST status */ 447215976Sjmallett uint64_t reserved_12_15 : 4; 448215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 449215976Sjmallett uint64_t nbr : 3; /**< NCB receiver memory BIST status */ 450215976Sjmallett uint64_t nbt : 4; /**< NCB transmitter memory BIST status */ 451215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 452215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 453215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 454215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 455215976Sjmallett#else 456215976Sjmallett uint64_t adr : 1; 457215976Sjmallett uint64_t pend : 1; 458215976Sjmallett uint64_t fidx : 1; 459215976Sjmallett uint64_t index : 1; 460215976Sjmallett uint64_t nbt : 4; 461215976Sjmallett uint64_t nbr : 3; 462215976Sjmallett uint64_t cam : 1; 463215976Sjmallett uint64_t reserved_12_15 : 4; 464215976Sjmallett uint64_t pp : 6; 465215976Sjmallett uint64_t reserved_22_63 : 42; 466215976Sjmallett#endif 467215976Sjmallett } cn63xx; 468215976Sjmallett struct cvmx_pow_bist_stat_cn63xx cn63xxp1; 469215976Sjmallett}; 470215976Sjmalletttypedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t; 471215976Sjmallett 472215976Sjmallett/** 473215976Sjmallett * cvmx_pow_ds_pc 474215976Sjmallett * 475215976Sjmallett * POW_DS_PC = POW De-Schedule Performance Counter 476215976Sjmallett * 477215976Sjmallett * Counts the number of de-schedule requests. Write to clear. 478215976Sjmallett */ 479215976Sjmallettunion cvmx_pow_ds_pc 480215976Sjmallett{ 481215976Sjmallett uint64_t u64; 482215976Sjmallett struct cvmx_pow_ds_pc_s 483215976Sjmallett { 484215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 485215976Sjmallett uint64_t reserved_32_63 : 32; 486215976Sjmallett uint64_t ds_pc : 32; /**< De-schedule performance counter */ 487215976Sjmallett#else 488215976Sjmallett uint64_t ds_pc : 32; 489215976Sjmallett uint64_t reserved_32_63 : 32; 490215976Sjmallett#endif 491215976Sjmallett } s; 492215976Sjmallett struct cvmx_pow_ds_pc_s cn30xx; 493215976Sjmallett struct cvmx_pow_ds_pc_s cn31xx; 494215976Sjmallett struct cvmx_pow_ds_pc_s cn38xx; 495215976Sjmallett struct cvmx_pow_ds_pc_s cn38xxp2; 496215976Sjmallett struct cvmx_pow_ds_pc_s cn50xx; 497215976Sjmallett struct cvmx_pow_ds_pc_s cn52xx; 498215976Sjmallett struct cvmx_pow_ds_pc_s cn52xxp1; 499215976Sjmallett struct cvmx_pow_ds_pc_s cn56xx; 500215976Sjmallett struct cvmx_pow_ds_pc_s cn56xxp1; 501215976Sjmallett struct cvmx_pow_ds_pc_s cn58xx; 502215976Sjmallett struct cvmx_pow_ds_pc_s cn58xxp1; 503215976Sjmallett struct cvmx_pow_ds_pc_s cn63xx; 504215976Sjmallett struct cvmx_pow_ds_pc_s cn63xxp1; 505215976Sjmallett}; 506215976Sjmalletttypedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t; 507215976Sjmallett 508215976Sjmallett/** 509215976Sjmallett * cvmx_pow_ecc_err 510215976Sjmallett * 511215976Sjmallett * POW_ECC_ERR = POW ECC Error Register 512215976Sjmallett * 513215976Sjmallett * Contains the single and double error bits and the corresponding interrupt enables for the ECC- 514215976Sjmallett * protected POW index memory. Also contains the syndrome value in the event of an ECC error. 515215976Sjmallett * 516215976Sjmallett * Also contains the remote pointer error bit and interrupt enable. RPE is set when the POW detected 517215976Sjmallett * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail pointer 518215976Sjmallett * for the L2/DRAM input queue did not match the last entry on the the list). This is caused by 519215976Sjmallett * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad work 520215976Sjmallett * queue entries. 521215976Sjmallett * 522215976Sjmallett * This register also contains the illegal operation error bits and the corresponding interrupt 523215976Sjmallett * enables as follows: 524215976Sjmallett * 525215976Sjmallett * <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state 526215976Sjmallett * <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state 527215976Sjmallett * <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC 528215976Sjmallett * <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL 529215976Sjmallett * <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL 530215976Sjmallett * <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending 531215976Sjmallett * <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending 532215976Sjmallett * <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending 533215976Sjmallett * <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending 534215976Sjmallett * <9> Received illegal opcode 535215976Sjmallett * <10> Received ADD_WORK with tag specified as NULL_NULL 536215976Sjmallett * <11> Received DBG load from PP with DBG load pending 537215976Sjmallett * <12> Received CSR load from PP with CSR load pending 538215976Sjmallett */ 539215976Sjmallettunion cvmx_pow_ecc_err 540215976Sjmallett{ 541215976Sjmallett uint64_t u64; 542215976Sjmallett struct cvmx_pow_ecc_err_s 543215976Sjmallett { 544215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 545215976Sjmallett uint64_t reserved_45_63 : 19; 546215976Sjmallett uint64_t iop_ie : 13; /**< Illegal operation interrupt enables */ 547215976Sjmallett uint64_t reserved_29_31 : 3; 548215976Sjmallett uint64_t iop : 13; /**< Illegal operation errors */ 549215976Sjmallett uint64_t reserved_14_15 : 2; 550215976Sjmallett uint64_t rpe_ie : 1; /**< Remote pointer error interrupt enable */ 551215976Sjmallett uint64_t rpe : 1; /**< Remote pointer error */ 552215976Sjmallett uint64_t reserved_9_11 : 3; 553215976Sjmallett uint64_t syn : 5; /**< Syndrome value (only valid when DBE or SBE is set) */ 554215976Sjmallett uint64_t dbe_ie : 1; /**< Double bit error interrupt enable */ 555215976Sjmallett uint64_t sbe_ie : 1; /**< Single bit error interrupt enable */ 556215976Sjmallett uint64_t dbe : 1; /**< Double bit error */ 557215976Sjmallett uint64_t sbe : 1; /**< Single bit error */ 558215976Sjmallett#else 559215976Sjmallett uint64_t sbe : 1; 560215976Sjmallett uint64_t dbe : 1; 561215976Sjmallett uint64_t sbe_ie : 1; 562215976Sjmallett uint64_t dbe_ie : 1; 563215976Sjmallett uint64_t syn : 5; 564215976Sjmallett uint64_t reserved_9_11 : 3; 565215976Sjmallett uint64_t rpe : 1; 566215976Sjmallett uint64_t rpe_ie : 1; 567215976Sjmallett uint64_t reserved_14_15 : 2; 568215976Sjmallett uint64_t iop : 13; 569215976Sjmallett uint64_t reserved_29_31 : 3; 570215976Sjmallett uint64_t iop_ie : 13; 571215976Sjmallett uint64_t reserved_45_63 : 19; 572215976Sjmallett#endif 573215976Sjmallett } s; 574215976Sjmallett struct cvmx_pow_ecc_err_s cn30xx; 575215976Sjmallett struct cvmx_pow_ecc_err_cn31xx 576215976Sjmallett { 577215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 578215976Sjmallett uint64_t reserved_14_63 : 50; 579215976Sjmallett uint64_t rpe_ie : 1; /**< Remote pointer error interrupt enable */ 580215976Sjmallett uint64_t rpe : 1; /**< Remote pointer error */ 581215976Sjmallett uint64_t reserved_9_11 : 3; 582215976Sjmallett uint64_t syn : 5; /**< Syndrome value (only valid when DBE or SBE is set) */ 583215976Sjmallett uint64_t dbe_ie : 1; /**< Double bit error interrupt enable */ 584215976Sjmallett uint64_t sbe_ie : 1; /**< Single bit error interrupt enable */ 585215976Sjmallett uint64_t dbe : 1; /**< Double bit error */ 586215976Sjmallett uint64_t sbe : 1; /**< Single bit error */ 587215976Sjmallett#else 588215976Sjmallett uint64_t sbe : 1; 589215976Sjmallett uint64_t dbe : 1; 590215976Sjmallett uint64_t sbe_ie : 1; 591215976Sjmallett uint64_t dbe_ie : 1; 592215976Sjmallett uint64_t syn : 5; 593215976Sjmallett uint64_t reserved_9_11 : 3; 594215976Sjmallett uint64_t rpe : 1; 595215976Sjmallett uint64_t rpe_ie : 1; 596215976Sjmallett uint64_t reserved_14_63 : 50; 597215976Sjmallett#endif 598215976Sjmallett } cn31xx; 599215976Sjmallett struct cvmx_pow_ecc_err_s cn38xx; 600215976Sjmallett struct cvmx_pow_ecc_err_cn31xx cn38xxp2; 601215976Sjmallett struct cvmx_pow_ecc_err_s cn50xx; 602215976Sjmallett struct cvmx_pow_ecc_err_s cn52xx; 603215976Sjmallett struct cvmx_pow_ecc_err_s cn52xxp1; 604215976Sjmallett struct cvmx_pow_ecc_err_s cn56xx; 605215976Sjmallett struct cvmx_pow_ecc_err_s cn56xxp1; 606215976Sjmallett struct cvmx_pow_ecc_err_s cn58xx; 607215976Sjmallett struct cvmx_pow_ecc_err_s cn58xxp1; 608215976Sjmallett struct cvmx_pow_ecc_err_s cn63xx; 609215976Sjmallett struct cvmx_pow_ecc_err_s cn63xxp1; 610215976Sjmallett}; 611215976Sjmalletttypedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t; 612215976Sjmallett 613215976Sjmallett/** 614215976Sjmallett * cvmx_pow_int_ctl 615215976Sjmallett * 616215976Sjmallett * POW_INT_CTL = POW Internal Control Register 617215976Sjmallett * 618215976Sjmallett * Contains POW internal control values (for internal use, not typically for customer use): 619215976Sjmallett * 620215976Sjmallett * PFR_DIS = Disable high-performance pre-fetch reset mode. 621215976Sjmallett * 622215976Sjmallett * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less 623215976Sjmallett * than or equal to this value. 624215976Sjmallett */ 625215976Sjmallettunion cvmx_pow_int_ctl 626215976Sjmallett{ 627215976Sjmallett uint64_t u64; 628215976Sjmallett struct cvmx_pow_int_ctl_s 629215976Sjmallett { 630215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 631215976Sjmallett uint64_t reserved_6_63 : 58; 632215976Sjmallett uint64_t pfr_dis : 1; /**< High-perf pre-fetch reset mode disable */ 633215976Sjmallett uint64_t nbr_thr : 5; /**< NBR busy threshold */ 634215976Sjmallett#else 635215976Sjmallett uint64_t nbr_thr : 5; 636215976Sjmallett uint64_t pfr_dis : 1; 637215976Sjmallett uint64_t reserved_6_63 : 58; 638215976Sjmallett#endif 639215976Sjmallett } s; 640215976Sjmallett struct cvmx_pow_int_ctl_s cn30xx; 641215976Sjmallett struct cvmx_pow_int_ctl_s cn31xx; 642215976Sjmallett struct cvmx_pow_int_ctl_s cn38xx; 643215976Sjmallett struct cvmx_pow_int_ctl_s cn38xxp2; 644215976Sjmallett struct cvmx_pow_int_ctl_s cn50xx; 645215976Sjmallett struct cvmx_pow_int_ctl_s cn52xx; 646215976Sjmallett struct cvmx_pow_int_ctl_s cn52xxp1; 647215976Sjmallett struct cvmx_pow_int_ctl_s cn56xx; 648215976Sjmallett struct cvmx_pow_int_ctl_s cn56xxp1; 649215976Sjmallett struct cvmx_pow_int_ctl_s cn58xx; 650215976Sjmallett struct cvmx_pow_int_ctl_s cn58xxp1; 651215976Sjmallett struct cvmx_pow_int_ctl_s cn63xx; 652215976Sjmallett struct cvmx_pow_int_ctl_s cn63xxp1; 653215976Sjmallett}; 654215976Sjmalletttypedef union cvmx_pow_int_ctl cvmx_pow_int_ctl_t; 655215976Sjmallett 656215976Sjmallett/** 657215976Sjmallett * cvmx_pow_iq_cnt# 658215976Sjmallett * 659215976Sjmallett * POW_IQ_CNTX = POW Input Queue Count Register (1 per QOS level) 660215976Sjmallett * 661215976Sjmallett * Contains a read-only count of the number of work queue entries for each QOS level. 662215976Sjmallett */ 663215976Sjmallettunion cvmx_pow_iq_cntx 664215976Sjmallett{ 665215976Sjmallett uint64_t u64; 666215976Sjmallett struct cvmx_pow_iq_cntx_s 667215976Sjmallett { 668215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 669215976Sjmallett uint64_t reserved_32_63 : 32; 670215976Sjmallett uint64_t iq_cnt : 32; /**< Input queue count for QOS level X */ 671215976Sjmallett#else 672215976Sjmallett uint64_t iq_cnt : 32; 673215976Sjmallett uint64_t reserved_32_63 : 32; 674215976Sjmallett#endif 675215976Sjmallett } s; 676215976Sjmallett struct cvmx_pow_iq_cntx_s cn30xx; 677215976Sjmallett struct cvmx_pow_iq_cntx_s cn31xx; 678215976Sjmallett struct cvmx_pow_iq_cntx_s cn38xx; 679215976Sjmallett struct cvmx_pow_iq_cntx_s cn38xxp2; 680215976Sjmallett struct cvmx_pow_iq_cntx_s cn50xx; 681215976Sjmallett struct cvmx_pow_iq_cntx_s cn52xx; 682215976Sjmallett struct cvmx_pow_iq_cntx_s cn52xxp1; 683215976Sjmallett struct cvmx_pow_iq_cntx_s cn56xx; 684215976Sjmallett struct cvmx_pow_iq_cntx_s cn56xxp1; 685215976Sjmallett struct cvmx_pow_iq_cntx_s cn58xx; 686215976Sjmallett struct cvmx_pow_iq_cntx_s cn58xxp1; 687215976Sjmallett struct cvmx_pow_iq_cntx_s cn63xx; 688215976Sjmallett struct cvmx_pow_iq_cntx_s cn63xxp1; 689215976Sjmallett}; 690215976Sjmalletttypedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t; 691215976Sjmallett 692215976Sjmallett/** 693215976Sjmallett * cvmx_pow_iq_com_cnt 694215976Sjmallett * 695215976Sjmallett * POW_IQ_COM_CNT = POW Input Queue Combined Count Register 696215976Sjmallett * 697215976Sjmallett * Contains a read-only count of the total number of work queue entries in all QOS levels. 698215976Sjmallett */ 699215976Sjmallettunion cvmx_pow_iq_com_cnt 700215976Sjmallett{ 701215976Sjmallett uint64_t u64; 702215976Sjmallett struct cvmx_pow_iq_com_cnt_s 703215976Sjmallett { 704215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 705215976Sjmallett uint64_t reserved_32_63 : 32; 706215976Sjmallett uint64_t iq_cnt : 32; /**< Input queue combined count */ 707215976Sjmallett#else 708215976Sjmallett uint64_t iq_cnt : 32; 709215976Sjmallett uint64_t reserved_32_63 : 32; 710215976Sjmallett#endif 711215976Sjmallett } s; 712215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn30xx; 713215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn31xx; 714215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn38xx; 715215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn38xxp2; 716215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn50xx; 717215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn52xx; 718215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn52xxp1; 719215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn56xx; 720215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn56xxp1; 721215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn58xx; 722215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn58xxp1; 723215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn63xx; 724215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn63xxp1; 725215976Sjmallett}; 726215976Sjmalletttypedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t; 727215976Sjmallett 728215976Sjmallett/** 729215976Sjmallett * cvmx_pow_iq_int 730215976Sjmallett * 731215976Sjmallett * POW_IQ_INT = POW Input Queue Interrupt Register 732215976Sjmallett * 733215976Sjmallett * Contains the bits (1 per QOS level) that can trigger the input queue interrupt. An IQ_INT bit 734215976Sjmallett * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#. 735215976Sjmallett */ 736215976Sjmallettunion cvmx_pow_iq_int 737215976Sjmallett{ 738215976Sjmallett uint64_t u64; 739215976Sjmallett struct cvmx_pow_iq_int_s 740215976Sjmallett { 741215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 742215976Sjmallett uint64_t reserved_8_63 : 56; 743215976Sjmallett uint64_t iq_int : 8; /**< Input queue interrupt bits */ 744215976Sjmallett#else 745215976Sjmallett uint64_t iq_int : 8; 746215976Sjmallett uint64_t reserved_8_63 : 56; 747215976Sjmallett#endif 748215976Sjmallett } s; 749215976Sjmallett struct cvmx_pow_iq_int_s cn52xx; 750215976Sjmallett struct cvmx_pow_iq_int_s cn52xxp1; 751215976Sjmallett struct cvmx_pow_iq_int_s cn56xx; 752215976Sjmallett struct cvmx_pow_iq_int_s cn56xxp1; 753215976Sjmallett struct cvmx_pow_iq_int_s cn63xx; 754215976Sjmallett struct cvmx_pow_iq_int_s cn63xxp1; 755215976Sjmallett}; 756215976Sjmalletttypedef union cvmx_pow_iq_int cvmx_pow_iq_int_t; 757215976Sjmallett 758215976Sjmallett/** 759215976Sjmallett * cvmx_pow_iq_int_en 760215976Sjmallett * 761215976Sjmallett * POW_IQ_INT_EN = POW Input Queue Interrupt Enable Register 762215976Sjmallett * 763215976Sjmallett * Contains the bits (1 per QOS level) that enable the input queue interrupt. 764215976Sjmallett */ 765215976Sjmallettunion cvmx_pow_iq_int_en 766215976Sjmallett{ 767215976Sjmallett uint64_t u64; 768215976Sjmallett struct cvmx_pow_iq_int_en_s 769215976Sjmallett { 770215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 771215976Sjmallett uint64_t reserved_8_63 : 56; 772215976Sjmallett uint64_t int_en : 8; /**< Input queue interrupt enable bits */ 773215976Sjmallett#else 774215976Sjmallett uint64_t int_en : 8; 775215976Sjmallett uint64_t reserved_8_63 : 56; 776215976Sjmallett#endif 777215976Sjmallett } s; 778215976Sjmallett struct cvmx_pow_iq_int_en_s cn52xx; 779215976Sjmallett struct cvmx_pow_iq_int_en_s cn52xxp1; 780215976Sjmallett struct cvmx_pow_iq_int_en_s cn56xx; 781215976Sjmallett struct cvmx_pow_iq_int_en_s cn56xxp1; 782215976Sjmallett struct cvmx_pow_iq_int_en_s cn63xx; 783215976Sjmallett struct cvmx_pow_iq_int_en_s cn63xxp1; 784215976Sjmallett}; 785215976Sjmalletttypedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t; 786215976Sjmallett 787215976Sjmallett/** 788215976Sjmallett * cvmx_pow_iq_thr# 789215976Sjmallett * 790215976Sjmallett * POW_IQ_THRX = POW Input Queue Threshold Register (1 per QOS level) 791215976Sjmallett * 792215976Sjmallett * Threshold value for triggering input queue interrupts. 793215976Sjmallett */ 794215976Sjmallettunion cvmx_pow_iq_thrx 795215976Sjmallett{ 796215976Sjmallett uint64_t u64; 797215976Sjmallett struct cvmx_pow_iq_thrx_s 798215976Sjmallett { 799215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 800215976Sjmallett uint64_t reserved_32_63 : 32; 801215976Sjmallett uint64_t iq_thr : 32; /**< Input queue threshold for QOS level X */ 802215976Sjmallett#else 803215976Sjmallett uint64_t iq_thr : 32; 804215976Sjmallett uint64_t reserved_32_63 : 32; 805215976Sjmallett#endif 806215976Sjmallett } s; 807215976Sjmallett struct cvmx_pow_iq_thrx_s cn52xx; 808215976Sjmallett struct cvmx_pow_iq_thrx_s cn52xxp1; 809215976Sjmallett struct cvmx_pow_iq_thrx_s cn56xx; 810215976Sjmallett struct cvmx_pow_iq_thrx_s cn56xxp1; 811215976Sjmallett struct cvmx_pow_iq_thrx_s cn63xx; 812215976Sjmallett struct cvmx_pow_iq_thrx_s cn63xxp1; 813215976Sjmallett}; 814215976Sjmalletttypedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t; 815215976Sjmallett 816215976Sjmallett/** 817215976Sjmallett * cvmx_pow_nos_cnt 818215976Sjmallett * 819215976Sjmallett * POW_NOS_CNT = POW No-schedule Count Register 820215976Sjmallett * 821215976Sjmallett * Contains the number of work queue entries on the no-schedule list. 822215976Sjmallett */ 823215976Sjmallettunion cvmx_pow_nos_cnt 824215976Sjmallett{ 825215976Sjmallett uint64_t u64; 826215976Sjmallett struct cvmx_pow_nos_cnt_s 827215976Sjmallett { 828215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 829215976Sjmallett uint64_t reserved_12_63 : 52; 830215976Sjmallett uint64_t nos_cnt : 12; /**< # of work queue entries on the no-schedule list */ 831215976Sjmallett#else 832215976Sjmallett uint64_t nos_cnt : 12; 833215976Sjmallett uint64_t reserved_12_63 : 52; 834215976Sjmallett#endif 835215976Sjmallett } s; 836215976Sjmallett struct cvmx_pow_nos_cnt_cn30xx 837215976Sjmallett { 838215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 839215976Sjmallett uint64_t reserved_7_63 : 57; 840215976Sjmallett uint64_t nos_cnt : 7; /**< # of work queue entries on the no-schedule list */ 841215976Sjmallett#else 842215976Sjmallett uint64_t nos_cnt : 7; 843215976Sjmallett uint64_t reserved_7_63 : 57; 844215976Sjmallett#endif 845215976Sjmallett } cn30xx; 846215976Sjmallett struct cvmx_pow_nos_cnt_cn31xx 847215976Sjmallett { 848215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 849215976Sjmallett uint64_t reserved_9_63 : 55; 850215976Sjmallett uint64_t nos_cnt : 9; /**< # of work queue entries on the no-schedule list */ 851215976Sjmallett#else 852215976Sjmallett uint64_t nos_cnt : 9; 853215976Sjmallett uint64_t reserved_9_63 : 55; 854215976Sjmallett#endif 855215976Sjmallett } cn31xx; 856215976Sjmallett struct cvmx_pow_nos_cnt_s cn38xx; 857215976Sjmallett struct cvmx_pow_nos_cnt_s cn38xxp2; 858215976Sjmallett struct cvmx_pow_nos_cnt_cn31xx cn50xx; 859215976Sjmallett struct cvmx_pow_nos_cnt_cn52xx 860215976Sjmallett { 861215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 862215976Sjmallett uint64_t reserved_10_63 : 54; 863215976Sjmallett uint64_t nos_cnt : 10; /**< # of work queue entries on the no-schedule list */ 864215976Sjmallett#else 865215976Sjmallett uint64_t nos_cnt : 10; 866215976Sjmallett uint64_t reserved_10_63 : 54; 867215976Sjmallett#endif 868215976Sjmallett } cn52xx; 869215976Sjmallett struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; 870215976Sjmallett struct cvmx_pow_nos_cnt_s cn56xx; 871215976Sjmallett struct cvmx_pow_nos_cnt_s cn56xxp1; 872215976Sjmallett struct cvmx_pow_nos_cnt_s cn58xx; 873215976Sjmallett struct cvmx_pow_nos_cnt_s cn58xxp1; 874215976Sjmallett struct cvmx_pow_nos_cnt_cn63xx 875215976Sjmallett { 876215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 877215976Sjmallett uint64_t reserved_11_63 : 53; 878215976Sjmallett uint64_t nos_cnt : 11; /**< # of work queue entries on the no-schedule list */ 879215976Sjmallett#else 880215976Sjmallett uint64_t nos_cnt : 11; 881215976Sjmallett uint64_t reserved_11_63 : 53; 882215976Sjmallett#endif 883215976Sjmallett } cn63xx; 884215976Sjmallett struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; 885215976Sjmallett}; 886215976Sjmalletttypedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t; 887215976Sjmallett 888215976Sjmallett/** 889215976Sjmallett * cvmx_pow_nw_tim 890215976Sjmallett * 891215976Sjmallett * POW_NW_TIM = POW New Work Timer Period Register 892215976Sjmallett * 893215976Sjmallett * Sets the minimum period for a new work request timeout. Period is specified in n-1 notation 894215976Sjmallett * where the increment value is 1024 clock cycles. Thus, a value of 0x0 in this register translates 895215976Sjmallett * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc... Note: the 896215976Sjmallett * maximum period for a new work request timeout is 2 times the minimum period. Note: the new work 897215976Sjmallett * request timeout counter is reset when this register is written. 898215976Sjmallett * 899215976Sjmallett * There are two new work request timeout cases: 900215976Sjmallett * 901215976Sjmallett * - WAIT bit clear. The new work request can timeout if the timer expires before the pre-fetch 902215976Sjmallett * engine has reached the end of all work queues. This can occur if the executable work queue 903215976Sjmallett * entry is deep in the queue and the pre-fetch engine is subject to many resets (i.e. high switch, 904215976Sjmallett * de-schedule, or new work load from other PP's). Thus, it is possible for a PP to receive a work 905215976Sjmallett * response with the NO_WORK bit set even though there was at least one executable entry in the 906215976Sjmallett * work queues. The other (and typical) scenario for receiving a NO_WORK response with the WAIT 907215976Sjmallett * bit clear is that the pre-fetch engine has reached the end of all work queues without finding 908215976Sjmallett * executable work. 909215976Sjmallett * 910215976Sjmallett * - WAIT bit set. The new work request can timeout if the timer expires before the pre-fetch 911215976Sjmallett * engine has found executable work. In this case, the only scenario where the PP will receive a 912215976Sjmallett * work response with the NO_WORK bit set is if the timer expires. Note: it is still possible for 913215976Sjmallett * a PP to receive a NO_WORK response even though there was at least one executable entry in the 914215976Sjmallett * work queues. 915215976Sjmallett * 916215976Sjmallett * In either case, it's important to note that switches and de-schedules are higher priority 917215976Sjmallett * operations that can cause the pre-fetch engine to reset. Thus in a system with many switches or 918215976Sjmallett * de-schedules occuring, it's possible for the new work timer to expire (resulting in NO_WORK 919215976Sjmallett * responses) before the pre-fetch engine is able to get very deep into the work queues. 920215976Sjmallett */ 921215976Sjmallettunion cvmx_pow_nw_tim 922215976Sjmallett{ 923215976Sjmallett uint64_t u64; 924215976Sjmallett struct cvmx_pow_nw_tim_s 925215976Sjmallett { 926215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 927215976Sjmallett uint64_t reserved_10_63 : 54; 928215976Sjmallett uint64_t nw_tim : 10; /**< New work timer period */ 929215976Sjmallett#else 930215976Sjmallett uint64_t nw_tim : 10; 931215976Sjmallett uint64_t reserved_10_63 : 54; 932215976Sjmallett#endif 933215976Sjmallett } s; 934215976Sjmallett struct cvmx_pow_nw_tim_s cn30xx; 935215976Sjmallett struct cvmx_pow_nw_tim_s cn31xx; 936215976Sjmallett struct cvmx_pow_nw_tim_s cn38xx; 937215976Sjmallett struct cvmx_pow_nw_tim_s cn38xxp2; 938215976Sjmallett struct cvmx_pow_nw_tim_s cn50xx; 939215976Sjmallett struct cvmx_pow_nw_tim_s cn52xx; 940215976Sjmallett struct cvmx_pow_nw_tim_s cn52xxp1; 941215976Sjmallett struct cvmx_pow_nw_tim_s cn56xx; 942215976Sjmallett struct cvmx_pow_nw_tim_s cn56xxp1; 943215976Sjmallett struct cvmx_pow_nw_tim_s cn58xx; 944215976Sjmallett struct cvmx_pow_nw_tim_s cn58xxp1; 945215976Sjmallett struct cvmx_pow_nw_tim_s cn63xx; 946215976Sjmallett struct cvmx_pow_nw_tim_s cn63xxp1; 947215976Sjmallett}; 948215976Sjmalletttypedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t; 949215976Sjmallett 950215976Sjmallett/** 951215976Sjmallett * cvmx_pow_pf_rst_msk 952215976Sjmallett * 953215976Sjmallett * POW_PF_RST_MSK = POW Prefetch Reset Mask 954215976Sjmallett * 955215976Sjmallett * Resets the work prefetch engine when work is stored in an internal buffer (either when the add 956215976Sjmallett * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level 957215976Sjmallett * (1 bit per QOS level). 958215976Sjmallett */ 959215976Sjmallettunion cvmx_pow_pf_rst_msk 960215976Sjmallett{ 961215976Sjmallett uint64_t u64; 962215976Sjmallett struct cvmx_pow_pf_rst_msk_s 963215976Sjmallett { 964215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 965215976Sjmallett uint64_t reserved_8_63 : 56; 966215976Sjmallett uint64_t rst_msk : 8; /**< Prefetch engine reset mask */ 967215976Sjmallett#else 968215976Sjmallett uint64_t rst_msk : 8; 969215976Sjmallett uint64_t reserved_8_63 : 56; 970215976Sjmallett#endif 971215976Sjmallett } s; 972215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn50xx; 973215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn52xx; 974215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn52xxp1; 975215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn56xx; 976215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn56xxp1; 977215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn58xx; 978215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn58xxp1; 979215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn63xx; 980215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn63xxp1; 981215976Sjmallett}; 982215976Sjmalletttypedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t; 983215976Sjmallett 984215976Sjmallett/** 985215976Sjmallett * cvmx_pow_pp_grp_msk# 986215976Sjmallett * 987215976Sjmallett * POW_PP_GRP_MSKX = POW PP Group Mask Register (1 per PP) 988215976Sjmallett * 989215976Sjmallett * Selects which group(s) a PP belongs to. A '1' in any bit position sets the PP's membership in 990215976Sjmallett * the corresponding group. A value of 0x0 will prevent the PP from receiving new work. Note: 991215976Sjmallett * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order to 992215976Sjmallett * maximize POW performance. 993215976Sjmallett * 994215976Sjmallett * Also contains the QOS level priorities for each PP. 0x0 is highest priority, and 0x7 the lowest. 995215976Sjmallett * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level. 996215976Sjmallett * Priority values 0x8 through 0xe are reserved and should not be used. For a given PP, priorities 997215976Sjmallett * should begin at 0x0 and remain contiguous throughout the range. 998215976Sjmallett */ 999215976Sjmallettunion cvmx_pow_pp_grp_mskx 1000215976Sjmallett{ 1001215976Sjmallett uint64_t u64; 1002215976Sjmallett struct cvmx_pow_pp_grp_mskx_s 1003215976Sjmallett { 1004215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1005215976Sjmallett uint64_t reserved_48_63 : 16; 1006215976Sjmallett uint64_t qos7_pri : 4; /**< PPX priority for QOS level 7 */ 1007215976Sjmallett uint64_t qos6_pri : 4; /**< PPX priority for QOS level 6 */ 1008215976Sjmallett uint64_t qos5_pri : 4; /**< PPX priority for QOS level 5 */ 1009215976Sjmallett uint64_t qos4_pri : 4; /**< PPX priority for QOS level 4 */ 1010215976Sjmallett uint64_t qos3_pri : 4; /**< PPX priority for QOS level 3 */ 1011215976Sjmallett uint64_t qos2_pri : 4; /**< PPX priority for QOS level 2 */ 1012215976Sjmallett uint64_t qos1_pri : 4; /**< PPX priority for QOS level 1 */ 1013215976Sjmallett uint64_t qos0_pri : 4; /**< PPX priority for QOS level 0 */ 1014215976Sjmallett uint64_t grp_msk : 16; /**< PPX group mask */ 1015215976Sjmallett#else 1016215976Sjmallett uint64_t grp_msk : 16; 1017215976Sjmallett uint64_t qos0_pri : 4; 1018215976Sjmallett uint64_t qos1_pri : 4; 1019215976Sjmallett uint64_t qos2_pri : 4; 1020215976Sjmallett uint64_t qos3_pri : 4; 1021215976Sjmallett uint64_t qos4_pri : 4; 1022215976Sjmallett uint64_t qos5_pri : 4; 1023215976Sjmallett uint64_t qos6_pri : 4; 1024215976Sjmallett uint64_t qos7_pri : 4; 1025215976Sjmallett uint64_t reserved_48_63 : 16; 1026215976Sjmallett#endif 1027215976Sjmallett } s; 1028215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx 1029215976Sjmallett { 1030215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1031215976Sjmallett uint64_t reserved_16_63 : 48; 1032215976Sjmallett uint64_t grp_msk : 16; /**< PPX group mask */ 1033215976Sjmallett#else 1034215976Sjmallett uint64_t grp_msk : 16; 1035215976Sjmallett uint64_t reserved_16_63 : 48; 1036215976Sjmallett#endif 1037215976Sjmallett } cn30xx; 1038215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; 1039215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; 1040215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2; 1041215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn50xx; 1042215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn52xx; 1043215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn52xxp1; 1044215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn56xx; 1045215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn56xxp1; 1046215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn58xx; 1047215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn58xxp1; 1048215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn63xx; 1049215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn63xxp1; 1050215976Sjmallett}; 1051215976Sjmalletttypedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t; 1052215976Sjmallett 1053215976Sjmallett/** 1054215976Sjmallett * cvmx_pow_qos_rnd# 1055215976Sjmallett * 1056215976Sjmallett * POW_QOS_RNDX = POW QOS Issue Round Register (4 rounds per register x 8 registers = 32 rounds) 1057215976Sjmallett * 1058215976Sjmallett * Contains the round definitions for issuing new work. Each round consists of 8 bits with each bit 1059215976Sjmallett * corresponding to a QOS level. There are 4 rounds contained in each register for a total of 32 1060215976Sjmallett * rounds. The issue logic traverses through the rounds sequentially (lowest round to highest round) 1061215976Sjmallett * in an attempt to find new work for each PP. Within each round, the issue logic traverses through 1062215976Sjmallett * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a clear 1063215976Sjmallett * bit in the round mask. Note: setting a QOS level to all zeroes in all issue round registers will 1064215976Sjmallett * prevent work from being issued from that QOS level. 1065215976Sjmallett */ 1066215976Sjmallettunion cvmx_pow_qos_rndx 1067215976Sjmallett{ 1068215976Sjmallett uint64_t u64; 1069215976Sjmallett struct cvmx_pow_qos_rndx_s 1070215976Sjmallett { 1071215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1072215976Sjmallett uint64_t reserved_32_63 : 32; 1073215976Sjmallett uint64_t rnd_p3 : 8; /**< Round mask for round Xx4+3 */ 1074215976Sjmallett uint64_t rnd_p2 : 8; /**< Round mask for round Xx4+2 */ 1075215976Sjmallett uint64_t rnd_p1 : 8; /**< Round mask for round Xx4+1 */ 1076215976Sjmallett uint64_t rnd : 8; /**< Round mask for round Xx4 */ 1077215976Sjmallett#else 1078215976Sjmallett uint64_t rnd : 8; 1079215976Sjmallett uint64_t rnd_p1 : 8; 1080215976Sjmallett uint64_t rnd_p2 : 8; 1081215976Sjmallett uint64_t rnd_p3 : 8; 1082215976Sjmallett uint64_t reserved_32_63 : 32; 1083215976Sjmallett#endif 1084215976Sjmallett } s; 1085215976Sjmallett struct cvmx_pow_qos_rndx_s cn30xx; 1086215976Sjmallett struct cvmx_pow_qos_rndx_s cn31xx; 1087215976Sjmallett struct cvmx_pow_qos_rndx_s cn38xx; 1088215976Sjmallett struct cvmx_pow_qos_rndx_s cn38xxp2; 1089215976Sjmallett struct cvmx_pow_qos_rndx_s cn50xx; 1090215976Sjmallett struct cvmx_pow_qos_rndx_s cn52xx; 1091215976Sjmallett struct cvmx_pow_qos_rndx_s cn52xxp1; 1092215976Sjmallett struct cvmx_pow_qos_rndx_s cn56xx; 1093215976Sjmallett struct cvmx_pow_qos_rndx_s cn56xxp1; 1094215976Sjmallett struct cvmx_pow_qos_rndx_s cn58xx; 1095215976Sjmallett struct cvmx_pow_qos_rndx_s cn58xxp1; 1096215976Sjmallett struct cvmx_pow_qos_rndx_s cn63xx; 1097215976Sjmallett struct cvmx_pow_qos_rndx_s cn63xxp1; 1098215976Sjmallett}; 1099215976Sjmalletttypedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t; 1100215976Sjmallett 1101215976Sjmallett/** 1102215976Sjmallett * cvmx_pow_qos_thr# 1103215976Sjmallett * 1104215976Sjmallett * POW_QOS_THRX = POW QOS Threshold Register (1 per QOS level) 1105215976Sjmallett * 1106215976Sjmallett * Contains the thresholds for allocating POW internal storage buffers. If the number of remaining 1107215976Sjmallett * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers for 1108215976Sjmallett * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries 1109215976Sjmallett * will be buffered externally rather than internally. This register also contains a read-only count 1110215976Sjmallett * of the current number of free buffers (FREE_CNT), the number of internal buffers currently 1111215976Sjmallett * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list 1112215976Sjmallett * (DES_CNT) (which is not the same as the total number of de-scheduled buffers). 1113215976Sjmallett */ 1114215976Sjmallettunion cvmx_pow_qos_thrx 1115215976Sjmallett{ 1116215976Sjmallett uint64_t u64; 1117215976Sjmallett struct cvmx_pow_qos_thrx_s 1118215976Sjmallett { 1119215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1120215976Sjmallett uint64_t reserved_60_63 : 4; 1121215976Sjmallett uint64_t des_cnt : 12; /**< # of buffers on de-schedule list */ 1122215976Sjmallett uint64_t buf_cnt : 12; /**< # of internal buffers allocated to QOS level X */ 1123215976Sjmallett uint64_t free_cnt : 12; /**< # of total free buffers */ 1124215976Sjmallett uint64_t reserved_23_23 : 1; 1125215976Sjmallett uint64_t max_thr : 11; /**< Max threshold for QOS level X */ 1126215976Sjmallett uint64_t reserved_11_11 : 1; 1127215976Sjmallett uint64_t min_thr : 11; /**< Min threshold for QOS level X */ 1128215976Sjmallett#else 1129215976Sjmallett uint64_t min_thr : 11; 1130215976Sjmallett uint64_t reserved_11_11 : 1; 1131215976Sjmallett uint64_t max_thr : 11; 1132215976Sjmallett uint64_t reserved_23_23 : 1; 1133215976Sjmallett uint64_t free_cnt : 12; 1134215976Sjmallett uint64_t buf_cnt : 12; 1135215976Sjmallett uint64_t des_cnt : 12; 1136215976Sjmallett uint64_t reserved_60_63 : 4; 1137215976Sjmallett#endif 1138215976Sjmallett } s; 1139215976Sjmallett struct cvmx_pow_qos_thrx_cn30xx 1140215976Sjmallett { 1141215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1142215976Sjmallett uint64_t reserved_55_63 : 9; 1143215976Sjmallett uint64_t des_cnt : 7; /**< # of buffers on de-schedule list */ 1144215976Sjmallett uint64_t reserved_43_47 : 5; 1145215976Sjmallett uint64_t buf_cnt : 7; /**< # of internal buffers allocated to QOS level X */ 1146215976Sjmallett uint64_t reserved_31_35 : 5; 1147215976Sjmallett uint64_t free_cnt : 7; /**< # of total free buffers */ 1148215976Sjmallett uint64_t reserved_18_23 : 6; 1149215976Sjmallett uint64_t max_thr : 6; /**< Max threshold for QOS level X */ 1150215976Sjmallett uint64_t reserved_6_11 : 6; 1151215976Sjmallett uint64_t min_thr : 6; /**< Min threshold for QOS level X */ 1152215976Sjmallett#else 1153215976Sjmallett uint64_t min_thr : 6; 1154215976Sjmallett uint64_t reserved_6_11 : 6; 1155215976Sjmallett uint64_t max_thr : 6; 1156215976Sjmallett uint64_t reserved_18_23 : 6; 1157215976Sjmallett uint64_t free_cnt : 7; 1158215976Sjmallett uint64_t reserved_31_35 : 5; 1159215976Sjmallett uint64_t buf_cnt : 7; 1160215976Sjmallett uint64_t reserved_43_47 : 5; 1161215976Sjmallett uint64_t des_cnt : 7; 1162215976Sjmallett uint64_t reserved_55_63 : 9; 1163215976Sjmallett#endif 1164215976Sjmallett } cn30xx; 1165215976Sjmallett struct cvmx_pow_qos_thrx_cn31xx 1166215976Sjmallett { 1167215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1168215976Sjmallett uint64_t reserved_57_63 : 7; 1169215976Sjmallett uint64_t des_cnt : 9; /**< # of buffers on de-schedule list */ 1170215976Sjmallett uint64_t reserved_45_47 : 3; 1171215976Sjmallett uint64_t buf_cnt : 9; /**< # of internal buffers allocated to QOS level X */ 1172215976Sjmallett uint64_t reserved_33_35 : 3; 1173215976Sjmallett uint64_t free_cnt : 9; /**< # of total free buffers */ 1174215976Sjmallett uint64_t reserved_20_23 : 4; 1175215976Sjmallett uint64_t max_thr : 8; /**< Max threshold for QOS level X */ 1176215976Sjmallett uint64_t reserved_8_11 : 4; 1177215976Sjmallett uint64_t min_thr : 8; /**< Min threshold for QOS level X */ 1178215976Sjmallett#else 1179215976Sjmallett uint64_t min_thr : 8; 1180215976Sjmallett uint64_t reserved_8_11 : 4; 1181215976Sjmallett uint64_t max_thr : 8; 1182215976Sjmallett uint64_t reserved_20_23 : 4; 1183215976Sjmallett uint64_t free_cnt : 9; 1184215976Sjmallett uint64_t reserved_33_35 : 3; 1185215976Sjmallett uint64_t buf_cnt : 9; 1186215976Sjmallett uint64_t reserved_45_47 : 3; 1187215976Sjmallett uint64_t des_cnt : 9; 1188215976Sjmallett uint64_t reserved_57_63 : 7; 1189215976Sjmallett#endif 1190215976Sjmallett } cn31xx; 1191215976Sjmallett struct cvmx_pow_qos_thrx_s cn38xx; 1192215976Sjmallett struct cvmx_pow_qos_thrx_s cn38xxp2; 1193215976Sjmallett struct cvmx_pow_qos_thrx_cn31xx cn50xx; 1194215976Sjmallett struct cvmx_pow_qos_thrx_cn52xx 1195215976Sjmallett { 1196215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1197215976Sjmallett uint64_t reserved_58_63 : 6; 1198215976Sjmallett uint64_t des_cnt : 10; /**< # of buffers on de-schedule list */ 1199215976Sjmallett uint64_t reserved_46_47 : 2; 1200215976Sjmallett uint64_t buf_cnt : 10; /**< # of internal buffers allocated to QOS level X */ 1201215976Sjmallett uint64_t reserved_34_35 : 2; 1202215976Sjmallett uint64_t free_cnt : 10; /**< # of total free buffers */ 1203215976Sjmallett uint64_t reserved_21_23 : 3; 1204215976Sjmallett uint64_t max_thr : 9; /**< Max threshold for QOS level X */ 1205215976Sjmallett uint64_t reserved_9_11 : 3; 1206215976Sjmallett uint64_t min_thr : 9; /**< Min threshold for QOS level X */ 1207215976Sjmallett#else 1208215976Sjmallett uint64_t min_thr : 9; 1209215976Sjmallett uint64_t reserved_9_11 : 3; 1210215976Sjmallett uint64_t max_thr : 9; 1211215976Sjmallett uint64_t reserved_21_23 : 3; 1212215976Sjmallett uint64_t free_cnt : 10; 1213215976Sjmallett uint64_t reserved_34_35 : 2; 1214215976Sjmallett uint64_t buf_cnt : 10; 1215215976Sjmallett uint64_t reserved_46_47 : 2; 1216215976Sjmallett uint64_t des_cnt : 10; 1217215976Sjmallett uint64_t reserved_58_63 : 6; 1218215976Sjmallett#endif 1219215976Sjmallett } cn52xx; 1220215976Sjmallett struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; 1221215976Sjmallett struct cvmx_pow_qos_thrx_s cn56xx; 1222215976Sjmallett struct cvmx_pow_qos_thrx_s cn56xxp1; 1223215976Sjmallett struct cvmx_pow_qos_thrx_s cn58xx; 1224215976Sjmallett struct cvmx_pow_qos_thrx_s cn58xxp1; 1225215976Sjmallett struct cvmx_pow_qos_thrx_cn63xx 1226215976Sjmallett { 1227215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1228215976Sjmallett uint64_t reserved_59_63 : 5; 1229215976Sjmallett uint64_t des_cnt : 11; /**< # of buffers on de-schedule list */ 1230215976Sjmallett uint64_t reserved_47_47 : 1; 1231215976Sjmallett uint64_t buf_cnt : 11; /**< # of internal buffers allocated to QOS level X */ 1232215976Sjmallett uint64_t reserved_35_35 : 1; 1233215976Sjmallett uint64_t free_cnt : 11; /**< # of total free buffers */ 1234215976Sjmallett uint64_t reserved_22_23 : 2; 1235215976Sjmallett uint64_t max_thr : 10; /**< Max threshold for QOS level X */ 1236215976Sjmallett uint64_t reserved_10_11 : 2; 1237215976Sjmallett uint64_t min_thr : 10; /**< Min threshold for QOS level X */ 1238215976Sjmallett#else 1239215976Sjmallett uint64_t min_thr : 10; 1240215976Sjmallett uint64_t reserved_10_11 : 2; 1241215976Sjmallett uint64_t max_thr : 10; 1242215976Sjmallett uint64_t reserved_22_23 : 2; 1243215976Sjmallett uint64_t free_cnt : 11; 1244215976Sjmallett uint64_t reserved_35_35 : 1; 1245215976Sjmallett uint64_t buf_cnt : 11; 1246215976Sjmallett uint64_t reserved_47_47 : 1; 1247215976Sjmallett uint64_t des_cnt : 11; 1248215976Sjmallett uint64_t reserved_59_63 : 5; 1249215976Sjmallett#endif 1250215976Sjmallett } cn63xx; 1251215976Sjmallett struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; 1252215976Sjmallett}; 1253215976Sjmalletttypedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t; 1254215976Sjmallett 1255215976Sjmallett/** 1256215976Sjmallett * cvmx_pow_ts_pc 1257215976Sjmallett * 1258215976Sjmallett * POW_TS_PC = POW Tag Switch Performance Counter 1259215976Sjmallett * 1260215976Sjmallett * Counts the number of tag switch requests. Write to clear. 1261215976Sjmallett */ 1262215976Sjmallettunion cvmx_pow_ts_pc 1263215976Sjmallett{ 1264215976Sjmallett uint64_t u64; 1265215976Sjmallett struct cvmx_pow_ts_pc_s 1266215976Sjmallett { 1267215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1268215976Sjmallett uint64_t reserved_32_63 : 32; 1269215976Sjmallett uint64_t ts_pc : 32; /**< Tag switch performance counter */ 1270215976Sjmallett#else 1271215976Sjmallett uint64_t ts_pc : 32; 1272215976Sjmallett uint64_t reserved_32_63 : 32; 1273215976Sjmallett#endif 1274215976Sjmallett } s; 1275215976Sjmallett struct cvmx_pow_ts_pc_s cn30xx; 1276215976Sjmallett struct cvmx_pow_ts_pc_s cn31xx; 1277215976Sjmallett struct cvmx_pow_ts_pc_s cn38xx; 1278215976Sjmallett struct cvmx_pow_ts_pc_s cn38xxp2; 1279215976Sjmallett struct cvmx_pow_ts_pc_s cn50xx; 1280215976Sjmallett struct cvmx_pow_ts_pc_s cn52xx; 1281215976Sjmallett struct cvmx_pow_ts_pc_s cn52xxp1; 1282215976Sjmallett struct cvmx_pow_ts_pc_s cn56xx; 1283215976Sjmallett struct cvmx_pow_ts_pc_s cn56xxp1; 1284215976Sjmallett struct cvmx_pow_ts_pc_s cn58xx; 1285215976Sjmallett struct cvmx_pow_ts_pc_s cn58xxp1; 1286215976Sjmallett struct cvmx_pow_ts_pc_s cn63xx; 1287215976Sjmallett struct cvmx_pow_ts_pc_s cn63xxp1; 1288215976Sjmallett}; 1289215976Sjmalletttypedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t; 1290215976Sjmallett 1291215976Sjmallett/** 1292215976Sjmallett * cvmx_pow_wa_com_pc 1293215976Sjmallett * 1294215976Sjmallett * POW_WA_COM_PC = POW Work Add Combined Performance Counter 1295215976Sjmallett * 1296215976Sjmallett * Counts the number of add new work requests for all QOS levels. Write to clear. 1297215976Sjmallett */ 1298215976Sjmallettunion cvmx_pow_wa_com_pc 1299215976Sjmallett{ 1300215976Sjmallett uint64_t u64; 1301215976Sjmallett struct cvmx_pow_wa_com_pc_s 1302215976Sjmallett { 1303215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1304215976Sjmallett uint64_t reserved_32_63 : 32; 1305215976Sjmallett uint64_t wa_pc : 32; /**< Work add combined performance counter */ 1306215976Sjmallett#else 1307215976Sjmallett uint64_t wa_pc : 32; 1308215976Sjmallett uint64_t reserved_32_63 : 32; 1309215976Sjmallett#endif 1310215976Sjmallett } s; 1311215976Sjmallett struct cvmx_pow_wa_com_pc_s cn30xx; 1312215976Sjmallett struct cvmx_pow_wa_com_pc_s cn31xx; 1313215976Sjmallett struct cvmx_pow_wa_com_pc_s cn38xx; 1314215976Sjmallett struct cvmx_pow_wa_com_pc_s cn38xxp2; 1315215976Sjmallett struct cvmx_pow_wa_com_pc_s cn50xx; 1316215976Sjmallett struct cvmx_pow_wa_com_pc_s cn52xx; 1317215976Sjmallett struct cvmx_pow_wa_com_pc_s cn52xxp1; 1318215976Sjmallett struct cvmx_pow_wa_com_pc_s cn56xx; 1319215976Sjmallett struct cvmx_pow_wa_com_pc_s cn56xxp1; 1320215976Sjmallett struct cvmx_pow_wa_com_pc_s cn58xx; 1321215976Sjmallett struct cvmx_pow_wa_com_pc_s cn58xxp1; 1322215976Sjmallett struct cvmx_pow_wa_com_pc_s cn63xx; 1323215976Sjmallett struct cvmx_pow_wa_com_pc_s cn63xxp1; 1324215976Sjmallett}; 1325215976Sjmalletttypedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t; 1326215976Sjmallett 1327215976Sjmallett/** 1328215976Sjmallett * cvmx_pow_wa_pc# 1329215976Sjmallett * 1330215976Sjmallett * POW_WA_PCX = POW Work Add Performance Counter (1 per QOS level) 1331215976Sjmallett * 1332215976Sjmallett * Counts the number of add new work requests for each QOS level. Write to clear. 1333215976Sjmallett */ 1334215976Sjmallettunion cvmx_pow_wa_pcx 1335215976Sjmallett{ 1336215976Sjmallett uint64_t u64; 1337215976Sjmallett struct cvmx_pow_wa_pcx_s 1338215976Sjmallett { 1339215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1340215976Sjmallett uint64_t reserved_32_63 : 32; 1341215976Sjmallett uint64_t wa_pc : 32; /**< Work add performance counter for QOS level X */ 1342215976Sjmallett#else 1343215976Sjmallett uint64_t wa_pc : 32; 1344215976Sjmallett uint64_t reserved_32_63 : 32; 1345215976Sjmallett#endif 1346215976Sjmallett } s; 1347215976Sjmallett struct cvmx_pow_wa_pcx_s cn30xx; 1348215976Sjmallett struct cvmx_pow_wa_pcx_s cn31xx; 1349215976Sjmallett struct cvmx_pow_wa_pcx_s cn38xx; 1350215976Sjmallett struct cvmx_pow_wa_pcx_s cn38xxp2; 1351215976Sjmallett struct cvmx_pow_wa_pcx_s cn50xx; 1352215976Sjmallett struct cvmx_pow_wa_pcx_s cn52xx; 1353215976Sjmallett struct cvmx_pow_wa_pcx_s cn52xxp1; 1354215976Sjmallett struct cvmx_pow_wa_pcx_s cn56xx; 1355215976Sjmallett struct cvmx_pow_wa_pcx_s cn56xxp1; 1356215976Sjmallett struct cvmx_pow_wa_pcx_s cn58xx; 1357215976Sjmallett struct cvmx_pow_wa_pcx_s cn58xxp1; 1358215976Sjmallett struct cvmx_pow_wa_pcx_s cn63xx; 1359215976Sjmallett struct cvmx_pow_wa_pcx_s cn63xxp1; 1360215976Sjmallett}; 1361215976Sjmalletttypedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t; 1362215976Sjmallett 1363215976Sjmallett/** 1364215976Sjmallett * cvmx_pow_wq_int 1365215976Sjmallett * 1366215976Sjmallett * POW_WQ_INT = POW Work Queue Interrupt Register 1367215976Sjmallett * 1368215976Sjmallett * Contains the bits (1 per group) that set work queue interrupts and are used to clear these 1369215976Sjmallett * interrupts. Also contains the input queue interrupt temporary disable bits (1 per group). For 1370215976Sjmallett * more information regarding this register, see the interrupt section. 1371215976Sjmallett */ 1372215976Sjmallettunion cvmx_pow_wq_int 1373215976Sjmallett{ 1374215976Sjmallett uint64_t u64; 1375215976Sjmallett struct cvmx_pow_wq_int_s 1376215976Sjmallett { 1377215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1378215976Sjmallett uint64_t reserved_32_63 : 32; 1379215976Sjmallett uint64_t iq_dis : 16; /**< Input queue interrupt temporary disable mask 1380215976Sjmallett Corresponding WQ_INT<*> bit cannot be set due to 1381215976Sjmallett IQ_CNT/IQ_THR check when this bit is set. 1382215976Sjmallett Corresponding IQ_DIS bit is cleared by HW whenever: 1383215976Sjmallett - POW_WQ_INT_CNT*[IQ_CNT] is zero, or 1384215976Sjmallett - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic 1385215976Sjmallett counter POW_WQ_INT_PC[PC]==0 */ 1386215976Sjmallett uint64_t wq_int : 16; /**< Work queue interrupt bits 1387215976Sjmallett Corresponding WQ_INT bit is set by HW whenever: 1388215976Sjmallett - POW_WQ_INT_CNT*[IQ_CNT] >= 1389215976Sjmallett POW_WQ_INT_THR*[IQ_THR] and the threshold 1390215976Sjmallett interrupt is not disabled. 1391215976Sjmallett IQ_DIS<*>==1 disables the interrupt. 1392215976Sjmallett POW_WQ_INT_THR*[IQ_THR]==0 disables the int. 1393215976Sjmallett - POW_WQ_INT_CNT*[DS_CNT] >= 1394215976Sjmallett POW_WQ_INT_THR*[DS_THR] and the threshold 1395215976Sjmallett interrupt is not disabled 1396215976Sjmallett POW_WQ_INT_THR*[DS_THR]==0 disables the int. 1397215976Sjmallett - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic 1398215976Sjmallett counter POW_WQ_INT_PC[PC]==0 and 1399215976Sjmallett POW_WQ_INT_THR*[TC_EN]==1 and at least one of: 1400215976Sjmallett - POW_WQ_INT_CNT*[IQ_CNT] > 0 1401215976Sjmallett - POW_WQ_INT_CNT*[DS_CNT] > 0 */ 1402215976Sjmallett#else 1403215976Sjmallett uint64_t wq_int : 16; 1404215976Sjmallett uint64_t iq_dis : 16; 1405215976Sjmallett uint64_t reserved_32_63 : 32; 1406215976Sjmallett#endif 1407215976Sjmallett } s; 1408215976Sjmallett struct cvmx_pow_wq_int_s cn30xx; 1409215976Sjmallett struct cvmx_pow_wq_int_s cn31xx; 1410215976Sjmallett struct cvmx_pow_wq_int_s cn38xx; 1411215976Sjmallett struct cvmx_pow_wq_int_s cn38xxp2; 1412215976Sjmallett struct cvmx_pow_wq_int_s cn50xx; 1413215976Sjmallett struct cvmx_pow_wq_int_s cn52xx; 1414215976Sjmallett struct cvmx_pow_wq_int_s cn52xxp1; 1415215976Sjmallett struct cvmx_pow_wq_int_s cn56xx; 1416215976Sjmallett struct cvmx_pow_wq_int_s cn56xxp1; 1417215976Sjmallett struct cvmx_pow_wq_int_s cn58xx; 1418215976Sjmallett struct cvmx_pow_wq_int_s cn58xxp1; 1419215976Sjmallett struct cvmx_pow_wq_int_s cn63xx; 1420215976Sjmallett struct cvmx_pow_wq_int_s cn63xxp1; 1421215976Sjmallett}; 1422215976Sjmalletttypedef union cvmx_pow_wq_int cvmx_pow_wq_int_t; 1423215976Sjmallett 1424215976Sjmallett/** 1425215976Sjmallett * cvmx_pow_wq_int_cnt# 1426215976Sjmallett * 1427215976Sjmallett * POW_WQ_INT_CNTX = POW Work Queue Interrupt Count Register (1 per group) 1428215976Sjmallett * 1429215976Sjmallett * Contains a read-only copy of the counts used to trigger work queue interrupts. For more 1430215976Sjmallett * information regarding this register, see the interrupt section. 1431215976Sjmallett */ 1432215976Sjmallettunion cvmx_pow_wq_int_cntx 1433215976Sjmallett{ 1434215976Sjmallett uint64_t u64; 1435215976Sjmallett struct cvmx_pow_wq_int_cntx_s 1436215976Sjmallett { 1437215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1438215976Sjmallett uint64_t reserved_28_63 : 36; 1439215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1440215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1441215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1442215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1443215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1444215976Sjmallett with a 1 by SW 1445215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1446215976Sjmallett with a 1 by SW 1447215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1448215976Sjmallett - TC_CNT==1 and periodic counter 1449215976Sjmallett POW_WQ_INT_PC[PC]==0 1450215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1451215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1452215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1453215976Sjmallett uint64_t ds_cnt : 12; /**< De-schedule executable count for group X */ 1454215976Sjmallett uint64_t iq_cnt : 12; /**< Input queue executable count for group X */ 1455215976Sjmallett#else 1456215976Sjmallett uint64_t iq_cnt : 12; 1457215976Sjmallett uint64_t ds_cnt : 12; 1458215976Sjmallett uint64_t tc_cnt : 4; 1459215976Sjmallett uint64_t reserved_28_63 : 36; 1460215976Sjmallett#endif 1461215976Sjmallett } s; 1462215976Sjmallett struct cvmx_pow_wq_int_cntx_cn30xx 1463215976Sjmallett { 1464215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1465215976Sjmallett uint64_t reserved_28_63 : 36; 1466215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1467215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1468215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1469215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1470215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1471215976Sjmallett with a 1 by SW 1472215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1473215976Sjmallett with a 1 by SW 1474215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1475215976Sjmallett - TC_CNT==1 and periodic counter 1476215976Sjmallett POW_WQ_INT_PC[PC]==0 1477215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1478215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1479215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1480215976Sjmallett uint64_t reserved_19_23 : 5; 1481215976Sjmallett uint64_t ds_cnt : 7; /**< De-schedule executable count for group X */ 1482215976Sjmallett uint64_t reserved_7_11 : 5; 1483215976Sjmallett uint64_t iq_cnt : 7; /**< Input queue executable count for group X */ 1484215976Sjmallett#else 1485215976Sjmallett uint64_t iq_cnt : 7; 1486215976Sjmallett uint64_t reserved_7_11 : 5; 1487215976Sjmallett uint64_t ds_cnt : 7; 1488215976Sjmallett uint64_t reserved_19_23 : 5; 1489215976Sjmallett uint64_t tc_cnt : 4; 1490215976Sjmallett uint64_t reserved_28_63 : 36; 1491215976Sjmallett#endif 1492215976Sjmallett } cn30xx; 1493215976Sjmallett struct cvmx_pow_wq_int_cntx_cn31xx 1494215976Sjmallett { 1495215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1496215976Sjmallett uint64_t reserved_28_63 : 36; 1497215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1498215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1499215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1500215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1501215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1502215976Sjmallett with a 1 by SW 1503215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1504215976Sjmallett with a 1 by SW 1505215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1506215976Sjmallett - TC_CNT==1 and periodic counter 1507215976Sjmallett POW_WQ_INT_PC[PC]==0 1508215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1509215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1510215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1511215976Sjmallett uint64_t reserved_21_23 : 3; 1512215976Sjmallett uint64_t ds_cnt : 9; /**< De-schedule executable count for group X */ 1513215976Sjmallett uint64_t reserved_9_11 : 3; 1514215976Sjmallett uint64_t iq_cnt : 9; /**< Input queue executable count for group X */ 1515215976Sjmallett#else 1516215976Sjmallett uint64_t iq_cnt : 9; 1517215976Sjmallett uint64_t reserved_9_11 : 3; 1518215976Sjmallett uint64_t ds_cnt : 9; 1519215976Sjmallett uint64_t reserved_21_23 : 3; 1520215976Sjmallett uint64_t tc_cnt : 4; 1521215976Sjmallett uint64_t reserved_28_63 : 36; 1522215976Sjmallett#endif 1523215976Sjmallett } cn31xx; 1524215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn38xx; 1525215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn38xxp2; 1526215976Sjmallett struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; 1527215976Sjmallett struct cvmx_pow_wq_int_cntx_cn52xx 1528215976Sjmallett { 1529215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1530215976Sjmallett uint64_t reserved_28_63 : 36; 1531215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1532215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1533215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1534215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1535215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1536215976Sjmallett with a 1 by SW 1537215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1538215976Sjmallett with a 1 by SW 1539215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1540215976Sjmallett - TC_CNT==1 and periodic counter 1541215976Sjmallett POW_WQ_INT_PC[PC]==0 1542215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1543215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1544215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1545215976Sjmallett uint64_t reserved_22_23 : 2; 1546215976Sjmallett uint64_t ds_cnt : 10; /**< De-schedule executable count for group X */ 1547215976Sjmallett uint64_t reserved_10_11 : 2; 1548215976Sjmallett uint64_t iq_cnt : 10; /**< Input queue executable count for group X */ 1549215976Sjmallett#else 1550215976Sjmallett uint64_t iq_cnt : 10; 1551215976Sjmallett uint64_t reserved_10_11 : 2; 1552215976Sjmallett uint64_t ds_cnt : 10; 1553215976Sjmallett uint64_t reserved_22_23 : 2; 1554215976Sjmallett uint64_t tc_cnt : 4; 1555215976Sjmallett uint64_t reserved_28_63 : 36; 1556215976Sjmallett#endif 1557215976Sjmallett } cn52xx; 1558215976Sjmallett struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; 1559215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn56xx; 1560215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn56xxp1; 1561215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn58xx; 1562215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn58xxp1; 1563215976Sjmallett struct cvmx_pow_wq_int_cntx_cn63xx 1564215976Sjmallett { 1565215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1566215976Sjmallett uint64_t reserved_28_63 : 36; 1567215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1568215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1569215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1570215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1571215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1572215976Sjmallett with a 1 by SW 1573215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1574215976Sjmallett with a 1 by SW 1575215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1576215976Sjmallett - TC_CNT==1 and periodic counter 1577215976Sjmallett POW_WQ_INT_PC[PC]==0 1578215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1579215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1580215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1581215976Sjmallett uint64_t reserved_23_23 : 1; 1582215976Sjmallett uint64_t ds_cnt : 11; /**< De-schedule executable count for group X */ 1583215976Sjmallett uint64_t reserved_11_11 : 1; 1584215976Sjmallett uint64_t iq_cnt : 11; /**< Input queue executable count for group X */ 1585215976Sjmallett#else 1586215976Sjmallett uint64_t iq_cnt : 11; 1587215976Sjmallett uint64_t reserved_11_11 : 1; 1588215976Sjmallett uint64_t ds_cnt : 11; 1589215976Sjmallett uint64_t reserved_23_23 : 1; 1590215976Sjmallett uint64_t tc_cnt : 4; 1591215976Sjmallett uint64_t reserved_28_63 : 36; 1592215976Sjmallett#endif 1593215976Sjmallett } cn63xx; 1594215976Sjmallett struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; 1595215976Sjmallett}; 1596215976Sjmalletttypedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t; 1597215976Sjmallett 1598215976Sjmallett/** 1599215976Sjmallett * cvmx_pow_wq_int_pc 1600215976Sjmallett * 1601215976Sjmallett * POW_WQ_INT_PC = POW Work Queue Interrupt Periodic Counter Register 1602215976Sjmallett * 1603215976Sjmallett * Contains the threshold value for the work queue interrupt periodic counter and also a read-only 1604215976Sjmallett * copy of the periodic counter. For more information regarding this register, see the interrupt 1605215976Sjmallett * section. 1606215976Sjmallett */ 1607215976Sjmallettunion cvmx_pow_wq_int_pc 1608215976Sjmallett{ 1609215976Sjmallett uint64_t u64; 1610215976Sjmallett struct cvmx_pow_wq_int_pc_s 1611215976Sjmallett { 1612215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1613215976Sjmallett uint64_t reserved_60_63 : 4; 1614215976Sjmallett uint64_t pc : 28; /**< Work queue interrupt periodic counter */ 1615215976Sjmallett uint64_t reserved_28_31 : 4; 1616215976Sjmallett uint64_t pc_thr : 20; /**< Work queue interrupt periodic counter threshold */ 1617215976Sjmallett uint64_t reserved_0_7 : 8; 1618215976Sjmallett#else 1619215976Sjmallett uint64_t reserved_0_7 : 8; 1620215976Sjmallett uint64_t pc_thr : 20; 1621215976Sjmallett uint64_t reserved_28_31 : 4; 1622215976Sjmallett uint64_t pc : 28; 1623215976Sjmallett uint64_t reserved_60_63 : 4; 1624215976Sjmallett#endif 1625215976Sjmallett } s; 1626215976Sjmallett struct cvmx_pow_wq_int_pc_s cn30xx; 1627215976Sjmallett struct cvmx_pow_wq_int_pc_s cn31xx; 1628215976Sjmallett struct cvmx_pow_wq_int_pc_s cn38xx; 1629215976Sjmallett struct cvmx_pow_wq_int_pc_s cn38xxp2; 1630215976Sjmallett struct cvmx_pow_wq_int_pc_s cn50xx; 1631215976Sjmallett struct cvmx_pow_wq_int_pc_s cn52xx; 1632215976Sjmallett struct cvmx_pow_wq_int_pc_s cn52xxp1; 1633215976Sjmallett struct cvmx_pow_wq_int_pc_s cn56xx; 1634215976Sjmallett struct cvmx_pow_wq_int_pc_s cn56xxp1; 1635215976Sjmallett struct cvmx_pow_wq_int_pc_s cn58xx; 1636215976Sjmallett struct cvmx_pow_wq_int_pc_s cn58xxp1; 1637215976Sjmallett struct cvmx_pow_wq_int_pc_s cn63xx; 1638215976Sjmallett struct cvmx_pow_wq_int_pc_s cn63xxp1; 1639215976Sjmallett}; 1640215976Sjmalletttypedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t; 1641215976Sjmallett 1642215976Sjmallett/** 1643215976Sjmallett * cvmx_pow_wq_int_thr# 1644215976Sjmallett * 1645215976Sjmallett * POW_WQ_INT_THRX = POW Work Queue Interrupt Threshold Register (1 per group) 1646215976Sjmallett * 1647215976Sjmallett * Contains the thresholds for enabling and setting work queue interrupts. For more information 1648215976Sjmallett * regarding this register, see the interrupt section. 1649215976Sjmallett * 1650215976Sjmallett * Note: Up to 8 of the POW's internal storage buffers can be allocated for hardware use and are 1651215976Sjmallett * therefore not available for incoming work queue entries. Additionally, any PP that is not in the 1652215976Sjmallett * NULL_NULL state consumes a buffer. Thus in a 6 PP system, it is not advisable to set either 1653215976Sjmallett * IQ_THR or DS_THR to greater than 1024 - 8 - 6 = 1010. Doing so may prevent the interrupt from 1654215976Sjmallett * ever triggering. 1655215976Sjmallett */ 1656215976Sjmallettunion cvmx_pow_wq_int_thrx 1657215976Sjmallett{ 1658215976Sjmallett uint64_t u64; 1659215976Sjmallett struct cvmx_pow_wq_int_thrx_s 1660215976Sjmallett { 1661215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1662215976Sjmallett uint64_t reserved_29_63 : 35; 1663215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1664215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1665215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1666215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1667215976Sjmallett uint64_t reserved_23_23 : 1; 1668215976Sjmallett uint64_t ds_thr : 11; /**< De-schedule count threshold for group X 1669215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1670215976Sjmallett uint64_t reserved_11_11 : 1; 1671215976Sjmallett uint64_t iq_thr : 11; /**< Input queue count threshold for group X 1672215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1673215976Sjmallett#else 1674215976Sjmallett uint64_t iq_thr : 11; 1675215976Sjmallett uint64_t reserved_11_11 : 1; 1676215976Sjmallett uint64_t ds_thr : 11; 1677215976Sjmallett uint64_t reserved_23_23 : 1; 1678215976Sjmallett uint64_t tc_thr : 4; 1679215976Sjmallett uint64_t tc_en : 1; 1680215976Sjmallett uint64_t reserved_29_63 : 35; 1681215976Sjmallett#endif 1682215976Sjmallett } s; 1683215976Sjmallett struct cvmx_pow_wq_int_thrx_cn30xx 1684215976Sjmallett { 1685215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1686215976Sjmallett uint64_t reserved_29_63 : 35; 1687215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1688215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1689215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1690215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1691215976Sjmallett uint64_t reserved_18_23 : 6; 1692215976Sjmallett uint64_t ds_thr : 6; /**< De-schedule count threshold for group X 1693215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1694215976Sjmallett uint64_t reserved_6_11 : 6; 1695215976Sjmallett uint64_t iq_thr : 6; /**< Input queue count threshold for group X 1696215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1697215976Sjmallett#else 1698215976Sjmallett uint64_t iq_thr : 6; 1699215976Sjmallett uint64_t reserved_6_11 : 6; 1700215976Sjmallett uint64_t ds_thr : 6; 1701215976Sjmallett uint64_t reserved_18_23 : 6; 1702215976Sjmallett uint64_t tc_thr : 4; 1703215976Sjmallett uint64_t tc_en : 1; 1704215976Sjmallett uint64_t reserved_29_63 : 35; 1705215976Sjmallett#endif 1706215976Sjmallett } cn30xx; 1707215976Sjmallett struct cvmx_pow_wq_int_thrx_cn31xx 1708215976Sjmallett { 1709215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1710215976Sjmallett uint64_t reserved_29_63 : 35; 1711215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1712215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1713215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1714215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1715215976Sjmallett uint64_t reserved_20_23 : 4; 1716215976Sjmallett uint64_t ds_thr : 8; /**< De-schedule count threshold for group X 1717215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1718215976Sjmallett uint64_t reserved_8_11 : 4; 1719215976Sjmallett uint64_t iq_thr : 8; /**< Input queue count threshold for group X 1720215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1721215976Sjmallett#else 1722215976Sjmallett uint64_t iq_thr : 8; 1723215976Sjmallett uint64_t reserved_8_11 : 4; 1724215976Sjmallett uint64_t ds_thr : 8; 1725215976Sjmallett uint64_t reserved_20_23 : 4; 1726215976Sjmallett uint64_t tc_thr : 4; 1727215976Sjmallett uint64_t tc_en : 1; 1728215976Sjmallett uint64_t reserved_29_63 : 35; 1729215976Sjmallett#endif 1730215976Sjmallett } cn31xx; 1731215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn38xx; 1732215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn38xxp2; 1733215976Sjmallett struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; 1734215976Sjmallett struct cvmx_pow_wq_int_thrx_cn52xx 1735215976Sjmallett { 1736215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1737215976Sjmallett uint64_t reserved_29_63 : 35; 1738215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1739215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1740215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1741215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1742215976Sjmallett uint64_t reserved_21_23 : 3; 1743215976Sjmallett uint64_t ds_thr : 9; /**< De-schedule count threshold for group X 1744215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1745215976Sjmallett uint64_t reserved_9_11 : 3; 1746215976Sjmallett uint64_t iq_thr : 9; /**< Input queue count threshold for group X 1747215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1748215976Sjmallett#else 1749215976Sjmallett uint64_t iq_thr : 9; 1750215976Sjmallett uint64_t reserved_9_11 : 3; 1751215976Sjmallett uint64_t ds_thr : 9; 1752215976Sjmallett uint64_t reserved_21_23 : 3; 1753215976Sjmallett uint64_t tc_thr : 4; 1754215976Sjmallett uint64_t tc_en : 1; 1755215976Sjmallett uint64_t reserved_29_63 : 35; 1756215976Sjmallett#endif 1757215976Sjmallett } cn52xx; 1758215976Sjmallett struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; 1759215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn56xx; 1760215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn56xxp1; 1761215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn58xx; 1762215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn58xxp1; 1763215976Sjmallett struct cvmx_pow_wq_int_thrx_cn63xx 1764215976Sjmallett { 1765215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1766215976Sjmallett uint64_t reserved_29_63 : 35; 1767215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1768215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1769215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1770215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1771215976Sjmallett uint64_t reserved_22_23 : 2; 1772215976Sjmallett uint64_t ds_thr : 10; /**< De-schedule count threshold for group X 1773215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1774215976Sjmallett uint64_t reserved_10_11 : 2; 1775215976Sjmallett uint64_t iq_thr : 10; /**< Input queue count threshold for group X 1776215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1777215976Sjmallett#else 1778215976Sjmallett uint64_t iq_thr : 10; 1779215976Sjmallett uint64_t reserved_10_11 : 2; 1780215976Sjmallett uint64_t ds_thr : 10; 1781215976Sjmallett uint64_t reserved_22_23 : 2; 1782215976Sjmallett uint64_t tc_thr : 4; 1783215976Sjmallett uint64_t tc_en : 1; 1784215976Sjmallett uint64_t reserved_29_63 : 35; 1785215976Sjmallett#endif 1786215976Sjmallett } cn63xx; 1787215976Sjmallett struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; 1788215976Sjmallett}; 1789215976Sjmalletttypedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t; 1790215976Sjmallett 1791215976Sjmallett/** 1792215976Sjmallett * cvmx_pow_ws_pc# 1793215976Sjmallett * 1794215976Sjmallett * POW_WS_PCX = POW Work Schedule Performance Counter (1 per group) 1795215976Sjmallett * 1796215976Sjmallett * Counts the number of work schedules for each group. Write to clear. 1797215976Sjmallett */ 1798215976Sjmallettunion cvmx_pow_ws_pcx 1799215976Sjmallett{ 1800215976Sjmallett uint64_t u64; 1801215976Sjmallett struct cvmx_pow_ws_pcx_s 1802215976Sjmallett { 1803215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1804215976Sjmallett uint64_t reserved_32_63 : 32; 1805215976Sjmallett uint64_t ws_pc : 32; /**< Work schedule performance counter for group X */ 1806215976Sjmallett#else 1807215976Sjmallett uint64_t ws_pc : 32; 1808215976Sjmallett uint64_t reserved_32_63 : 32; 1809215976Sjmallett#endif 1810215976Sjmallett } s; 1811215976Sjmallett struct cvmx_pow_ws_pcx_s cn30xx; 1812215976Sjmallett struct cvmx_pow_ws_pcx_s cn31xx; 1813215976Sjmallett struct cvmx_pow_ws_pcx_s cn38xx; 1814215976Sjmallett struct cvmx_pow_ws_pcx_s cn38xxp2; 1815215976Sjmallett struct cvmx_pow_ws_pcx_s cn50xx; 1816215976Sjmallett struct cvmx_pow_ws_pcx_s cn52xx; 1817215976Sjmallett struct cvmx_pow_ws_pcx_s cn52xxp1; 1818215976Sjmallett struct cvmx_pow_ws_pcx_s cn56xx; 1819215976Sjmallett struct cvmx_pow_ws_pcx_s cn56xxp1; 1820215976Sjmallett struct cvmx_pow_ws_pcx_s cn58xx; 1821215976Sjmallett struct cvmx_pow_ws_pcx_s cn58xxp1; 1822215976Sjmallett struct cvmx_pow_ws_pcx_s cn63xx; 1823215976Sjmallett struct cvmx_pow_ws_pcx_s cn63xxp1; 1824215976Sjmallett}; 1825215976Sjmalletttypedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t; 1826215976Sjmallett 1827215976Sjmallett#endif 1828