1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pescx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pescx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_PESCX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_PESCX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 61215976Sjmallett cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 62215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 73215976Sjmallett cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 84215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 85215976Sjmallett cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id); 86215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull; 87215976Sjmallett} 88215976Sjmallett#else 89215976Sjmallett#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 96215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 97215976Sjmallett cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id); 98215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 109215976Sjmallett cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 121215976Sjmallett cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 122215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull; 123215976Sjmallett} 124215976Sjmallett#else 125215976Sjmallett#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull) 126215976Sjmallett#endif 127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128215976Sjmallettstatic inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id) 129215976Sjmallett{ 130215976Sjmallett if (!( 131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 132215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 133215976Sjmallett cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id); 134215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull; 135215976Sjmallett} 136215976Sjmallett#else 137215976Sjmallett#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull) 138215976Sjmallett#endif 139215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140215976Sjmallettstatic inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id) 141215976Sjmallett{ 142215976Sjmallett if (!( 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 145215976Sjmallett cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id); 146215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id) 153215976Sjmallett{ 154215976Sjmallett if (!( 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 156215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 157215976Sjmallett cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id); 158215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull; 159215976Sjmallett} 160215976Sjmallett#else 161215976Sjmallett#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallettstatic inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id) 165215976Sjmallett{ 166215976Sjmallett if (!( 167215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 168215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 169215976Sjmallett cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 181215976Sjmallett cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull; 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 192215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 193215976Sjmallett cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id); 194215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull; 195215976Sjmallett} 196215976Sjmallett#else 197215976Sjmallett#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull) 198215976Sjmallett#endif 199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200215976Sjmallettstatic inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id) 201215976Sjmallett{ 202215976Sjmallett if (!( 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 205215976Sjmallett cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))))) 217215976Sjmallett cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id); 218215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16; 219215976Sjmallett} 220215976Sjmallett#else 221215976Sjmallett#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 222215976Sjmallett#endif 223215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224215976Sjmallettstatic inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id) 225215976Sjmallett{ 226215976Sjmallett if (!( 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))))) 229215976Sjmallett cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 241215976Sjmallett cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 242215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull; 243215976Sjmallett} 244215976Sjmallett#else 245215976Sjmallett#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull) 246215976Sjmallett#endif 247215976Sjmallett 248215976Sjmallett/** 249215976Sjmallett * cvmx_pesc#_bist_status 250215976Sjmallett * 251215976Sjmallett * PESC_BIST_STATUS = PESC Bist Status 252215976Sjmallett * 253215976Sjmallett * Contains the diffrent interrupt summary bits of the PESC. 254215976Sjmallett */ 255215976Sjmallettunion cvmx_pescx_bist_status 256215976Sjmallett{ 257215976Sjmallett uint64_t u64; 258215976Sjmallett struct cvmx_pescx_bist_status_s 259215976Sjmallett { 260215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 261215976Sjmallett uint64_t reserved_13_63 : 51; 262215976Sjmallett uint64_t rqdata5 : 1; /**< Rx Queue Data Memory5. */ 263215976Sjmallett uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */ 264215976Sjmallett uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */ 265215976Sjmallett uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */ 266215976Sjmallett uint64_t retry : 1; /**< Retry Buffer. */ 267215976Sjmallett uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 268215976Sjmallett uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 269215976Sjmallett uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 270215976Sjmallett uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 271215976Sjmallett uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */ 272215976Sjmallett uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 273215976Sjmallett uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 274215976Sjmallett uint64_t sot : 1; /**< SOT Buffer. */ 275215976Sjmallett#else 276215976Sjmallett uint64_t sot : 1; 277215976Sjmallett uint64_t rqhdr0 : 1; 278215976Sjmallett uint64_t rqhdr1 : 1; 279215976Sjmallett uint64_t rqdata4 : 1; 280215976Sjmallett uint64_t rqdata3 : 1; 281215976Sjmallett uint64_t rqdata2 : 1; 282215976Sjmallett uint64_t rqdata1 : 1; 283215976Sjmallett uint64_t rqdata0 : 1; 284215976Sjmallett uint64_t retry : 1; 285215976Sjmallett uint64_t ptlp_or : 1; 286215976Sjmallett uint64_t ntlp_or : 1; 287215976Sjmallett uint64_t ctlp_or : 1; 288215976Sjmallett uint64_t rqdata5 : 1; 289215976Sjmallett uint64_t reserved_13_63 : 51; 290215976Sjmallett#endif 291215976Sjmallett } s; 292215976Sjmallett struct cvmx_pescx_bist_status_s cn52xx; 293215976Sjmallett struct cvmx_pescx_bist_status_cn52xxp1 294215976Sjmallett { 295215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 296215976Sjmallett uint64_t reserved_12_63 : 52; 297215976Sjmallett uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */ 298215976Sjmallett uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */ 299215976Sjmallett uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */ 300215976Sjmallett uint64_t retry : 1; /**< Retry Buffer. */ 301215976Sjmallett uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 302215976Sjmallett uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 303215976Sjmallett uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 304215976Sjmallett uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 305215976Sjmallett uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */ 306215976Sjmallett uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 307215976Sjmallett uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 308215976Sjmallett uint64_t sot : 1; /**< SOT Buffer. */ 309215976Sjmallett#else 310215976Sjmallett uint64_t sot : 1; 311215976Sjmallett uint64_t rqhdr0 : 1; 312215976Sjmallett uint64_t rqhdr1 : 1; 313215976Sjmallett uint64_t rqdata4 : 1; 314215976Sjmallett uint64_t rqdata3 : 1; 315215976Sjmallett uint64_t rqdata2 : 1; 316215976Sjmallett uint64_t rqdata1 : 1; 317215976Sjmallett uint64_t rqdata0 : 1; 318215976Sjmallett uint64_t retry : 1; 319215976Sjmallett uint64_t ptlp_or : 1; 320215976Sjmallett uint64_t ntlp_or : 1; 321215976Sjmallett uint64_t ctlp_or : 1; 322215976Sjmallett uint64_t reserved_12_63 : 52; 323215976Sjmallett#endif 324215976Sjmallett } cn52xxp1; 325215976Sjmallett struct cvmx_pescx_bist_status_s cn56xx; 326215976Sjmallett struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; 327215976Sjmallett}; 328215976Sjmalletttypedef union cvmx_pescx_bist_status cvmx_pescx_bist_status_t; 329215976Sjmallett 330215976Sjmallett/** 331215976Sjmallett * cvmx_pesc#_bist_status2 332215976Sjmallett * 333215976Sjmallett * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register 334215976Sjmallett * 335215976Sjmallett * Results from BIST runs of PESC's memories. 336215976Sjmallett */ 337215976Sjmallettunion cvmx_pescx_bist_status2 338215976Sjmallett{ 339215976Sjmallett uint64_t u64; 340215976Sjmallett struct cvmx_pescx_bist_status2_s 341215976Sjmallett { 342215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 343215976Sjmallett uint64_t reserved_14_63 : 50; 344215976Sjmallett uint64_t cto_p2e : 1; /**< BIST Status for the cto_p2e_fifo */ 345215976Sjmallett uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */ 346215976Sjmallett uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */ 347215976Sjmallett uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */ 348215976Sjmallett uint64_t e2p_rsl : 1; /**< BIST Status for the e2p_rsl__fifo */ 349215976Sjmallett uint64_t dbg_p2e : 1; /**< BIST Status for the dbg_p2e_fifo */ 350215976Sjmallett uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */ 351215976Sjmallett uint64_t rsl_p2e : 1; /**< BIST Status for the rsl_p2e_fifo */ 352215976Sjmallett uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */ 353215976Sjmallett uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */ 354215976Sjmallett uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */ 355215976Sjmallett uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */ 356215976Sjmallett uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */ 357215976Sjmallett uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */ 358215976Sjmallett#else 359215976Sjmallett uint64_t ppf : 1; 360215976Sjmallett uint64_t pef_tc0 : 1; 361215976Sjmallett uint64_t pef_tcf1 : 1; 362215976Sjmallett uint64_t pef_tnf : 1; 363215976Sjmallett uint64_t pef_tpf0 : 1; 364215976Sjmallett uint64_t pef_tpf1 : 1; 365215976Sjmallett uint64_t rsl_p2e : 1; 366215976Sjmallett uint64_t peai_p2e : 1; 367215976Sjmallett uint64_t dbg_p2e : 1; 368215976Sjmallett uint64_t e2p_rsl : 1; 369215976Sjmallett uint64_t e2p_p : 1; 370215976Sjmallett uint64_t e2p_n : 1; 371215976Sjmallett uint64_t e2p_cpl : 1; 372215976Sjmallett uint64_t cto_p2e : 1; 373215976Sjmallett uint64_t reserved_14_63 : 50; 374215976Sjmallett#endif 375215976Sjmallett } s; 376215976Sjmallett struct cvmx_pescx_bist_status2_s cn52xx; 377215976Sjmallett struct cvmx_pescx_bist_status2_s cn52xxp1; 378215976Sjmallett struct cvmx_pescx_bist_status2_s cn56xx; 379215976Sjmallett struct cvmx_pescx_bist_status2_s cn56xxp1; 380215976Sjmallett}; 381215976Sjmalletttypedef union cvmx_pescx_bist_status2 cvmx_pescx_bist_status2_t; 382215976Sjmallett 383215976Sjmallett/** 384215976Sjmallett * cvmx_pesc#_cfg_rd 385215976Sjmallett * 386215976Sjmallett * PESC_CFG_RD = PESC Configuration Read 387215976Sjmallett * 388215976Sjmallett * Allows read access to the configuration in the PCIe Core. 389215976Sjmallett */ 390215976Sjmallettunion cvmx_pescx_cfg_rd 391215976Sjmallett{ 392215976Sjmallett uint64_t u64; 393215976Sjmallett struct cvmx_pescx_cfg_rd_s 394215976Sjmallett { 395215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 396215976Sjmallett uint64_t data : 32; /**< Data. */ 397215976Sjmallett uint64_t addr : 32; /**< Address to read. A write to this register 398215976Sjmallett starts a read operation. */ 399215976Sjmallett#else 400215976Sjmallett uint64_t addr : 32; 401215976Sjmallett uint64_t data : 32; 402215976Sjmallett#endif 403215976Sjmallett } s; 404215976Sjmallett struct cvmx_pescx_cfg_rd_s cn52xx; 405215976Sjmallett struct cvmx_pescx_cfg_rd_s cn52xxp1; 406215976Sjmallett struct cvmx_pescx_cfg_rd_s cn56xx; 407215976Sjmallett struct cvmx_pescx_cfg_rd_s cn56xxp1; 408215976Sjmallett}; 409215976Sjmalletttypedef union cvmx_pescx_cfg_rd cvmx_pescx_cfg_rd_t; 410215976Sjmallett 411215976Sjmallett/** 412215976Sjmallett * cvmx_pesc#_cfg_wr 413215976Sjmallett * 414215976Sjmallett * PESC_CFG_WR = PESC Configuration Write 415215976Sjmallett * 416215976Sjmallett * Allows write access to the configuration in the PCIe Core. 417215976Sjmallett */ 418215976Sjmallettunion cvmx_pescx_cfg_wr 419215976Sjmallett{ 420215976Sjmallett uint64_t u64; 421215976Sjmallett struct cvmx_pescx_cfg_wr_s 422215976Sjmallett { 423215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 424215976Sjmallett uint64_t data : 32; /**< Data to write. A write to this register starts 425215976Sjmallett a write operation. */ 426215976Sjmallett uint64_t addr : 32; /**< Address to write. A write to this register starts 427215976Sjmallett a write operation. */ 428215976Sjmallett#else 429215976Sjmallett uint64_t addr : 32; 430215976Sjmallett uint64_t data : 32; 431215976Sjmallett#endif 432215976Sjmallett } s; 433215976Sjmallett struct cvmx_pescx_cfg_wr_s cn52xx; 434215976Sjmallett struct cvmx_pescx_cfg_wr_s cn52xxp1; 435215976Sjmallett struct cvmx_pescx_cfg_wr_s cn56xx; 436215976Sjmallett struct cvmx_pescx_cfg_wr_s cn56xxp1; 437215976Sjmallett}; 438215976Sjmalletttypedef union cvmx_pescx_cfg_wr cvmx_pescx_cfg_wr_t; 439215976Sjmallett 440215976Sjmallett/** 441215976Sjmallett * cvmx_pesc#_cpl_lut_valid 442215976Sjmallett * 443215976Sjmallett * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid 444215976Sjmallett * 445215976Sjmallett * Bit set for outstanding tag read. 446215976Sjmallett */ 447215976Sjmallettunion cvmx_pescx_cpl_lut_valid 448215976Sjmallett{ 449215976Sjmallett uint64_t u64; 450215976Sjmallett struct cvmx_pescx_cpl_lut_valid_s 451215976Sjmallett { 452215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 453215976Sjmallett uint64_t reserved_32_63 : 32; 454215976Sjmallett uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag 455215976Sjmallett expecting a completion. */ 456215976Sjmallett#else 457215976Sjmallett uint64_t tag : 32; 458215976Sjmallett uint64_t reserved_32_63 : 32; 459215976Sjmallett#endif 460215976Sjmallett } s; 461215976Sjmallett struct cvmx_pescx_cpl_lut_valid_s cn52xx; 462215976Sjmallett struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; 463215976Sjmallett struct cvmx_pescx_cpl_lut_valid_s cn56xx; 464215976Sjmallett struct cvmx_pescx_cpl_lut_valid_s cn56xxp1; 465215976Sjmallett}; 466215976Sjmalletttypedef union cvmx_pescx_cpl_lut_valid cvmx_pescx_cpl_lut_valid_t; 467215976Sjmallett 468215976Sjmallett/** 469215976Sjmallett * cvmx_pesc#_ctl_status 470215976Sjmallett * 471215976Sjmallett * PESC_CTL_STATUS = PESC Control Status 472215976Sjmallett * 473215976Sjmallett * General control and status of the PESC. 474215976Sjmallett */ 475215976Sjmallettunion cvmx_pescx_ctl_status 476215976Sjmallett{ 477215976Sjmallett uint64_t u64; 478215976Sjmallett struct cvmx_pescx_ctl_status_s 479215976Sjmallett { 480215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 481215976Sjmallett uint64_t reserved_28_63 : 36; 482215976Sjmallett uint64_t dnum : 5; /**< Primary bus device number. */ 483215976Sjmallett uint64_t pbus : 8; /**< Primary bus number. */ 484215976Sjmallett uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */ 485215976Sjmallett uint64_t lane_swp : 1; /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1' 486215976Sjmallett enables LANE SWAP. THis bit has no effect on PEDC0. 487215976Sjmallett This bit should be set before enabling PEDC1. */ 488215976Sjmallett uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 489215976Sjmallett to the PCIe core pm_xmt_turnoff port. RC mode. */ 490215976Sjmallett uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 491215976Sjmallett to the PCIe core pm_xmt_pme port. EP mode. */ 492215976Sjmallett uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 493215976Sjmallett to the PCIe core outband_pwrup_cmd port. EP mode. */ 494215976Sjmallett uint64_t reserved_7_8 : 2; 495215976Sjmallett uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 496215976Sjmallett uint64_t dly_one : 1; /**< When set the output client state machines will 497215976Sjmallett wait one cycle before starting a new TLP out. */ 498215976Sjmallett uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 499215976Sjmallett link is disabled. This bit only is active when in 500215976Sjmallett RC mode. */ 501215976Sjmallett uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 502215976Sjmallett not wait for P-TLPs that normaly would be sent 503215976Sjmallett first. */ 504215976Sjmallett uint64_t reserved_2_2 : 1; 505215976Sjmallett uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 506215976Sjmallett uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 507215976Sjmallett#else 508215976Sjmallett uint64_t inv_lcrc : 1; 509215976Sjmallett uint64_t inv_ecrc : 1; 510215976Sjmallett uint64_t reserved_2_2 : 1; 511215976Sjmallett uint64_t ro_ctlp : 1; 512215976Sjmallett uint64_t lnk_enb : 1; 513215976Sjmallett uint64_t dly_one : 1; 514215976Sjmallett uint64_t nf_ecrc : 1; 515215976Sjmallett uint64_t reserved_7_8 : 2; 516215976Sjmallett uint64_t ob_p_cmd : 1; 517215976Sjmallett uint64_t pm_xpme : 1; 518215976Sjmallett uint64_t pm_xtoff : 1; 519215976Sjmallett uint64_t lane_swp : 1; 520215976Sjmallett uint64_t qlm_cfg : 2; 521215976Sjmallett uint64_t pbus : 8; 522215976Sjmallett uint64_t dnum : 5; 523215976Sjmallett uint64_t reserved_28_63 : 36; 524215976Sjmallett#endif 525215976Sjmallett } s; 526215976Sjmallett struct cvmx_pescx_ctl_status_s cn52xx; 527215976Sjmallett struct cvmx_pescx_ctl_status_s cn52xxp1; 528215976Sjmallett struct cvmx_pescx_ctl_status_cn56xx 529215976Sjmallett { 530215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 531215976Sjmallett uint64_t reserved_28_63 : 36; 532215976Sjmallett uint64_t dnum : 5; /**< Primary bus device number. */ 533215976Sjmallett uint64_t pbus : 8; /**< Primary bus number. */ 534215976Sjmallett uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */ 535215976Sjmallett uint64_t reserved_12_12 : 1; 536215976Sjmallett uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 537215976Sjmallett to the PCIe core pm_xmt_turnoff port. RC mode. */ 538215976Sjmallett uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 539215976Sjmallett to the PCIe core pm_xmt_pme port. EP mode. */ 540215976Sjmallett uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 541215976Sjmallett to the PCIe core outband_pwrup_cmd port. EP mode. */ 542215976Sjmallett uint64_t reserved_7_8 : 2; 543215976Sjmallett uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 544215976Sjmallett uint64_t dly_one : 1; /**< When set the output client state machines will 545215976Sjmallett wait one cycle before starting a new TLP out. */ 546215976Sjmallett uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 547215976Sjmallett link is disabled. This bit only is active when in 548215976Sjmallett RC mode. */ 549215976Sjmallett uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 550215976Sjmallett not wait for P-TLPs that normaly would be sent 551215976Sjmallett first. */ 552215976Sjmallett uint64_t reserved_2_2 : 1; 553215976Sjmallett uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 554215976Sjmallett uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 555215976Sjmallett#else 556215976Sjmallett uint64_t inv_lcrc : 1; 557215976Sjmallett uint64_t inv_ecrc : 1; 558215976Sjmallett uint64_t reserved_2_2 : 1; 559215976Sjmallett uint64_t ro_ctlp : 1; 560215976Sjmallett uint64_t lnk_enb : 1; 561215976Sjmallett uint64_t dly_one : 1; 562215976Sjmallett uint64_t nf_ecrc : 1; 563215976Sjmallett uint64_t reserved_7_8 : 2; 564215976Sjmallett uint64_t ob_p_cmd : 1; 565215976Sjmallett uint64_t pm_xpme : 1; 566215976Sjmallett uint64_t pm_xtoff : 1; 567215976Sjmallett uint64_t reserved_12_12 : 1; 568215976Sjmallett uint64_t qlm_cfg : 2; 569215976Sjmallett uint64_t pbus : 8; 570215976Sjmallett uint64_t dnum : 5; 571215976Sjmallett uint64_t reserved_28_63 : 36; 572215976Sjmallett#endif 573215976Sjmallett } cn56xx; 574215976Sjmallett struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; 575215976Sjmallett}; 576215976Sjmalletttypedef union cvmx_pescx_ctl_status cvmx_pescx_ctl_status_t; 577215976Sjmallett 578215976Sjmallett/** 579215976Sjmallett * cvmx_pesc#_ctl_status2 580215976Sjmallett * 581215976Sjmallett * Below are in PESC 582215976Sjmallett * 583215976Sjmallett * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register 584215976Sjmallett * 585215976Sjmallett * Results from BIST runs of PESC's memories. 586215976Sjmallett */ 587215976Sjmallettunion cvmx_pescx_ctl_status2 588215976Sjmallett{ 589215976Sjmallett uint64_t u64; 590215976Sjmallett struct cvmx_pescx_ctl_status2_s 591215976Sjmallett { 592215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 593215976Sjmallett uint64_t reserved_2_63 : 62; 594215976Sjmallett uint64_t pclk_run : 1; /**< When the pce_clk is running this bit will be '1'. 595215976Sjmallett Writing a '1' to this location will cause the 596215976Sjmallett bit to be cleared, but if the pce_clk is running 597215976Sjmallett this bit will be re-set. */ 598215976Sjmallett uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */ 599215976Sjmallett#else 600215976Sjmallett uint64_t pcierst : 1; 601215976Sjmallett uint64_t pclk_run : 1; 602215976Sjmallett uint64_t reserved_2_63 : 62; 603215976Sjmallett#endif 604215976Sjmallett } s; 605215976Sjmallett struct cvmx_pescx_ctl_status2_s cn52xx; 606215976Sjmallett struct cvmx_pescx_ctl_status2_cn52xxp1 607215976Sjmallett { 608215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 609215976Sjmallett uint64_t reserved_1_63 : 63; 610215976Sjmallett uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */ 611215976Sjmallett#else 612215976Sjmallett uint64_t pcierst : 1; 613215976Sjmallett uint64_t reserved_1_63 : 63; 614215976Sjmallett#endif 615215976Sjmallett } cn52xxp1; 616215976Sjmallett struct cvmx_pescx_ctl_status2_s cn56xx; 617215976Sjmallett struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; 618215976Sjmallett}; 619215976Sjmalletttypedef union cvmx_pescx_ctl_status2 cvmx_pescx_ctl_status2_t; 620215976Sjmallett 621215976Sjmallett/** 622215976Sjmallett * cvmx_pesc#_dbg_info 623215976Sjmallett * 624215976Sjmallett * PESC(0..1)_DBG_INFO = PESC Debug Information 625215976Sjmallett * 626215976Sjmallett * General debug info. 627215976Sjmallett */ 628215976Sjmallettunion cvmx_pescx_dbg_info 629215976Sjmallett{ 630215976Sjmallett uint64_t u64; 631215976Sjmallett struct cvmx_pescx_dbg_info_s 632215976Sjmallett { 633215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 634215976Sjmallett uint64_t reserved_31_63 : 33; 635215976Sjmallett uint64_t ecrc_e : 1; /**< Received a ECRC error. 636215976Sjmallett radm_ecrc_err */ 637215976Sjmallett uint64_t rawwpp : 1; /**< Received a write with poisoned payload 638215976Sjmallett radm_rcvd_wreq_poisoned */ 639215976Sjmallett uint64_t racpp : 1; /**< Received a completion with poisoned payload 640215976Sjmallett radm_rcvd_cpl_poisoned */ 641215976Sjmallett uint64_t ramtlp : 1; /**< Received a malformed TLP 642215976Sjmallett radm_mlf_tlp_err */ 643215976Sjmallett uint64_t rarwdns : 1; /**< Recieved a request which device does not support 644215976Sjmallett radm_rcvd_ur_req */ 645215976Sjmallett uint64_t caar : 1; /**< Completer aborted a request 646215976Sjmallett radm_rcvd_ca_req 647215976Sjmallett This bit will never be set because Octeon does 648215976Sjmallett not generate Completer Aborts. */ 649215976Sjmallett uint64_t racca : 1; /**< Received a completion with CA status 650215976Sjmallett radm_rcvd_cpl_ca */ 651215976Sjmallett uint64_t racur : 1; /**< Received a completion with UR status 652215976Sjmallett radm_rcvd_cpl_ur */ 653215976Sjmallett uint64_t rauc : 1; /**< Received an unexpected completion 654215976Sjmallett radm_unexp_cpl_err */ 655215976Sjmallett uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when 656215976Sjmallett flow control advertisements are ignored 657215976Sjmallett radm_qoverflow */ 658215976Sjmallett uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks) 659215976Sjmallett int_xadm_fc_prot_err */ 660215976Sjmallett uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error 661215976Sjmallett (RxStatus = 3b100) or disparity error 662215976Sjmallett (RxStatus = 3b111), the signal rmlh_rcvd_err will 663215976Sjmallett be asserted. 664215976Sjmallett rmlh_rcvd_err */ 665215976Sjmallett uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer) 666215976Sjmallett rtlh_fc_prot_err */ 667215976Sjmallett uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP) 668215976Sjmallett rdlh_prot_err */ 669215976Sjmallett uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error 670215976Sjmallett rdlh_bad_tlp_err */ 671215976Sjmallett uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error 672215976Sjmallett rdlh_bad_dllp_err */ 673215976Sjmallett uint64_t mre : 1; /**< Max Retries Exceeded 674215976Sjmallett xdlh_replay_num_rlover_err */ 675215976Sjmallett uint64_t rte : 1; /**< Replay Timer Expired 676215976Sjmallett xdlh_replay_timeout_err 677215976Sjmallett This bit is set when the REPLAY_TIMER expires in 678215976Sjmallett the PCIE core. The probability of this bit being 679215976Sjmallett set will increase with the traffic load. */ 680215976Sjmallett uint64_t acto : 1; /**< A Completion Timeout Occured 681215976Sjmallett pedc_radm_cpl_timeout */ 682215976Sjmallett uint64_t rvdm : 1; /**< Received Vendor-Defined Message 683215976Sjmallett pedc_radm_vendor_msg */ 684215976Sjmallett uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only) 685215976Sjmallett pedc_radm_msg_unlock */ 686215976Sjmallett uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message 687215976Sjmallett (RC Mode only) 688215976Sjmallett pedc_radm_pm_to_ack */ 689215976Sjmallett uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only) 690215976Sjmallett pedc_radm_pm_pme */ 691215976Sjmallett uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only) 692215976Sjmallett pedc_radm_fatal_err 693215976Sjmallett Bit set when a message with ERR_FATAL is set. */ 694215976Sjmallett uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only) 695215976Sjmallett pedc_radm_nonfatal_err */ 696215976Sjmallett uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only) 697215976Sjmallett pedc_radm_correctable_err */ 698215976Sjmallett uint64_t rpoison : 1; /**< Received Poisoned TLP 699215976Sjmallett pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */ 700215976Sjmallett uint64_t recrce : 1; /**< Received ECRC Error 701215976Sjmallett pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */ 702215976Sjmallett uint64_t rtlplle : 1; /**< Received TLP has link layer error 703215976Sjmallett pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */ 704215976Sjmallett uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message. 705215976Sjmallett pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot 706215976Sjmallett If the core receives a MSG (or Vendor Message) 707215976Sjmallett this bit will be set. */ 708215976Sjmallett uint64_t spoison : 1; /**< Poisoned TLP sent 709215976Sjmallett peai__client0_tlp_ep & peai__client0_tlp_hv */ 710215976Sjmallett#else 711215976Sjmallett uint64_t spoison : 1; 712215976Sjmallett uint64_t rtlpmal : 1; 713215976Sjmallett uint64_t rtlplle : 1; 714215976Sjmallett uint64_t recrce : 1; 715215976Sjmallett uint64_t rpoison : 1; 716215976Sjmallett uint64_t rcemrc : 1; 717215976Sjmallett uint64_t rnfemrc : 1; 718215976Sjmallett uint64_t rfemrc : 1; 719215976Sjmallett uint64_t rpmerc : 1; 720215976Sjmallett uint64_t rptamrc : 1; 721215976Sjmallett uint64_t rumep : 1; 722215976Sjmallett uint64_t rvdm : 1; 723215976Sjmallett uint64_t acto : 1; 724215976Sjmallett uint64_t rte : 1; 725215976Sjmallett uint64_t mre : 1; 726215976Sjmallett uint64_t rdwdle : 1; 727215976Sjmallett uint64_t rtwdle : 1; 728215976Sjmallett uint64_t dpeoosd : 1; 729215976Sjmallett uint64_t fcpvwt : 1; 730215976Sjmallett uint64_t rpe : 1; 731215976Sjmallett uint64_t fcuv : 1; 732215976Sjmallett uint64_t rqo : 1; 733215976Sjmallett uint64_t rauc : 1; 734215976Sjmallett uint64_t racur : 1; 735215976Sjmallett uint64_t racca : 1; 736215976Sjmallett uint64_t caar : 1; 737215976Sjmallett uint64_t rarwdns : 1; 738215976Sjmallett uint64_t ramtlp : 1; 739215976Sjmallett uint64_t racpp : 1; 740215976Sjmallett uint64_t rawwpp : 1; 741215976Sjmallett uint64_t ecrc_e : 1; 742215976Sjmallett uint64_t reserved_31_63 : 33; 743215976Sjmallett#endif 744215976Sjmallett } s; 745215976Sjmallett struct cvmx_pescx_dbg_info_s cn52xx; 746215976Sjmallett struct cvmx_pescx_dbg_info_s cn52xxp1; 747215976Sjmallett struct cvmx_pescx_dbg_info_s cn56xx; 748215976Sjmallett struct cvmx_pescx_dbg_info_s cn56xxp1; 749215976Sjmallett}; 750215976Sjmalletttypedef union cvmx_pescx_dbg_info cvmx_pescx_dbg_info_t; 751215976Sjmallett 752215976Sjmallett/** 753215976Sjmallett * cvmx_pesc#_dbg_info_en 754215976Sjmallett * 755215976Sjmallett * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable 756215976Sjmallett * 757215976Sjmallett * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set. 758215976Sjmallett */ 759215976Sjmallettunion cvmx_pescx_dbg_info_en 760215976Sjmallett{ 761215976Sjmallett uint64_t u64; 762215976Sjmallett struct cvmx_pescx_dbg_info_en_s 763215976Sjmallett { 764215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 765215976Sjmallett uint64_t reserved_31_63 : 33; 766215976Sjmallett uint64_t ecrc_e : 1; /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */ 767215976Sjmallett uint64_t rawwpp : 1; /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */ 768215976Sjmallett uint64_t racpp : 1; /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */ 769215976Sjmallett uint64_t ramtlp : 1; /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */ 770215976Sjmallett uint64_t rarwdns : 1; /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */ 771215976Sjmallett uint64_t caar : 1; /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */ 772215976Sjmallett uint64_t racca : 1; /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */ 773215976Sjmallett uint64_t racur : 1; /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */ 774215976Sjmallett uint64_t rauc : 1; /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */ 775215976Sjmallett uint64_t rqo : 1; /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */ 776215976Sjmallett uint64_t fcuv : 1; /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */ 777215976Sjmallett uint64_t rpe : 1; /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */ 778215976Sjmallett uint64_t fcpvwt : 1; /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */ 779215976Sjmallett uint64_t dpeoosd : 1; /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */ 780215976Sjmallett uint64_t rtwdle : 1; /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */ 781215976Sjmallett uint64_t rdwdle : 1; /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */ 782215976Sjmallett uint64_t mre : 1; /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */ 783215976Sjmallett uint64_t rte : 1; /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */ 784215976Sjmallett uint64_t acto : 1; /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */ 785215976Sjmallett uint64_t rvdm : 1; /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */ 786215976Sjmallett uint64_t rumep : 1; /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */ 787215976Sjmallett uint64_t rptamrc : 1; /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */ 788215976Sjmallett uint64_t rpmerc : 1; /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */ 789215976Sjmallett uint64_t rfemrc : 1; /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */ 790215976Sjmallett uint64_t rnfemrc : 1; /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */ 791215976Sjmallett uint64_t rcemrc : 1; /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */ 792215976Sjmallett uint64_t rpoison : 1; /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */ 793215976Sjmallett uint64_t recrce : 1; /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */ 794215976Sjmallett uint64_t rtlplle : 1; /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */ 795215976Sjmallett uint64_t rtlpmal : 1; /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */ 796215976Sjmallett uint64_t spoison : 1; /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */ 797215976Sjmallett#else 798215976Sjmallett uint64_t spoison : 1; 799215976Sjmallett uint64_t rtlpmal : 1; 800215976Sjmallett uint64_t rtlplle : 1; 801215976Sjmallett uint64_t recrce : 1; 802215976Sjmallett uint64_t rpoison : 1; 803215976Sjmallett uint64_t rcemrc : 1; 804215976Sjmallett uint64_t rnfemrc : 1; 805215976Sjmallett uint64_t rfemrc : 1; 806215976Sjmallett uint64_t rpmerc : 1; 807215976Sjmallett uint64_t rptamrc : 1; 808215976Sjmallett uint64_t rumep : 1; 809215976Sjmallett uint64_t rvdm : 1; 810215976Sjmallett uint64_t acto : 1; 811215976Sjmallett uint64_t rte : 1; 812215976Sjmallett uint64_t mre : 1; 813215976Sjmallett uint64_t rdwdle : 1; 814215976Sjmallett uint64_t rtwdle : 1; 815215976Sjmallett uint64_t dpeoosd : 1; 816215976Sjmallett uint64_t fcpvwt : 1; 817215976Sjmallett uint64_t rpe : 1; 818215976Sjmallett uint64_t fcuv : 1; 819215976Sjmallett uint64_t rqo : 1; 820215976Sjmallett uint64_t rauc : 1; 821215976Sjmallett uint64_t racur : 1; 822215976Sjmallett uint64_t racca : 1; 823215976Sjmallett uint64_t caar : 1; 824215976Sjmallett uint64_t rarwdns : 1; 825215976Sjmallett uint64_t ramtlp : 1; 826215976Sjmallett uint64_t racpp : 1; 827215976Sjmallett uint64_t rawwpp : 1; 828215976Sjmallett uint64_t ecrc_e : 1; 829215976Sjmallett uint64_t reserved_31_63 : 33; 830215976Sjmallett#endif 831215976Sjmallett } s; 832215976Sjmallett struct cvmx_pescx_dbg_info_en_s cn52xx; 833215976Sjmallett struct cvmx_pescx_dbg_info_en_s cn52xxp1; 834215976Sjmallett struct cvmx_pescx_dbg_info_en_s cn56xx; 835215976Sjmallett struct cvmx_pescx_dbg_info_en_s cn56xxp1; 836215976Sjmallett}; 837215976Sjmalletttypedef union cvmx_pescx_dbg_info_en cvmx_pescx_dbg_info_en_t; 838215976Sjmallett 839215976Sjmallett/** 840215976Sjmallett * cvmx_pesc#_diag_status 841215976Sjmallett * 842215976Sjmallett * PESC_DIAG_STATUS = PESC Diagnostic Status 843215976Sjmallett * 844215976Sjmallett * Selection control for the cores diagnostic bus. 845215976Sjmallett */ 846215976Sjmallettunion cvmx_pescx_diag_status 847215976Sjmallett{ 848215976Sjmallett uint64_t u64; 849215976Sjmallett struct cvmx_pescx_diag_status_s 850215976Sjmallett { 851215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 852215976Sjmallett uint64_t reserved_4_63 : 60; 853215976Sjmallett uint64_t pm_dst : 1; /**< Current power management DSTATE. */ 854215976Sjmallett uint64_t pm_stat : 1; /**< Power Management Status. */ 855215976Sjmallett uint64_t pm_en : 1; /**< Power Management Event Enable. */ 856215976Sjmallett uint64_t aux_en : 1; /**< Auxilary Power Enable. */ 857215976Sjmallett#else 858215976Sjmallett uint64_t aux_en : 1; 859215976Sjmallett uint64_t pm_en : 1; 860215976Sjmallett uint64_t pm_stat : 1; 861215976Sjmallett uint64_t pm_dst : 1; 862215976Sjmallett uint64_t reserved_4_63 : 60; 863215976Sjmallett#endif 864215976Sjmallett } s; 865215976Sjmallett struct cvmx_pescx_diag_status_s cn52xx; 866215976Sjmallett struct cvmx_pescx_diag_status_s cn52xxp1; 867215976Sjmallett struct cvmx_pescx_diag_status_s cn56xx; 868215976Sjmallett struct cvmx_pescx_diag_status_s cn56xxp1; 869215976Sjmallett}; 870215976Sjmalletttypedef union cvmx_pescx_diag_status cvmx_pescx_diag_status_t; 871215976Sjmallett 872215976Sjmallett/** 873215976Sjmallett * cvmx_pesc#_p2n_bar0_start 874215976Sjmallett * 875215976Sjmallett * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start 876215976Sjmallett * 877215976Sjmallett * The starting address for addresses to forwarded to the NPEI in RC Mode. 878215976Sjmallett */ 879215976Sjmallettunion cvmx_pescx_p2n_bar0_start 880215976Sjmallett{ 881215976Sjmallett uint64_t u64; 882215976Sjmallett struct cvmx_pescx_p2n_bar0_start_s 883215976Sjmallett { 884215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 885215976Sjmallett uint64_t addr : 50; /**< The starting address of the 16KB address space that 886215976Sjmallett is the BAR0 address space. */ 887215976Sjmallett uint64_t reserved_0_13 : 14; 888215976Sjmallett#else 889215976Sjmallett uint64_t reserved_0_13 : 14; 890215976Sjmallett uint64_t addr : 50; 891215976Sjmallett#endif 892215976Sjmallett } s; 893215976Sjmallett struct cvmx_pescx_p2n_bar0_start_s cn52xx; 894215976Sjmallett struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; 895215976Sjmallett struct cvmx_pescx_p2n_bar0_start_s cn56xx; 896215976Sjmallett struct cvmx_pescx_p2n_bar0_start_s cn56xxp1; 897215976Sjmallett}; 898215976Sjmalletttypedef union cvmx_pescx_p2n_bar0_start cvmx_pescx_p2n_bar0_start_t; 899215976Sjmallett 900215976Sjmallett/** 901215976Sjmallett * cvmx_pesc#_p2n_bar1_start 902215976Sjmallett * 903215976Sjmallett * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start 904215976Sjmallett * 905215976Sjmallett * The starting address for addresses to forwarded to the NPEI in RC Mode. 906215976Sjmallett */ 907215976Sjmallettunion cvmx_pescx_p2n_bar1_start 908215976Sjmallett{ 909215976Sjmallett uint64_t u64; 910215976Sjmallett struct cvmx_pescx_p2n_bar1_start_s 911215976Sjmallett { 912215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 913215976Sjmallett uint64_t addr : 38; /**< The starting address of the 64KB address space 914215976Sjmallett that is the BAR1 address space. */ 915215976Sjmallett uint64_t reserved_0_25 : 26; 916215976Sjmallett#else 917215976Sjmallett uint64_t reserved_0_25 : 26; 918215976Sjmallett uint64_t addr : 38; 919215976Sjmallett#endif 920215976Sjmallett } s; 921215976Sjmallett struct cvmx_pescx_p2n_bar1_start_s cn52xx; 922215976Sjmallett struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; 923215976Sjmallett struct cvmx_pescx_p2n_bar1_start_s cn56xx; 924215976Sjmallett struct cvmx_pescx_p2n_bar1_start_s cn56xxp1; 925215976Sjmallett}; 926215976Sjmalletttypedef union cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar1_start_t; 927215976Sjmallett 928215976Sjmallett/** 929215976Sjmallett * cvmx_pesc#_p2n_bar2_start 930215976Sjmallett * 931215976Sjmallett * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start 932215976Sjmallett * 933215976Sjmallett * The starting address for addresses to forwarded to the NPEI in RC Mode. 934215976Sjmallett */ 935215976Sjmallettunion cvmx_pescx_p2n_bar2_start 936215976Sjmallett{ 937215976Sjmallett uint64_t u64; 938215976Sjmallett struct cvmx_pescx_p2n_bar2_start_s 939215976Sjmallett { 940215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 941215976Sjmallett uint64_t addr : 25; /**< The starting address of the 2^39 address space 942215976Sjmallett that is the BAR2 address space. */ 943215976Sjmallett uint64_t reserved_0_38 : 39; 944215976Sjmallett#else 945215976Sjmallett uint64_t reserved_0_38 : 39; 946215976Sjmallett uint64_t addr : 25; 947215976Sjmallett#endif 948215976Sjmallett } s; 949215976Sjmallett struct cvmx_pescx_p2n_bar2_start_s cn52xx; 950215976Sjmallett struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; 951215976Sjmallett struct cvmx_pescx_p2n_bar2_start_s cn56xx; 952215976Sjmallett struct cvmx_pescx_p2n_bar2_start_s cn56xxp1; 953215976Sjmallett}; 954215976Sjmalletttypedef union cvmx_pescx_p2n_bar2_start cvmx_pescx_p2n_bar2_start_t; 955215976Sjmallett 956215976Sjmallett/** 957215976Sjmallett * cvmx_pesc#_p2p_bar#_end 958215976Sjmallett * 959215976Sjmallett * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End 960215976Sjmallett * 961215976Sjmallett * The ending address for addresses to forwarded to the PCIe peer port. 962215976Sjmallett */ 963215976Sjmallettunion cvmx_pescx_p2p_barx_end 964215976Sjmallett{ 965215976Sjmallett uint64_t u64; 966215976Sjmallett struct cvmx_pescx_p2p_barx_end_s 967215976Sjmallett { 968215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 969215976Sjmallett uint64_t addr : 52; /**< The ending address of the address window created 970215976Sjmallett this field and the PESC_P2P_BAR0_START[63:12] 971215976Sjmallett field. The full 64-bits of address are created by: 972215976Sjmallett [ADDR[63:12], 12'b0]. */ 973215976Sjmallett uint64_t reserved_0_11 : 12; 974215976Sjmallett#else 975215976Sjmallett uint64_t reserved_0_11 : 12; 976215976Sjmallett uint64_t addr : 52; 977215976Sjmallett#endif 978215976Sjmallett } s; 979215976Sjmallett struct cvmx_pescx_p2p_barx_end_s cn52xx; 980215976Sjmallett struct cvmx_pescx_p2p_barx_end_s cn52xxp1; 981215976Sjmallett struct cvmx_pescx_p2p_barx_end_s cn56xx; 982215976Sjmallett struct cvmx_pescx_p2p_barx_end_s cn56xxp1; 983215976Sjmallett}; 984215976Sjmalletttypedef union cvmx_pescx_p2p_barx_end cvmx_pescx_p2p_barx_end_t; 985215976Sjmallett 986215976Sjmallett/** 987215976Sjmallett * cvmx_pesc#_p2p_bar#_start 988215976Sjmallett * 989215976Sjmallett * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start 990215976Sjmallett * 991215976Sjmallett * The starting address and enable for addresses to forwarded to the PCIe peer port. 992215976Sjmallett */ 993215976Sjmallettunion cvmx_pescx_p2p_barx_start 994215976Sjmallett{ 995215976Sjmallett uint64_t u64; 996215976Sjmallett struct cvmx_pescx_p2p_barx_start_s 997215976Sjmallett { 998215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 999215976Sjmallett uint64_t addr : 52; /**< The starting address of the address window created 1000215976Sjmallett this field and the PESC_P2P_BAR0_END[63:12] field. 1001215976Sjmallett The full 64-bits of address are created by: 1002215976Sjmallett [ADDR[63:12], 12'b0]. */ 1003215976Sjmallett uint64_t reserved_0_11 : 12; 1004215976Sjmallett#else 1005215976Sjmallett uint64_t reserved_0_11 : 12; 1006215976Sjmallett uint64_t addr : 52; 1007215976Sjmallett#endif 1008215976Sjmallett } s; 1009215976Sjmallett struct cvmx_pescx_p2p_barx_start_s cn52xx; 1010215976Sjmallett struct cvmx_pescx_p2p_barx_start_s cn52xxp1; 1011215976Sjmallett struct cvmx_pescx_p2p_barx_start_s cn56xx; 1012215976Sjmallett struct cvmx_pescx_p2p_barx_start_s cn56xxp1; 1013215976Sjmallett}; 1014215976Sjmalletttypedef union cvmx_pescx_p2p_barx_start cvmx_pescx_p2p_barx_start_t; 1015215976Sjmallett 1016215976Sjmallett/** 1017215976Sjmallett * cvmx_pesc#_tlp_credits 1018215976Sjmallett * 1019215976Sjmallett * PESC_TLP_CREDITS = PESC TLP Credits 1020215976Sjmallett * 1021215976Sjmallett * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are 1022215976Sjmallett * reset to the register value. A write to this register should take place BEFORE traffic flow starts. 1023215976Sjmallett */ 1024215976Sjmallettunion cvmx_pescx_tlp_credits 1025215976Sjmallett{ 1026215976Sjmallett uint64_t u64; 1027215976Sjmallett struct cvmx_pescx_tlp_credits_s 1028215976Sjmallett { 1029215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1030215976Sjmallett uint64_t reserved_0_63 : 64; 1031215976Sjmallett#else 1032215976Sjmallett uint64_t reserved_0_63 : 64; 1033215976Sjmallett#endif 1034215976Sjmallett } s; 1035215976Sjmallett struct cvmx_pescx_tlp_credits_cn52xx 1036215976Sjmallett { 1037215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1038215976Sjmallett uint64_t reserved_56_63 : 8; 1039215976Sjmallett uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer. 1040215976Sjmallett Legal values are 0x24 to 0x80. */ 1041215976Sjmallett uint64_t pesc_cpl : 8; /**< TLP credits for Completion TLPs in the Peer. 1042215976Sjmallett Legal values are 0x24 to 0x80. */ 1043215976Sjmallett uint64_t pesc_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer. 1044215976Sjmallett Legal values are 0x4 to 0x10. */ 1045215976Sjmallett uint64_t pesc_p : 8; /**< TLP credits for Posted TLPs in the Peer. 1046215976Sjmallett Legal values are 0x24 to 0x80. */ 1047215976Sjmallett uint64_t npei_cpl : 8; /**< TLP credits for Completion TLPs in the NPEI. 1048215976Sjmallett Legal values are 0x24 to 0x80. */ 1049215976Sjmallett uint64_t npei_np : 8; /**< TLP credits for Non-Posted TLPs in the NPEI. 1050215976Sjmallett Legal values are 0x4 to 0x10. */ 1051215976Sjmallett uint64_t npei_p : 8; /**< TLP credits for Posted TLPs in the NPEI. 1052215976Sjmallett Legal values are 0x24 to 0x80. */ 1053215976Sjmallett#else 1054215976Sjmallett uint64_t npei_p : 8; 1055215976Sjmallett uint64_t npei_np : 8; 1056215976Sjmallett uint64_t npei_cpl : 8; 1057215976Sjmallett uint64_t pesc_p : 8; 1058215976Sjmallett uint64_t pesc_np : 8; 1059215976Sjmallett uint64_t pesc_cpl : 8; 1060215976Sjmallett uint64_t peai_ppf : 8; 1061215976Sjmallett uint64_t reserved_56_63 : 8; 1062215976Sjmallett#endif 1063215976Sjmallett } cn52xx; 1064215976Sjmallett struct cvmx_pescx_tlp_credits_cn52xxp1 1065215976Sjmallett { 1066215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1067215976Sjmallett uint64_t reserved_38_63 : 26; 1068215976Sjmallett uint64_t peai_ppf : 8; /**< TLP credits in core clk pre-buffer that holds TLPs 1069215976Sjmallett being sent from PCIe Core to NPEI or PEER. */ 1070215976Sjmallett uint64_t pesc_cpl : 5; /**< TLP credits for Completion TLPs in the Peer. */ 1071215976Sjmallett uint64_t pesc_np : 5; /**< TLP credits for Non-Posted TLPs in the Peer. */ 1072215976Sjmallett uint64_t pesc_p : 5; /**< TLP credits for Posted TLPs in the Peer. */ 1073215976Sjmallett uint64_t npei_cpl : 5; /**< TLP credits for Completion TLPs in the NPEI. */ 1074215976Sjmallett uint64_t npei_np : 5; /**< TLP credits for Non-Posted TLPs in the NPEI. */ 1075215976Sjmallett uint64_t npei_p : 5; /**< TLP credits for Posted TLPs in the NPEI. */ 1076215976Sjmallett#else 1077215976Sjmallett uint64_t npei_p : 5; 1078215976Sjmallett uint64_t npei_np : 5; 1079215976Sjmallett uint64_t npei_cpl : 5; 1080215976Sjmallett uint64_t pesc_p : 5; 1081215976Sjmallett uint64_t pesc_np : 5; 1082215976Sjmallett uint64_t pesc_cpl : 5; 1083215976Sjmallett uint64_t peai_ppf : 8; 1084215976Sjmallett uint64_t reserved_38_63 : 26; 1085215976Sjmallett#endif 1086215976Sjmallett } cn52xxp1; 1087215976Sjmallett struct cvmx_pescx_tlp_credits_cn52xx cn56xx; 1088215976Sjmallett struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; 1089215976Sjmallett}; 1090215976Sjmalletttypedef union cvmx_pescx_tlp_credits cvmx_pescx_tlp_credits_t; 1091215976Sjmallett 1092215976Sjmallett#endif 1093