1258945Sroberto/***********************license start*************** 2258945Sroberto * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3258945Sroberto * reserved. 4258945Sroberto * 5258945Sroberto * 6258945Sroberto * Redistribution and use in source and binary forms, with or without 7258945Sroberto * modification, are permitted provided that the following conditions are 8258945Sroberto * met: 9258945Sroberto * 10258945Sroberto * * Redistributions of source code must retain the above copyright 11258945Sroberto * notice, this list of conditions and the following disclaimer. 12258945Sroberto * 13258945Sroberto * * Redistributions in binary form must reproduce the above 14258945Sroberto * copyright notice, this list of conditions and the following 15258945Sroberto * disclaimer in the documentation and/or other materials provided 16258945Sroberto * with the distribution. 17258945Sroberto 18280849Scy * * Neither the name of Cavium Networks nor the names of 19258945Sroberto * its contributors may be used to endorse or promote products 20258945Sroberto * derived from this software without specific prior written 21258945Sroberto * permission. 22258945Sroberto 23258945Sroberto * This Software, including technical data, may be subject to U.S. export control 24258945Sroberto * laws, including the U.S. Export Administration Act and its associated 25258945Sroberto * regulations, and may be subject to export or import regulations in other 26258945Sroberto * countries. 27258945Sroberto 28258945Sroberto * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29258945Sroberto * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30258945Sroberto * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31258945Sroberto * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32258945Sroberto * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33258945Sroberto * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34258945Sroberto * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35258945Sroberto * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36258945Sroberto * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37258945Sroberto * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38258945Sroberto ***********************license end**************************************/ 39258945Sroberto 40258945Sroberto 41258945Sroberto/** 42258945Sroberto * cvmx-pemx-defs.h 43258945Sroberto * 44258945Sroberto * Configuration and status register (CSR) type definitions for 45258945Sroberto * Octeon pemx. 46258945Sroberto * 47258945Sroberto * This file is auto generated. Do not edit. 48258945Sroberto * 49258945Sroberto * <hr>$Revision$<hr> 50258945Sroberto * 51258945Sroberto */ 52258945Sroberto#ifndef __CVMX_PEMX_TYPEDEFS_H__ 53258945Sroberto#define __CVMX_PEMX_TYPEDEFS_H__ 54258945Sroberto 55258945Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))))) 60 cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id); 61 return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8; 62} 63#else 64#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id) 68{ 69 if (!( 70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 71 cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id); 72 return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull; 73} 74#else 75#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 82 cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 83 return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull; 84} 85#else 86#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id) 90{ 91 if (!( 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 93 cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); 94 return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull; 95} 96#else 97#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 104 cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id); 105 return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull; 106} 107#else 108#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 115 cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id); 116 return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull; 117} 118#else 119#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 126 cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id); 127 return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull; 128} 129#else 130#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 137 cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 138 return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull; 139} 140#else 141#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 148 cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id); 149 return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull; 150} 151#else 152#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 159 cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id); 160 return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull; 161} 162#else 163#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 170 cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id); 171 return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull; 172} 173#else 174#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id) 178{ 179 if (!( 180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 181 cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull; 183} 184#else 185#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192 cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id); 193 return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull; 194} 195#else 196#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 203 cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id); 204 return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull; 205} 206#else 207#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 214 cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id); 215 return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull; 216} 217#else 218#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 225 cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id); 226 return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull; 227} 228#else 229#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 236 cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id); 237 return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull; 238} 239#else 240#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) 247 cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id); 248 return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16; 249} 250#else 251#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) 258 cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id); 259 return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16; 260} 261#else 262#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id) 266{ 267 if (!( 268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 269 cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 270 return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull; 271} 272#else 273#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull) 274#endif 275 276/** 277 * cvmx_pem#_bar1_index# 278 * 279 * PEM_BAR1_INDEXX = PEM BAR1 IndexX Register 280 * 281 * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22]. 282 */ 283union cvmx_pemx_bar1_indexx 284{ 285 uint64_t u64; 286 struct cvmx_pemx_bar1_indexx_s 287 { 288#if __BYTE_ORDER == __BIG_ENDIAN 289 uint64_t reserved_20_63 : 44; 290 uint64_t addr_idx : 16; /**< Address bits [37:22] sent to L2C */ 291 uint64_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 292 uint64_t end_swp : 2; /**< Endian Swap Mode */ 293 uint64_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 294#else 295 uint64_t addr_v : 1; 296 uint64_t end_swp : 2; 297 uint64_t ca : 1; 298 uint64_t addr_idx : 16; 299 uint64_t reserved_20_63 : 44; 300#endif 301 } s; 302 struct cvmx_pemx_bar1_indexx_s cn63xx; 303 struct cvmx_pemx_bar1_indexx_s cn63xxp1; 304}; 305typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t; 306 307/** 308 * cvmx_pem#_bar_ctl 309 * 310 * PEM_BAR_CTUS = PEM BAR Control 311 * 312 * Contains control for BAR accesses. 313 */ 314union cvmx_pemx_bar_ctl 315{ 316 uint64_t u64; 317 struct cvmx_pemx_bar_ctl_s 318 { 319#if __BYTE_ORDER == __BIG_ENDIAN 320 uint64_t reserved_7_63 : 57; 321 uint64_t bar1_siz : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB, 322 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB, 323 0 and 7 are reserved. */ 324 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 325 clear '0' BAR2 access will cause UR responses. */ 326 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[39:38] to 327 determine the endian swap mode. */ 328 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[40] to 329 determine the L2 cache attribute. 330 Not cached in L2 if XOR result is 1 */ 331#else 332 uint64_t bar2_cax : 1; 333 uint64_t bar2_esx : 2; 334 uint64_t bar2_enb : 1; 335 uint64_t bar1_siz : 3; 336 uint64_t reserved_7_63 : 57; 337#endif 338 } s; 339 struct cvmx_pemx_bar_ctl_s cn63xx; 340 struct cvmx_pemx_bar_ctl_s cn63xxp1; 341}; 342typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t; 343 344/** 345 * cvmx_pem#_bist_status 346 * 347 * PEM_BIST_STATUS = PEM Bist Status 348 * 349 * Contains the diffrent interrupt summary bits of the PEM. 350 */ 351union cvmx_pemx_bist_status 352{ 353 uint64_t u64; 354 struct cvmx_pemx_bist_status_s 355 { 356#if __BYTE_ORDER == __BIG_ENDIAN 357 uint64_t reserved_8_63 : 56; 358 uint64_t retry : 1; /**< Retry Buffer. */ 359 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 360 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 361 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 362 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 363 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 364 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 365 uint64_t sot : 1; /**< SOT Buffer. */ 366#else 367 uint64_t sot : 1; 368 uint64_t rqhdr0 : 1; 369 uint64_t rqhdr1 : 1; 370 uint64_t rqdata3 : 1; 371 uint64_t rqdata2 : 1; 372 uint64_t rqdata1 : 1; 373 uint64_t rqdata0 : 1; 374 uint64_t retry : 1; 375 uint64_t reserved_8_63 : 56; 376#endif 377 } s; 378 struct cvmx_pemx_bist_status_s cn63xx; 379 struct cvmx_pemx_bist_status_s cn63xxp1; 380}; 381typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t; 382 383/** 384 * cvmx_pem#_bist_status2 385 * 386 * PEM(0..1)_BIST_STATUS2 = PEM BIST Status Register 387 * 388 * Results from BIST runs of PEM's memories. 389 */ 390union cvmx_pemx_bist_status2 391{ 392 uint64_t u64; 393 struct cvmx_pemx_bist_status2_s 394 { 395#if __BYTE_ORDER == __BIG_ENDIAN 396 uint64_t reserved_10_63 : 54; 397 uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */ 398 uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */ 399 uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */ 400 uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */ 401 uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */ 402 uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */ 403 uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */ 404 uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */ 405 uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */ 406 uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */ 407#else 408 uint64_t ppf : 1; 409 uint64_t pef_tc0 : 1; 410 uint64_t pef_tcf1 : 1; 411 uint64_t pef_tnf : 1; 412 uint64_t pef_tpf0 : 1; 413 uint64_t pef_tpf1 : 1; 414 uint64_t peai_p2e : 1; 415 uint64_t e2p_p : 1; 416 uint64_t e2p_n : 1; 417 uint64_t e2p_cpl : 1; 418 uint64_t reserved_10_63 : 54; 419#endif 420 } s; 421 struct cvmx_pemx_bist_status2_s cn63xx; 422 struct cvmx_pemx_bist_status2_s cn63xxp1; 423}; 424typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t; 425 426/** 427 * cvmx_pem#_cfg_rd 428 * 429 * PEM_CFG_RD = PEM Configuration Read 430 * 431 * Allows read access to the configuration in the PCIe Core. 432 */ 433union cvmx_pemx_cfg_rd 434{ 435 uint64_t u64; 436 struct cvmx_pemx_cfg_rd_s 437 { 438#if __BYTE_ORDER == __BIG_ENDIAN 439 uint64_t data : 32; /**< Data. */ 440 uint64_t addr : 32; /**< Address to read. A write to this register 441 starts a read operation. */ 442#else 443 uint64_t addr : 32; 444 uint64_t data : 32; 445#endif 446 } s; 447 struct cvmx_pemx_cfg_rd_s cn63xx; 448 struct cvmx_pemx_cfg_rd_s cn63xxp1; 449}; 450typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t; 451 452/** 453 * cvmx_pem#_cfg_wr 454 * 455 * PEM_CFG_WR = PEM Configuration Write 456 * 457 * Allows write access to the configuration in the PCIe Core. 458 */ 459union cvmx_pemx_cfg_wr 460{ 461 uint64_t u64; 462 struct cvmx_pemx_cfg_wr_s 463 { 464#if __BYTE_ORDER == __BIG_ENDIAN 465 uint64_t data : 32; /**< Data to write. A write to this register starts 466 a write operation. */ 467 uint64_t addr : 32; /**< Address to write. A write to this register starts 468 a write operation. */ 469#else 470 uint64_t addr : 32; 471 uint64_t data : 32; 472#endif 473 } s; 474 struct cvmx_pemx_cfg_wr_s cn63xx; 475 struct cvmx_pemx_cfg_wr_s cn63xxp1; 476}; 477typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t; 478 479/** 480 * cvmx_pem#_cpl_lut_valid 481 * 482 * PEM_CPL_LUT_VALID = PEM Cmpletion Lookup Table Valid 483 * 484 * Bit set for outstanding tag read. 485 */ 486union cvmx_pemx_cpl_lut_valid 487{ 488 uint64_t u64; 489 struct cvmx_pemx_cpl_lut_valid_s 490 { 491#if __BYTE_ORDER == __BIG_ENDIAN 492 uint64_t reserved_32_63 : 32; 493 uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag 494 expecting a completion. */ 495#else 496 uint64_t tag : 32; 497 uint64_t reserved_32_63 : 32; 498#endif 499 } s; 500 struct cvmx_pemx_cpl_lut_valid_s cn63xx; 501 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1; 502}; 503typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t; 504 505/** 506 * cvmx_pem#_ctl_status 507 * 508 * PEM_CTL_STATUS = PEM Control Status 509 * 510 * General control and status of the PEM. 511 */ 512union cvmx_pemx_ctl_status 513{ 514 uint64_t u64; 515 struct cvmx_pemx_ctl_status_s 516 { 517#if __BYTE_ORDER == __BIG_ENDIAN 518 uint64_t reserved_48_63 : 16; 519 uint64_t auto_sd : 1; /**< Link Hardware Autonomous Speed Disable. */ 520 uint64_t dnum : 5; /**< Primary bus device number. */ 521 uint64_t pbus : 8; /**< Primary bus number. */ 522 uint64_t reserved_32_33 : 2; 523 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a 524 CPL to a CFG RD that does not carry a Retry Status. 525 Until such time that the timeout occurs and Retry 526 Status is received for a CFG RD, the Read CFG Read 527 will be resent. A value of 0 disables retries and 528 treats a CPL Retry as a CPL UR. 529 When enabled only one CFG RD may be issued until 530 either successful completion or CPL UR. */ 531 uint64_t reserved_12_15 : 4; 532 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 533 to the PCIe core pm_xmt_turnoff port. RC mode. */ 534 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 535 to the PCIe core pm_xmt_pme port. EP mode. */ 536 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 537 to the PCIe core outband_pwrup_cmd port. EP mode. */ 538 uint64_t reserved_7_8 : 2; 539 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 540 uint64_t dly_one : 1; /**< When set the output client state machines will 541 wait one cycle before starting a new TLP out. */ 542 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 543 link is disabled. This bit only is active when in 544 RC mode. */ 545 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 546 not wait for P-TLPs that normaly would be sent 547 first. */ 548 uint64_t fast_lm : 1; /**< When '1' forces fast link mode. */ 549 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 550 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 551#else 552 uint64_t inv_lcrc : 1; 553 uint64_t inv_ecrc : 1; 554 uint64_t fast_lm : 1; 555 uint64_t ro_ctlp : 1; 556 uint64_t lnk_enb : 1; 557 uint64_t dly_one : 1; 558 uint64_t nf_ecrc : 1; 559 uint64_t reserved_7_8 : 2; 560 uint64_t ob_p_cmd : 1; 561 uint64_t pm_xpme : 1; 562 uint64_t pm_xtoff : 1; 563 uint64_t reserved_12_15 : 4; 564 uint64_t cfg_rtry : 16; 565 uint64_t reserved_32_33 : 2; 566 uint64_t pbus : 8; 567 uint64_t dnum : 5; 568 uint64_t auto_sd : 1; 569 uint64_t reserved_48_63 : 16; 570#endif 571 } s; 572 struct cvmx_pemx_ctl_status_s cn63xx; 573 struct cvmx_pemx_ctl_status_s cn63xxp1; 574}; 575typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t; 576 577/** 578 * cvmx_pem#_dbg_info 579 * 580 * PEM(0..1)_DBG_INFO = PEM Debug Information 581 * 582 * General debug info. 583 */ 584union cvmx_pemx_dbg_info 585{ 586 uint64_t u64; 587 struct cvmx_pemx_dbg_info_s 588 { 589#if __BYTE_ORDER == __BIG_ENDIAN 590 uint64_t reserved_31_63 : 33; 591 uint64_t ecrc_e : 1; /**< Received a ECRC error. 592 radm_ecrc_err */ 593 uint64_t rawwpp : 1; /**< Received a write with poisoned payload 594 radm_rcvd_wreq_poisoned */ 595 uint64_t racpp : 1; /**< Received a completion with poisoned payload 596 radm_rcvd_cpl_poisoned */ 597 uint64_t ramtlp : 1; /**< Received a malformed TLP 598 radm_mlf_tlp_err */ 599 uint64_t rarwdns : 1; /**< Recieved a request which device does not support 600 radm_rcvd_ur_req */ 601 uint64_t caar : 1; /**< Completer aborted a request 602 radm_rcvd_ca_req 603 This bit will never be set because Octeon does 604 not generate Completer Aborts. */ 605 uint64_t racca : 1; /**< Received a completion with CA status 606 radm_rcvd_cpl_ca */ 607 uint64_t racur : 1; /**< Received a completion with UR status 608 radm_rcvd_cpl_ur */ 609 uint64_t rauc : 1; /**< Received an unexpected completion 610 radm_unexp_cpl_err */ 611 uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when 612 flow control advertisements are ignored 613 radm_qoverflow */ 614 uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks) 615 int_xadm_fc_prot_err */ 616 uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error 617 (RxStatus = 3b100) or disparity error 618 (RxStatus = 3b111), the signal rmlh_rcvd_err will 619 be asserted. 620 rmlh_rcvd_err */ 621 uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer) 622 rtlh_fc_prot_err */ 623 uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP) 624 rdlh_prot_err */ 625 uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error 626 rdlh_bad_tlp_err */ 627 uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error 628 rdlh_bad_dllp_err */ 629 uint64_t mre : 1; /**< Max Retries Exceeded 630 xdlh_replay_num_rlover_err */ 631 uint64_t rte : 1; /**< Replay Timer Expired 632 xdlh_replay_timeout_err 633 This bit is set when the REPLAY_TIMER expires in 634 the PCIE core. The probability of this bit being 635 set will increase with the traffic load. */ 636 uint64_t acto : 1; /**< A Completion Timeout Occured 637 pedc_radm_cpl_timeout */ 638 uint64_t rvdm : 1; /**< Received Vendor-Defined Message 639 pedc_radm_vendor_msg */ 640 uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only) 641 pedc_radm_msg_unlock */ 642 uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message 643 (RC Mode only) 644 pedc_radm_pm_to_ack */ 645 uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only) 646 pedc_radm_pm_pme */ 647 uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only) 648 pedc_radm_fatal_err 649 Bit set when a message with ERR_FATAL is set. */ 650 uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only) 651 pedc_radm_nonfatal_err */ 652 uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only) 653 pedc_radm_correctable_err */ 654 uint64_t rpoison : 1; /**< Received Poisoned TLP 655 pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */ 656 uint64_t recrce : 1; /**< Received ECRC Error 657 pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */ 658 uint64_t rtlplle : 1; /**< Received TLP has link layer error 659 pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */ 660 uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message. 661 pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot 662 If the core receives a MSG (or Vendor Message) 663 this bit will be set. */ 664 uint64_t spoison : 1; /**< Poisoned TLP sent 665 peai__client0_tlp_ep & peai__client0_tlp_hv */ 666#else 667 uint64_t spoison : 1; 668 uint64_t rtlpmal : 1; 669 uint64_t rtlplle : 1; 670 uint64_t recrce : 1; 671 uint64_t rpoison : 1; 672 uint64_t rcemrc : 1; 673 uint64_t rnfemrc : 1; 674 uint64_t rfemrc : 1; 675 uint64_t rpmerc : 1; 676 uint64_t rptamrc : 1; 677 uint64_t rumep : 1; 678 uint64_t rvdm : 1; 679 uint64_t acto : 1; 680 uint64_t rte : 1; 681 uint64_t mre : 1; 682 uint64_t rdwdle : 1; 683 uint64_t rtwdle : 1; 684 uint64_t dpeoosd : 1; 685 uint64_t fcpvwt : 1; 686 uint64_t rpe : 1; 687 uint64_t fcuv : 1; 688 uint64_t rqo : 1; 689 uint64_t rauc : 1; 690 uint64_t racur : 1; 691 uint64_t racca : 1; 692 uint64_t caar : 1; 693 uint64_t rarwdns : 1; 694 uint64_t ramtlp : 1; 695 uint64_t racpp : 1; 696 uint64_t rawwpp : 1; 697 uint64_t ecrc_e : 1; 698 uint64_t reserved_31_63 : 33; 699#endif 700 } s; 701 struct cvmx_pemx_dbg_info_s cn63xx; 702 struct cvmx_pemx_dbg_info_s cn63xxp1; 703}; 704typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t; 705 706/** 707 * cvmx_pem#_dbg_info_en 708 * 709 * PEM(0..1)_DBG_INFO_EN = PEM Debug Information Enable 710 * 711 * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set. 712 */ 713union cvmx_pemx_dbg_info_en 714{ 715 uint64_t u64; 716 struct cvmx_pemx_dbg_info_en_s 717 { 718#if __BYTE_ORDER == __BIG_ENDIAN 719 uint64_t reserved_31_63 : 33; 720 uint64_t ecrc_e : 1; /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */ 721 uint64_t rawwpp : 1; /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */ 722 uint64_t racpp : 1; /**< Allows PEM_DBG_INFO[28] to generate an interrupt. */ 723 uint64_t ramtlp : 1; /**< Allows PEM_DBG_INFO[27] to generate an interrupt. */ 724 uint64_t rarwdns : 1; /**< Allows PEM_DBG_INFO[26] to generate an interrupt. */ 725 uint64_t caar : 1; /**< Allows PEM_DBG_INFO[25] to generate an interrupt. */ 726 uint64_t racca : 1; /**< Allows PEM_DBG_INFO[24] to generate an interrupt. */ 727 uint64_t racur : 1; /**< Allows PEM_DBG_INFO[23] to generate an interrupt. */ 728 uint64_t rauc : 1; /**< Allows PEM_DBG_INFO[22] to generate an interrupt. */ 729 uint64_t rqo : 1; /**< Allows PEM_DBG_INFO[21] to generate an interrupt. */ 730 uint64_t fcuv : 1; /**< Allows PEM_DBG_INFO[20] to generate an interrupt. */ 731 uint64_t rpe : 1; /**< Allows PEM_DBG_INFO[19] to generate an interrupt. */ 732 uint64_t fcpvwt : 1; /**< Allows PEM_DBG_INFO[18] to generate an interrupt. */ 733 uint64_t dpeoosd : 1; /**< Allows PEM_DBG_INFO[17] to generate an interrupt. */ 734 uint64_t rtwdle : 1; /**< Allows PEM_DBG_INFO[16] to generate an interrupt. */ 735 uint64_t rdwdle : 1; /**< Allows PEM_DBG_INFO[15] to generate an interrupt. */ 736 uint64_t mre : 1; /**< Allows PEM_DBG_INFO[14] to generate an interrupt. */ 737 uint64_t rte : 1; /**< Allows PEM_DBG_INFO[13] to generate an interrupt. */ 738 uint64_t acto : 1; /**< Allows PEM_DBG_INFO[12] to generate an interrupt. */ 739 uint64_t rvdm : 1; /**< Allows PEM_DBG_INFO[11] to generate an interrupt. */ 740 uint64_t rumep : 1; /**< Allows PEM_DBG_INFO[10] to generate an interrupt. */ 741 uint64_t rptamrc : 1; /**< Allows PEM_DBG_INFO[9] to generate an interrupt. */ 742 uint64_t rpmerc : 1; /**< Allows PEM_DBG_INFO[8] to generate an interrupt. */ 743 uint64_t rfemrc : 1; /**< Allows PEM_DBG_INFO[7] to generate an interrupt. */ 744 uint64_t rnfemrc : 1; /**< Allows PEM_DBG_INFO[6] to generate an interrupt. */ 745 uint64_t rcemrc : 1; /**< Allows PEM_DBG_INFO[5] to generate an interrupt. */ 746 uint64_t rpoison : 1; /**< Allows PEM_DBG_INFO[4] to generate an interrupt. */ 747 uint64_t recrce : 1; /**< Allows PEM_DBG_INFO[3] to generate an interrupt. */ 748 uint64_t rtlplle : 1; /**< Allows PEM_DBG_INFO[2] to generate an interrupt. */ 749 uint64_t rtlpmal : 1; /**< Allows PEM_DBG_INFO[1] to generate an interrupt. */ 750 uint64_t spoison : 1; /**< Allows PEM_DBG_INFO[0] to generate an interrupt. */ 751#else 752 uint64_t spoison : 1; 753 uint64_t rtlpmal : 1; 754 uint64_t rtlplle : 1; 755 uint64_t recrce : 1; 756 uint64_t rpoison : 1; 757 uint64_t rcemrc : 1; 758 uint64_t rnfemrc : 1; 759 uint64_t rfemrc : 1; 760 uint64_t rpmerc : 1; 761 uint64_t rptamrc : 1; 762 uint64_t rumep : 1; 763 uint64_t rvdm : 1; 764 uint64_t acto : 1; 765 uint64_t rte : 1; 766 uint64_t mre : 1; 767 uint64_t rdwdle : 1; 768 uint64_t rtwdle : 1; 769 uint64_t dpeoosd : 1; 770 uint64_t fcpvwt : 1; 771 uint64_t rpe : 1; 772 uint64_t fcuv : 1; 773 uint64_t rqo : 1; 774 uint64_t rauc : 1; 775 uint64_t racur : 1; 776 uint64_t racca : 1; 777 uint64_t caar : 1; 778 uint64_t rarwdns : 1; 779 uint64_t ramtlp : 1; 780 uint64_t racpp : 1; 781 uint64_t rawwpp : 1; 782 uint64_t ecrc_e : 1; 783 uint64_t reserved_31_63 : 33; 784#endif 785 } s; 786 struct cvmx_pemx_dbg_info_en_s cn63xx; 787 struct cvmx_pemx_dbg_info_en_s cn63xxp1; 788}; 789typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t; 790 791/** 792 * cvmx_pem#_diag_status 793 * 794 * PEM_DIAG_STATUS = PEM Diagnostic Status 795 * 796 * Selection control for the cores diagnostic bus. 797 */ 798union cvmx_pemx_diag_status 799{ 800 uint64_t u64; 801 struct cvmx_pemx_diag_status_s 802 { 803#if __BYTE_ORDER == __BIG_ENDIAN 804 uint64_t reserved_4_63 : 60; 805 uint64_t pm_dst : 1; /**< Current power management DSTATE. */ 806 uint64_t pm_stat : 1; /**< Power Management Status. */ 807 uint64_t pm_en : 1; /**< Power Management Event Enable. */ 808 uint64_t aux_en : 1; /**< Auxilary Power Enable. */ 809#else 810 uint64_t aux_en : 1; 811 uint64_t pm_en : 1; 812 uint64_t pm_stat : 1; 813 uint64_t pm_dst : 1; 814 uint64_t reserved_4_63 : 60; 815#endif 816 } s; 817 struct cvmx_pemx_diag_status_s cn63xx; 818 struct cvmx_pemx_diag_status_s cn63xxp1; 819}; 820typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t; 821 822/** 823 * cvmx_pem#_int_enb 824 * 825 * PEM(0..1)_INT_ENB = PEM Interrupt Enable 826 * 827 * Enables interrupt conditions for the PEM to generate an RSL interrupt. 828 */ 829union cvmx_pemx_int_enb 830{ 831 uint64_t u64; 832 struct cvmx_pemx_int_enb_s 833 { 834#if __BYTE_ORDER == __BIG_ENDIAN 835 uint64_t reserved_14_63 : 50; 836 uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an 837 interrupt to the MIO. */ 838 uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an 839 interrupt to the MIO. */ 840 uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an 841 interrupt to the MIO. */ 842 uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an 843 interrupt to the MIO. */ 844 uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an 845 interrupt to the MIO. */ 846 uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an 847 interrupt to the MIO. */ 848 uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an 849 interrupt to the MIO. */ 850 uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an 851 interrupt to the MIO. */ 852 uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an 853 interrupt to the MIO. */ 854 uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an 855 interrupt to the MIO. */ 856 uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an 857 interrupt to the MIO. */ 858 uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an 859 interrupt to the MIO. */ 860 uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an 861 interrupt to the MIO. */ 862 uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an 863 interrupt to the MIO. */ 864#else 865 uint64_t aeri : 1; 866 uint64_t se : 1; 867 uint64_t pmei : 1; 868 uint64_t pmem : 1; 869 uint64_t up_b1 : 1; 870 uint64_t up_b2 : 1; 871 uint64_t up_bx : 1; 872 uint64_t un_b1 : 1; 873 uint64_t un_b2 : 1; 874 uint64_t un_bx : 1; 875 uint64_t exc : 1; 876 uint64_t rdlk : 1; 877 uint64_t crs_er : 1; 878 uint64_t crs_dr : 1; 879 uint64_t reserved_14_63 : 50; 880#endif 881 } s; 882 struct cvmx_pemx_int_enb_s cn63xx; 883 struct cvmx_pemx_int_enb_s cn63xxp1; 884}; 885typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t; 886 887/** 888 * cvmx_pem#_int_enb_int 889 * 890 * PEM(0..1)_INT_ENB_INT = PEM Interrupt Enable 891 * 892 * Enables interrupt conditions for the PEM to generate an RSL interrupt. 893 */ 894union cvmx_pemx_int_enb_int 895{ 896 uint64_t u64; 897 struct cvmx_pemx_int_enb_int_s 898 { 899#if __BYTE_ORDER == __BIG_ENDIAN 900 uint64_t reserved_14_63 : 50; 901 uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an 902 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 903 uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an 904 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 905 uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an 906 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 907 uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an 908 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 909 uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an 910 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 911 uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an 912 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 913 uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an 914 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 915 uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an 916 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 917 uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an 918 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 919 uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an 920 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 921 uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an 922 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 923 uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an 924 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 925 uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an 926 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 927 uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an 928 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 929#else 930 uint64_t aeri : 1; 931 uint64_t se : 1; 932 uint64_t pmei : 1; 933 uint64_t pmem : 1; 934 uint64_t up_b1 : 1; 935 uint64_t up_b2 : 1; 936 uint64_t up_bx : 1; 937 uint64_t un_b1 : 1; 938 uint64_t un_b2 : 1; 939 uint64_t un_bx : 1; 940 uint64_t exc : 1; 941 uint64_t rdlk : 1; 942 uint64_t crs_er : 1; 943 uint64_t crs_dr : 1; 944 uint64_t reserved_14_63 : 50; 945#endif 946 } s; 947 struct cvmx_pemx_int_enb_int_s cn63xx; 948 struct cvmx_pemx_int_enb_int_s cn63xxp1; 949}; 950typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t; 951 952/** 953 * cvmx_pem#_int_sum 954 * 955 * Below are in pesc_csr 956 * 957 * PEM(0..1)_INT_SUM = PEM Interrupt Summary 958 * 959 * Interrupt conditions for the PEM. 960 */ 961union cvmx_pemx_int_sum 962{ 963 uint64_t u64; 964 struct cvmx_pemx_int_sum_s 965 { 966#if __BYTE_ORDER == __BIG_ENDIAN 967 uint64_t reserved_14_63 : 50; 968 uint64_t crs_dr : 1; /**< Had a CRS Timeout when Retries were disabled. */ 969 uint64_t crs_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 970 uint64_t rdlk : 1; /**< Received Read Lock TLP. */ 971 uint64_t exc : 1; /**< Set when the PEM_DBG_INFO register has a bit 972 set and its cooresponding PEM_DBG_INFO_EN bit 973 is set. */ 974 uint64_t un_bx : 1; /**< Received N-TLP for an unknown Bar. */ 975 uint64_t un_b2 : 1; /**< Received N-TLP for Bar2 when bar2 is disabled. */ 976 uint64_t un_b1 : 1; /**< Received N-TLP for Bar1 when bar1 index valid 977 is not set. */ 978 uint64_t up_bx : 1; /**< Received P-TLP for an unknown Bar. */ 979 uint64_t up_b2 : 1; /**< Received P-TLP for Bar2 when bar2 is disabeld. */ 980 uint64_t up_b1 : 1; /**< Received P-TLP for Bar1 when bar1 index valid 981 is not set. */ 982 uint64_t pmem : 1; /**< Recived PME MSG. 983 (radm_pm_pme) */ 984 uint64_t pmei : 1; /**< PME Interrupt. 985 (cfg_pme_int) */ 986 uint64_t se : 1; /**< System Error, RC Mode Only. 987 (cfg_sys_err_rc) */ 988 uint64_t aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 989 (cfg_aer_rc_err_int). */ 990#else 991 uint64_t aeri : 1; 992 uint64_t se : 1; 993 uint64_t pmei : 1; 994 uint64_t pmem : 1; 995 uint64_t up_b1 : 1; 996 uint64_t up_b2 : 1; 997 uint64_t up_bx : 1; 998 uint64_t un_b1 : 1; 999 uint64_t un_b2 : 1; 1000 uint64_t un_bx : 1; 1001 uint64_t exc : 1; 1002 uint64_t rdlk : 1; 1003 uint64_t crs_er : 1; 1004 uint64_t crs_dr : 1; 1005 uint64_t reserved_14_63 : 50; 1006#endif 1007 } s; 1008 struct cvmx_pemx_int_sum_s cn63xx; 1009 struct cvmx_pemx_int_sum_s cn63xxp1; 1010}; 1011typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t; 1012 1013/** 1014 * cvmx_pem#_p2n_bar0_start 1015 * 1016 * PEM_P2N_BAR0_START = PEM PCIe to Npei BAR0 Start 1017 * 1018 * The starting address for addresses to forwarded to the SLI in RC Mode. 1019 */ 1020union cvmx_pemx_p2n_bar0_start 1021{ 1022 uint64_t u64; 1023 struct cvmx_pemx_p2n_bar0_start_s 1024 { 1025#if __BYTE_ORDER == __BIG_ENDIAN 1026 uint64_t addr : 50; /**< The starting address of the 16KB address space that 1027 is the BAR0 address space. */ 1028 uint64_t reserved_0_13 : 14; 1029#else 1030 uint64_t reserved_0_13 : 14; 1031 uint64_t addr : 50; 1032#endif 1033 } s; 1034 struct cvmx_pemx_p2n_bar0_start_s cn63xx; 1035 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1; 1036}; 1037typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t; 1038 1039/** 1040 * cvmx_pem#_p2n_bar1_start 1041 * 1042 * PEM_P2N_BAR1_START = PEM PCIe to Npei BAR1 Start 1043 * 1044 * The starting address for addresses to forwarded to the SLI in RC Mode. 1045 */ 1046union cvmx_pemx_p2n_bar1_start 1047{ 1048 uint64_t u64; 1049 struct cvmx_pemx_p2n_bar1_start_s 1050 { 1051#if __BYTE_ORDER == __BIG_ENDIAN 1052 uint64_t addr : 38; /**< The starting address of the 64KB address space 1053 that is the BAR1 address space. */ 1054 uint64_t reserved_0_25 : 26; 1055#else 1056 uint64_t reserved_0_25 : 26; 1057 uint64_t addr : 38; 1058#endif 1059 } s; 1060 struct cvmx_pemx_p2n_bar1_start_s cn63xx; 1061 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1; 1062}; 1063typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t; 1064 1065/** 1066 * cvmx_pem#_p2n_bar2_start 1067 * 1068 * PEM_P2N_BAR2_START = PEM PCIe to Npei BAR2 Start 1069 * 1070 * The starting address for addresses to forwarded to the SLI in RC Mode. 1071 */ 1072union cvmx_pemx_p2n_bar2_start 1073{ 1074 uint64_t u64; 1075 struct cvmx_pemx_p2n_bar2_start_s 1076 { 1077#if __BYTE_ORDER == __BIG_ENDIAN 1078 uint64_t addr : 23; /**< The starting address of the 2^41 address space 1079 that is the BAR2 address space. */ 1080 uint64_t reserved_0_40 : 41; 1081#else 1082 uint64_t reserved_0_40 : 41; 1083 uint64_t addr : 23; 1084#endif 1085 } s; 1086 struct cvmx_pemx_p2n_bar2_start_s cn63xx; 1087 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1; 1088}; 1089typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t; 1090 1091/** 1092 * cvmx_pem#_p2p_bar#_end 1093 * 1094 * PEM_P2P_BAR#_END = PEM Peer-To-Peer BAR0 End 1095 * 1096 * The ending address for addresses to forwarded to the PCIe peer port. 1097 */ 1098union cvmx_pemx_p2p_barx_end 1099{ 1100 uint64_t u64; 1101 struct cvmx_pemx_p2p_barx_end_s 1102 { 1103#if __BYTE_ORDER == __BIG_ENDIAN 1104 uint64_t addr : 52; /**< The ending address of the address window created 1105 this field and the PEM_P2P_BAR0_START[63:12] 1106 field. The full 64-bits of address are created by: 1107 [ADDR[63:12], 12'b0]. */ 1108 uint64_t reserved_0_11 : 12; 1109#else 1110 uint64_t reserved_0_11 : 12; 1111 uint64_t addr : 52; 1112#endif 1113 } s; 1114 struct cvmx_pemx_p2p_barx_end_s cn63xx; 1115 struct cvmx_pemx_p2p_barx_end_s cn63xxp1; 1116}; 1117typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t; 1118 1119/** 1120 * cvmx_pem#_p2p_bar#_start 1121 * 1122 * PEM_P2P_BAR#_START = PEM Peer-To-Peer BAR0 Start 1123 * 1124 * The starting address and enable for addresses to forwarded to the PCIe peer port. 1125 */ 1126union cvmx_pemx_p2p_barx_start 1127{ 1128 uint64_t u64; 1129 struct cvmx_pemx_p2p_barx_start_s 1130 { 1131#if __BYTE_ORDER == __BIG_ENDIAN 1132 uint64_t addr : 52; /**< The starting address of the address window created 1133 by this field and the PEM_P2P_BAR0_END[63:12] 1134 field. The full 64-bits of address are created by: 1135 [ADDR[63:12], 12'b0]. */ 1136 uint64_t reserved_0_11 : 12; 1137#else 1138 uint64_t reserved_0_11 : 12; 1139 uint64_t addr : 52; 1140#endif 1141 } s; 1142 struct cvmx_pemx_p2p_barx_start_s cn63xx; 1143 struct cvmx_pemx_p2p_barx_start_s cn63xxp1; 1144}; 1145typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t; 1146 1147/** 1148 * cvmx_pem#_tlp_credits 1149 * 1150 * PEM_TLP_CREDITS = PEM TLP Credits 1151 * 1152 * Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are 1153 * reset to the register value. A write to this register should take place BEFORE traffic flow starts. 1154 */ 1155union cvmx_pemx_tlp_credits 1156{ 1157 uint64_t u64; 1158 struct cvmx_pemx_tlp_credits_s 1159 { 1160#if __BYTE_ORDER == __BIG_ENDIAN 1161 uint64_t reserved_56_63 : 8; 1162 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer. 1163 Legal values are 0x24 to 0x80. */ 1164 uint64_t pem_cpl : 8; /**< TLP credits for Completion TLPs in the Peer. 1165 Legal values are 0x24 to 0x80. */ 1166 uint64_t pem_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer. 1167 Legal values are 0x4 to 0x10. */ 1168 uint64_t pem_p : 8; /**< TLP credits for Posted TLPs in the Peer. 1169 Legal values are 0x24 to 0x80. */ 1170 uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI. 1171 Legal values are 0x24 to 0x80. */ 1172 uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI. 1173 Legal values are 0x4 to 0x10. */ 1174 uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI. 1175 Legal values are 0x24 to 0x80. */ 1176#else 1177 uint64_t sli_p : 8; 1178 uint64_t sli_np : 8; 1179 uint64_t sli_cpl : 8; 1180 uint64_t pem_p : 8; 1181 uint64_t pem_np : 8; 1182 uint64_t pem_cpl : 8; 1183 uint64_t peai_ppf : 8; 1184 uint64_t reserved_56_63 : 8; 1185#endif 1186 } s; 1187 struct cvmx_pemx_tlp_credits_s cn63xx; 1188 struct cvmx_pemx_tlp_credits_s cn63xxp1; 1189}; 1190typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t; 1191 1192#endif 1193