1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pcsxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pcsxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_PCSXX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_PCSXX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 62215976Sjmallett cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id); 63215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull; 64215976Sjmallett} 65215976Sjmallett#else 66215976Sjmallett#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull) 67215976Sjmallett#endif 68215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69215976Sjmallettstatic inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) 70215976Sjmallett{ 71215976Sjmallett if (!( 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 73215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 75215976Sjmallett cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id); 76215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull; 77215976Sjmallett} 78215976Sjmallett#else 79215976Sjmallett#define CVMX_PCSXX_BIST_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallettstatic inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) 83215976Sjmallett{ 84215976Sjmallett if (!( 85215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 86215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 87215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 88215976Sjmallett cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id); 89215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull; 90215976Sjmallett} 91215976Sjmallett#else 92215976Sjmallett#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull) 93215976Sjmallett#endif 94215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95215976Sjmallettstatic inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) 96215976Sjmallett{ 97215976Sjmallett if (!( 98215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 99215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 100215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 101215976Sjmallett cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id); 102215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull; 103215976Sjmallett} 104215976Sjmallett#else 105215976Sjmallett#define CVMX_PCSXX_CONTROL1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull) 106215976Sjmallett#endif 107215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108215976Sjmallettstatic inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) 109215976Sjmallett{ 110215976Sjmallett if (!( 111215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 112215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 113215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 114215976Sjmallett cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id); 115215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull; 116215976Sjmallett} 117215976Sjmallett#else 118215976Sjmallett#define CVMX_PCSXX_CONTROL2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull) 119215976Sjmallett#endif 120215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121215976Sjmallettstatic inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) 122215976Sjmallett{ 123215976Sjmallett if (!( 124215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 126215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 127215976Sjmallett cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id); 128215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull; 129215976Sjmallett} 130215976Sjmallett#else 131215976Sjmallett#define CVMX_PCSXX_INT_EN_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull) 132215976Sjmallett#endif 133215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134215976Sjmallettstatic inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) 135215976Sjmallett{ 136215976Sjmallett if (!( 137215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 138215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 139215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 140215976Sjmallett cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id); 141215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull; 142215976Sjmallett} 143215976Sjmallett#else 144215976Sjmallett#define CVMX_PCSXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull) 145215976Sjmallett#endif 146215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147215976Sjmallettstatic inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) 148215976Sjmallett{ 149215976Sjmallett if (!( 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 151215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 152215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 153215976Sjmallett cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id); 154215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull; 155215976Sjmallett} 156215976Sjmallett#else 157215976Sjmallett#define CVMX_PCSXX_LOG_ANL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull) 158215976Sjmallett#endif 159215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160215976Sjmallettstatic inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) 161215976Sjmallett{ 162215976Sjmallett if (!( 163215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 166215976Sjmallett cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id); 167215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull; 168215976Sjmallett} 169215976Sjmallett#else 170215976Sjmallett#define CVMX_PCSXX_MISC_CTL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull) 171215976Sjmallett#endif 172215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173215976Sjmallettstatic inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) 174215976Sjmallett{ 175215976Sjmallett if (!( 176215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 177215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 179215976Sjmallett cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id); 180215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull; 181215976Sjmallett} 182215976Sjmallett#else 183215976Sjmallett#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull) 184215976Sjmallett#endif 185215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186215976Sjmallettstatic inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) 187215976Sjmallett{ 188215976Sjmallett if (!( 189215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 190215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 192215976Sjmallett cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull; 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_PCSXX_SPD_ABIL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallettstatic inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) 200215976Sjmallett{ 201215976Sjmallett if (!( 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 205215976Sjmallett cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_PCSXX_STATUS1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) 213215976Sjmallett{ 214215976Sjmallett if (!( 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 217215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 218215976Sjmallett cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id); 219215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull; 220215976Sjmallett} 221215976Sjmallett#else 222215976Sjmallett#define CVMX_PCSXX_STATUS2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull) 223215976Sjmallett#endif 224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225215976Sjmallettstatic inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) 226215976Sjmallett{ 227215976Sjmallett if (!( 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 230215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 231215976Sjmallett cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id); 232215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull; 233215976Sjmallett} 234215976Sjmallett#else 235215976Sjmallett#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull) 236215976Sjmallett#endif 237215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238215976Sjmallettstatic inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) 239215976Sjmallett{ 240215976Sjmallett if (!( 241215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 242215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 243215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 244215976Sjmallett cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id); 245215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull; 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull) 249215976Sjmallett#endif 250215976Sjmallett 251215976Sjmallett/** 252215976Sjmallett * cvmx_pcsx#_10gbx_status_reg 253215976Sjmallett * 254215976Sjmallett * PCSX_10GBX_STATUS_REG = 10gbx_status_reg 255215976Sjmallett * 256215976Sjmallett */ 257215976Sjmallettunion cvmx_pcsxx_10gbx_status_reg 258215976Sjmallett{ 259215976Sjmallett uint64_t u64; 260215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s 261215976Sjmallett { 262215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 263215976Sjmallett uint64_t reserved_13_63 : 51; 264215976Sjmallett uint64_t alignd : 1; /**< 1=Lane alignment achieved, 0=Lanes not aligned */ 265215976Sjmallett uint64_t pattst : 1; /**< Always at 0, no pattern testing capability */ 266215976Sjmallett uint64_t reserved_4_10 : 7; 267215976Sjmallett uint64_t l3sync : 1; /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */ 268215976Sjmallett uint64_t l2sync : 1; /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */ 269215976Sjmallett uint64_t l1sync : 1; /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */ 270215976Sjmallett uint64_t l0sync : 1; /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */ 271215976Sjmallett#else 272215976Sjmallett uint64_t l0sync : 1; 273215976Sjmallett uint64_t l1sync : 1; 274215976Sjmallett uint64_t l2sync : 1; 275215976Sjmallett uint64_t l3sync : 1; 276215976Sjmallett uint64_t reserved_4_10 : 7; 277215976Sjmallett uint64_t pattst : 1; 278215976Sjmallett uint64_t alignd : 1; 279215976Sjmallett uint64_t reserved_13_63 : 51; 280215976Sjmallett#endif 281215976Sjmallett } s; 282215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; 283215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; 284215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; 285215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; 286215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; 287215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; 288215976Sjmallett}; 289215976Sjmalletttypedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t; 290215976Sjmallett 291215976Sjmallett/** 292215976Sjmallett * cvmx_pcsx#_bist_status_reg 293215976Sjmallett * 294215976Sjmallett * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1 295215976Sjmallett * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0]. 296215976Sjmallett * See pcs.csr for sgmii/1000Base-X logic analyzer mode. 297215976Sjmallett * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 298215976Sjmallett * 299215976Sjmallett * 300215976Sjmallett * PCSX Bist Status Register 301215976Sjmallett */ 302215976Sjmallettunion cvmx_pcsxx_bist_status_reg 303215976Sjmallett{ 304215976Sjmallett uint64_t u64; 305215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s 306215976Sjmallett { 307215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 308215976Sjmallett uint64_t reserved_1_63 : 63; 309215976Sjmallett uint64_t bist_status : 1; /**< 1=bist failure, 0=bisted memory ok or bist in progress 310215976Sjmallett pcsx.tx_sm.drf8x36m1_async_bist */ 311215976Sjmallett#else 312215976Sjmallett uint64_t bist_status : 1; 313215976Sjmallett uint64_t reserved_1_63 : 63; 314215976Sjmallett#endif 315215976Sjmallett } s; 316215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn52xx; 317215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; 318215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn56xx; 319215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; 320215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn63xx; 321215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; 322215976Sjmallett}; 323215976Sjmalletttypedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t; 324215976Sjmallett 325215976Sjmallett/** 326215976Sjmallett * cvmx_pcsx#_bit_lock_status_reg 327215976Sjmallett * 328215976Sjmallett * LN_SWAP for XAUI is to simplify interconnection layout between devices 329215976Sjmallett * 330215976Sjmallett * 331215976Sjmallett * PCSX Bit Lock Status Register 332215976Sjmallett */ 333215976Sjmallettunion cvmx_pcsxx_bit_lock_status_reg 334215976Sjmallett{ 335215976Sjmallett uint64_t u64; 336215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s 337215976Sjmallett { 338215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 339215976Sjmallett uint64_t reserved_4_63 : 60; 340215976Sjmallett uint64_t bitlck3 : 1; /**< Receive Lane 3 bit lock status */ 341215976Sjmallett uint64_t bitlck2 : 1; /**< Receive Lane 2 bit lock status */ 342215976Sjmallett uint64_t bitlck1 : 1; /**< Receive Lane 1 bit lock status */ 343215976Sjmallett uint64_t bitlck0 : 1; /**< Receive Lane 0 bit lock status */ 344215976Sjmallett#else 345215976Sjmallett uint64_t bitlck0 : 1; 346215976Sjmallett uint64_t bitlck1 : 1; 347215976Sjmallett uint64_t bitlck2 : 1; 348215976Sjmallett uint64_t bitlck3 : 1; 349215976Sjmallett uint64_t reserved_4_63 : 60; 350215976Sjmallett#endif 351215976Sjmallett } s; 352215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; 353215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; 354215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; 355215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; 356215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; 357215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; 358215976Sjmallett}; 359215976Sjmalletttypedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t; 360215976Sjmallett 361215976Sjmallett/** 362215976Sjmallett * cvmx_pcsx#_control1_reg 363215976Sjmallett * 364215976Sjmallett * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1 365215976Sjmallett * For normal operation(sgmii or 1000Base-X), this bit must be 0. 366215976Sjmallett * See pcsx.csr for xaui logic analyzer mode. 367215976Sjmallett * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 368215976Sjmallett * 369215976Sjmallett * 370215976Sjmallett * PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3 371215976Sjmallett * 372215976Sjmallett * 373215976Sjmallett * PCSX_CONTROL1_REG = Control Register1 374215976Sjmallett */ 375215976Sjmallettunion cvmx_pcsxx_control1_reg 376215976Sjmallett{ 377215976Sjmallett uint64_t u64; 378215976Sjmallett struct cvmx_pcsxx_control1_reg_s 379215976Sjmallett { 380215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 381215976Sjmallett uint64_t reserved_16_63 : 48; 382215976Sjmallett uint64_t reset : 1; /**< 1=SW PCSX Reset, the bit will return to 0 after pcs 383215976Sjmallett has been reset. Takes 32 eclk cycles to reset pcs 384215976Sjmallett 0=Normal operation */ 385215976Sjmallett uint64_t loopbck1 : 1; /**< 0=normal operation, 1=internal loopback mode 386215976Sjmallett xgmii tx data received from gmx tx port is returned 387215976Sjmallett back into gmx, xgmii rx port. */ 388215976Sjmallett uint64_t spdsel1 : 1; /**< See bit 6 description */ 389215976Sjmallett uint64_t reserved_12_12 : 1; 390215976Sjmallett uint64_t lo_pwr : 1; /**< 1=Power Down(HW reset), 0=Normal operation */ 391215976Sjmallett uint64_t reserved_7_10 : 4; 392215976Sjmallett uint64_t spdsel0 : 1; /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has 393215976Sjmallett no effect. 394215976Sjmallett [<6>, <13>]Link Speed selection 395215976Sjmallett 1 1 Bits 5:2 select speed */ 396215976Sjmallett uint64_t spd : 4; /**< Always select 10Gb/s, writes have no effect */ 397215976Sjmallett uint64_t reserved_0_1 : 2; 398215976Sjmallett#else 399215976Sjmallett uint64_t reserved_0_1 : 2; 400215976Sjmallett uint64_t spd : 4; 401215976Sjmallett uint64_t spdsel0 : 1; 402215976Sjmallett uint64_t reserved_7_10 : 4; 403215976Sjmallett uint64_t lo_pwr : 1; 404215976Sjmallett uint64_t reserved_12_12 : 1; 405215976Sjmallett uint64_t spdsel1 : 1; 406215976Sjmallett uint64_t loopbck1 : 1; 407215976Sjmallett uint64_t reset : 1; 408215976Sjmallett uint64_t reserved_16_63 : 48; 409215976Sjmallett#endif 410215976Sjmallett } s; 411215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn52xx; 412215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn52xxp1; 413215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn56xx; 414215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn56xxp1; 415215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn63xx; 416215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn63xxp1; 417215976Sjmallett}; 418215976Sjmalletttypedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t; 419215976Sjmallett 420215976Sjmallett/** 421215976Sjmallett * cvmx_pcsx#_control2_reg 422215976Sjmallett * 423215976Sjmallett * PCSX_CONTROL2_REG = Control Register2 424215976Sjmallett * 425215976Sjmallett */ 426215976Sjmallettunion cvmx_pcsxx_control2_reg 427215976Sjmallett{ 428215976Sjmallett uint64_t u64; 429215976Sjmallett struct cvmx_pcsxx_control2_reg_s 430215976Sjmallett { 431215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 432215976Sjmallett uint64_t reserved_2_63 : 62; 433215976Sjmallett uint64_t type : 2; /**< Always 2'b01, 10GBASE-X only supported */ 434215976Sjmallett#else 435215976Sjmallett uint64_t type : 2; 436215976Sjmallett uint64_t reserved_2_63 : 62; 437215976Sjmallett#endif 438215976Sjmallett } s; 439215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn52xx; 440215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn52xxp1; 441215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn56xx; 442215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn56xxp1; 443215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn63xx; 444215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn63xxp1; 445215976Sjmallett}; 446215976Sjmalletttypedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t; 447215976Sjmallett 448215976Sjmallett/** 449215976Sjmallett * cvmx_pcsx#_int_en_reg 450215976Sjmallett * 451215976Sjmallett * Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state machine in 452215976Sjmallett * Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2 453215976Sjmallett * indicating an invalid code group was received on one of the 4 receive lanes. 454215976Sjmallett * This interrupt should be always disabled and used only for link problem debugging help. 455215976Sjmallett * 456215976Sjmallett * 457215976Sjmallett * PCSX Interrupt Enable Register 458215976Sjmallett */ 459215976Sjmallettunion cvmx_pcsxx_int_en_reg 460215976Sjmallett{ 461215976Sjmallett uint64_t u64; 462215976Sjmallett struct cvmx_pcsxx_int_en_reg_s 463215976Sjmallett { 464215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 465215976Sjmallett uint64_t reserved_7_63 : 57; 466215976Sjmallett uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */ 467215976Sjmallett uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */ 468215976Sjmallett uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */ 469215976Sjmallett uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */ 470215976Sjmallett uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */ 471215976Sjmallett uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */ 472215976Sjmallett uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */ 473215976Sjmallett#else 474215976Sjmallett uint64_t txflt_en : 1; 475215976Sjmallett uint64_t rxbad_en : 1; 476215976Sjmallett uint64_t rxsynbad_en : 1; 477215976Sjmallett uint64_t bitlckls_en : 1; 478215976Sjmallett uint64_t synlos_en : 1; 479215976Sjmallett uint64_t algnlos_en : 1; 480215976Sjmallett uint64_t dbg_sync_en : 1; 481215976Sjmallett uint64_t reserved_7_63 : 57; 482215976Sjmallett#endif 483215976Sjmallett } s; 484215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx 485215976Sjmallett { 486215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 487215976Sjmallett uint64_t reserved_6_63 : 58; 488215976Sjmallett uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */ 489215976Sjmallett uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */ 490215976Sjmallett uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */ 491215976Sjmallett uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */ 492215976Sjmallett uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */ 493215976Sjmallett uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */ 494215976Sjmallett#else 495215976Sjmallett uint64_t txflt_en : 1; 496215976Sjmallett uint64_t rxbad_en : 1; 497215976Sjmallett uint64_t rxsynbad_en : 1; 498215976Sjmallett uint64_t bitlckls_en : 1; 499215976Sjmallett uint64_t synlos_en : 1; 500215976Sjmallett uint64_t algnlos_en : 1; 501215976Sjmallett uint64_t reserved_6_63 : 58; 502215976Sjmallett#endif 503215976Sjmallett } cn52xx; 504215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; 505215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; 506215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; 507215976Sjmallett struct cvmx_pcsxx_int_en_reg_s cn63xx; 508215976Sjmallett struct cvmx_pcsxx_int_en_reg_s cn63xxp1; 509215976Sjmallett}; 510215976Sjmalletttypedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t; 511215976Sjmallett 512215976Sjmallett/** 513215976Sjmallett * cvmx_pcsx#_int_reg 514215976Sjmallett * 515215976Sjmallett * PCSX Interrupt Register 516215976Sjmallett * 517215976Sjmallett */ 518215976Sjmallettunion cvmx_pcsxx_int_reg 519215976Sjmallett{ 520215976Sjmallett uint64_t u64; 521215976Sjmallett struct cvmx_pcsxx_int_reg_s 522215976Sjmallett { 523215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 524215976Sjmallett uint64_t reserved_7_63 : 57; 525215976Sjmallett uint64_t dbg_sync : 1; /**< Code Group sync failure debug help, see Note below */ 526215976Sjmallett uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */ 527215976Sjmallett uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */ 528215976Sjmallett uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */ 529215976Sjmallett uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state 530215976Sjmallett in one of the 4 xaui lanes */ 531215976Sjmallett uint64_t rxbad : 1; /**< Set when RX state machine in bad state */ 532215976Sjmallett uint64_t txflt : 1; /**< None defined at this time, always 0x0 */ 533215976Sjmallett#else 534215976Sjmallett uint64_t txflt : 1; 535215976Sjmallett uint64_t rxbad : 1; 536215976Sjmallett uint64_t rxsynbad : 1; 537215976Sjmallett uint64_t bitlckls : 1; 538215976Sjmallett uint64_t synlos : 1; 539215976Sjmallett uint64_t algnlos : 1; 540215976Sjmallett uint64_t dbg_sync : 1; 541215976Sjmallett uint64_t reserved_7_63 : 57; 542215976Sjmallett#endif 543215976Sjmallett } s; 544215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx 545215976Sjmallett { 546215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 547215976Sjmallett uint64_t reserved_6_63 : 58; 548215976Sjmallett uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */ 549215976Sjmallett uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */ 550215976Sjmallett uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */ 551215976Sjmallett uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state 552215976Sjmallett in one of the 4 xaui lanes */ 553215976Sjmallett uint64_t rxbad : 1; /**< Set when RX state machine in bad state */ 554215976Sjmallett uint64_t txflt : 1; /**< None defined at this time, always 0x0 */ 555215976Sjmallett#else 556215976Sjmallett uint64_t txflt : 1; 557215976Sjmallett uint64_t rxbad : 1; 558215976Sjmallett uint64_t rxsynbad : 1; 559215976Sjmallett uint64_t bitlckls : 1; 560215976Sjmallett uint64_t synlos : 1; 561215976Sjmallett uint64_t algnlos : 1; 562215976Sjmallett uint64_t reserved_6_63 : 58; 563215976Sjmallett#endif 564215976Sjmallett } cn52xx; 565215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; 566215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx cn56xx; 567215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; 568215976Sjmallett struct cvmx_pcsxx_int_reg_s cn63xx; 569215976Sjmallett struct cvmx_pcsxx_int_reg_s cn63xxp1; 570215976Sjmallett}; 571215976Sjmalletttypedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t; 572215976Sjmallett 573215976Sjmallett/** 574215976Sjmallett * cvmx_pcsx#_log_anl_reg 575215976Sjmallett * 576215976Sjmallett * PCSX Logic Analyzer Register 577215976Sjmallett * 578215976Sjmallett */ 579215976Sjmallettunion cvmx_pcsxx_log_anl_reg 580215976Sjmallett{ 581215976Sjmallett uint64_t u64; 582215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s 583215976Sjmallett { 584215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 585215976Sjmallett uint64_t reserved_7_63 : 57; 586215976Sjmallett uint64_t enc_mode : 1; /**< 1=send xaui encoded data, 0=send xaui raw data to GMX 587215976Sjmallett See .../rtl/pcs/readme_logic_analyzer.txt for details */ 588215976Sjmallett uint64_t drop_ln : 2; /**< xaui lane# to drop from logic analyzer packets 589215976Sjmallett [<5>, <4>] Drop lane \# 590215976Sjmallett 0 0 Drop lane 0 data 591215976Sjmallett 0 1 Drop lane 1 data 592215976Sjmallett 1 0 Drop lane 2 data 593215976Sjmallett 1 1 Drop lane 3 data */ 594215976Sjmallett uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed one or more times 595215976Sjmallett during packetization. 596215976Sjmallett Write 1 to clear this bit */ 597215976Sjmallett uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */ 598215976Sjmallett uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size 599215976Sjmallett 0 0 Packet size 1k bytes 600215976Sjmallett 0 1 Packet size 4k bytes 601215976Sjmallett 1 0 Packet size 8k bytes 602215976Sjmallett 1 1 Packet size 16k bytes */ 603215976Sjmallett#else 604215976Sjmallett uint64_t pkt_sz : 2; 605215976Sjmallett uint64_t la_en : 1; 606215976Sjmallett uint64_t lafifovfl : 1; 607215976Sjmallett uint64_t drop_ln : 2; 608215976Sjmallett uint64_t enc_mode : 1; 609215976Sjmallett uint64_t reserved_7_63 : 57; 610215976Sjmallett#endif 611215976Sjmallett } s; 612215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn52xx; 613215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; 614215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn56xx; 615215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; 616215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn63xx; 617215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; 618215976Sjmallett}; 619215976Sjmalletttypedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t; 620215976Sjmallett 621215976Sjmallett/** 622215976Sjmallett * cvmx_pcsx#_misc_ctl_reg 623215976Sjmallett * 624215976Sjmallett * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6> ^ [4[RXPLRT<1>]]; 625215976Sjmallett * 626215976Sjmallett * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2> ^ [4[TXPLRT<0>]]; 627215976Sjmallett * 628215976Sjmallett * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities 629215976Sjmallett * 630215976Sjmallett * 631215976Sjmallett * 632215976Sjmallett * PCSX Misc Control Register 633215976Sjmallett */ 634215976Sjmallettunion cvmx_pcsxx_misc_ctl_reg 635215976Sjmallett{ 636215976Sjmallett uint64_t u64; 637215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s 638215976Sjmallett { 639215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 640215976Sjmallett uint64_t reserved_4_63 : 60; 641215976Sjmallett uint64_t tx_swap : 1; /**< 0=do not swap xaui lanes going out to qlm's 642215976Sjmallett 1=swap lanes 3 <-> 0 and 2 <-> 1 */ 643215976Sjmallett uint64_t rx_swap : 1; /**< 0=do not swap xaui lanes coming in from qlm's 644215976Sjmallett 1=swap lanes 3 <-> 0 and 2 <-> 1 */ 645215976Sjmallett uint64_t xaui : 1; /**< 1=XAUI mode selected, 0=not XAUI mode selected 646215976Sjmallett This bit represents pi_qlm1/3_cfg[1:0] pin status */ 647215976Sjmallett uint64_t gmxeno : 1; /**< GMX port enable override, GMX en/dis status is held 648215976Sjmallett during data packet reception. */ 649215976Sjmallett#else 650215976Sjmallett uint64_t gmxeno : 1; 651215976Sjmallett uint64_t xaui : 1; 652215976Sjmallett uint64_t rx_swap : 1; 653215976Sjmallett uint64_t tx_swap : 1; 654215976Sjmallett uint64_t reserved_4_63 : 60; 655215976Sjmallett#endif 656215976Sjmallett } s; 657215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; 658215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; 659215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; 660215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; 661215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; 662215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; 663215976Sjmallett}; 664215976Sjmalletttypedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t; 665215976Sjmallett 666215976Sjmallett/** 667215976Sjmallett * cvmx_pcsx#_rx_sync_states_reg 668215976Sjmallett * 669215976Sjmallett * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register 670215976Sjmallett * 671215976Sjmallett */ 672215976Sjmallettunion cvmx_pcsxx_rx_sync_states_reg 673215976Sjmallett{ 674215976Sjmallett uint64_t u64; 675215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s 676215976Sjmallett { 677215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 678215976Sjmallett uint64_t reserved_16_63 : 48; 679215976Sjmallett uint64_t sync3st : 4; /**< Receive lane 3 code grp sync state machine state */ 680215976Sjmallett uint64_t sync2st : 4; /**< Receive lane 2 code grp sync state machine state */ 681215976Sjmallett uint64_t sync1st : 4; /**< Receive lane 1 code grp sync state machine state */ 682215976Sjmallett uint64_t sync0st : 4; /**< Receive lane 0 code grp sync state machine state */ 683215976Sjmallett#else 684215976Sjmallett uint64_t sync0st : 4; 685215976Sjmallett uint64_t sync1st : 4; 686215976Sjmallett uint64_t sync2st : 4; 687215976Sjmallett uint64_t sync3st : 4; 688215976Sjmallett uint64_t reserved_16_63 : 48; 689215976Sjmallett#endif 690215976Sjmallett } s; 691215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; 692215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; 693215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; 694215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; 695215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; 696215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; 697215976Sjmallett}; 698215976Sjmalletttypedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t; 699215976Sjmallett 700215976Sjmallett/** 701215976Sjmallett * cvmx_pcsx#_spd_abil_reg 702215976Sjmallett * 703215976Sjmallett * PCSX_SPD_ABIL_REG = Speed ability register 704215976Sjmallett * 705215976Sjmallett */ 706215976Sjmallettunion cvmx_pcsxx_spd_abil_reg 707215976Sjmallett{ 708215976Sjmallett uint64_t u64; 709215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s 710215976Sjmallett { 711215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 712215976Sjmallett uint64_t reserved_2_63 : 62; 713215976Sjmallett uint64_t tenpasst : 1; /**< Always 0, no 10PASS-TS/2BASE-TL capability support */ 714215976Sjmallett uint64_t tengb : 1; /**< Always 1, 10Gb/s supported */ 715215976Sjmallett#else 716215976Sjmallett uint64_t tengb : 1; 717215976Sjmallett uint64_t tenpasst : 1; 718215976Sjmallett uint64_t reserved_2_63 : 62; 719215976Sjmallett#endif 720215976Sjmallett } s; 721215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn52xx; 722215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; 723215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn56xx; 724215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; 725215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn63xx; 726215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; 727215976Sjmallett}; 728215976Sjmalletttypedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t; 729215976Sjmallett 730215976Sjmallett/** 731215976Sjmallett * cvmx_pcsx#_status1_reg 732215976Sjmallett * 733215976Sjmallett * PCSX_STATUS1_REG = Status Register1 734215976Sjmallett * 735215976Sjmallett */ 736215976Sjmallettunion cvmx_pcsxx_status1_reg 737215976Sjmallett{ 738215976Sjmallett uint64_t u64; 739215976Sjmallett struct cvmx_pcsxx_status1_reg_s 740215976Sjmallett { 741215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 742215976Sjmallett uint64_t reserved_8_63 : 56; 743215976Sjmallett uint64_t flt : 1; /**< 1=Fault condition detected, 0=No fault condition 744215976Sjmallett This bit is a logical OR of Status2 reg bits 11,10 */ 745215976Sjmallett uint64_t reserved_3_6 : 4; 746215976Sjmallett uint64_t rcv_lnk : 1; /**< 1=Receive Link up, 0=Receive Link down 747215976Sjmallett Latching Low version of r_10gbx_status_reg[12], 748215976Sjmallett Link down status continues until SW read. */ 749215976Sjmallett uint64_t lpable : 1; /**< Always set to 1 for Low Power ablility indication */ 750215976Sjmallett uint64_t reserved_0_0 : 1; 751215976Sjmallett#else 752215976Sjmallett uint64_t reserved_0_0 : 1; 753215976Sjmallett uint64_t lpable : 1; 754215976Sjmallett uint64_t rcv_lnk : 1; 755215976Sjmallett uint64_t reserved_3_6 : 4; 756215976Sjmallett uint64_t flt : 1; 757215976Sjmallett uint64_t reserved_8_63 : 56; 758215976Sjmallett#endif 759215976Sjmallett } s; 760215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn52xx; 761215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn52xxp1; 762215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn56xx; 763215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn56xxp1; 764215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn63xx; 765215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn63xxp1; 766215976Sjmallett}; 767215976Sjmalletttypedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t; 768215976Sjmallett 769215976Sjmallett/** 770215976Sjmallett * cvmx_pcsx#_status2_reg 771215976Sjmallett * 772215976Sjmallett * PCSX_STATUS2_REG = Status Register2 773215976Sjmallett * 774215976Sjmallett */ 775215976Sjmallettunion cvmx_pcsxx_status2_reg 776215976Sjmallett{ 777215976Sjmallett uint64_t u64; 778215976Sjmallett struct cvmx_pcsxx_status2_reg_s 779215976Sjmallett { 780215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 781215976Sjmallett uint64_t reserved_16_63 : 48; 782215976Sjmallett uint64_t dev : 2; /**< Always at 2'b10, means a Device present at the addr */ 783215976Sjmallett uint64_t reserved_12_13 : 2; 784215976Sjmallett uint64_t xmtflt : 1; /**< 0=No xmit fault, 1=xmit fault. Implements latching 785215976Sjmallett High function until SW read. */ 786215976Sjmallett uint64_t rcvflt : 1; /**< 0=No rcv fault, 1=rcv fault. Implements latching 787215976Sjmallett High function until SW read */ 788215976Sjmallett uint64_t reserved_3_9 : 7; 789215976Sjmallett uint64_t tengb_w : 1; /**< Always 0, no 10GBASE-W capability */ 790215976Sjmallett uint64_t tengb_x : 1; /**< Always 1, 10GBASE-X capable */ 791215976Sjmallett uint64_t tengb_r : 1; /**< Always 0, no 10GBASE-R capability */ 792215976Sjmallett#else 793215976Sjmallett uint64_t tengb_r : 1; 794215976Sjmallett uint64_t tengb_x : 1; 795215976Sjmallett uint64_t tengb_w : 1; 796215976Sjmallett uint64_t reserved_3_9 : 7; 797215976Sjmallett uint64_t rcvflt : 1; 798215976Sjmallett uint64_t xmtflt : 1; 799215976Sjmallett uint64_t reserved_12_13 : 2; 800215976Sjmallett uint64_t dev : 2; 801215976Sjmallett uint64_t reserved_16_63 : 48; 802215976Sjmallett#endif 803215976Sjmallett } s; 804215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn52xx; 805215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn52xxp1; 806215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn56xx; 807215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn56xxp1; 808215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn63xx; 809215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn63xxp1; 810215976Sjmallett}; 811215976Sjmalletttypedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t; 812215976Sjmallett 813215976Sjmallett/** 814215976Sjmallett * cvmx_pcsx#_tx_rx_polarity_reg 815215976Sjmallett * 816215976Sjmallett * PCSX_POLARITY_REG = TX_RX polarity reg 817215976Sjmallett * 818215976Sjmallett */ 819215976Sjmallettunion cvmx_pcsxx_tx_rx_polarity_reg 820215976Sjmallett{ 821215976Sjmallett uint64_t u64; 822215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s 823215976Sjmallett { 824215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 825215976Sjmallett uint64_t reserved_10_63 : 54; 826215976Sjmallett uint64_t xor_rxplrt : 4; /**< Per lane RX polarity control */ 827215976Sjmallett uint64_t xor_txplrt : 4; /**< Per lane TX polarity control */ 828215976Sjmallett uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 829215976Sjmallett uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 830215976Sjmallett#else 831215976Sjmallett uint64_t txplrt : 1; 832215976Sjmallett uint64_t rxplrt : 1; 833215976Sjmallett uint64_t xor_txplrt : 4; 834215976Sjmallett uint64_t xor_rxplrt : 4; 835215976Sjmallett uint64_t reserved_10_63 : 54; 836215976Sjmallett#endif 837215976Sjmallett } s; 838215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; 839215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 840215976Sjmallett { 841215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 842215976Sjmallett uint64_t reserved_2_63 : 62; 843215976Sjmallett uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 844215976Sjmallett uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 845215976Sjmallett#else 846215976Sjmallett uint64_t txplrt : 1; 847215976Sjmallett uint64_t rxplrt : 1; 848215976Sjmallett uint64_t reserved_2_63 : 62; 849215976Sjmallett#endif 850215976Sjmallett } cn52xxp1; 851215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; 852215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; 853215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; 854215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; 855215976Sjmallett}; 856215976Sjmalletttypedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t; 857215976Sjmallett 858215976Sjmallett/** 859215976Sjmallett * cvmx_pcsx#_tx_rx_states_reg 860215976Sjmallett * 861215976Sjmallett * PCSX_TX_RX_STATES_REG = Transmit Receive States Register 862215976Sjmallett * 863215976Sjmallett */ 864215976Sjmallettunion cvmx_pcsxx_tx_rx_states_reg 865215976Sjmallett{ 866215976Sjmallett uint64_t u64; 867215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s 868215976Sjmallett { 869215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 870215976Sjmallett uint64_t reserved_14_63 : 50; 871215976Sjmallett uint64_t term_err : 1; /**< 1=Check end function detected error in packet 872215976Sjmallett terminate ||T|| column or the one after it */ 873215976Sjmallett uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */ 874215976Sjmallett uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */ 875215976Sjmallett uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */ 876215976Sjmallett uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */ 877215976Sjmallett uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */ 878215976Sjmallett uint64_t algn_st : 3; /**< Lane alignment state machine state state */ 879215976Sjmallett uint64_t rx_st : 2; /**< Receive state machine state state */ 880215976Sjmallett uint64_t tx_st : 3; /**< Transmit state machine state state */ 881215976Sjmallett#else 882215976Sjmallett uint64_t tx_st : 3; 883215976Sjmallett uint64_t rx_st : 2; 884215976Sjmallett uint64_t algn_st : 3; 885215976Sjmallett uint64_t rxbad : 1; 886215976Sjmallett uint64_t syn0bad : 1; 887215976Sjmallett uint64_t syn1bad : 1; 888215976Sjmallett uint64_t syn2bad : 1; 889215976Sjmallett uint64_t syn3bad : 1; 890215976Sjmallett uint64_t term_err : 1; 891215976Sjmallett uint64_t reserved_14_63 : 50; 892215976Sjmallett#endif 893215976Sjmallett } s; 894215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; 895215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 896215976Sjmallett { 897215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 898215976Sjmallett uint64_t reserved_13_63 : 51; 899215976Sjmallett uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */ 900215976Sjmallett uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */ 901215976Sjmallett uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */ 902215976Sjmallett uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */ 903215976Sjmallett uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */ 904215976Sjmallett uint64_t algn_st : 3; /**< Lane alignment state machine state state */ 905215976Sjmallett uint64_t rx_st : 2; /**< Receive state machine state state */ 906215976Sjmallett uint64_t tx_st : 3; /**< Transmit state machine state state */ 907215976Sjmallett#else 908215976Sjmallett uint64_t tx_st : 3; 909215976Sjmallett uint64_t rx_st : 2; 910215976Sjmallett uint64_t algn_st : 3; 911215976Sjmallett uint64_t rxbad : 1; 912215976Sjmallett uint64_t syn0bad : 1; 913215976Sjmallett uint64_t syn1bad : 1; 914215976Sjmallett uint64_t syn2bad : 1; 915215976Sjmallett uint64_t syn3bad : 1; 916215976Sjmallett uint64_t reserved_13_63 : 51; 917215976Sjmallett#endif 918215976Sjmallett } cn52xxp1; 919215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; 920215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; 921215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; 922215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; 923215976Sjmallett}; 924215976Sjmalletttypedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t; 925215976Sjmallett 926215976Sjmallett#endif 927