1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-ndf-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon ndf. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_NDF_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_NDF_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60215976Sjmallett cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000018ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_NDF_CMD_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71215976Sjmallett cvmx_warn("CVMX_NDF_CMD not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000000ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_NDF_DRBELL_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82215976Sjmallett cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000030ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93215976Sjmallett cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000010ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_NDF_INT CVMX_NDF_INT_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_NDF_INT_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 104215976Sjmallett cvmx_warn("CVMX_NDF_INT not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000020ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_NDF_INT_EN_FUNC(void) 113215976Sjmallett{ 114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115215976Sjmallett cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000028ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_NDF_MISC_FUNC(void) 124215976Sjmallett{ 125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126215976Sjmallett cvmx_warn("CVMX_NDF_MISC not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000008ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_NDF_ST_REG_FUNC(void) 135215976Sjmallett{ 136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 137215976Sjmallett cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070001000038ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull)) 142215976Sjmallett#endif 143215976Sjmallett 144215976Sjmallett/** 145215976Sjmallett * cvmx_ndf_bt_pg_info 146215976Sjmallett * 147215976Sjmallett * Notes: 148215976Sjmallett * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR 149215976Sjmallett * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is 150215976Sjmallett * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is 151215976Sjmallett * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value. 152215976Sjmallett * 153215976Sjmallett * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes. 154215976Sjmallett * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values 155215976Sjmallett * 156215976Sjmallett * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this 157215976Sjmallett * field, and a SW CSR write with a value greater than 8, will write an 8 to this field. 158215976Sjmallett * 159215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 160215976Sjmallett */ 161215976Sjmallettunion cvmx_ndf_bt_pg_info 162215976Sjmallett{ 163215976Sjmallett uint64_t u64; 164215976Sjmallett struct cvmx_ndf_bt_pg_info_s 165215976Sjmallett { 166215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 167215976Sjmallett uint64_t reserved_11_63 : 53; 168215976Sjmallett uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0] 169215976Sjmallett command */ 170215976Sjmallett uint64_t adr_cyc : 4; /**< # of column address cycles */ 171215976Sjmallett uint64_t size : 3; /**< bytes per page in the nand device */ 172215976Sjmallett#else 173215976Sjmallett uint64_t size : 3; 174215976Sjmallett uint64_t adr_cyc : 4; 175215976Sjmallett uint64_t t_mult : 4; 176215976Sjmallett uint64_t reserved_11_63 : 53; 177215976Sjmallett#endif 178215976Sjmallett } s; 179215976Sjmallett struct cvmx_ndf_bt_pg_info_s cn52xx; 180215976Sjmallett struct cvmx_ndf_bt_pg_info_s cn63xx; 181215976Sjmallett struct cvmx_ndf_bt_pg_info_s cn63xxp1; 182215976Sjmallett}; 183215976Sjmalletttypedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t; 184215976Sjmallett 185215976Sjmallett/** 186215976Sjmallett * cvmx_ndf_cmd 187215976Sjmallett * 188215976Sjmallett * Notes: 189215976Sjmallett * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes 190215976Sjmallett * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it 191215976Sjmallett * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these 192215976Sjmallett * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr. 193215976Sjmallett * 194215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 195215976Sjmallett */ 196215976Sjmallettunion cvmx_ndf_cmd 197215976Sjmallett{ 198215976Sjmallett uint64_t u64; 199215976Sjmallett struct cvmx_ndf_cmd_s 200215976Sjmallett { 201215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 202215976Sjmallett uint64_t nf_cmd : 64; /**< 8 Command Bytes */ 203215976Sjmallett#else 204215976Sjmallett uint64_t nf_cmd : 64; 205215976Sjmallett#endif 206215976Sjmallett } s; 207215976Sjmallett struct cvmx_ndf_cmd_s cn52xx; 208215976Sjmallett struct cvmx_ndf_cmd_s cn63xx; 209215976Sjmallett struct cvmx_ndf_cmd_s cn63xxp1; 210215976Sjmallett}; 211215976Sjmalletttypedef union cvmx_ndf_cmd cvmx_ndf_cmd_t; 212215976Sjmallett 213215976Sjmallett/** 214215976Sjmallett * cvmx_ndf_drbell 215215976Sjmallett * 216215976Sjmallett * Notes: 217215976Sjmallett * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value. 218215976Sjmallett * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the 219215976Sjmallett * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will 220215976Sjmallett * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a 221215976Sjmallett * non-zero data value, can the execution unit come out of the stalled condition, and resume execution. 222215976Sjmallett * 223215976Sjmallett * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit 224215976Sjmallett * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by 225215976Sjmallett * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of 226215976Sjmallett * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and 227215976Sjmallett * the last command in the sequence will be a bus release command. The execution unit will start execution of 228215976Sjmallett * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first 229215976Sjmallett * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command 230215976Sjmallett * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the 231215976Sjmallett * CNT field by the number of the command sequences, loaded to the command fifo. 232215976Sjmallett * 233215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 234215976Sjmallett */ 235215976Sjmallettunion cvmx_ndf_drbell 236215976Sjmallett{ 237215976Sjmallett uint64_t u64; 238215976Sjmallett struct cvmx_ndf_drbell_s 239215976Sjmallett { 240215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 241215976Sjmallett uint64_t reserved_8_63 : 56; 242215976Sjmallett uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */ 243215976Sjmallett#else 244215976Sjmallett uint64_t cnt : 8; 245215976Sjmallett uint64_t reserved_8_63 : 56; 246215976Sjmallett#endif 247215976Sjmallett } s; 248215976Sjmallett struct cvmx_ndf_drbell_s cn52xx; 249215976Sjmallett struct cvmx_ndf_drbell_s cn63xx; 250215976Sjmallett struct cvmx_ndf_drbell_s cn63xxp1; 251215976Sjmallett}; 252215976Sjmalletttypedef union cvmx_ndf_drbell cvmx_ndf_drbell_t; 253215976Sjmallett 254215976Sjmallett/** 255215976Sjmallett * cvmx_ndf_ecc_cnt 256215976Sjmallett * 257215976Sjmallett * Notes: 258215976Sjmallett * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256] 259215976Sjmallett * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot 260215976Sjmallett * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash 261215976Sjmallett * 262215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 263215976Sjmallett */ 264215976Sjmallettunion cvmx_ndf_ecc_cnt 265215976Sjmallett{ 266215976Sjmallett uint64_t u64; 267215976Sjmallett struct cvmx_ndf_ecc_cnt_s 268215976Sjmallett { 269215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 270215976Sjmallett uint64_t reserved_32_63 : 32; 271215976Sjmallett uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated 272215976Sjmallett bytes. The value pertains to the last 1 bit ecc err */ 273215976Sjmallett uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot 274215976Sjmallett This count saturates instead of wrapping around. */ 275215976Sjmallett#else 276215976Sjmallett uint64_t ecc_err : 8; 277215976Sjmallett uint64_t xor_ecc : 24; 278215976Sjmallett uint64_t reserved_32_63 : 32; 279215976Sjmallett#endif 280215976Sjmallett } s; 281215976Sjmallett struct cvmx_ndf_ecc_cnt_s cn52xx; 282215976Sjmallett struct cvmx_ndf_ecc_cnt_s cn63xx; 283215976Sjmallett struct cvmx_ndf_ecc_cnt_s cn63xxp1; 284215976Sjmallett}; 285215976Sjmalletttypedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t; 286215976Sjmallett 287215976Sjmallett/** 288215976Sjmallett * cvmx_ndf_int 289215976Sjmallett * 290215976Sjmallett * Notes: 291215976Sjmallett * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it. 292215976Sjmallett * 293215976Sjmallett * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the 294215976Sjmallett * last instruction out of the command fifo. 295215976Sjmallett * 296215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 297215976Sjmallett */ 298215976Sjmallettunion cvmx_ndf_int 299215976Sjmallett{ 300215976Sjmallett uint64_t u64; 301215976Sjmallett struct cvmx_ndf_int_s 302215976Sjmallett { 303215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 304215976Sjmallett uint64_t reserved_7_63 : 57; 305215976Sjmallett uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a 306215976Sjmallett fatal error. */ 307215976Sjmallett uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 308215976Sjmallett uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 309215976Sjmallett uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 310215976Sjmallett uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 311215976Sjmallett uint64_t full : 1; /**< Command fifo is full */ 312215976Sjmallett uint64_t empty : 1; /**< Command fifo is empty */ 313215976Sjmallett#else 314215976Sjmallett uint64_t empty : 1; 315215976Sjmallett uint64_t full : 1; 316215976Sjmallett uint64_t wdog : 1; 317215976Sjmallett uint64_t sm_bad : 1; 318215976Sjmallett uint64_t ecc_1bit : 1; 319215976Sjmallett uint64_t ecc_mult : 1; 320215976Sjmallett uint64_t ovrf : 1; 321215976Sjmallett uint64_t reserved_7_63 : 57; 322215976Sjmallett#endif 323215976Sjmallett } s; 324215976Sjmallett struct cvmx_ndf_int_s cn52xx; 325215976Sjmallett struct cvmx_ndf_int_s cn63xx; 326215976Sjmallett struct cvmx_ndf_int_s cn63xxp1; 327215976Sjmallett}; 328215976Sjmalletttypedef union cvmx_ndf_int cvmx_ndf_int_t; 329215976Sjmallett 330215976Sjmallett/** 331215976Sjmallett * cvmx_ndf_int_en 332215976Sjmallett * 333215976Sjmallett * Notes: 334215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 335215976Sjmallett * 336215976Sjmallett */ 337215976Sjmallettunion cvmx_ndf_int_en 338215976Sjmallett{ 339215976Sjmallett uint64_t u64; 340215976Sjmallett struct cvmx_ndf_int_en_s 341215976Sjmallett { 342215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 343215976Sjmallett uint64_t reserved_7_63 : 57; 344215976Sjmallett uint64_t ovrf : 1; /**< Wrote to a full command fifo */ 345215976Sjmallett uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 346215976Sjmallett uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 347215976Sjmallett uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 348215976Sjmallett uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 349215976Sjmallett uint64_t full : 1; /**< Command fifo is full */ 350215976Sjmallett uint64_t empty : 1; /**< Command fifo is empty */ 351215976Sjmallett#else 352215976Sjmallett uint64_t empty : 1; 353215976Sjmallett uint64_t full : 1; 354215976Sjmallett uint64_t wdog : 1; 355215976Sjmallett uint64_t sm_bad : 1; 356215976Sjmallett uint64_t ecc_1bit : 1; 357215976Sjmallett uint64_t ecc_mult : 1; 358215976Sjmallett uint64_t ovrf : 1; 359215976Sjmallett uint64_t reserved_7_63 : 57; 360215976Sjmallett#endif 361215976Sjmallett } s; 362215976Sjmallett struct cvmx_ndf_int_en_s cn52xx; 363215976Sjmallett struct cvmx_ndf_int_en_s cn63xx; 364215976Sjmallett struct cvmx_ndf_int_en_s cn63xxp1; 365215976Sjmallett}; 366215976Sjmalletttypedef union cvmx_ndf_int_en cvmx_ndf_int_en_t; 367215976Sjmallett 368215976Sjmallett/** 369215976Sjmallett * cvmx_ndf_misc 370215976Sjmallett * 371215976Sjmallett * Notes: 372215976Sjmallett * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo. 373215976Sjmallett * the fifo size is 16 entries. 374215976Sjmallett * 375215976Sjmallett * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count 376215976Sjmallett * represents number of eclk cycles. 377215976Sjmallett * 378215976Sjmallett * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands 379215976Sjmallett * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1) 380215976Sjmallett * 381215976Sjmallett * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo, 382215976Sjmallett * in response to RD_CMD bit being set to 1 by SW. 383215976Sjmallett * 384215976Sjmallett * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response 385215976Sjmallett * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0. 386215976Sjmallett * 387215976Sjmallett * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the 388215976Sjmallett * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the 389215976Sjmallett * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the 390215976Sjmallett * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD 391215976Sjmallett * bit will be cleared on any NDF_CMD csr write by SW. 392215976Sjmallett * 393215976Sjmallett * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin. 394215976Sjmallett * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0 395215976Sjmallett * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is 396215976Sjmallett * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0. 397215976Sjmallett * 398215976Sjmallett * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended. 399215976Sjmallett * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must 400215976Sjmallett * never be set when booting from nand flash and region zero is enabled. 401215976Sjmallett * 402215976Sjmallett * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command 403215976Sjmallett * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution 404215976Sjmallett * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo 405215976Sjmallett * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0. 406215976Sjmallett * 407215976Sjmallett * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting 408215976Sjmallett * the fifo. The fifo comes up empty at the end of power on reset. 409215976Sjmallett * 410215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 411215976Sjmallett */ 412215976Sjmallettunion cvmx_ndf_misc 413215976Sjmallett{ 414215976Sjmallett uint64_t u64; 415215976Sjmallett struct cvmx_ndf_misc_s 416215976Sjmallett { 417215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 418215976Sjmallett uint64_t reserved_28_63 : 36; 419215976Sjmallett uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads 420215976Sjmallett or boot dma's proceed as if no multi bit errors 421215976Sjmallett occured. HW will fix single bit errors as usual */ 422215976Sjmallett uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 423215976Sjmallett uint64_t wait_cnt : 6; /**< WAIT input filter count */ 424215976Sjmallett uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 425215976Sjmallett uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 426215976Sjmallett command fifo read out, in response to RD_CMD */ 427215976Sjmallett uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 428215976Sjmallett bytes from Command fifo into the NDF_CMD csr 429215976Sjmallett SW reads NDF_CMD csr, HW clears this bit to 0 */ 430215976Sjmallett uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 431215976Sjmallett bytes at a time into the NDF_CMD csr */ 432215976Sjmallett uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 433215976Sjmallett uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 434215976Sjmallett causes boot state mchines to sleep */ 435215976Sjmallett uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 436215976Sjmallett next command in the fifo. */ 437215976Sjmallett uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 438215976Sjmallett 0=normal operation */ 439215976Sjmallett#else 440215976Sjmallett uint64_t rst_ff : 1; 441215976Sjmallett uint64_t ex_dis : 1; 442215976Sjmallett uint64_t bt_dis : 1; 443215976Sjmallett uint64_t bt_dma : 1; 444215976Sjmallett uint64_t rd_cmd : 1; 445215976Sjmallett uint64_t rd_val : 1; 446215976Sjmallett uint64_t rd_done : 1; 447215976Sjmallett uint64_t fr_byt : 11; 448215976Sjmallett uint64_t wait_cnt : 6; 449215976Sjmallett uint64_t nbr_hwm : 3; 450215976Sjmallett uint64_t mb_dis : 1; 451215976Sjmallett uint64_t reserved_28_63 : 36; 452215976Sjmallett#endif 453215976Sjmallett } s; 454215976Sjmallett struct cvmx_ndf_misc_cn52xx 455215976Sjmallett { 456215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 457215976Sjmallett uint64_t reserved_27_63 : 37; 458215976Sjmallett uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 459215976Sjmallett uint64_t wait_cnt : 6; /**< WAIT input filter count */ 460215976Sjmallett uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 461215976Sjmallett uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 462215976Sjmallett command fifo read out, in response to RD_CMD */ 463215976Sjmallett uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 464215976Sjmallett bytes from Command fifo into the NDF_CMD csr 465215976Sjmallett SW reads NDF_CMD csr, HW clears this bit to 0 */ 466215976Sjmallett uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 467215976Sjmallett bytes at a time into the NDF_CMD csr */ 468215976Sjmallett uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 469215976Sjmallett uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 470215976Sjmallett causes boot state mchines to sleep */ 471215976Sjmallett uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 472215976Sjmallett next command in the fifo. */ 473215976Sjmallett uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 474215976Sjmallett 0=normal operation */ 475215976Sjmallett#else 476215976Sjmallett uint64_t rst_ff : 1; 477215976Sjmallett uint64_t ex_dis : 1; 478215976Sjmallett uint64_t bt_dis : 1; 479215976Sjmallett uint64_t bt_dma : 1; 480215976Sjmallett uint64_t rd_cmd : 1; 481215976Sjmallett uint64_t rd_val : 1; 482215976Sjmallett uint64_t rd_done : 1; 483215976Sjmallett uint64_t fr_byt : 11; 484215976Sjmallett uint64_t wait_cnt : 6; 485215976Sjmallett uint64_t nbr_hwm : 3; 486215976Sjmallett uint64_t reserved_27_63 : 37; 487215976Sjmallett#endif 488215976Sjmallett } cn52xx; 489215976Sjmallett struct cvmx_ndf_misc_s cn63xx; 490215976Sjmallett struct cvmx_ndf_misc_s cn63xxp1; 491215976Sjmallett}; 492215976Sjmalletttypedef union cvmx_ndf_misc cvmx_ndf_misc_t; 493215976Sjmallett 494215976Sjmallett/** 495215976Sjmallett * cvmx_ndf_st_reg 496215976Sjmallett * 497215976Sjmallett * Notes: 498215976Sjmallett * This CSR aggregates all state machines used in nand flash controller for debug. 499215976Sjmallett * Like all NDF_... registers, 64-bit operations must be used to access this register 500215976Sjmallett */ 501215976Sjmallettunion cvmx_ndf_st_reg 502215976Sjmallett{ 503215976Sjmallett uint64_t u64; 504215976Sjmallett struct cvmx_ndf_st_reg_s 505215976Sjmallett { 506215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 507215976Sjmallett uint64_t reserved_16_63 : 48; 508215976Sjmallett uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy 509215976Sjmallett 1 means execution of command sequence is complete 510215976Sjmallett and command fifo is empty */ 511215976Sjmallett uint64_t exe_sm : 4; /**< Command Execution State machine states */ 512215976Sjmallett uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */ 513215976Sjmallett uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */ 514215976Sjmallett uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */ 515215976Sjmallett uint64_t main_bad : 1; /**< Main State machine in bad state */ 516215976Sjmallett uint64_t main_sm : 3; /**< Main State machine states */ 517215976Sjmallett#else 518215976Sjmallett uint64_t main_sm : 3; 519215976Sjmallett uint64_t main_bad : 1; 520215976Sjmallett uint64_t rd_ff : 2; 521215976Sjmallett uint64_t rd_ff_bad : 1; 522215976Sjmallett uint64_t bt_sm : 4; 523215976Sjmallett uint64_t exe_sm : 4; 524215976Sjmallett uint64_t exe_idle : 1; 525215976Sjmallett uint64_t reserved_16_63 : 48; 526215976Sjmallett#endif 527215976Sjmallett } s; 528215976Sjmallett struct cvmx_ndf_st_reg_s cn52xx; 529215976Sjmallett struct cvmx_ndf_st_reg_s cn63xx; 530215976Sjmallett struct cvmx_ndf_st_reg_s cn63xxp1; 531215976Sjmallett}; 532215976Sjmalletttypedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t; 533215976Sjmallett 534215976Sjmallett#endif 535